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[deliverable/linux.git] / drivers / video / exynos / exynos_mipi_dsi_common.c
1 /* linux/drivers/video/exynos/exynos_mipi_dsi_common.c
2 *
3 * Samsung SoC MIPI-DSI common driver.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd
6 *
7 * InKi Dae, <inki.dae@samsung.com>
8 * Donghwa Lee, <dh09.lee@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/mutex.h>
19 #include <linux/wait.h>
20 #include <linux/fs.h>
21 #include <linux/mm.h>
22 #include <linux/fb.h>
23 #include <linux/ctype.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/memory.h>
27 #include <linux/delay.h>
28 #include <linux/irqreturn.h>
29 #include <linux/kthread.h>
30
31 #include <video/mipi_display.h>
32 #include <video/exynos_mipi_dsim.h>
33
34 #include <mach/map.h>
35
36 #include "exynos_mipi_dsi_regs.h"
37 #include "exynos_mipi_dsi_lowlevel.h"
38 #include "exynos_mipi_dsi_common.h"
39
40 #define MIPI_FIFO_TIMEOUT msecs_to_jiffies(250)
41 #define MIPI_RX_FIFO_READ_DONE 0x30800002
42 #define MIPI_MAX_RX_FIFO 20
43 #define MHZ (1000 * 1000)
44 #define FIN_HZ (24 * MHZ)
45
46 #define DFIN_PLL_MIN_HZ (6 * MHZ)
47 #define DFIN_PLL_MAX_HZ (12 * MHZ)
48
49 #define DFVCO_MIN_HZ (500 * MHZ)
50 #define DFVCO_MAX_HZ (1000 * MHZ)
51
52 #define TRY_GET_FIFO_TIMEOUT (5000 * 2)
53 #define TRY_FIFO_CLEAR (10)
54
55 /* MIPI-DSIM status types. */
56 enum {
57 DSIM_STATE_INIT, /* should be initialized. */
58 DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
59 DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
60 DSIM_STATE_ULPS
61 };
62
63 /* define DSI lane types. */
64 enum {
65 DSIM_LANE_CLOCK = (1 << 0),
66 DSIM_LANE_DATA0 = (1 << 1),
67 DSIM_LANE_DATA1 = (1 << 2),
68 DSIM_LANE_DATA2 = (1 << 3),
69 DSIM_LANE_DATA3 = (1 << 4)
70 };
71
72 static unsigned int dpll_table[15] = {
73 100, 120, 170, 220, 270,
74 320, 390, 450, 510, 560,
75 640, 690, 770, 870, 950
76 };
77
78 irqreturn_t exynos_mipi_dsi_interrupt_handler(int irq, void *dev_id)
79 {
80 struct mipi_dsim_device *dsim = dev_id;
81 unsigned int intsrc, intmsk;
82
83 intsrc = exynos_mipi_dsi_read_interrupt(dsim);
84 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim);
85 intmsk = ~intmsk & intsrc;
86
87 if (intsrc & INTMSK_RX_DONE) {
88 complete(&dsim_rd_comp);
89 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n");
90 }
91 if (intsrc & INTMSK_FIFO_EMPTY) {
92 complete(&dsim_wr_comp);
93 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n");
94 }
95
96 exynos_mipi_dsi_clear_interrupt(dsim, intmsk);
97
98 return IRQ_HANDLED;
99 }
100
101 /*
102 * write long packet to mipi dsi slave
103 * @dsim: mipi dsim device structure.
104 * @data0: packet data to send.
105 * @data1: size of packet data
106 */
107 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
108 const unsigned char *data0, unsigned int data_size)
109 {
110 unsigned int data_cnt = 0, payload = 0;
111
112 /* in case that data count is more then 4 */
113 for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
114 /*
115 * after sending 4bytes per one time,
116 * send remainder data less then 4.
117 */
118 if ((data_size - data_cnt) < 4) {
119 if ((data_size - data_cnt) == 3) {
120 payload = data0[data_cnt] |
121 data0[data_cnt + 1] << 8 |
122 data0[data_cnt + 2] << 16;
123 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
124 payload, data0[data_cnt],
125 data0[data_cnt + 1],
126 data0[data_cnt + 2]);
127 } else if ((data_size - data_cnt) == 2) {
128 payload = data0[data_cnt] |
129 data0[data_cnt + 1] << 8;
130 dev_dbg(dsim->dev,
131 "count = 2 payload = %x, %x %x\n", payload,
132 data0[data_cnt],
133 data0[data_cnt + 1]);
134 } else if ((data_size - data_cnt) == 1) {
135 payload = data0[data_cnt];
136 }
137
138 exynos_mipi_dsi_wr_tx_data(dsim, payload);
139 /* send 4bytes per one time. */
140 } else {
141 payload = data0[data_cnt] |
142 data0[data_cnt + 1] << 8 |
143 data0[data_cnt + 2] << 16 |
144 data0[data_cnt + 3] << 24;
145
146 dev_dbg(dsim->dev,
147 "count = 4 payload = %x, %x %x %x %x\n",
148 payload, *(u8 *)(data0 + data_cnt),
149 data0[data_cnt + 1],
150 data0[data_cnt + 2],
151 data0[data_cnt + 3]);
152
153 exynos_mipi_dsi_wr_tx_data(dsim, payload);
154 }
155 }
156 }
157
158 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
159 const unsigned char *data0, unsigned int data_size)
160 {
161 unsigned int check_rx_ack = 0;
162
163 if (dsim->state == DSIM_STATE_ULPS) {
164 dev_err(dsim->dev, "state is ULPS.\n");
165
166 return -EINVAL;
167 }
168
169 /* FIXME!!! why does it need this delay? */
170 msleep(20);
171
172 mutex_lock(&dsim->lock);
173
174 switch (data_id) {
175 /* short packet types of packet types for command. */
176 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
177 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
178 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
179 case MIPI_DSI_DCS_SHORT_WRITE:
180 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
181 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
182 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
183 if (check_rx_ack) {
184 /* process response func should be implemented */
185 mutex_unlock(&dsim->lock);
186 return 0;
187 } else {
188 mutex_unlock(&dsim->lock);
189 return -EINVAL;
190 }
191
192 /* general command */
193 case MIPI_DSI_COLOR_MODE_OFF:
194 case MIPI_DSI_COLOR_MODE_ON:
195 case MIPI_DSI_SHUTDOWN_PERIPHERAL:
196 case MIPI_DSI_TURN_ON_PERIPHERAL:
197 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
198 if (check_rx_ack) {
199 /* process response func should be implemented. */
200 mutex_unlock(&dsim->lock);
201 return 0;
202 } else {
203 mutex_unlock(&dsim->lock);
204 return -EINVAL;
205 }
206
207 /* packet types for video data */
208 case MIPI_DSI_V_SYNC_START:
209 case MIPI_DSI_V_SYNC_END:
210 case MIPI_DSI_H_SYNC_START:
211 case MIPI_DSI_H_SYNC_END:
212 case MIPI_DSI_END_OF_TRANSMISSION:
213 mutex_unlock(&dsim->lock);
214 return 0;
215
216 /* long packet type and null packet */
217 case MIPI_DSI_NULL_PACKET:
218 case MIPI_DSI_BLANKING_PACKET:
219 mutex_unlock(&dsim->lock);
220 return 0;
221 case MIPI_DSI_GENERIC_LONG_WRITE:
222 case MIPI_DSI_DCS_LONG_WRITE:
223 {
224 unsigned int size, payload = 0;
225 INIT_COMPLETION(dsim_wr_comp);
226
227 size = data_size * 4;
228
229 /* if data count is less then 4, then send 3bytes data. */
230 if (data_size < 4) {
231 payload = data0[0] |
232 data0[1] << 8 |
233 data0[2] << 16;
234
235 exynos_mipi_dsi_wr_tx_data(dsim, payload);
236
237 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
238 data_size, payload, data0[0],
239 data0[1], data0[2]);
240
241 /* in case that data count is more then 4 */
242 } else
243 exynos_mipi_dsi_long_data_wr(dsim, data0, data_size);
244
245 /* put data into header fifo */
246 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff,
247 (data_size & 0xff00) >> 8);
248
249 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp,
250 MIPI_FIFO_TIMEOUT)) {
251 dev_warn(dsim->dev, "command write timeout.\n");
252 mutex_unlock(&dsim->lock);
253 return -EAGAIN;
254 }
255
256 if (check_rx_ack) {
257 /* process response func should be implemented. */
258 mutex_unlock(&dsim->lock);
259 return 0;
260 } else {
261 mutex_unlock(&dsim->lock);
262 return -EINVAL;
263 }
264 }
265
266 /* packet typo for video data */
267 case MIPI_DSI_PACKED_PIXEL_STREAM_16:
268 case MIPI_DSI_PACKED_PIXEL_STREAM_18:
269 case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
270 case MIPI_DSI_PACKED_PIXEL_STREAM_24:
271 if (check_rx_ack) {
272 /* process response func should be implemented. */
273 mutex_unlock(&dsim->lock);
274 return 0;
275 } else {
276 mutex_unlock(&dsim->lock);
277 return -EINVAL;
278 }
279 default:
280 dev_warn(dsim->dev,
281 "data id %x is not supported current DSI spec.\n",
282 data_id);
283
284 mutex_unlock(&dsim->lock);
285 return -EINVAL;
286 }
287 }
288
289 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim,
290 unsigned int req_size, unsigned int rx_data, u8 *rx_buf)
291 {
292 unsigned int rcv_pkt, i, j;
293 u16 rxsize;
294
295 /* for long packet */
296 rxsize = (u16)((rx_data & 0x00ffff00) >> 8);
297 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize);
298 if (rxsize != req_size) {
299 dev_dbg(dsim->dev,
300 "received size mismatch received: %d, requested: %d\n",
301 rxsize, req_size);
302 goto err;
303 }
304
305 for (i = 0; i < (rxsize >> 2); i++) {
306 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
307 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
308 for (j = 0; j < 4; j++) {
309 rx_buf[(i * 4) + j] =
310 (u8)(rcv_pkt >> (j * 8)) & 0xff;
311 dev_dbg(dsim->dev, "received value : %02x\n",
312 (rcv_pkt >> (j * 8)) & 0xff);
313 }
314 }
315 if (rxsize % 4) {
316 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
317 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt);
318 for (j = 0; j < (rxsize % 4); j++) {
319 rx_buf[(i * 4) + j] =
320 (u8)(rcv_pkt >> (j * 8)) & 0xff;
321 dev_dbg(dsim->dev, "received value : %02x\n",
322 (rcv_pkt >> (j * 8)) & 0xff);
323 }
324 }
325
326 return rxsize;
327
328 err:
329 return -EINVAL;
330 }
331
332 static unsigned int exynos_mipi_dsi_response_size(unsigned int req_size)
333 {
334 switch (req_size) {
335 case 1:
336 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE;
337 case 2:
338 return MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE;
339 default:
340 return MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE;
341 }
342 }
343
344 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
345 unsigned int data0, unsigned int req_size, u8 *rx_buf)
346 {
347 unsigned int rx_data, rcv_pkt, i;
348 u8 response = 0;
349 u16 rxsize;
350
351 if (dsim->state == DSIM_STATE_ULPS) {
352 dev_err(dsim->dev, "state is ULPS.\n");
353
354 return -EINVAL;
355 }
356
357 /* FIXME!!! */
358 msleep(20);
359
360 mutex_lock(&dsim->lock);
361 INIT_COMPLETION(dsim_rd_comp);
362 exynos_mipi_dsi_rd_tx_header(dsim,
363 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, req_size);
364
365 response = exynos_mipi_dsi_response_size(req_size);
366
367 switch (data_id) {
368 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
369 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
370 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
371 case MIPI_DSI_DCS_READ:
372 exynos_mipi_dsi_rd_tx_header(dsim,
373 data_id, data0);
374 /* process response func should be implemented. */
375 break;
376 default:
377 dev_warn(dsim->dev,
378 "data id %x is not supported current DSI spec.\n",
379 data_id);
380
381 return -EINVAL;
382 }
383
384 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp,
385 MIPI_FIFO_TIMEOUT)) {
386 pr_err("RX done interrupt timeout\n");
387 mutex_unlock(&dsim->lock);
388 return 0;
389 }
390
391 msleep(20);
392
393 rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim);
394
395 if ((u8)(rx_data & 0xff) != response) {
396 printk(KERN_ERR
397 "mipi dsi wrong response rx_data : %x, response:%x\n",
398 rx_data, response);
399 goto clear_rx_fifo;
400 }
401
402 if (req_size <= 2) {
403 /* for short packet */
404 for (i = 0; i < req_size; i++)
405 rx_buf[i] = (rx_data >> (8 + (i * 8))) & 0xff;
406 rxsize = req_size;
407 } else {
408 /* for long packet */
409 rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data,
410 rx_buf);
411 if (rxsize != req_size)
412 goto clear_rx_fifo;
413 }
414
415 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
416
417 msleep(20);
418
419 if (rcv_pkt != MIPI_RX_FIFO_READ_DONE) {
420 dev_info(dsim->dev,
421 "Can't found RX FIFO READ DONE FLAG : %x\n", rcv_pkt);
422 goto clear_rx_fifo;
423 }
424
425 mutex_unlock(&dsim->lock);
426
427 return rxsize;
428
429 clear_rx_fifo:
430 i = 0;
431 while (1) {
432 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim);
433 if ((rcv_pkt == MIPI_RX_FIFO_READ_DONE)
434 || (i > MIPI_MAX_RX_FIFO))
435 break;
436 dev_dbg(dsim->dev,
437 "mipi dsi clear rx fifo : %08x\n", rcv_pkt);
438 i++;
439 }
440 dev_info(dsim->dev,
441 "mipi dsi rx done count : %d, rcv_pkt : %08x\n", i, rcv_pkt);
442
443 mutex_unlock(&dsim->lock);
444
445 return 0;
446 }
447
448 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim,
449 unsigned int enable)
450 {
451 int sw_timeout;
452
453 if (enable) {
454 sw_timeout = 1000;
455
456 exynos_mipi_dsi_enable_pll(dsim, 1);
457 while (1) {
458 sw_timeout--;
459 if (exynos_mipi_dsi_is_pll_stable(dsim))
460 return 0;
461 if (sw_timeout == 0)
462 return -EINVAL;
463 }
464 } else
465 exynos_mipi_dsi_enable_pll(dsim, 0);
466
467 return 0;
468 }
469
470 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
471 unsigned int pre_divider, unsigned int main_divider,
472 unsigned int scaler)
473 {
474 unsigned long dfin_pll, dfvco, dpll_out;
475 unsigned int i, freq_band = 0xf;
476
477 dfin_pll = (FIN_HZ / pre_divider);
478
479 /******************************************************
480 * Serial Clock(=ByteClk X 8) FreqBand[3:0] *
481 ******************************************************
482 * ~ 99.99 MHz 0000
483 * 100 ~ 119.99 MHz 0001
484 * 120 ~ 159.99 MHz 0010
485 * 160 ~ 199.99 MHz 0011
486 * 200 ~ 239.99 MHz 0100
487 * 140 ~ 319.99 MHz 0101
488 * 320 ~ 389.99 MHz 0110
489 * 390 ~ 449.99 MHz 0111
490 * 450 ~ 509.99 MHz 1000
491 * 510 ~ 559.99 MHz 1001
492 * 560 ~ 639.99 MHz 1010
493 * 640 ~ 689.99 MHz 1011
494 * 690 ~ 769.99 MHz 1100
495 * 770 ~ 869.99 MHz 1101
496 * 870 ~ 949.99 MHz 1110
497 * 950 ~ 1000 MHz 1111
498 ******************************************************/
499 if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
500 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n");
501 exynos_mipi_dsi_enable_afc(dsim, 0, 0);
502 } else {
503 if (dfin_pll < 7 * MHZ)
504 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
505 else if (dfin_pll < 8 * MHZ)
506 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
507 else if (dfin_pll < 9 * MHZ)
508 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
509 else if (dfin_pll < 10 * MHZ)
510 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
511 else if (dfin_pll < 11 * MHZ)
512 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
513 else
514 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
515 }
516
517 dfvco = dfin_pll * main_divider;
518 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
519 dfvco, dfin_pll, main_divider);
520 if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
521 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n");
522
523 dpll_out = dfvco / (1 << scaler);
524 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
525 dpll_out, dfvco, scaler);
526
527 for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
528 if (dpll_out < dpll_table[i] * MHZ) {
529 freq_band = i;
530 break;
531 }
532 }
533
534 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
535
536 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
537
538 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
539 exynos_mipi_dsi_prep_ctrl(dsim, 0);
540
541 /* Freq Band */
542 exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
543
544 /* Stable time */
545 exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time);
546
547 /* Enable PLL */
548 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
549 (dpll_out / MHZ));
550
551 return dpll_out;
552 }
553
554 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
555 unsigned int byte_clk_sel, unsigned int enable)
556 {
557 unsigned int esc_div;
558 unsigned long esc_clk_error_rate;
559 unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
560
561 if (enable) {
562 dsim->e_clk_src = byte_clk_sel;
563
564 /* Escape mode clock and byte clock source */
565 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
566
567 /* DPHY, DSIM Link : D-PHY clock out */
568 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
569 hs_clk = exynos_mipi_dsi_change_pll(dsim,
570 dsim->dsim_config->p, dsim->dsim_config->m,
571 dsim->dsim_config->s);
572 if (hs_clk == 0) {
573 dev_err(dsim->dev,
574 "failed to get hs clock.\n");
575 return -EINVAL;
576 }
577
578 byte_clk = hs_clk / 8;
579 exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
580 exynos_mipi_dsi_pll_on(dsim, 1);
581 /* DPHY : D-PHY clock out, DSIM link : external clock out */
582 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8) {
583 dev_warn(dsim->dev, "this project is not support\n");
584 dev_warn(dsim->dev,
585 "external clock source for MIPI DSIM.\n");
586 } else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS) {
587 dev_warn(dsim->dev, "this project is not support\n");
588 dev_warn(dsim->dev,
589 "external clock source for MIPI DSIM\n");
590 }
591
592 /* escape clock divider */
593 esc_div = byte_clk / (dsim->dsim_config->esc_clk);
594 dev_dbg(dsim->dev,
595 "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
596 esc_div, byte_clk, dsim->dsim_config->esc_clk);
597 if ((byte_clk / esc_div) >= (20 * MHZ) ||
598 (byte_clk / esc_div) >
599 dsim->dsim_config->esc_clk)
600 esc_div += 1;
601
602 escape_clk = byte_clk / esc_div;
603 dev_dbg(dsim->dev,
604 "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
605 escape_clk, byte_clk, esc_div);
606
607 /* enable escape clock. */
608 exynos_mipi_dsi_enable_byte_clock(dsim, 1);
609
610 /* enable byte clk and escape clock */
611 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
612 /* escape clock on lane */
613 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
614 (DSIM_LANE_CLOCK | dsim->data_lane), 1);
615
616 dev_dbg(dsim->dev, "byte clock is %luMHz\n",
617 (byte_clk / MHZ));
618 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
619 (dsim->dsim_config->esc_clk / MHZ));
620 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
621 dev_dbg(dsim->dev, "escape clock is %luMHz\n",
622 ((byte_clk / esc_div) / MHZ));
623
624 if ((byte_clk / esc_div) > escape_clk) {
625 esc_clk_error_rate = escape_clk /
626 (byte_clk / esc_div);
627 dev_warn(dsim->dev, "error rate is %lu over.\n",
628 (esc_clk_error_rate / 100));
629 } else if ((byte_clk / esc_div) < (escape_clk)) {
630 esc_clk_error_rate = (byte_clk / esc_div) /
631 escape_clk;
632 dev_warn(dsim->dev, "error rate is %lu under.\n",
633 (esc_clk_error_rate / 100));
634 }
635 } else {
636 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
637 (DSIM_LANE_CLOCK | dsim->data_lane), 0);
638 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
639
640 /* disable escape clock. */
641 exynos_mipi_dsi_enable_byte_clock(dsim, 0);
642
643 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
644 exynos_mipi_dsi_pll_on(dsim, 0);
645 }
646
647 return 0;
648 }
649
650 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
651 {
652 dsim->state = DSIM_STATE_INIT;
653
654 switch (dsim->dsim_config->e_no_data_lane) {
655 case DSIM_DATA_LANE_1:
656 dsim->data_lane = DSIM_LANE_DATA0;
657 break;
658 case DSIM_DATA_LANE_2:
659 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
660 break;
661 case DSIM_DATA_LANE_3:
662 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
663 DSIM_LANE_DATA2;
664 break;
665 case DSIM_DATA_LANE_4:
666 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
667 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
668 break;
669 default:
670 dev_info(dsim->dev, "data lane is invalid.\n");
671 return -EINVAL;
672 };
673
674 exynos_mipi_dsi_sw_reset(dsim);
675 exynos_mipi_dsi_func_reset(dsim);
676
677 exynos_mipi_dsi_dp_dn_swap(dsim, 0);
678
679 return 0;
680 }
681
682 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim)
683 {
684 unsigned int src = 0;
685
686 src = (INTSRC_SFR_FIFO_EMPTY | INTSRC_RX_DATA_DONE);
687 exynos_mipi_dsi_set_interrupt(dsim, src, 1);
688
689 src = 0;
690 src = ~(INTMSK_RX_DONE | INTMSK_FIFO_EMPTY);
691 exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1);
692 }
693
694 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
695 unsigned int enable)
696 {
697 /* enable only frame done interrupt */
698 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
699
700 return 0;
701 }
702
703 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
704 unsigned int enable)
705 {
706
707 /* consider Main display and Sub display. */
708
709 exynos_mipi_dsi_set_main_stand_by(dsim, enable);
710 }
711
712 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
713 struct mipi_dsim_config *dsim_config)
714 {
715 struct mipi_dsim_platform_data *dsim_pd;
716 struct fb_videomode *timing;
717
718 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd;
719 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info;
720
721 /* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
722 if (dsim_config->e_interface == (u32) DSIM_VIDEO) {
723 if (dsim_config->auto_vertical_cnt == 0) {
724 exynos_mipi_dsi_set_main_disp_vporch(dsim,
725 dsim_config->cmd_allow,
726 timing->lower_margin,
727 timing->upper_margin);
728 exynos_mipi_dsi_set_main_disp_hporch(dsim,
729 timing->right_margin,
730 timing->left_margin);
731 exynos_mipi_dsi_set_main_disp_sync_area(dsim,
732 timing->vsync_len,
733 timing->hsync_len);
734 }
735 }
736
737 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres,
738 timing->yres);
739
740 exynos_mipi_dsi_display_config(dsim, dsim_config);
741
742 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n",
743 timing->xres, timing->yres);
744
745 return 0;
746 }
747
748 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
749 {
750 unsigned int time_out = 100;
751
752 switch (dsim->state) {
753 case DSIM_STATE_INIT:
754 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
755
756 /* dsi configuration */
757 exynos_mipi_dsi_init_config(dsim);
758 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
759 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
760
761 /* set clock configuration */
762 exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1);
763
764 /* check clock and data lane state are stop state */
765 while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
766 time_out--;
767 if (time_out == 0) {
768 dev_err(dsim->dev,
769 "DSI Master is not stop state.\n");
770 dev_err(dsim->dev,
771 "Check initialization process\n");
772
773 return -EINVAL;
774 }
775 }
776 if (time_out != 0) {
777 dev_info(dsim->dev,
778 "DSI Master driver has been completed.\n");
779 dev_info(dsim->dev, "DSI Master state is stop state\n");
780 }
781
782 dsim->state = DSIM_STATE_STOP;
783
784 /* BTA sequence counters */
785 exynos_mipi_dsi_set_stop_state_counter(dsim,
786 dsim->dsim_config->stop_holding_cnt);
787 exynos_mipi_dsi_set_bta_timeout(dsim,
788 dsim->dsim_config->bta_timeout);
789 exynos_mipi_dsi_set_lpdr_timeout(dsim,
790 dsim->dsim_config->rx_timeout);
791
792 return 0;
793 default:
794 dev_info(dsim->dev, "DSI Master is already init.\n");
795 return 0;
796 }
797
798 return 0;
799 }
800
801 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
802 {
803 if (dsim->state != DSIM_STATE_STOP) {
804 dev_warn(dsim->dev, "DSIM is not in stop state.\n");
805 return 0;
806 }
807
808 if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) {
809 dev_warn(dsim->dev, "clock source is external bypass.\n");
810 return 0;
811 }
812
813 dsim->state = DSIM_STATE_HSCLKEN;
814
815 /* set LCDC and CPU transfer mode to HS. */
816 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
817 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
818 exynos_mipi_dsi_enable_hs_clock(dsim, 1);
819
820 return 0;
821 }
822
823 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
824 unsigned int mode)
825 {
826 if (mode) {
827 if (dsim->state != DSIM_STATE_HSCLKEN) {
828 dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
829 return -EINVAL;
830 }
831
832 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
833 } else {
834 if (dsim->state == DSIM_STATE_INIT || dsim->state ==
835 DSIM_STATE_ULPS) {
836 dev_err(dsim->dev,
837 "DSI Master is not STOP or HSDT state.\n");
838 return -EINVAL;
839 }
840
841 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
842 }
843
844 return 0;
845 }
846
847 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
848 {
849 return _exynos_mipi_dsi_get_frame_done_status(dsim);
850 }
851
852 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
853 {
854 _exynos_mipi_dsi_clear_frame_done(dsim);
855
856 return 0;
857 }
858
859 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
860 unsigned int val)
861 {
862 int try = TRY_FIFO_CLEAR;
863
864 exynos_mipi_dsi_sw_reset_release(dsim);
865 exynos_mipi_dsi_func_reset(dsim);
866
867 do {
868 if (exynos_mipi_dsi_get_sw_reset_release(dsim)) {
869 exynos_mipi_dsi_init_interrupt(dsim);
870 dev_dbg(dsim->dev, "reset release done.\n");
871 return 0;
872 }
873 } while (--try);
874
875 dev_err(dsim->dev, "failed to clear dsim fifo.\n");
876 return -EAGAIN;
877 }
878
879 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
880 MODULE_DESCRIPTION("Samusung SoC MIPI-DSI common driver");
881 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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