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Merge tag 'trace-4.1-tracefs' of git://git.kernel.org/pub/scm/linux/kernel/git/rosted...
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
1 /*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
41 #include <linux/of.h>
42
43 #include <video/omapdss.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47 #include "dispc.h"
48
49 /* DISPC */
50 #define DISPC_SZ_REGS SZ_4K
51
52 enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56 };
57
58 #define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61 #define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
64 struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
78 const struct omap_video_timings *mgr_timings,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
83 unsigned long (*calc_core_clk) (unsigned long pclk,
84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
86 u8 num_fifos;
87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
96
97 bool set_max_preload:1;
98 };
99
100 #define DISPC_MAX_NR_FIFOS 5
101
102 static struct {
103 struct platform_device *pdev;
104 void __iomem *base;
105
106 int irq;
107 irq_handler_t user_handler;
108 void *user_data;
109
110 unsigned long core_clk_rate;
111 unsigned long tv_pclk_rate;
112
113 u32 fifo_size[DISPC_MAX_NR_FIFOS];
114 /* maps which plane is using a fifo. fifo-id -> plane-id */
115 int fifo_assignment[DISPC_MAX_NR_FIFOS];
116
117 bool ctx_valid;
118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
119
120 const struct dispc_features *feat;
121
122 bool is_enabled;
123
124 struct regmap *syscon_pol;
125 u32 syscon_pol_offset;
126 } dispc;
127
128 enum omap_color_component {
129 /* used for all color formats for OMAP3 and earlier
130 * and for RGB and Y color component on OMAP4
131 */
132 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
133 /* used for UV component for
134 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
135 * color formats on OMAP4
136 */
137 DISPC_COLOR_COMPONENT_UV = 1 << 1,
138 };
139
140 enum mgr_reg_fields {
141 DISPC_MGR_FLD_ENABLE,
142 DISPC_MGR_FLD_STNTFT,
143 DISPC_MGR_FLD_GO,
144 DISPC_MGR_FLD_TFTDATALINES,
145 DISPC_MGR_FLD_STALLMODE,
146 DISPC_MGR_FLD_TCKENABLE,
147 DISPC_MGR_FLD_TCKSELECTION,
148 DISPC_MGR_FLD_CPR,
149 DISPC_MGR_FLD_FIFOHANDCHECK,
150 /* used to maintain a count of the above fields */
151 DISPC_MGR_FLD_NUM,
152 };
153
154 struct dispc_reg_field {
155 u16 reg;
156 u8 high;
157 u8 low;
158 };
159
160 static const struct {
161 const char *name;
162 u32 vsync_irq;
163 u32 framedone_irq;
164 u32 sync_lost_irq;
165 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
166 } mgr_desc[] = {
167 [OMAP_DSS_CHANNEL_LCD] = {
168 .name = "LCD",
169 .vsync_irq = DISPC_IRQ_VSYNC,
170 .framedone_irq = DISPC_IRQ_FRAMEDONE,
171 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
172 .reg_desc = {
173 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
174 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
175 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
176 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
177 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
178 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
179 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
180 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
181 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
182 },
183 },
184 [OMAP_DSS_CHANNEL_DIGIT] = {
185 .name = "DIGIT",
186 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
187 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
188 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
189 .reg_desc = {
190 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
191 [DISPC_MGR_FLD_STNTFT] = { },
192 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
193 [DISPC_MGR_FLD_TFTDATALINES] = { },
194 [DISPC_MGR_FLD_STALLMODE] = { },
195 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
196 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
197 [DISPC_MGR_FLD_CPR] = { },
198 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
199 },
200 },
201 [OMAP_DSS_CHANNEL_LCD2] = {
202 .name = "LCD2",
203 .vsync_irq = DISPC_IRQ_VSYNC2,
204 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
205 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
206 .reg_desc = {
207 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
208 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
209 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
210 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
211 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
212 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
213 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
214 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
215 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
216 },
217 },
218 [OMAP_DSS_CHANNEL_LCD3] = {
219 .name = "LCD3",
220 .vsync_irq = DISPC_IRQ_VSYNC3,
221 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
222 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
223 .reg_desc = {
224 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
225 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
226 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
227 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
228 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
229 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
230 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
231 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
232 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
233 },
234 },
235 };
236
237 struct color_conv_coef {
238 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
239 int full_range;
240 };
241
242 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
243 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
244
245 static inline void dispc_write_reg(const u16 idx, u32 val)
246 {
247 __raw_writel(val, dispc.base + idx);
248 }
249
250 static inline u32 dispc_read_reg(const u16 idx)
251 {
252 return __raw_readl(dispc.base + idx);
253 }
254
255 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
256 {
257 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
258 return REG_GET(rfld.reg, rfld.high, rfld.low);
259 }
260
261 static void mgr_fld_write(enum omap_channel channel,
262 enum mgr_reg_fields regfld, int val) {
263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
264 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
265 }
266
267 #define SR(reg) \
268 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
269 #define RR(reg) \
270 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
271
272 static void dispc_save_context(void)
273 {
274 int i, j;
275
276 DSSDBG("dispc_save_context\n");
277
278 SR(IRQENABLE);
279 SR(CONTROL);
280 SR(CONFIG);
281 SR(LINE_NUMBER);
282 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
283 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
284 SR(GLOBAL_ALPHA);
285 if (dss_has_feature(FEAT_MGR_LCD2)) {
286 SR(CONTROL2);
287 SR(CONFIG2);
288 }
289 if (dss_has_feature(FEAT_MGR_LCD3)) {
290 SR(CONTROL3);
291 SR(CONFIG3);
292 }
293
294 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
295 SR(DEFAULT_COLOR(i));
296 SR(TRANS_COLOR(i));
297 SR(SIZE_MGR(i));
298 if (i == OMAP_DSS_CHANNEL_DIGIT)
299 continue;
300 SR(TIMING_H(i));
301 SR(TIMING_V(i));
302 SR(POL_FREQ(i));
303 SR(DIVISORo(i));
304
305 SR(DATA_CYCLE1(i));
306 SR(DATA_CYCLE2(i));
307 SR(DATA_CYCLE3(i));
308
309 if (dss_has_feature(FEAT_CPR)) {
310 SR(CPR_COEF_R(i));
311 SR(CPR_COEF_G(i));
312 SR(CPR_COEF_B(i));
313 }
314 }
315
316 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
317 SR(OVL_BA0(i));
318 SR(OVL_BA1(i));
319 SR(OVL_POSITION(i));
320 SR(OVL_SIZE(i));
321 SR(OVL_ATTRIBUTES(i));
322 SR(OVL_FIFO_THRESHOLD(i));
323 SR(OVL_ROW_INC(i));
324 SR(OVL_PIXEL_INC(i));
325 if (dss_has_feature(FEAT_PRELOAD))
326 SR(OVL_PRELOAD(i));
327 if (i == OMAP_DSS_GFX) {
328 SR(OVL_WINDOW_SKIP(i));
329 SR(OVL_TABLE_BA(i));
330 continue;
331 }
332 SR(OVL_FIR(i));
333 SR(OVL_PICTURE_SIZE(i));
334 SR(OVL_ACCU0(i));
335 SR(OVL_ACCU1(i));
336
337 for (j = 0; j < 8; j++)
338 SR(OVL_FIR_COEF_H(i, j));
339
340 for (j = 0; j < 8; j++)
341 SR(OVL_FIR_COEF_HV(i, j));
342
343 for (j = 0; j < 5; j++)
344 SR(OVL_CONV_COEF(i, j));
345
346 if (dss_has_feature(FEAT_FIR_COEF_V)) {
347 for (j = 0; j < 8; j++)
348 SR(OVL_FIR_COEF_V(i, j));
349 }
350
351 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
352 SR(OVL_BA0_UV(i));
353 SR(OVL_BA1_UV(i));
354 SR(OVL_FIR2(i));
355 SR(OVL_ACCU2_0(i));
356 SR(OVL_ACCU2_1(i));
357
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_H2(i, j));
360
361 for (j = 0; j < 8; j++)
362 SR(OVL_FIR_COEF_HV2(i, j));
363
364 for (j = 0; j < 8; j++)
365 SR(OVL_FIR_COEF_V2(i, j));
366 }
367 if (dss_has_feature(FEAT_ATTR2))
368 SR(OVL_ATTRIBUTES2(i));
369 }
370
371 if (dss_has_feature(FEAT_CORE_CLK_DIV))
372 SR(DIVISOR);
373
374 dispc.ctx_valid = true;
375
376 DSSDBG("context saved\n");
377 }
378
379 static void dispc_restore_context(void)
380 {
381 int i, j;
382
383 DSSDBG("dispc_restore_context\n");
384
385 if (!dispc.ctx_valid)
386 return;
387
388 /*RR(IRQENABLE);*/
389 /*RR(CONTROL);*/
390 RR(CONFIG);
391 RR(LINE_NUMBER);
392 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
393 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
394 RR(GLOBAL_ALPHA);
395 if (dss_has_feature(FEAT_MGR_LCD2))
396 RR(CONFIG2);
397 if (dss_has_feature(FEAT_MGR_LCD3))
398 RR(CONFIG3);
399
400 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
401 RR(DEFAULT_COLOR(i));
402 RR(TRANS_COLOR(i));
403 RR(SIZE_MGR(i));
404 if (i == OMAP_DSS_CHANNEL_DIGIT)
405 continue;
406 RR(TIMING_H(i));
407 RR(TIMING_V(i));
408 RR(POL_FREQ(i));
409 RR(DIVISORo(i));
410
411 RR(DATA_CYCLE1(i));
412 RR(DATA_CYCLE2(i));
413 RR(DATA_CYCLE3(i));
414
415 if (dss_has_feature(FEAT_CPR)) {
416 RR(CPR_COEF_R(i));
417 RR(CPR_COEF_G(i));
418 RR(CPR_COEF_B(i));
419 }
420 }
421
422 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
423 RR(OVL_BA0(i));
424 RR(OVL_BA1(i));
425 RR(OVL_POSITION(i));
426 RR(OVL_SIZE(i));
427 RR(OVL_ATTRIBUTES(i));
428 RR(OVL_FIFO_THRESHOLD(i));
429 RR(OVL_ROW_INC(i));
430 RR(OVL_PIXEL_INC(i));
431 if (dss_has_feature(FEAT_PRELOAD))
432 RR(OVL_PRELOAD(i));
433 if (i == OMAP_DSS_GFX) {
434 RR(OVL_WINDOW_SKIP(i));
435 RR(OVL_TABLE_BA(i));
436 continue;
437 }
438 RR(OVL_FIR(i));
439 RR(OVL_PICTURE_SIZE(i));
440 RR(OVL_ACCU0(i));
441 RR(OVL_ACCU1(i));
442
443 for (j = 0; j < 8; j++)
444 RR(OVL_FIR_COEF_H(i, j));
445
446 for (j = 0; j < 8; j++)
447 RR(OVL_FIR_COEF_HV(i, j));
448
449 for (j = 0; j < 5; j++)
450 RR(OVL_CONV_COEF(i, j));
451
452 if (dss_has_feature(FEAT_FIR_COEF_V)) {
453 for (j = 0; j < 8; j++)
454 RR(OVL_FIR_COEF_V(i, j));
455 }
456
457 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
458 RR(OVL_BA0_UV(i));
459 RR(OVL_BA1_UV(i));
460 RR(OVL_FIR2(i));
461 RR(OVL_ACCU2_0(i));
462 RR(OVL_ACCU2_1(i));
463
464 for (j = 0; j < 8; j++)
465 RR(OVL_FIR_COEF_H2(i, j));
466
467 for (j = 0; j < 8; j++)
468 RR(OVL_FIR_COEF_HV2(i, j));
469
470 for (j = 0; j < 8; j++)
471 RR(OVL_FIR_COEF_V2(i, j));
472 }
473 if (dss_has_feature(FEAT_ATTR2))
474 RR(OVL_ATTRIBUTES2(i));
475 }
476
477 if (dss_has_feature(FEAT_CORE_CLK_DIV))
478 RR(DIVISOR);
479
480 /* enable last, because LCD & DIGIT enable are here */
481 RR(CONTROL);
482 if (dss_has_feature(FEAT_MGR_LCD2))
483 RR(CONTROL2);
484 if (dss_has_feature(FEAT_MGR_LCD3))
485 RR(CONTROL3);
486 /* clear spurious SYNC_LOST_DIGIT interrupts */
487 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
488
489 /*
490 * enable last so IRQs won't trigger before
491 * the context is fully restored
492 */
493 RR(IRQENABLE);
494
495 DSSDBG("context restored\n");
496 }
497
498 #undef SR
499 #undef RR
500
501 int dispc_runtime_get(void)
502 {
503 int r;
504
505 DSSDBG("dispc_runtime_get\n");
506
507 r = pm_runtime_get_sync(&dispc.pdev->dev);
508 WARN_ON(r < 0);
509 return r < 0 ? r : 0;
510 }
511 EXPORT_SYMBOL(dispc_runtime_get);
512
513 void dispc_runtime_put(void)
514 {
515 int r;
516
517 DSSDBG("dispc_runtime_put\n");
518
519 r = pm_runtime_put_sync(&dispc.pdev->dev);
520 WARN_ON(r < 0 && r != -ENOSYS);
521 }
522 EXPORT_SYMBOL(dispc_runtime_put);
523
524 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
525 {
526 return mgr_desc[channel].vsync_irq;
527 }
528 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
529
530 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
531 {
532 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
533 return 0;
534
535 return mgr_desc[channel].framedone_irq;
536 }
537 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
538
539 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
540 {
541 return mgr_desc[channel].sync_lost_irq;
542 }
543 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
544
545 u32 dispc_wb_get_framedone_irq(void)
546 {
547 return DISPC_IRQ_FRAMEDONEWB;
548 }
549
550 bool dispc_mgr_go_busy(enum omap_channel channel)
551 {
552 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
553 }
554 EXPORT_SYMBOL(dispc_mgr_go_busy);
555
556 void dispc_mgr_go(enum omap_channel channel)
557 {
558 WARN_ON(dispc_mgr_is_enabled(channel) == false);
559 WARN_ON(dispc_mgr_go_busy(channel));
560
561 DSSDBG("GO %s\n", mgr_desc[channel].name);
562
563 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
564 }
565 EXPORT_SYMBOL(dispc_mgr_go);
566
567 bool dispc_wb_go_busy(void)
568 {
569 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
570 }
571
572 void dispc_wb_go(void)
573 {
574 enum omap_plane plane = OMAP_DSS_WB;
575 bool enable, go;
576
577 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
578
579 if (!enable)
580 return;
581
582 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583 if (go) {
584 DSSERR("GO bit not down for WB\n");
585 return;
586 }
587
588 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
589 }
590
591 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
592 {
593 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
594 }
595
596 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
597 {
598 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
599 }
600
601 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
602 {
603 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
604 }
605
606 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
607 {
608 BUG_ON(plane == OMAP_DSS_GFX);
609
610 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
611 }
612
613 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
614 u32 value)
615 {
616 BUG_ON(plane == OMAP_DSS_GFX);
617
618 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
619 }
620
621 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
622 {
623 BUG_ON(plane == OMAP_DSS_GFX);
624
625 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
626 }
627
628 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
629 int fir_vinc, int five_taps,
630 enum omap_color_component color_comp)
631 {
632 const struct dispc_coef *h_coef, *v_coef;
633 int i;
634
635 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
636 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
637
638 for (i = 0; i < 8; i++) {
639 u32 h, hv;
640
641 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
642 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
643 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
644 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
645 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
646 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
647 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
648 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
649
650 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
651 dispc_ovl_write_firh_reg(plane, i, h);
652 dispc_ovl_write_firhv_reg(plane, i, hv);
653 } else {
654 dispc_ovl_write_firh2_reg(plane, i, h);
655 dispc_ovl_write_firhv2_reg(plane, i, hv);
656 }
657
658 }
659
660 if (five_taps) {
661 for (i = 0; i < 8; i++) {
662 u32 v;
663 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
664 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
665 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
666 dispc_ovl_write_firv_reg(plane, i, v);
667 else
668 dispc_ovl_write_firv2_reg(plane, i, v);
669 }
670 }
671 }
672
673
674 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
675 const struct color_conv_coef *ct)
676 {
677 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
678
679 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
681 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
683 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
684
685 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
686
687 #undef CVAL
688 }
689
690 static void dispc_setup_color_conv_coef(void)
691 {
692 int i;
693 int num_ovl = dss_feat_get_num_ovls();
694 int num_wb = dss_feat_get_num_wbs();
695 const struct color_conv_coef ctbl_bt601_5_ovl = {
696 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
697 };
698 const struct color_conv_coef ctbl_bt601_5_wb = {
699 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
700 };
701
702 for (i = 1; i < num_ovl; i++)
703 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
704
705 for (; i < num_wb; i++)
706 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
707 }
708
709 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
710 {
711 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
712 }
713
714 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
715 {
716 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
717 }
718
719 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
720 {
721 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
722 }
723
724 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
725 {
726 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
727 }
728
729 static void dispc_ovl_set_pos(enum omap_plane plane,
730 enum omap_overlay_caps caps, int x, int y)
731 {
732 u32 val;
733
734 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
735 return;
736
737 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
738
739 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
740 }
741
742 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
743 int height)
744 {
745 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
746
747 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
748 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
749 else
750 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
751 }
752
753 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
754 int height)
755 {
756 u32 val;
757
758 BUG_ON(plane == OMAP_DSS_GFX);
759
760 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
761
762 if (plane == OMAP_DSS_WB)
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
764 else
765 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
766 }
767
768 static void dispc_ovl_set_zorder(enum omap_plane plane,
769 enum omap_overlay_caps caps, u8 zorder)
770 {
771 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
772 return;
773
774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
775 }
776
777 static void dispc_ovl_enable_zorder_planes(void)
778 {
779 int i;
780
781 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
782 return;
783
784 for (i = 0; i < dss_feat_get_num_ovls(); i++)
785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
786 }
787
788 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
789 enum omap_overlay_caps caps, bool enable)
790 {
791 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
792 return;
793
794 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
795 }
796
797 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
798 enum omap_overlay_caps caps, u8 global_alpha)
799 {
800 static const unsigned shifts[] = { 0, 8, 16, 24, };
801 int shift;
802
803 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
804 return;
805
806 shift = shifts[plane];
807 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
808 }
809
810 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
811 {
812 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
813 }
814
815 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
816 {
817 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
818 }
819
820 static void dispc_ovl_set_color_mode(enum omap_plane plane,
821 enum omap_color_mode color_mode)
822 {
823 u32 m = 0;
824 if (plane != OMAP_DSS_GFX) {
825 switch (color_mode) {
826 case OMAP_DSS_COLOR_NV12:
827 m = 0x0; break;
828 case OMAP_DSS_COLOR_RGBX16:
829 m = 0x1; break;
830 case OMAP_DSS_COLOR_RGBA16:
831 m = 0x2; break;
832 case OMAP_DSS_COLOR_RGB12U:
833 m = 0x4; break;
834 case OMAP_DSS_COLOR_ARGB16:
835 m = 0x5; break;
836 case OMAP_DSS_COLOR_RGB16:
837 m = 0x6; break;
838 case OMAP_DSS_COLOR_ARGB16_1555:
839 m = 0x7; break;
840 case OMAP_DSS_COLOR_RGB24U:
841 m = 0x8; break;
842 case OMAP_DSS_COLOR_RGB24P:
843 m = 0x9; break;
844 case OMAP_DSS_COLOR_YUV2:
845 m = 0xa; break;
846 case OMAP_DSS_COLOR_UYVY:
847 m = 0xb; break;
848 case OMAP_DSS_COLOR_ARGB32:
849 m = 0xc; break;
850 case OMAP_DSS_COLOR_RGBA32:
851 m = 0xd; break;
852 case OMAP_DSS_COLOR_RGBX32:
853 m = 0xe; break;
854 case OMAP_DSS_COLOR_XRGB16_1555:
855 m = 0xf; break;
856 default:
857 BUG(); return;
858 }
859 } else {
860 switch (color_mode) {
861 case OMAP_DSS_COLOR_CLUT1:
862 m = 0x0; break;
863 case OMAP_DSS_COLOR_CLUT2:
864 m = 0x1; break;
865 case OMAP_DSS_COLOR_CLUT4:
866 m = 0x2; break;
867 case OMAP_DSS_COLOR_CLUT8:
868 m = 0x3; break;
869 case OMAP_DSS_COLOR_RGB12U:
870 m = 0x4; break;
871 case OMAP_DSS_COLOR_ARGB16:
872 m = 0x5; break;
873 case OMAP_DSS_COLOR_RGB16:
874 m = 0x6; break;
875 case OMAP_DSS_COLOR_ARGB16_1555:
876 m = 0x7; break;
877 case OMAP_DSS_COLOR_RGB24U:
878 m = 0x8; break;
879 case OMAP_DSS_COLOR_RGB24P:
880 m = 0x9; break;
881 case OMAP_DSS_COLOR_RGBX16:
882 m = 0xa; break;
883 case OMAP_DSS_COLOR_RGBA16:
884 m = 0xb; break;
885 case OMAP_DSS_COLOR_ARGB32:
886 m = 0xc; break;
887 case OMAP_DSS_COLOR_RGBA32:
888 m = 0xd; break;
889 case OMAP_DSS_COLOR_RGBX32:
890 m = 0xe; break;
891 case OMAP_DSS_COLOR_XRGB16_1555:
892 m = 0xf; break;
893 default:
894 BUG(); return;
895 }
896 }
897
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
899 }
900
901 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
902 enum omap_dss_rotation_type rotation_type)
903 {
904 if (dss_has_feature(FEAT_BURST_2D) == 0)
905 return;
906
907 if (rotation_type == OMAP_DSS_ROT_TILER)
908 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
909 else
910 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
911 }
912
913 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
914 {
915 int shift;
916 u32 val;
917 int chan = 0, chan2 = 0;
918
919 switch (plane) {
920 case OMAP_DSS_GFX:
921 shift = 8;
922 break;
923 case OMAP_DSS_VIDEO1:
924 case OMAP_DSS_VIDEO2:
925 case OMAP_DSS_VIDEO3:
926 shift = 16;
927 break;
928 default:
929 BUG();
930 return;
931 }
932
933 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
934 if (dss_has_feature(FEAT_MGR_LCD2)) {
935 switch (channel) {
936 case OMAP_DSS_CHANNEL_LCD:
937 chan = 0;
938 chan2 = 0;
939 break;
940 case OMAP_DSS_CHANNEL_DIGIT:
941 chan = 1;
942 chan2 = 0;
943 break;
944 case OMAP_DSS_CHANNEL_LCD2:
945 chan = 0;
946 chan2 = 1;
947 break;
948 case OMAP_DSS_CHANNEL_LCD3:
949 if (dss_has_feature(FEAT_MGR_LCD3)) {
950 chan = 0;
951 chan2 = 2;
952 } else {
953 BUG();
954 return;
955 }
956 break;
957 default:
958 BUG();
959 return;
960 }
961
962 val = FLD_MOD(val, chan, shift, shift);
963 val = FLD_MOD(val, chan2, 31, 30);
964 } else {
965 val = FLD_MOD(val, channel, shift, shift);
966 }
967 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
968 }
969 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
970
971 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
972 {
973 int shift;
974 u32 val;
975 enum omap_channel channel;
976
977 switch (plane) {
978 case OMAP_DSS_GFX:
979 shift = 8;
980 break;
981 case OMAP_DSS_VIDEO1:
982 case OMAP_DSS_VIDEO2:
983 case OMAP_DSS_VIDEO3:
984 shift = 16;
985 break;
986 default:
987 BUG();
988 return 0;
989 }
990
991 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
992
993 if (dss_has_feature(FEAT_MGR_LCD3)) {
994 if (FLD_GET(val, 31, 30) == 0)
995 channel = FLD_GET(val, shift, shift);
996 else if (FLD_GET(val, 31, 30) == 1)
997 channel = OMAP_DSS_CHANNEL_LCD2;
998 else
999 channel = OMAP_DSS_CHANNEL_LCD3;
1000 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
1001 if (FLD_GET(val, 31, 30) == 0)
1002 channel = FLD_GET(val, shift, shift);
1003 else
1004 channel = OMAP_DSS_CHANNEL_LCD2;
1005 } else {
1006 channel = FLD_GET(val, shift, shift);
1007 }
1008
1009 return channel;
1010 }
1011
1012 void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1013 {
1014 enum omap_plane plane = OMAP_DSS_WB;
1015
1016 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1017 }
1018
1019 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1020 enum omap_burst_size burst_size)
1021 {
1022 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1023 int shift;
1024
1025 shift = shifts[plane];
1026 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1027 }
1028
1029 static void dispc_configure_burst_sizes(void)
1030 {
1031 int i;
1032 const int burst_size = BURST_SIZE_X8;
1033
1034 /* Configure burst size always to maximum size */
1035 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1036 dispc_ovl_set_burst_size(i, burst_size);
1037 }
1038
1039 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1040 {
1041 unsigned unit = dss_feat_get_burst_size_unit();
1042 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1043 return unit * 8;
1044 }
1045
1046 void dispc_enable_gamma_table(bool enable)
1047 {
1048 /*
1049 * This is partially implemented to support only disabling of
1050 * the gamma table.
1051 */
1052 if (enable) {
1053 DSSWARN("Gamma table enabling for TV not yet supported");
1054 return;
1055 }
1056
1057 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1058 }
1059
1060 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1061 {
1062 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1063 return;
1064
1065 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1066 }
1067
1068 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1069 const struct omap_dss_cpr_coefs *coefs)
1070 {
1071 u32 coef_r, coef_g, coef_b;
1072
1073 if (!dss_mgr_is_lcd(channel))
1074 return;
1075
1076 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1077 FLD_VAL(coefs->rb, 9, 0);
1078 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1079 FLD_VAL(coefs->gb, 9, 0);
1080 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1081 FLD_VAL(coefs->bb, 9, 0);
1082
1083 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1084 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1085 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1086 }
1087
1088 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1089 {
1090 u32 val;
1091
1092 BUG_ON(plane == OMAP_DSS_GFX);
1093
1094 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1095 val = FLD_MOD(val, enable, 9, 9);
1096 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1097 }
1098
1099 static void dispc_ovl_enable_replication(enum omap_plane plane,
1100 enum omap_overlay_caps caps, bool enable)
1101 {
1102 static const unsigned shifts[] = { 5, 10, 10, 10 };
1103 int shift;
1104
1105 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1106 return;
1107
1108 shift = shifts[plane];
1109 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1110 }
1111
1112 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1113 u16 height)
1114 {
1115 u32 val;
1116
1117 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1118 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1119
1120 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1121 }
1122
1123 static void dispc_init_fifos(void)
1124 {
1125 u32 size;
1126 int fifo;
1127 u8 start, end;
1128 u32 unit;
1129
1130 unit = dss_feat_get_buffer_size_unit();
1131
1132 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1133
1134 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1135 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1136 size *= unit;
1137 dispc.fifo_size[fifo] = size;
1138
1139 /*
1140 * By default fifos are mapped directly to overlays, fifo 0 to
1141 * ovl 0, fifo 1 to ovl 1, etc.
1142 */
1143 dispc.fifo_assignment[fifo] = fifo;
1144 }
1145
1146 /*
1147 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1148 * causes problems with certain use cases, like using the tiler in 2D
1149 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1150 * giving GFX plane a larger fifo. WB but should work fine with a
1151 * smaller fifo.
1152 */
1153 if (dispc.feat->gfx_fifo_workaround) {
1154 u32 v;
1155
1156 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1157
1158 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1159 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1160 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1161 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1162
1163 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1164
1165 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1166 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1167 }
1168 }
1169
1170 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1171 {
1172 int fifo;
1173 u32 size = 0;
1174
1175 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1176 if (dispc.fifo_assignment[fifo] == plane)
1177 size += dispc.fifo_size[fifo];
1178 }
1179
1180 return size;
1181 }
1182
1183 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1184 {
1185 u8 hi_start, hi_end, lo_start, lo_end;
1186 u32 unit;
1187
1188 unit = dss_feat_get_buffer_size_unit();
1189
1190 WARN_ON(low % unit != 0);
1191 WARN_ON(high % unit != 0);
1192
1193 low /= unit;
1194 high /= unit;
1195
1196 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1197 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1198
1199 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1200 plane,
1201 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1202 lo_start, lo_end) * unit,
1203 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1204 hi_start, hi_end) * unit,
1205 low * unit, high * unit);
1206
1207 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1208 FLD_VAL(high, hi_start, hi_end) |
1209 FLD_VAL(low, lo_start, lo_end));
1210
1211 /*
1212 * configure the preload to the pipeline's high threhold, if HT it's too
1213 * large for the preload field, set the threshold to the maximum value
1214 * that can be held by the preload register
1215 */
1216 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1217 plane != OMAP_DSS_WB)
1218 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1219 }
1220 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
1221
1222 void dispc_enable_fifomerge(bool enable)
1223 {
1224 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1225 WARN_ON(enable);
1226 return;
1227 }
1228
1229 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1230 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1231 }
1232
1233 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1234 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1235 bool manual_update)
1236 {
1237 /*
1238 * All sizes are in bytes. Both the buffer and burst are made of
1239 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1240 */
1241
1242 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1243 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1244 int i;
1245
1246 burst_size = dispc_ovl_get_burst_size(plane);
1247 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1248
1249 if (use_fifomerge) {
1250 total_fifo_size = 0;
1251 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1252 total_fifo_size += dispc_ovl_get_fifo_size(i);
1253 } else {
1254 total_fifo_size = ovl_fifo_size;
1255 }
1256
1257 /*
1258 * We use the same low threshold for both fifomerge and non-fifomerge
1259 * cases, but for fifomerge we calculate the high threshold using the
1260 * combined fifo size
1261 */
1262
1263 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1264 *fifo_low = ovl_fifo_size - burst_size * 2;
1265 *fifo_high = total_fifo_size - burst_size;
1266 } else if (plane == OMAP_DSS_WB) {
1267 /*
1268 * Most optimal configuration for writeback is to push out data
1269 * to the interconnect the moment writeback pushes enough pixels
1270 * in the FIFO to form a burst
1271 */
1272 *fifo_low = 0;
1273 *fifo_high = burst_size;
1274 } else {
1275 *fifo_low = ovl_fifo_size - burst_size;
1276 *fifo_high = total_fifo_size - buf_unit;
1277 }
1278 }
1279 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
1280
1281 static void dispc_ovl_set_fir(enum omap_plane plane,
1282 int hinc, int vinc,
1283 enum omap_color_component color_comp)
1284 {
1285 u32 val;
1286
1287 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1288 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1289
1290 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1291 &hinc_start, &hinc_end);
1292 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1293 &vinc_start, &vinc_end);
1294 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1295 FLD_VAL(hinc, hinc_start, hinc_end);
1296
1297 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1298 } else {
1299 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1300 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1301 }
1302 }
1303
1304 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1305 {
1306 u32 val;
1307 u8 hor_start, hor_end, vert_start, vert_end;
1308
1309 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1310 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1311
1312 val = FLD_VAL(vaccu, vert_start, vert_end) |
1313 FLD_VAL(haccu, hor_start, hor_end);
1314
1315 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1316 }
1317
1318 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1319 {
1320 u32 val;
1321 u8 hor_start, hor_end, vert_start, vert_end;
1322
1323 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1324 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1325
1326 val = FLD_VAL(vaccu, vert_start, vert_end) |
1327 FLD_VAL(haccu, hor_start, hor_end);
1328
1329 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1330 }
1331
1332 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1333 int vaccu)
1334 {
1335 u32 val;
1336
1337 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1338 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1339 }
1340
1341 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1342 int vaccu)
1343 {
1344 u32 val;
1345
1346 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1347 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1348 }
1349
1350 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1351 u16 orig_width, u16 orig_height,
1352 u16 out_width, u16 out_height,
1353 bool five_taps, u8 rotation,
1354 enum omap_color_component color_comp)
1355 {
1356 int fir_hinc, fir_vinc;
1357
1358 fir_hinc = 1024 * orig_width / out_width;
1359 fir_vinc = 1024 * orig_height / out_height;
1360
1361 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1362 color_comp);
1363 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1364 }
1365
1366 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1367 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1368 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1369 {
1370 int h_accu2_0, h_accu2_1;
1371 int v_accu2_0, v_accu2_1;
1372 int chroma_hinc, chroma_vinc;
1373 int idx;
1374
1375 struct accu {
1376 s8 h0_m, h0_n;
1377 s8 h1_m, h1_n;
1378 s8 v0_m, v0_n;
1379 s8 v1_m, v1_n;
1380 };
1381
1382 const struct accu *accu_table;
1383 const struct accu *accu_val;
1384
1385 static const struct accu accu_nv12[4] = {
1386 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1387 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1388 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1389 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1390 };
1391
1392 static const struct accu accu_nv12_ilace[4] = {
1393 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1394 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1395 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1396 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1397 };
1398
1399 static const struct accu accu_yuv[4] = {
1400 { 0, 1, 0, 1, 0, 1, 0, 1 },
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { -1, 1, 0, 1, 0, 1, 0, 1 },
1403 { 0, 1, 0, 1, -1, 1, 0, 1 },
1404 };
1405
1406 switch (rotation) {
1407 case OMAP_DSS_ROT_0:
1408 idx = 0;
1409 break;
1410 case OMAP_DSS_ROT_90:
1411 idx = 1;
1412 break;
1413 case OMAP_DSS_ROT_180:
1414 idx = 2;
1415 break;
1416 case OMAP_DSS_ROT_270:
1417 idx = 3;
1418 break;
1419 default:
1420 BUG();
1421 return;
1422 }
1423
1424 switch (color_mode) {
1425 case OMAP_DSS_COLOR_NV12:
1426 if (ilace)
1427 accu_table = accu_nv12_ilace;
1428 else
1429 accu_table = accu_nv12;
1430 break;
1431 case OMAP_DSS_COLOR_YUV2:
1432 case OMAP_DSS_COLOR_UYVY:
1433 accu_table = accu_yuv;
1434 break;
1435 default:
1436 BUG();
1437 return;
1438 }
1439
1440 accu_val = &accu_table[idx];
1441
1442 chroma_hinc = 1024 * orig_width / out_width;
1443 chroma_vinc = 1024 * orig_height / out_height;
1444
1445 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1446 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1447 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1448 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1449
1450 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1451 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1452 }
1453
1454 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1455 u16 orig_width, u16 orig_height,
1456 u16 out_width, u16 out_height,
1457 bool ilace, bool five_taps,
1458 bool fieldmode, enum omap_color_mode color_mode,
1459 u8 rotation)
1460 {
1461 int accu0 = 0;
1462 int accu1 = 0;
1463 u32 l;
1464
1465 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1466 out_width, out_height, five_taps,
1467 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1468 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1469
1470 /* RESIZEENABLE and VERTICALTAPS */
1471 l &= ~((0x3 << 5) | (0x1 << 21));
1472 l |= (orig_width != out_width) ? (1 << 5) : 0;
1473 l |= (orig_height != out_height) ? (1 << 6) : 0;
1474 l |= five_taps ? (1 << 21) : 0;
1475
1476 /* VRESIZECONF and HRESIZECONF */
1477 if (dss_has_feature(FEAT_RESIZECONF)) {
1478 l &= ~(0x3 << 7);
1479 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1480 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1481 }
1482
1483 /* LINEBUFFERSPLIT */
1484 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1485 l &= ~(0x1 << 22);
1486 l |= five_taps ? (1 << 22) : 0;
1487 }
1488
1489 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1490
1491 /*
1492 * field 0 = even field = bottom field
1493 * field 1 = odd field = top field
1494 */
1495 if (ilace && !fieldmode) {
1496 accu1 = 0;
1497 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1498 if (accu0 >= 1024/2) {
1499 accu1 = 1024/2;
1500 accu0 -= accu1;
1501 }
1502 }
1503
1504 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1505 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1506 }
1507
1508 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1509 u16 orig_width, u16 orig_height,
1510 u16 out_width, u16 out_height,
1511 bool ilace, bool five_taps,
1512 bool fieldmode, enum omap_color_mode color_mode,
1513 u8 rotation)
1514 {
1515 int scale_x = out_width != orig_width;
1516 int scale_y = out_height != orig_height;
1517 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1518
1519 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1520 return;
1521 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1522 color_mode != OMAP_DSS_COLOR_UYVY &&
1523 color_mode != OMAP_DSS_COLOR_NV12)) {
1524 /* reset chroma resampling for RGB formats */
1525 if (plane != OMAP_DSS_WB)
1526 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1527 return;
1528 }
1529
1530 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1531 out_height, ilace, color_mode, rotation);
1532
1533 switch (color_mode) {
1534 case OMAP_DSS_COLOR_NV12:
1535 if (chroma_upscale) {
1536 /* UV is subsampled by 2 horizontally and vertically */
1537 orig_height >>= 1;
1538 orig_width >>= 1;
1539 } else {
1540 /* UV is downsampled by 2 horizontally and vertically */
1541 orig_height <<= 1;
1542 orig_width <<= 1;
1543 }
1544
1545 break;
1546 case OMAP_DSS_COLOR_YUV2:
1547 case OMAP_DSS_COLOR_UYVY:
1548 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1549 if (rotation == OMAP_DSS_ROT_0 ||
1550 rotation == OMAP_DSS_ROT_180) {
1551 if (chroma_upscale)
1552 /* UV is subsampled by 2 horizontally */
1553 orig_width >>= 1;
1554 else
1555 /* UV is downsampled by 2 horizontally */
1556 orig_width <<= 1;
1557 }
1558
1559 /* must use FIR for YUV422 if rotated */
1560 if (rotation != OMAP_DSS_ROT_0)
1561 scale_x = scale_y = true;
1562
1563 break;
1564 default:
1565 BUG();
1566 return;
1567 }
1568
1569 if (out_width != orig_width)
1570 scale_x = true;
1571 if (out_height != orig_height)
1572 scale_y = true;
1573
1574 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1575 out_width, out_height, five_taps,
1576 rotation, DISPC_COLOR_COMPONENT_UV);
1577
1578 if (plane != OMAP_DSS_WB)
1579 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1580 (scale_x || scale_y) ? 1 : 0, 8, 8);
1581
1582 /* set H scaling */
1583 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1584 /* set V scaling */
1585 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1586 }
1587
1588 static void dispc_ovl_set_scaling(enum omap_plane plane,
1589 u16 orig_width, u16 orig_height,
1590 u16 out_width, u16 out_height,
1591 bool ilace, bool five_taps,
1592 bool fieldmode, enum omap_color_mode color_mode,
1593 u8 rotation)
1594 {
1595 BUG_ON(plane == OMAP_DSS_GFX);
1596
1597 dispc_ovl_set_scaling_common(plane,
1598 orig_width, orig_height,
1599 out_width, out_height,
1600 ilace, five_taps,
1601 fieldmode, color_mode,
1602 rotation);
1603
1604 dispc_ovl_set_scaling_uv(plane,
1605 orig_width, orig_height,
1606 out_width, out_height,
1607 ilace, five_taps,
1608 fieldmode, color_mode,
1609 rotation);
1610 }
1611
1612 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1613 enum omap_dss_rotation_type rotation_type,
1614 bool mirroring, enum omap_color_mode color_mode)
1615 {
1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1655 row_repeat = true;
1656 else
1657 row_repeat = false;
1658 }
1659
1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
1664
1665 if (color_mode == OMAP_DSS_COLOR_NV12) {
1666 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1667 (rotation == OMAP_DSS_ROT_0 ||
1668 rotation == OMAP_DSS_ROT_180);
1669 /* DOUBLESTRIDE */
1670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1671 }
1672
1673 }
1674
1675 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1676 {
1677 switch (color_mode) {
1678 case OMAP_DSS_COLOR_CLUT1:
1679 return 1;
1680 case OMAP_DSS_COLOR_CLUT2:
1681 return 2;
1682 case OMAP_DSS_COLOR_CLUT4:
1683 return 4;
1684 case OMAP_DSS_COLOR_CLUT8:
1685 case OMAP_DSS_COLOR_NV12:
1686 return 8;
1687 case OMAP_DSS_COLOR_RGB12U:
1688 case OMAP_DSS_COLOR_RGB16:
1689 case OMAP_DSS_COLOR_ARGB16:
1690 case OMAP_DSS_COLOR_YUV2:
1691 case OMAP_DSS_COLOR_UYVY:
1692 case OMAP_DSS_COLOR_RGBA16:
1693 case OMAP_DSS_COLOR_RGBX16:
1694 case OMAP_DSS_COLOR_ARGB16_1555:
1695 case OMAP_DSS_COLOR_XRGB16_1555:
1696 return 16;
1697 case OMAP_DSS_COLOR_RGB24P:
1698 return 24;
1699 case OMAP_DSS_COLOR_RGB24U:
1700 case OMAP_DSS_COLOR_ARGB32:
1701 case OMAP_DSS_COLOR_RGBA32:
1702 case OMAP_DSS_COLOR_RGBX32:
1703 return 32;
1704 default:
1705 BUG();
1706 return 0;
1707 }
1708 }
1709
1710 static s32 pixinc(int pixels, u8 ps)
1711 {
1712 if (pixels == 1)
1713 return 1;
1714 else if (pixels > 1)
1715 return 1 + (pixels - 1) * ps;
1716 else if (pixels < 0)
1717 return 1 - (-pixels + 1) * ps;
1718 else
1719 BUG();
1720 return 0;
1721 }
1722
1723 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1724 u16 screen_width,
1725 u16 width, u16 height,
1726 enum omap_color_mode color_mode, bool fieldmode,
1727 unsigned int field_offset,
1728 unsigned *offset0, unsigned *offset1,
1729 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1730 {
1731 u8 ps;
1732
1733 /* FIXME CLUT formats */
1734 switch (color_mode) {
1735 case OMAP_DSS_COLOR_CLUT1:
1736 case OMAP_DSS_COLOR_CLUT2:
1737 case OMAP_DSS_COLOR_CLUT4:
1738 case OMAP_DSS_COLOR_CLUT8:
1739 BUG();
1740 return;
1741 case OMAP_DSS_COLOR_YUV2:
1742 case OMAP_DSS_COLOR_UYVY:
1743 ps = 4;
1744 break;
1745 default:
1746 ps = color_mode_to_bpp(color_mode) / 8;
1747 break;
1748 }
1749
1750 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1751 width, height);
1752
1753 /*
1754 * field 0 = even field = bottom field
1755 * field 1 = odd field = top field
1756 */
1757 switch (rotation + mirror * 4) {
1758 case OMAP_DSS_ROT_0:
1759 case OMAP_DSS_ROT_180:
1760 /*
1761 * If the pixel format is YUV or UYVY divide the width
1762 * of the image by 2 for 0 and 180 degree rotation.
1763 */
1764 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1765 color_mode == OMAP_DSS_COLOR_UYVY)
1766 width = width >> 1;
1767 case OMAP_DSS_ROT_90:
1768 case OMAP_DSS_ROT_270:
1769 *offset1 = 0;
1770 if (field_offset)
1771 *offset0 = field_offset * screen_width * ps;
1772 else
1773 *offset0 = 0;
1774
1775 *row_inc = pixinc(1 +
1776 (y_predecim * screen_width - x_predecim * width) +
1777 (fieldmode ? screen_width : 0), ps);
1778 *pix_inc = pixinc(x_predecim, ps);
1779 break;
1780
1781 case OMAP_DSS_ROT_0 + 4:
1782 case OMAP_DSS_ROT_180 + 4:
1783 /* If the pixel format is YUV or UYVY divide the width
1784 * of the image by 2 for 0 degree and 180 degree
1785 */
1786 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1787 color_mode == OMAP_DSS_COLOR_UYVY)
1788 width = width >> 1;
1789 case OMAP_DSS_ROT_90 + 4:
1790 case OMAP_DSS_ROT_270 + 4:
1791 *offset1 = 0;
1792 if (field_offset)
1793 *offset0 = field_offset * screen_width * ps;
1794 else
1795 *offset0 = 0;
1796 *row_inc = pixinc(1 -
1797 (y_predecim * screen_width + x_predecim * width) -
1798 (fieldmode ? screen_width : 0), ps);
1799 *pix_inc = pixinc(x_predecim, ps);
1800 break;
1801
1802 default:
1803 BUG();
1804 return;
1805 }
1806 }
1807
1808 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1809 u16 screen_width,
1810 u16 width, u16 height,
1811 enum omap_color_mode color_mode, bool fieldmode,
1812 unsigned int field_offset,
1813 unsigned *offset0, unsigned *offset1,
1814 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1815 {
1816 u8 ps;
1817 u16 fbw, fbh;
1818
1819 /* FIXME CLUT formats */
1820 switch (color_mode) {
1821 case OMAP_DSS_COLOR_CLUT1:
1822 case OMAP_DSS_COLOR_CLUT2:
1823 case OMAP_DSS_COLOR_CLUT4:
1824 case OMAP_DSS_COLOR_CLUT8:
1825 BUG();
1826 return;
1827 default:
1828 ps = color_mode_to_bpp(color_mode) / 8;
1829 break;
1830 }
1831
1832 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1833 width, height);
1834
1835 /* width & height are overlay sizes, convert to fb sizes */
1836
1837 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1838 fbw = width;
1839 fbh = height;
1840 } else {
1841 fbw = height;
1842 fbh = width;
1843 }
1844
1845 /*
1846 * field 0 = even field = bottom field
1847 * field 1 = odd field = top field
1848 */
1849 switch (rotation + mirror * 4) {
1850 case OMAP_DSS_ROT_0:
1851 *offset1 = 0;
1852 if (field_offset)
1853 *offset0 = *offset1 + field_offset * screen_width * ps;
1854 else
1855 *offset0 = *offset1;
1856 *row_inc = pixinc(1 +
1857 (y_predecim * screen_width - fbw * x_predecim) +
1858 (fieldmode ? screen_width : 0), ps);
1859 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1860 color_mode == OMAP_DSS_COLOR_UYVY)
1861 *pix_inc = pixinc(x_predecim, 2 * ps);
1862 else
1863 *pix_inc = pixinc(x_predecim, ps);
1864 break;
1865 case OMAP_DSS_ROT_90:
1866 *offset1 = screen_width * (fbh - 1) * ps;
1867 if (field_offset)
1868 *offset0 = *offset1 + field_offset * ps;
1869 else
1870 *offset0 = *offset1;
1871 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1872 y_predecim + (fieldmode ? 1 : 0), ps);
1873 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1874 break;
1875 case OMAP_DSS_ROT_180:
1876 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1877 if (field_offset)
1878 *offset0 = *offset1 - field_offset * screen_width * ps;
1879 else
1880 *offset0 = *offset1;
1881 *row_inc = pixinc(-1 -
1882 (y_predecim * screen_width - fbw * x_predecim) -
1883 (fieldmode ? screen_width : 0), ps);
1884 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1885 color_mode == OMAP_DSS_COLOR_UYVY)
1886 *pix_inc = pixinc(-x_predecim, 2 * ps);
1887 else
1888 *pix_inc = pixinc(-x_predecim, ps);
1889 break;
1890 case OMAP_DSS_ROT_270:
1891 *offset1 = (fbw - 1) * ps;
1892 if (field_offset)
1893 *offset0 = *offset1 - field_offset * ps;
1894 else
1895 *offset0 = *offset1;
1896 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1897 y_predecim - (fieldmode ? 1 : 0), ps);
1898 *pix_inc = pixinc(x_predecim * screen_width, ps);
1899 break;
1900
1901 /* mirroring */
1902 case OMAP_DSS_ROT_0 + 4:
1903 *offset1 = (fbw - 1) * ps;
1904 if (field_offset)
1905 *offset0 = *offset1 + field_offset * screen_width * ps;
1906 else
1907 *offset0 = *offset1;
1908 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1909 (fieldmode ? screen_width : 0),
1910 ps);
1911 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1912 color_mode == OMAP_DSS_COLOR_UYVY)
1913 *pix_inc = pixinc(-x_predecim, 2 * ps);
1914 else
1915 *pix_inc = pixinc(-x_predecim, ps);
1916 break;
1917
1918 case OMAP_DSS_ROT_90 + 4:
1919 *offset1 = 0;
1920 if (field_offset)
1921 *offset0 = *offset1 + field_offset * ps;
1922 else
1923 *offset0 = *offset1;
1924 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1925 y_predecim + (fieldmode ? 1 : 0),
1926 ps);
1927 *pix_inc = pixinc(x_predecim * screen_width, ps);
1928 break;
1929
1930 case OMAP_DSS_ROT_180 + 4:
1931 *offset1 = screen_width * (fbh - 1) * ps;
1932 if (field_offset)
1933 *offset0 = *offset1 - field_offset * screen_width * ps;
1934 else
1935 *offset0 = *offset1;
1936 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1937 (fieldmode ? screen_width : 0),
1938 ps);
1939 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1940 color_mode == OMAP_DSS_COLOR_UYVY)
1941 *pix_inc = pixinc(x_predecim, 2 * ps);
1942 else
1943 *pix_inc = pixinc(x_predecim, ps);
1944 break;
1945
1946 case OMAP_DSS_ROT_270 + 4:
1947 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1948 if (field_offset)
1949 *offset0 = *offset1 - field_offset * ps;
1950 else
1951 *offset0 = *offset1;
1952 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1953 y_predecim - (fieldmode ? 1 : 0),
1954 ps);
1955 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1956 break;
1957
1958 default:
1959 BUG();
1960 return;
1961 }
1962 }
1963
1964 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1965 enum omap_color_mode color_mode, bool fieldmode,
1966 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1967 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1968 {
1969 u8 ps;
1970
1971 switch (color_mode) {
1972 case OMAP_DSS_COLOR_CLUT1:
1973 case OMAP_DSS_COLOR_CLUT2:
1974 case OMAP_DSS_COLOR_CLUT4:
1975 case OMAP_DSS_COLOR_CLUT8:
1976 BUG();
1977 return;
1978 default:
1979 ps = color_mode_to_bpp(color_mode) / 8;
1980 break;
1981 }
1982
1983 DSSDBG("scrw %d, width %d\n", screen_width, width);
1984
1985 /*
1986 * field 0 = even field = bottom field
1987 * field 1 = odd field = top field
1988 */
1989 *offset1 = 0;
1990 if (field_offset)
1991 *offset0 = *offset1 + field_offset * screen_width * ps;
1992 else
1993 *offset0 = *offset1;
1994 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1995 (fieldmode ? screen_width : 0), ps);
1996 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1997 color_mode == OMAP_DSS_COLOR_UYVY)
1998 *pix_inc = pixinc(x_predecim, 2 * ps);
1999 else
2000 *pix_inc = pixinc(x_predecim, ps);
2001 }
2002
2003 /*
2004 * This function is used to avoid synclosts in OMAP3, because of some
2005 * undocumented horizontal position and timing related limitations.
2006 */
2007 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2008 const struct omap_video_timings *t, u16 pos_x,
2009 u16 width, u16 height, u16 out_width, u16 out_height,
2010 bool five_taps)
2011 {
2012 const int ds = DIV_ROUND_UP(height, out_height);
2013 unsigned long nonactive;
2014 static const u8 limits[3] = { 8, 10, 20 };
2015 u64 val, blank;
2016 int i;
2017
2018 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2019
2020 i = 0;
2021 if (out_height < height)
2022 i++;
2023 if (out_width < width)
2024 i++;
2025 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2026 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2027 if (blank <= limits[i])
2028 return -EINVAL;
2029
2030 /* FIXME add checks for 3-tap filter once the limitations are known */
2031 if (!five_taps)
2032 return 0;
2033
2034 /*
2035 * Pixel data should be prepared before visible display point starts.
2036 * So, atleast DS-2 lines must have already been fetched by DISPC
2037 * during nonactive - pos_x period.
2038 */
2039 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2040 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2041 val, max(0, ds - 2) * width);
2042 if (val < max(0, ds - 2) * width)
2043 return -EINVAL;
2044
2045 /*
2046 * All lines need to be refilled during the nonactive period of which
2047 * only one line can be loaded during the active period. So, atleast
2048 * DS - 1 lines should be loaded during nonactive period.
2049 */
2050 val = div_u64((u64)nonactive * lclk, pclk);
2051 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2052 val, max(0, ds - 1) * width);
2053 if (val < max(0, ds - 1) * width)
2054 return -EINVAL;
2055
2056 return 0;
2057 }
2058
2059 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2060 const struct omap_video_timings *mgr_timings, u16 width,
2061 u16 height, u16 out_width, u16 out_height,
2062 enum omap_color_mode color_mode)
2063 {
2064 u32 core_clk = 0;
2065 u64 tmp;
2066
2067 if (height <= out_height && width <= out_width)
2068 return (unsigned long) pclk;
2069
2070 if (height > out_height) {
2071 unsigned int ppl = mgr_timings->x_res;
2072
2073 tmp = pclk * height * out_width;
2074 do_div(tmp, 2 * out_height * ppl);
2075 core_clk = tmp;
2076
2077 if (height > 2 * out_height) {
2078 if (ppl == out_width)
2079 return 0;
2080
2081 tmp = pclk * (height - 2 * out_height) * out_width;
2082 do_div(tmp, 2 * out_height * (ppl - out_width));
2083 core_clk = max_t(u32, core_clk, tmp);
2084 }
2085 }
2086
2087 if (width > out_width) {
2088 tmp = pclk * width;
2089 do_div(tmp, out_width);
2090 core_clk = max_t(u32, core_clk, tmp);
2091
2092 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2093 core_clk <<= 1;
2094 }
2095
2096 return core_clk;
2097 }
2098
2099 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2100 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2101 {
2102 if (height > out_height && width > out_width)
2103 return pclk * 4;
2104 else
2105 return pclk * 2;
2106 }
2107
2108 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2109 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2110 {
2111 unsigned int hf, vf;
2112
2113 /*
2114 * FIXME how to determine the 'A' factor
2115 * for the no downscaling case ?
2116 */
2117
2118 if (width > 3 * out_width)
2119 hf = 4;
2120 else if (width > 2 * out_width)
2121 hf = 3;
2122 else if (width > out_width)
2123 hf = 2;
2124 else
2125 hf = 1;
2126 if (height > out_height)
2127 vf = 2;
2128 else
2129 vf = 1;
2130
2131 return pclk * vf * hf;
2132 }
2133
2134 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2135 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2136 {
2137 /*
2138 * If the overlay/writeback is in mem to mem mode, there are no
2139 * downscaling limitations with respect to pixel clock, return 1 as
2140 * required core clock to represent that we have sufficient enough
2141 * core clock to do maximum downscaling
2142 */
2143 if (mem_to_mem)
2144 return 1;
2145
2146 if (width > out_width)
2147 return DIV_ROUND_UP(pclk, out_width) * width;
2148 else
2149 return pclk;
2150 }
2151
2152 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2153 const struct omap_video_timings *mgr_timings,
2154 u16 width, u16 height, u16 out_width, u16 out_height,
2155 enum omap_color_mode color_mode, bool *five_taps,
2156 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2157 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2158 {
2159 int error;
2160 u16 in_width, in_height;
2161 int min_factor = min(*decim_x, *decim_y);
2162 const int maxsinglelinewidth =
2163 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2164
2165 *five_taps = false;
2166
2167 do {
2168 in_height = height / *decim_y;
2169 in_width = width / *decim_x;
2170 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2171 in_height, out_width, out_height, mem_to_mem);
2172 error = (in_width > maxsinglelinewidth || !*core_clk ||
2173 *core_clk > dispc_core_clk_rate());
2174 if (error) {
2175 if (*decim_x == *decim_y) {
2176 *decim_x = min_factor;
2177 ++*decim_y;
2178 } else {
2179 swap(*decim_x, *decim_y);
2180 if (*decim_x < *decim_y)
2181 ++*decim_x;
2182 }
2183 }
2184 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2185
2186 if (in_width > maxsinglelinewidth) {
2187 DSSERR("Cannot scale max input width exceeded");
2188 return -EINVAL;
2189 }
2190 return 0;
2191 }
2192
2193 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2194 const struct omap_video_timings *mgr_timings,
2195 u16 width, u16 height, u16 out_width, u16 out_height,
2196 enum omap_color_mode color_mode, bool *five_taps,
2197 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2198 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2199 {
2200 int error;
2201 u16 in_width, in_height;
2202 int min_factor = min(*decim_x, *decim_y);
2203 const int maxsinglelinewidth =
2204 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2205
2206 do {
2207 in_height = height / *decim_y;
2208 in_width = width / *decim_x;
2209 *five_taps = in_height > out_height;
2210
2211 if (in_width > maxsinglelinewidth)
2212 if (in_height > out_height &&
2213 in_height < out_height * 2)
2214 *five_taps = false;
2215 again:
2216 if (*five_taps)
2217 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2218 in_width, in_height, out_width,
2219 out_height, color_mode);
2220 else
2221 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2222 in_height, out_width, out_height,
2223 mem_to_mem);
2224
2225 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2226 pos_x, in_width, in_height, out_width,
2227 out_height, *five_taps);
2228 if (error && *five_taps) {
2229 *five_taps = false;
2230 goto again;
2231 }
2232
2233 error = (error || in_width > maxsinglelinewidth * 2 ||
2234 (in_width > maxsinglelinewidth && *five_taps) ||
2235 !*core_clk || *core_clk > dispc_core_clk_rate());
2236 if (error) {
2237 if (*decim_x == *decim_y) {
2238 *decim_x = min_factor;
2239 ++*decim_y;
2240 } else {
2241 swap(*decim_x, *decim_y);
2242 if (*decim_x < *decim_y)
2243 ++*decim_x;
2244 }
2245 }
2246 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2247
2248 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2249 height, out_width, out_height, *five_taps)) {
2250 DSSERR("horizontal timing too tight\n");
2251 return -EINVAL;
2252 }
2253
2254 if (in_width > (maxsinglelinewidth * 2)) {
2255 DSSERR("Cannot setup scaling");
2256 DSSERR("width exceeds maximum width possible");
2257 return -EINVAL;
2258 }
2259
2260 if (in_width > maxsinglelinewidth && *five_taps) {
2261 DSSERR("cannot setup scaling with five taps");
2262 return -EINVAL;
2263 }
2264 return 0;
2265 }
2266
2267 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2268 const struct omap_video_timings *mgr_timings,
2269 u16 width, u16 height, u16 out_width, u16 out_height,
2270 enum omap_color_mode color_mode, bool *five_taps,
2271 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2272 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2273 {
2274 u16 in_width, in_width_max;
2275 int decim_x_min = *decim_x;
2276 u16 in_height = height / *decim_y;
2277 const int maxsinglelinewidth =
2278 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2279 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2280
2281 if (mem_to_mem) {
2282 in_width_max = out_width * maxdownscale;
2283 } else {
2284 in_width_max = dispc_core_clk_rate() /
2285 DIV_ROUND_UP(pclk, out_width);
2286 }
2287
2288 *decim_x = DIV_ROUND_UP(width, in_width_max);
2289
2290 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2291 if (*decim_x > *x_predecim)
2292 return -EINVAL;
2293
2294 do {
2295 in_width = width / *decim_x;
2296 } while (*decim_x <= *x_predecim &&
2297 in_width > maxsinglelinewidth && ++*decim_x);
2298
2299 if (in_width > maxsinglelinewidth) {
2300 DSSERR("Cannot scale width exceeds max line width");
2301 return -EINVAL;
2302 }
2303
2304 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2305 out_width, out_height, mem_to_mem);
2306 return 0;
2307 }
2308
2309 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2310 enum omap_overlay_caps caps,
2311 const struct omap_video_timings *mgr_timings,
2312 u16 width, u16 height, u16 out_width, u16 out_height,
2313 enum omap_color_mode color_mode, bool *five_taps,
2314 int *x_predecim, int *y_predecim, u16 pos_x,
2315 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2316 {
2317 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2318 const int max_decim_limit = 16;
2319 unsigned long core_clk = 0;
2320 int decim_x, decim_y, ret;
2321
2322 if (width == out_width && height == out_height)
2323 return 0;
2324
2325 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2326 return -EINVAL;
2327
2328 if (mem_to_mem) {
2329 *x_predecim = *y_predecim = 1;
2330 } else {
2331 *x_predecim = max_decim_limit;
2332 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2333 dss_has_feature(FEAT_BURST_2D)) ?
2334 2 : max_decim_limit;
2335 }
2336
2337 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2338 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2339 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2340 color_mode == OMAP_DSS_COLOR_CLUT8) {
2341 *x_predecim = 1;
2342 *y_predecim = 1;
2343 *five_taps = false;
2344 return 0;
2345 }
2346
2347 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2348 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2349
2350 if (decim_x > *x_predecim || out_width > width * 8)
2351 return -EINVAL;
2352
2353 if (decim_y > *y_predecim || out_height > height * 8)
2354 return -EINVAL;
2355
2356 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2357 out_width, out_height, color_mode, five_taps,
2358 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2359 mem_to_mem);
2360 if (ret)
2361 return ret;
2362
2363 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2364 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2365
2366 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2367 DSSERR("failed to set up scaling, "
2368 "required core clk rate = %lu Hz, "
2369 "current core clk rate = %lu Hz\n",
2370 core_clk, dispc_core_clk_rate());
2371 return -EINVAL;
2372 }
2373
2374 *x_predecim = decim_x;
2375 *y_predecim = decim_y;
2376 return 0;
2377 }
2378
2379 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2380 const struct omap_overlay_info *oi,
2381 const struct omap_video_timings *timings,
2382 int *x_predecim, int *y_predecim)
2383 {
2384 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2385 bool five_taps = true;
2386 bool fieldmode = false;
2387 u16 in_height = oi->height;
2388 u16 in_width = oi->width;
2389 bool ilace = timings->interlace;
2390 u16 out_width, out_height;
2391 int pos_x = oi->pos_x;
2392 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2393 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2394
2395 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2396 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2397
2398 if (ilace && oi->height == out_height)
2399 fieldmode = true;
2400
2401 if (ilace) {
2402 if (fieldmode)
2403 in_height /= 2;
2404 out_height /= 2;
2405
2406 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2407 in_height, out_height);
2408 }
2409
2410 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2411 return -EINVAL;
2412
2413 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2414 in_height, out_width, out_height, oi->color_mode,
2415 &five_taps, x_predecim, y_predecim, pos_x,
2416 oi->rotation_type, false);
2417 }
2418 EXPORT_SYMBOL(dispc_ovl_check);
2419
2420 static int dispc_ovl_setup_common(enum omap_plane plane,
2421 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2422 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2423 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2424 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2425 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2426 bool replication, const struct omap_video_timings *mgr_timings,
2427 bool mem_to_mem)
2428 {
2429 bool five_taps = true;
2430 bool fieldmode = false;
2431 int r, cconv = 0;
2432 unsigned offset0, offset1;
2433 s32 row_inc;
2434 s32 pix_inc;
2435 u16 frame_width, frame_height;
2436 unsigned int field_offset = 0;
2437 u16 in_height = height;
2438 u16 in_width = width;
2439 int x_predecim = 1, y_predecim = 1;
2440 bool ilace = mgr_timings->interlace;
2441 unsigned long pclk = dispc_plane_pclk_rate(plane);
2442 unsigned long lclk = dispc_plane_lclk_rate(plane);
2443
2444 if (paddr == 0)
2445 return -EINVAL;
2446
2447 out_width = out_width == 0 ? width : out_width;
2448 out_height = out_height == 0 ? height : out_height;
2449
2450 if (ilace && height == out_height)
2451 fieldmode = true;
2452
2453 if (ilace) {
2454 if (fieldmode)
2455 in_height /= 2;
2456 pos_y /= 2;
2457 out_height /= 2;
2458
2459 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2460 "out_height %d\n", in_height, pos_y,
2461 out_height);
2462 }
2463
2464 if (!dss_feat_color_mode_supported(plane, color_mode))
2465 return -EINVAL;
2466
2467 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2468 in_height, out_width, out_height, color_mode,
2469 &five_taps, &x_predecim, &y_predecim, pos_x,
2470 rotation_type, mem_to_mem);
2471 if (r)
2472 return r;
2473
2474 in_width = in_width / x_predecim;
2475 in_height = in_height / y_predecim;
2476
2477 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2478 color_mode == OMAP_DSS_COLOR_UYVY ||
2479 color_mode == OMAP_DSS_COLOR_NV12)
2480 cconv = 1;
2481
2482 if (ilace && !fieldmode) {
2483 /*
2484 * when downscaling the bottom field may have to start several
2485 * source lines below the top field. Unfortunately ACCUI
2486 * registers will only hold the fractional part of the offset
2487 * so the integer part must be added to the base address of the
2488 * bottom field.
2489 */
2490 if (!in_height || in_height == out_height)
2491 field_offset = 0;
2492 else
2493 field_offset = in_height / out_height / 2;
2494 }
2495
2496 /* Fields are independent but interleaved in memory. */
2497 if (fieldmode)
2498 field_offset = 1;
2499
2500 offset0 = 0;
2501 offset1 = 0;
2502 row_inc = 0;
2503 pix_inc = 0;
2504
2505 if (plane == OMAP_DSS_WB) {
2506 frame_width = out_width;
2507 frame_height = out_height;
2508 } else {
2509 frame_width = in_width;
2510 frame_height = height;
2511 }
2512
2513 if (rotation_type == OMAP_DSS_ROT_TILER)
2514 calc_tiler_rotation_offset(screen_width, frame_width,
2515 color_mode, fieldmode, field_offset,
2516 &offset0, &offset1, &row_inc, &pix_inc,
2517 x_predecim, y_predecim);
2518 else if (rotation_type == OMAP_DSS_ROT_DMA)
2519 calc_dma_rotation_offset(rotation, mirror, screen_width,
2520 frame_width, frame_height,
2521 color_mode, fieldmode, field_offset,
2522 &offset0, &offset1, &row_inc, &pix_inc,
2523 x_predecim, y_predecim);
2524 else
2525 calc_vrfb_rotation_offset(rotation, mirror,
2526 screen_width, frame_width, frame_height,
2527 color_mode, fieldmode, field_offset,
2528 &offset0, &offset1, &row_inc, &pix_inc,
2529 x_predecim, y_predecim);
2530
2531 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2532 offset0, offset1, row_inc, pix_inc);
2533
2534 dispc_ovl_set_color_mode(plane, color_mode);
2535
2536 dispc_ovl_configure_burst_type(plane, rotation_type);
2537
2538 dispc_ovl_set_ba0(plane, paddr + offset0);
2539 dispc_ovl_set_ba1(plane, paddr + offset1);
2540
2541 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2542 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2543 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2544 }
2545
2546 dispc_ovl_set_row_inc(plane, row_inc);
2547 dispc_ovl_set_pix_inc(plane, pix_inc);
2548
2549 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2550 in_height, out_width, out_height);
2551
2552 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2553
2554 dispc_ovl_set_input_size(plane, in_width, in_height);
2555
2556 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2557 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2558 out_height, ilace, five_taps, fieldmode,
2559 color_mode, rotation);
2560 dispc_ovl_set_output_size(plane, out_width, out_height);
2561 dispc_ovl_set_vid_color_conv(plane, cconv);
2562 }
2563
2564 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2565 color_mode);
2566
2567 dispc_ovl_set_zorder(plane, caps, zorder);
2568 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2569 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2570
2571 dispc_ovl_enable_replication(plane, caps, replication);
2572
2573 return 0;
2574 }
2575
2576 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2577 bool replication, const struct omap_video_timings *mgr_timings,
2578 bool mem_to_mem)
2579 {
2580 int r;
2581 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2582 enum omap_channel channel;
2583
2584 channel = dispc_ovl_get_channel_out(plane);
2585
2586 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2587 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2588 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2589 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2590 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2591
2592 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2593 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2594 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2595 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2596 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2597
2598 return r;
2599 }
2600 EXPORT_SYMBOL(dispc_ovl_setup);
2601
2602 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2603 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2604 {
2605 int r;
2606 u32 l;
2607 enum omap_plane plane = OMAP_DSS_WB;
2608 const int pos_x = 0, pos_y = 0;
2609 const u8 zorder = 0, global_alpha = 0;
2610 const bool replication = false;
2611 bool truncation;
2612 int in_width = mgr_timings->x_res;
2613 int in_height = mgr_timings->y_res;
2614 enum omap_overlay_caps caps =
2615 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2616
2617 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2618 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2619 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2620 wi->mirror);
2621
2622 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2623 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2624 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2625 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2626 replication, mgr_timings, mem_to_mem);
2627
2628 switch (wi->color_mode) {
2629 case OMAP_DSS_COLOR_RGB16:
2630 case OMAP_DSS_COLOR_RGB24P:
2631 case OMAP_DSS_COLOR_ARGB16:
2632 case OMAP_DSS_COLOR_RGBA16:
2633 case OMAP_DSS_COLOR_RGB12U:
2634 case OMAP_DSS_COLOR_ARGB16_1555:
2635 case OMAP_DSS_COLOR_XRGB16_1555:
2636 case OMAP_DSS_COLOR_RGBX16:
2637 truncation = true;
2638 break;
2639 default:
2640 truncation = false;
2641 break;
2642 }
2643
2644 /* setup extra DISPC_WB_ATTRIBUTES */
2645 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2646 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2647 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2648 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2649
2650 return r;
2651 }
2652
2653 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2654 {
2655 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2656
2657 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2658
2659 return 0;
2660 }
2661 EXPORT_SYMBOL(dispc_ovl_enable);
2662
2663 bool dispc_ovl_enabled(enum omap_plane plane)
2664 {
2665 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2666 }
2667 EXPORT_SYMBOL(dispc_ovl_enabled);
2668
2669 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2670 {
2671 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2672 /* flush posted write */
2673 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2674 }
2675 EXPORT_SYMBOL(dispc_mgr_enable);
2676
2677 bool dispc_mgr_is_enabled(enum omap_channel channel)
2678 {
2679 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2680 }
2681 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2682
2683 void dispc_wb_enable(bool enable)
2684 {
2685 dispc_ovl_enable(OMAP_DSS_WB, enable);
2686 }
2687
2688 bool dispc_wb_is_enabled(void)
2689 {
2690 return dispc_ovl_enabled(OMAP_DSS_WB);
2691 }
2692
2693 static void dispc_lcd_enable_signal_polarity(bool act_high)
2694 {
2695 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2696 return;
2697
2698 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2699 }
2700
2701 void dispc_lcd_enable_signal(bool enable)
2702 {
2703 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2704 return;
2705
2706 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2707 }
2708
2709 void dispc_pck_free_enable(bool enable)
2710 {
2711 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2712 return;
2713
2714 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2715 }
2716
2717 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2718 {
2719 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2720 }
2721
2722
2723 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2724 {
2725 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2726 }
2727
2728 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2729 {
2730 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2731 }
2732
2733
2734 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2735 {
2736 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2737 }
2738
2739 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2740 enum omap_dss_trans_key_type type,
2741 u32 trans_key)
2742 {
2743 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2744
2745 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2746 }
2747
2748 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2749 {
2750 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2751 }
2752
2753 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2754 bool enable)
2755 {
2756 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2757 return;
2758
2759 if (ch == OMAP_DSS_CHANNEL_LCD)
2760 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2761 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2762 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2763 }
2764
2765 void dispc_mgr_setup(enum omap_channel channel,
2766 const struct omap_overlay_manager_info *info)
2767 {
2768 dispc_mgr_set_default_color(channel, info->default_color);
2769 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2770 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2771 dispc_mgr_enable_alpha_fixed_zorder(channel,
2772 info->partial_alpha_enabled);
2773 if (dss_has_feature(FEAT_CPR)) {
2774 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2775 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2776 }
2777 }
2778 EXPORT_SYMBOL(dispc_mgr_setup);
2779
2780 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2781 {
2782 int code;
2783
2784 switch (data_lines) {
2785 case 12:
2786 code = 0;
2787 break;
2788 case 16:
2789 code = 1;
2790 break;
2791 case 18:
2792 code = 2;
2793 break;
2794 case 24:
2795 code = 3;
2796 break;
2797 default:
2798 BUG();
2799 return;
2800 }
2801
2802 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2803 }
2804
2805 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2806 {
2807 u32 l;
2808 int gpout0, gpout1;
2809
2810 switch (mode) {
2811 case DSS_IO_PAD_MODE_RESET:
2812 gpout0 = 0;
2813 gpout1 = 0;
2814 break;
2815 case DSS_IO_PAD_MODE_RFBI:
2816 gpout0 = 1;
2817 gpout1 = 0;
2818 break;
2819 case DSS_IO_PAD_MODE_BYPASS:
2820 gpout0 = 1;
2821 gpout1 = 1;
2822 break;
2823 default:
2824 BUG();
2825 return;
2826 }
2827
2828 l = dispc_read_reg(DISPC_CONTROL);
2829 l = FLD_MOD(l, gpout0, 15, 15);
2830 l = FLD_MOD(l, gpout1, 16, 16);
2831 dispc_write_reg(DISPC_CONTROL, l);
2832 }
2833
2834 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2835 {
2836 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2837 }
2838
2839 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2840 const struct dss_lcd_mgr_config *config)
2841 {
2842 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2843
2844 dispc_mgr_enable_stallmode(channel, config->stallmode);
2845 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2846
2847 dispc_mgr_set_clock_div(channel, &config->clock_info);
2848
2849 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2850
2851 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2852
2853 dispc_mgr_set_lcd_type_tft(channel);
2854 }
2855 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2856
2857 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2858 {
2859 return width <= dispc.feat->mgr_width_max &&
2860 height <= dispc.feat->mgr_height_max;
2861 }
2862
2863 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2864 int vsw, int vfp, int vbp)
2865 {
2866 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2867 hfp < 1 || hfp > dispc.feat->hp_max ||
2868 hbp < 1 || hbp > dispc.feat->hp_max ||
2869 vsw < 1 || vsw > dispc.feat->sw_max ||
2870 vfp < 0 || vfp > dispc.feat->vp_max ||
2871 vbp < 0 || vbp > dispc.feat->vp_max)
2872 return false;
2873 return true;
2874 }
2875
2876 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2877 unsigned long pclk)
2878 {
2879 if (dss_mgr_is_lcd(channel))
2880 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2881 else
2882 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2883 }
2884
2885 bool dispc_mgr_timings_ok(enum omap_channel channel,
2886 const struct omap_video_timings *timings)
2887 {
2888 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2889 return false;
2890
2891 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2892 return false;
2893
2894 if (dss_mgr_is_lcd(channel)) {
2895 /* TODO: OMAP4+ supports interlace for LCD outputs */
2896 if (timings->interlace)
2897 return false;
2898
2899 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2900 timings->hbp, timings->vsw, timings->vfp,
2901 timings->vbp))
2902 return false;
2903 }
2904
2905 return true;
2906 }
2907
2908 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2909 int hfp, int hbp, int vsw, int vfp, int vbp,
2910 enum omap_dss_signal_level vsync_level,
2911 enum omap_dss_signal_level hsync_level,
2912 enum omap_dss_signal_edge data_pclk_edge,
2913 enum omap_dss_signal_level de_level,
2914 enum omap_dss_signal_edge sync_pclk_edge)
2915
2916 {
2917 u32 timing_h, timing_v, l;
2918 bool onoff, rf, ipc;
2919
2920 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2921 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2922 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2923 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2924 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2925 FLD_VAL(vbp, dispc.feat->bp_start, 20);
2926
2927 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2928 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2929
2930 switch (data_pclk_edge) {
2931 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2932 ipc = false;
2933 break;
2934 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2935 ipc = true;
2936 break;
2937 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2938 default:
2939 BUG();
2940 }
2941
2942 switch (sync_pclk_edge) {
2943 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2944 onoff = false;
2945 rf = false;
2946 break;
2947 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2948 onoff = true;
2949 rf = false;
2950 break;
2951 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2952 onoff = true;
2953 rf = true;
2954 break;
2955 default:
2956 BUG();
2957 }
2958
2959 l = FLD_VAL(onoff, 17, 17) |
2960 FLD_VAL(rf, 16, 16) |
2961 FLD_VAL(de_level, 15, 15) |
2962 FLD_VAL(ipc, 14, 14) |
2963 FLD_VAL(hsync_level, 13, 13) |
2964 FLD_VAL(vsync_level, 12, 12);
2965
2966 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2967
2968 if (dispc.syscon_pol) {
2969 const int shifts[] = {
2970 [OMAP_DSS_CHANNEL_LCD] = 0,
2971 [OMAP_DSS_CHANNEL_LCD2] = 1,
2972 [OMAP_DSS_CHANNEL_LCD3] = 2,
2973 };
2974
2975 u32 mask, val;
2976
2977 mask = (1 << 0) | (1 << 3) | (1 << 6);
2978 val = (rf << 0) | (ipc << 3) | (onoff << 6);
2979
2980 mask <<= 16 + shifts[channel];
2981 val <<= 16 + shifts[channel];
2982
2983 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
2984 mask, val);
2985 }
2986 }
2987
2988 /* change name to mode? */
2989 void dispc_mgr_set_timings(enum omap_channel channel,
2990 const struct omap_video_timings *timings)
2991 {
2992 unsigned xtot, ytot;
2993 unsigned long ht, vt;
2994 struct omap_video_timings t = *timings;
2995
2996 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2997
2998 if (!dispc_mgr_timings_ok(channel, &t)) {
2999 BUG();
3000 return;
3001 }
3002
3003 if (dss_mgr_is_lcd(channel)) {
3004 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3005 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3006 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3007
3008 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3009 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3010
3011 ht = timings->pixelclock / xtot;
3012 vt = timings->pixelclock / xtot / ytot;
3013
3014 DSSDBG("pck %u\n", timings->pixelclock);
3015 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3016 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3017 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3018 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3019 t.de_level, t.sync_pclk_edge);
3020
3021 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3022 } else {
3023 if (t.interlace == true)
3024 t.y_res /= 2;
3025 }
3026
3027 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3028 }
3029 EXPORT_SYMBOL(dispc_mgr_set_timings);
3030
3031 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3032 u16 pck_div)
3033 {
3034 BUG_ON(lck_div < 1);
3035 BUG_ON(pck_div < 1);
3036
3037 dispc_write_reg(DISPC_DIVISORo(channel),
3038 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3039
3040 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3041 channel == OMAP_DSS_CHANNEL_LCD)
3042 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3043 }
3044
3045 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3046 int *pck_div)
3047 {
3048 u32 l;
3049 l = dispc_read_reg(DISPC_DIVISORo(channel));
3050 *lck_div = FLD_GET(l, 23, 16);
3051 *pck_div = FLD_GET(l, 7, 0);
3052 }
3053
3054 unsigned long dispc_fclk_rate(void)
3055 {
3056 struct dss_pll *pll;
3057 unsigned long r = 0;
3058
3059 switch (dss_get_dispc_clk_source()) {
3060 case OMAP_DSS_CLK_SRC_FCK:
3061 r = dss_get_dispc_clk_rate();
3062 break;
3063 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3064 pll = dss_pll_find("dsi0");
3065 if (!pll)
3066 pll = dss_pll_find("video0");
3067
3068 r = pll->cinfo.clkout[0];
3069 break;
3070 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3071 pll = dss_pll_find("dsi1");
3072 if (!pll)
3073 pll = dss_pll_find("video1");
3074
3075 r = pll->cinfo.clkout[0];
3076 break;
3077 default:
3078 BUG();
3079 return 0;
3080 }
3081
3082 return r;
3083 }
3084
3085 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3086 {
3087 struct dss_pll *pll;
3088 int lcd;
3089 unsigned long r;
3090 u32 l;
3091
3092 if (dss_mgr_is_lcd(channel)) {
3093 l = dispc_read_reg(DISPC_DIVISORo(channel));
3094
3095 lcd = FLD_GET(l, 23, 16);
3096
3097 switch (dss_get_lcd_clk_source(channel)) {
3098 case OMAP_DSS_CLK_SRC_FCK:
3099 r = dss_get_dispc_clk_rate();
3100 break;
3101 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3102 pll = dss_pll_find("dsi0");
3103 if (!pll)
3104 pll = dss_pll_find("video0");
3105
3106 r = pll->cinfo.clkout[0];
3107 break;
3108 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3109 pll = dss_pll_find("dsi1");
3110 if (!pll)
3111 pll = dss_pll_find("video1");
3112
3113 r = pll->cinfo.clkout[0];
3114 break;
3115 default:
3116 BUG();
3117 return 0;
3118 }
3119
3120 return r / lcd;
3121 } else {
3122 return dispc_fclk_rate();
3123 }
3124 }
3125
3126 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3127 {
3128 unsigned long r;
3129
3130 if (dss_mgr_is_lcd(channel)) {
3131 int pcd;
3132 u32 l;
3133
3134 l = dispc_read_reg(DISPC_DIVISORo(channel));
3135
3136 pcd = FLD_GET(l, 7, 0);
3137
3138 r = dispc_mgr_lclk_rate(channel);
3139
3140 return r / pcd;
3141 } else {
3142 return dispc.tv_pclk_rate;
3143 }
3144 }
3145
3146 void dispc_set_tv_pclk(unsigned long pclk)
3147 {
3148 dispc.tv_pclk_rate = pclk;
3149 }
3150
3151 unsigned long dispc_core_clk_rate(void)
3152 {
3153 return dispc.core_clk_rate;
3154 }
3155
3156 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3157 {
3158 enum omap_channel channel;
3159
3160 if (plane == OMAP_DSS_WB)
3161 return 0;
3162
3163 channel = dispc_ovl_get_channel_out(plane);
3164
3165 return dispc_mgr_pclk_rate(channel);
3166 }
3167
3168 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3169 {
3170 enum omap_channel channel;
3171
3172 if (plane == OMAP_DSS_WB)
3173 return 0;
3174
3175 channel = dispc_ovl_get_channel_out(plane);
3176
3177 return dispc_mgr_lclk_rate(channel);
3178 }
3179
3180 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3181 {
3182 int lcd, pcd;
3183 enum omap_dss_clk_source lcd_clk_src;
3184
3185 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3186
3187 lcd_clk_src = dss_get_lcd_clk_source(channel);
3188
3189 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3190 dss_get_generic_clk_source_name(lcd_clk_src),
3191 dss_feat_get_clk_source_name(lcd_clk_src));
3192
3193 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3194
3195 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3196 dispc_mgr_lclk_rate(channel), lcd);
3197 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3198 dispc_mgr_pclk_rate(channel), pcd);
3199 }
3200
3201 void dispc_dump_clocks(struct seq_file *s)
3202 {
3203 int lcd;
3204 u32 l;
3205 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3206
3207 if (dispc_runtime_get())
3208 return;
3209
3210 seq_printf(s, "- DISPC -\n");
3211
3212 seq_printf(s, "dispc fclk source = %s (%s)\n",
3213 dss_get_generic_clk_source_name(dispc_clk_src),
3214 dss_feat_get_clk_source_name(dispc_clk_src));
3215
3216 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3217
3218 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3219 seq_printf(s, "- DISPC-CORE-CLK -\n");
3220 l = dispc_read_reg(DISPC_DIVISOR);
3221 lcd = FLD_GET(l, 23, 16);
3222
3223 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3224 (dispc_fclk_rate()/lcd), lcd);
3225 }
3226
3227 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3228
3229 if (dss_has_feature(FEAT_MGR_LCD2))
3230 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3231 if (dss_has_feature(FEAT_MGR_LCD3))
3232 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3233
3234 dispc_runtime_put();
3235 }
3236
3237 static void dispc_dump_regs(struct seq_file *s)
3238 {
3239 int i, j;
3240 const char *mgr_names[] = {
3241 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3242 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3243 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3244 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3245 };
3246 const char *ovl_names[] = {
3247 [OMAP_DSS_GFX] = "GFX",
3248 [OMAP_DSS_VIDEO1] = "VID1",
3249 [OMAP_DSS_VIDEO2] = "VID2",
3250 [OMAP_DSS_VIDEO3] = "VID3",
3251 };
3252 const char **p_names;
3253
3254 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3255
3256 if (dispc_runtime_get())
3257 return;
3258
3259 /* DISPC common registers */
3260 DUMPREG(DISPC_REVISION);
3261 DUMPREG(DISPC_SYSCONFIG);
3262 DUMPREG(DISPC_SYSSTATUS);
3263 DUMPREG(DISPC_IRQSTATUS);
3264 DUMPREG(DISPC_IRQENABLE);
3265 DUMPREG(DISPC_CONTROL);
3266 DUMPREG(DISPC_CONFIG);
3267 DUMPREG(DISPC_CAPABLE);
3268 DUMPREG(DISPC_LINE_STATUS);
3269 DUMPREG(DISPC_LINE_NUMBER);
3270 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3271 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3272 DUMPREG(DISPC_GLOBAL_ALPHA);
3273 if (dss_has_feature(FEAT_MGR_LCD2)) {
3274 DUMPREG(DISPC_CONTROL2);
3275 DUMPREG(DISPC_CONFIG2);
3276 }
3277 if (dss_has_feature(FEAT_MGR_LCD3)) {
3278 DUMPREG(DISPC_CONTROL3);
3279 DUMPREG(DISPC_CONFIG3);
3280 }
3281 if (dss_has_feature(FEAT_MFLAG))
3282 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3283
3284 #undef DUMPREG
3285
3286 #define DISPC_REG(i, name) name(i)
3287 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3288 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3289 dispc_read_reg(DISPC_REG(i, r)))
3290
3291 p_names = mgr_names;
3292
3293 /* DISPC channel specific registers */
3294 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3295 DUMPREG(i, DISPC_DEFAULT_COLOR);
3296 DUMPREG(i, DISPC_TRANS_COLOR);
3297 DUMPREG(i, DISPC_SIZE_MGR);
3298
3299 if (i == OMAP_DSS_CHANNEL_DIGIT)
3300 continue;
3301
3302 DUMPREG(i, DISPC_TIMING_H);
3303 DUMPREG(i, DISPC_TIMING_V);
3304 DUMPREG(i, DISPC_POL_FREQ);
3305 DUMPREG(i, DISPC_DIVISORo);
3306
3307 DUMPREG(i, DISPC_DATA_CYCLE1);
3308 DUMPREG(i, DISPC_DATA_CYCLE2);
3309 DUMPREG(i, DISPC_DATA_CYCLE3);
3310
3311 if (dss_has_feature(FEAT_CPR)) {
3312 DUMPREG(i, DISPC_CPR_COEF_R);
3313 DUMPREG(i, DISPC_CPR_COEF_G);
3314 DUMPREG(i, DISPC_CPR_COEF_B);
3315 }
3316 }
3317
3318 p_names = ovl_names;
3319
3320 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3321 DUMPREG(i, DISPC_OVL_BA0);
3322 DUMPREG(i, DISPC_OVL_BA1);
3323 DUMPREG(i, DISPC_OVL_POSITION);
3324 DUMPREG(i, DISPC_OVL_SIZE);
3325 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3326 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3327 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3328 DUMPREG(i, DISPC_OVL_ROW_INC);
3329 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3330
3331 if (dss_has_feature(FEAT_PRELOAD))
3332 DUMPREG(i, DISPC_OVL_PRELOAD);
3333 if (dss_has_feature(FEAT_MFLAG))
3334 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3335
3336 if (i == OMAP_DSS_GFX) {
3337 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3338 DUMPREG(i, DISPC_OVL_TABLE_BA);
3339 continue;
3340 }
3341
3342 DUMPREG(i, DISPC_OVL_FIR);
3343 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3344 DUMPREG(i, DISPC_OVL_ACCU0);
3345 DUMPREG(i, DISPC_OVL_ACCU1);
3346 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3347 DUMPREG(i, DISPC_OVL_BA0_UV);
3348 DUMPREG(i, DISPC_OVL_BA1_UV);
3349 DUMPREG(i, DISPC_OVL_FIR2);
3350 DUMPREG(i, DISPC_OVL_ACCU2_0);
3351 DUMPREG(i, DISPC_OVL_ACCU2_1);
3352 }
3353 if (dss_has_feature(FEAT_ATTR2))
3354 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3355 }
3356
3357 #undef DISPC_REG
3358 #undef DUMPREG
3359
3360 #define DISPC_REG(plane, name, i) name(plane, i)
3361 #define DUMPREG(plane, name, i) \
3362 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3363 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3364 dispc_read_reg(DISPC_REG(plane, name, i)))
3365
3366 /* Video pipeline coefficient registers */
3367
3368 /* start from OMAP_DSS_VIDEO1 */
3369 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3370 for (j = 0; j < 8; j++)
3371 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3372
3373 for (j = 0; j < 8; j++)
3374 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3375
3376 for (j = 0; j < 5; j++)
3377 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3378
3379 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3380 for (j = 0; j < 8; j++)
3381 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3382 }
3383
3384 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3385 for (j = 0; j < 8; j++)
3386 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3387
3388 for (j = 0; j < 8; j++)
3389 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3390
3391 for (j = 0; j < 8; j++)
3392 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3393 }
3394 }
3395
3396 dispc_runtime_put();
3397
3398 #undef DISPC_REG
3399 #undef DUMPREG
3400 }
3401
3402 /* calculate clock rates using dividers in cinfo */
3403 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3404 struct dispc_clock_info *cinfo)
3405 {
3406 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3407 return -EINVAL;
3408 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3409 return -EINVAL;
3410
3411 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3412 cinfo->pck = cinfo->lck / cinfo->pck_div;
3413
3414 return 0;
3415 }
3416
3417 bool dispc_div_calc(unsigned long dispc,
3418 unsigned long pck_min, unsigned long pck_max,
3419 dispc_div_calc_func func, void *data)
3420 {
3421 int lckd, lckd_start, lckd_stop;
3422 int pckd, pckd_start, pckd_stop;
3423 unsigned long pck, lck;
3424 unsigned long lck_max;
3425 unsigned long pckd_hw_min, pckd_hw_max;
3426 unsigned min_fck_per_pck;
3427 unsigned long fck;
3428
3429 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3430 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3431 #else
3432 min_fck_per_pck = 0;
3433 #endif
3434
3435 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3436 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3437
3438 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3439
3440 pck_min = pck_min ? pck_min : 1;
3441 pck_max = pck_max ? pck_max : ULONG_MAX;
3442
3443 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3444 lckd_stop = min(dispc / pck_min, 255ul);
3445
3446 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3447 lck = dispc / lckd;
3448
3449 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3450 pckd_stop = min(lck / pck_min, pckd_hw_max);
3451
3452 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3453 pck = lck / pckd;
3454
3455 /*
3456 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3457 * clock, which means we're configuring DISPC fclk here
3458 * also. Thus we need to use the calculated lck. For
3459 * OMAP4+ the DISPC fclk is a separate clock.
3460 */
3461 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3462 fck = dispc_core_clk_rate();
3463 else
3464 fck = lck;
3465
3466 if (fck < pck * min_fck_per_pck)
3467 continue;
3468
3469 if (func(lckd, pckd, lck, pck, data))
3470 return true;
3471 }
3472 }
3473
3474 return false;
3475 }
3476
3477 void dispc_mgr_set_clock_div(enum omap_channel channel,
3478 const struct dispc_clock_info *cinfo)
3479 {
3480 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3481 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3482
3483 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3484 }
3485
3486 int dispc_mgr_get_clock_div(enum omap_channel channel,
3487 struct dispc_clock_info *cinfo)
3488 {
3489 unsigned long fck;
3490
3491 fck = dispc_fclk_rate();
3492
3493 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3494 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3495
3496 cinfo->lck = fck / cinfo->lck_div;
3497 cinfo->pck = cinfo->lck / cinfo->pck_div;
3498
3499 return 0;
3500 }
3501
3502 u32 dispc_read_irqstatus(void)
3503 {
3504 return dispc_read_reg(DISPC_IRQSTATUS);
3505 }
3506 EXPORT_SYMBOL(dispc_read_irqstatus);
3507
3508 void dispc_clear_irqstatus(u32 mask)
3509 {
3510 dispc_write_reg(DISPC_IRQSTATUS, mask);
3511 }
3512 EXPORT_SYMBOL(dispc_clear_irqstatus);
3513
3514 u32 dispc_read_irqenable(void)
3515 {
3516 return dispc_read_reg(DISPC_IRQENABLE);
3517 }
3518 EXPORT_SYMBOL(dispc_read_irqenable);
3519
3520 void dispc_write_irqenable(u32 mask)
3521 {
3522 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3523
3524 /* clear the irqstatus for newly enabled irqs */
3525 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3526
3527 dispc_write_reg(DISPC_IRQENABLE, mask);
3528 }
3529 EXPORT_SYMBOL(dispc_write_irqenable);
3530
3531 void dispc_enable_sidle(void)
3532 {
3533 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3534 }
3535
3536 void dispc_disable_sidle(void)
3537 {
3538 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3539 }
3540
3541 static void _omap_dispc_initial_config(void)
3542 {
3543 u32 l;
3544
3545 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3546 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3547 l = dispc_read_reg(DISPC_DIVISOR);
3548 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3549 l = FLD_MOD(l, 1, 0, 0);
3550 l = FLD_MOD(l, 1, 23, 16);
3551 dispc_write_reg(DISPC_DIVISOR, l);
3552
3553 dispc.core_clk_rate = dispc_fclk_rate();
3554 }
3555
3556 /* FUNCGATED */
3557 if (dss_has_feature(FEAT_FUNCGATED))
3558 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3559
3560 dispc_setup_color_conv_coef();
3561
3562 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3563
3564 dispc_init_fifos();
3565
3566 dispc_configure_burst_sizes();
3567
3568 dispc_ovl_enable_zorder_planes();
3569
3570 if (dispc.feat->mstandby_workaround)
3571 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3572 }
3573
3574 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3575 .sw_start = 5,
3576 .fp_start = 15,
3577 .bp_start = 27,
3578 .sw_max = 64,
3579 .vp_max = 255,
3580 .hp_max = 256,
3581 .mgr_width_start = 10,
3582 .mgr_height_start = 26,
3583 .mgr_width_max = 2048,
3584 .mgr_height_max = 2048,
3585 .max_lcd_pclk = 66500000,
3586 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3587 .calc_core_clk = calc_core_clk_24xx,
3588 .num_fifos = 3,
3589 .no_framedone_tv = true,
3590 .set_max_preload = false,
3591 };
3592
3593 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3594 .sw_start = 5,
3595 .fp_start = 15,
3596 .bp_start = 27,
3597 .sw_max = 64,
3598 .vp_max = 255,
3599 .hp_max = 256,
3600 .mgr_width_start = 10,
3601 .mgr_height_start = 26,
3602 .mgr_width_max = 2048,
3603 .mgr_height_max = 2048,
3604 .max_lcd_pclk = 173000000,
3605 .max_tv_pclk = 59000000,
3606 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3607 .calc_core_clk = calc_core_clk_34xx,
3608 .num_fifos = 3,
3609 .no_framedone_tv = true,
3610 .set_max_preload = false,
3611 };
3612
3613 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3614 .sw_start = 7,
3615 .fp_start = 19,
3616 .bp_start = 31,
3617 .sw_max = 256,
3618 .vp_max = 4095,
3619 .hp_max = 4096,
3620 .mgr_width_start = 10,
3621 .mgr_height_start = 26,
3622 .mgr_width_max = 2048,
3623 .mgr_height_max = 2048,
3624 .max_lcd_pclk = 173000000,
3625 .max_tv_pclk = 59000000,
3626 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3627 .calc_core_clk = calc_core_clk_34xx,
3628 .num_fifos = 3,
3629 .no_framedone_tv = true,
3630 .set_max_preload = false,
3631 };
3632
3633 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3634 .sw_start = 7,
3635 .fp_start = 19,
3636 .bp_start = 31,
3637 .sw_max = 256,
3638 .vp_max = 4095,
3639 .hp_max = 4096,
3640 .mgr_width_start = 10,
3641 .mgr_height_start = 26,
3642 .mgr_width_max = 2048,
3643 .mgr_height_max = 2048,
3644 .max_lcd_pclk = 170000000,
3645 .max_tv_pclk = 185625000,
3646 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3647 .calc_core_clk = calc_core_clk_44xx,
3648 .num_fifos = 5,
3649 .gfx_fifo_workaround = true,
3650 .set_max_preload = true,
3651 };
3652
3653 static const struct dispc_features omap54xx_dispc_feats __initconst = {
3654 .sw_start = 7,
3655 .fp_start = 19,
3656 .bp_start = 31,
3657 .sw_max = 256,
3658 .vp_max = 4095,
3659 .hp_max = 4096,
3660 .mgr_width_start = 11,
3661 .mgr_height_start = 27,
3662 .mgr_width_max = 4096,
3663 .mgr_height_max = 4096,
3664 .max_lcd_pclk = 170000000,
3665 .max_tv_pclk = 186000000,
3666 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3667 .calc_core_clk = calc_core_clk_44xx,
3668 .num_fifos = 5,
3669 .gfx_fifo_workaround = true,
3670 .mstandby_workaround = true,
3671 .set_max_preload = true,
3672 };
3673
3674 static int __init dispc_init_features(struct platform_device *pdev)
3675 {
3676 const struct dispc_features *src;
3677 struct dispc_features *dst;
3678
3679 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3680 if (!dst) {
3681 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3682 return -ENOMEM;
3683 }
3684
3685 switch (omapdss_get_version()) {
3686 case OMAPDSS_VER_OMAP24xx:
3687 src = &omap24xx_dispc_feats;
3688 break;
3689
3690 case OMAPDSS_VER_OMAP34xx_ES1:
3691 src = &omap34xx_rev1_0_dispc_feats;
3692 break;
3693
3694 case OMAPDSS_VER_OMAP34xx_ES3:
3695 case OMAPDSS_VER_OMAP3630:
3696 case OMAPDSS_VER_AM35xx:
3697 case OMAPDSS_VER_AM43xx:
3698 src = &omap34xx_rev3_0_dispc_feats;
3699 break;
3700
3701 case OMAPDSS_VER_OMAP4430_ES1:
3702 case OMAPDSS_VER_OMAP4430_ES2:
3703 case OMAPDSS_VER_OMAP4:
3704 src = &omap44xx_dispc_feats;
3705 break;
3706
3707 case OMAPDSS_VER_OMAP5:
3708 case OMAPDSS_VER_DRA7xx:
3709 src = &omap54xx_dispc_feats;
3710 break;
3711
3712 default:
3713 return -ENODEV;
3714 }
3715
3716 memcpy(dst, src, sizeof(*dst));
3717 dispc.feat = dst;
3718
3719 return 0;
3720 }
3721
3722 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3723 {
3724 if (!dispc.is_enabled)
3725 return IRQ_NONE;
3726
3727 return dispc.user_handler(irq, dispc.user_data);
3728 }
3729
3730 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3731 {
3732 int r;
3733
3734 if (dispc.user_handler != NULL)
3735 return -EBUSY;
3736
3737 dispc.user_handler = handler;
3738 dispc.user_data = dev_id;
3739
3740 /* ensure the dispc_irq_handler sees the values above */
3741 smp_wmb();
3742
3743 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3744 IRQF_SHARED, "OMAP DISPC", &dispc);
3745 if (r) {
3746 dispc.user_handler = NULL;
3747 dispc.user_data = NULL;
3748 }
3749
3750 return r;
3751 }
3752 EXPORT_SYMBOL(dispc_request_irq);
3753
3754 void dispc_free_irq(void *dev_id)
3755 {
3756 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3757
3758 dispc.user_handler = NULL;
3759 dispc.user_data = NULL;
3760 }
3761 EXPORT_SYMBOL(dispc_free_irq);
3762
3763 /* DISPC HW IP initialisation */
3764 static int __init omap_dispchw_probe(struct platform_device *pdev)
3765 {
3766 u32 rev;
3767 int r = 0;
3768 struct resource *dispc_mem;
3769 struct device_node *np = pdev->dev.of_node;
3770
3771 dispc.pdev = pdev;
3772
3773 r = dispc_init_features(dispc.pdev);
3774 if (r)
3775 return r;
3776
3777 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3778 if (!dispc_mem) {
3779 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3780 return -EINVAL;
3781 }
3782
3783 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3784 resource_size(dispc_mem));
3785 if (!dispc.base) {
3786 DSSERR("can't ioremap DISPC\n");
3787 return -ENOMEM;
3788 }
3789
3790 dispc.irq = platform_get_irq(dispc.pdev, 0);
3791 if (dispc.irq < 0) {
3792 DSSERR("platform_get_irq failed\n");
3793 return -ENODEV;
3794 }
3795
3796 if (np && of_property_read_bool(np, "syscon-pol")) {
3797 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3798 if (IS_ERR(dispc.syscon_pol)) {
3799 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3800 return PTR_ERR(dispc.syscon_pol);
3801 }
3802
3803 if (of_property_read_u32_index(np, "syscon-pol", 1,
3804 &dispc.syscon_pol_offset)) {
3805 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3806 return -EINVAL;
3807 }
3808 }
3809
3810 pm_runtime_enable(&pdev->dev);
3811
3812 r = dispc_runtime_get();
3813 if (r)
3814 goto err_runtime_get;
3815
3816 _omap_dispc_initial_config();
3817
3818 rev = dispc_read_reg(DISPC_REVISION);
3819 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3820 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3821
3822 dispc_runtime_put();
3823
3824 dss_init_overlay_managers();
3825
3826 dss_debugfs_create_file("dispc", dispc_dump_regs);
3827
3828 return 0;
3829
3830 err_runtime_get:
3831 pm_runtime_disable(&pdev->dev);
3832 return r;
3833 }
3834
3835 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3836 {
3837 pm_runtime_disable(&pdev->dev);
3838
3839 dss_uninit_overlay_managers();
3840
3841 return 0;
3842 }
3843
3844 static int dispc_runtime_suspend(struct device *dev)
3845 {
3846 dispc.is_enabled = false;
3847 /* ensure the dispc_irq_handler sees the is_enabled value */
3848 smp_wmb();
3849 /* wait for current handler to finish before turning the DISPC off */
3850 synchronize_irq(dispc.irq);
3851
3852 dispc_save_context();
3853
3854 return 0;
3855 }
3856
3857 static int dispc_runtime_resume(struct device *dev)
3858 {
3859 /*
3860 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3861 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3862 * _omap_dispc_initial_config(). We can thus use it to detect if
3863 * we have lost register context.
3864 */
3865 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
3866 _omap_dispc_initial_config();
3867
3868 dispc_restore_context();
3869 }
3870
3871 dispc.is_enabled = true;
3872 /* ensure the dispc_irq_handler sees the is_enabled value */
3873 smp_wmb();
3874
3875 return 0;
3876 }
3877
3878 static const struct dev_pm_ops dispc_pm_ops = {
3879 .runtime_suspend = dispc_runtime_suspend,
3880 .runtime_resume = dispc_runtime_resume,
3881 };
3882
3883 static const struct of_device_id dispc_of_match[] = {
3884 { .compatible = "ti,omap2-dispc", },
3885 { .compatible = "ti,omap3-dispc", },
3886 { .compatible = "ti,omap4-dispc", },
3887 { .compatible = "ti,omap5-dispc", },
3888 { .compatible = "ti,dra7-dispc", },
3889 {},
3890 };
3891
3892 static struct platform_driver omap_dispchw_driver = {
3893 .remove = __exit_p(omap_dispchw_remove),
3894 .driver = {
3895 .name = "omapdss_dispc",
3896 .pm = &dispc_pm_ops,
3897 .of_match_table = dispc_of_match,
3898 .suppress_bind_attrs = true,
3899 },
3900 };
3901
3902 int __init dispc_init_platform_driver(void)
3903 {
3904 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3905 }
3906
3907 void __exit dispc_uninit_platform_driver(void)
3908 {
3909 platform_driver_unregister(&omap_dispchw_driver);
3910 }
Linux kernel - Deliverables
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