2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/sizes.h>
39 #include <linux/mfd/syscon.h>
40 #include <linux/regmap.h>
43 #include <video/omapdss.h>
46 #include "dss_features.h"
50 #define DISPC_SZ_REGS SZ_4K
52 enum omap_burst_size
{
58 #define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
61 #define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64 struct dispc_features
{
75 unsigned long max_lcd_pclk
;
76 unsigned long max_tv_pclk
;
77 int (*calc_scaling
) (unsigned long pclk
, unsigned long lclk
,
78 const struct omap_video_timings
*mgr_timings
,
79 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
80 enum omap_color_mode color_mode
, bool *five_taps
,
81 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
82 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
);
83 unsigned long (*calc_core_clk
) (unsigned long pclk
,
84 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround
:1;
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv
:1;
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround
:1;
97 bool set_max_preload
:1;
100 #define DISPC_MAX_NR_FIFOS 5
103 struct platform_device
*pdev
;
107 irq_handler_t user_handler
;
110 unsigned long core_clk_rate
;
111 unsigned long tv_pclk_rate
;
113 u32 fifo_size
[DISPC_MAX_NR_FIFOS
];
114 /* maps which plane is using a fifo. fifo-id -> plane-id */
115 int fifo_assignment
[DISPC_MAX_NR_FIFOS
];
118 u32 ctx
[DISPC_SZ_REGS
/ sizeof(u32
)];
120 const struct dispc_features
*feat
;
124 struct regmap
*syscon_pol
;
125 u32 syscon_pol_offset
;
128 enum omap_color_component
{
129 /* used for all color formats for OMAP3 and earlier
130 * and for RGB and Y color component on OMAP4
132 DISPC_COLOR_COMPONENT_RGB_Y
= 1 << 0,
133 /* used for UV component for
134 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
135 * color formats on OMAP4
137 DISPC_COLOR_COMPONENT_UV
= 1 << 1,
140 enum mgr_reg_fields
{
141 DISPC_MGR_FLD_ENABLE
,
142 DISPC_MGR_FLD_STNTFT
,
144 DISPC_MGR_FLD_TFTDATALINES
,
145 DISPC_MGR_FLD_STALLMODE
,
146 DISPC_MGR_FLD_TCKENABLE
,
147 DISPC_MGR_FLD_TCKSELECTION
,
149 DISPC_MGR_FLD_FIFOHANDCHECK
,
150 /* used to maintain a count of the above fields */
154 struct dispc_reg_field
{
160 static const struct {
165 struct dispc_reg_field reg_desc
[DISPC_MGR_FLD_NUM
];
167 [OMAP_DSS_CHANNEL_LCD
] = {
169 .vsync_irq
= DISPC_IRQ_VSYNC
,
170 .framedone_irq
= DISPC_IRQ_FRAMEDONE
,
171 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST
,
173 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL
, 0, 0 },
174 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL
, 3, 3 },
175 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL
, 5, 5 },
176 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL
, 9, 8 },
177 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL
, 11, 11 },
178 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG
, 10, 10 },
179 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG
, 11, 11 },
180 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG
, 15, 15 },
181 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG
, 16, 16 },
184 [OMAP_DSS_CHANNEL_DIGIT
] = {
186 .vsync_irq
= DISPC_IRQ_EVSYNC_ODD
| DISPC_IRQ_EVSYNC_EVEN
,
187 .framedone_irq
= DISPC_IRQ_FRAMEDONETV
,
188 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST_DIGIT
,
190 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL
, 1, 1 },
191 [DISPC_MGR_FLD_STNTFT
] = { },
192 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL
, 6, 6 },
193 [DISPC_MGR_FLD_TFTDATALINES
] = { },
194 [DISPC_MGR_FLD_STALLMODE
] = { },
195 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG
, 12, 12 },
196 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG
, 13, 13 },
197 [DISPC_MGR_FLD_CPR
] = { },
198 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG
, 16, 16 },
201 [OMAP_DSS_CHANNEL_LCD2
] = {
203 .vsync_irq
= DISPC_IRQ_VSYNC2
,
204 .framedone_irq
= DISPC_IRQ_FRAMEDONE2
,
205 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST2
,
207 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL2
, 0, 0 },
208 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL2
, 3, 3 },
209 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL2
, 5, 5 },
210 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL2
, 9, 8 },
211 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL2
, 11, 11 },
212 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG2
, 10, 10 },
213 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG2
, 11, 11 },
214 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG2
, 15, 15 },
215 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG2
, 16, 16 },
218 [OMAP_DSS_CHANNEL_LCD3
] = {
220 .vsync_irq
= DISPC_IRQ_VSYNC3
,
221 .framedone_irq
= DISPC_IRQ_FRAMEDONE3
,
222 .sync_lost_irq
= DISPC_IRQ_SYNC_LOST3
,
224 [DISPC_MGR_FLD_ENABLE
] = { DISPC_CONTROL3
, 0, 0 },
225 [DISPC_MGR_FLD_STNTFT
] = { DISPC_CONTROL3
, 3, 3 },
226 [DISPC_MGR_FLD_GO
] = { DISPC_CONTROL3
, 5, 5 },
227 [DISPC_MGR_FLD_TFTDATALINES
] = { DISPC_CONTROL3
, 9, 8 },
228 [DISPC_MGR_FLD_STALLMODE
] = { DISPC_CONTROL3
, 11, 11 },
229 [DISPC_MGR_FLD_TCKENABLE
] = { DISPC_CONFIG3
, 10, 10 },
230 [DISPC_MGR_FLD_TCKSELECTION
] = { DISPC_CONFIG3
, 11, 11 },
231 [DISPC_MGR_FLD_CPR
] = { DISPC_CONFIG3
, 15, 15 },
232 [DISPC_MGR_FLD_FIFOHANDCHECK
] = { DISPC_CONFIG3
, 16, 16 },
237 struct color_conv_coef
{
238 int ry
, rcr
, rcb
, gy
, gcr
, gcb
, by
, bcr
, bcb
;
242 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane
);
243 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane
);
245 static inline void dispc_write_reg(const u16 idx
, u32 val
)
247 __raw_writel(val
, dispc
.base
+ idx
);
250 static inline u32
dispc_read_reg(const u16 idx
)
252 return __raw_readl(dispc
.base
+ idx
);
255 static u32
mgr_fld_read(enum omap_channel channel
, enum mgr_reg_fields regfld
)
257 const struct dispc_reg_field rfld
= mgr_desc
[channel
].reg_desc
[regfld
];
258 return REG_GET(rfld
.reg
, rfld
.high
, rfld
.low
);
261 static void mgr_fld_write(enum omap_channel channel
,
262 enum mgr_reg_fields regfld
, int val
) {
263 const struct dispc_reg_field rfld
= mgr_desc
[channel
].reg_desc
[regfld
];
264 REG_FLD_MOD(rfld
.reg
, val
, rfld
.high
, rfld
.low
);
268 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
270 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
272 static void dispc_save_context(void)
276 DSSDBG("dispc_save_context\n");
282 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
283 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
285 if (dss_has_feature(FEAT_MGR_LCD2
)) {
289 if (dss_has_feature(FEAT_MGR_LCD3
)) {
294 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
295 SR(DEFAULT_COLOR(i
));
298 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
309 if (dss_has_feature(FEAT_CPR
)) {
316 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
321 SR(OVL_ATTRIBUTES(i
));
322 SR(OVL_FIFO_THRESHOLD(i
));
324 SR(OVL_PIXEL_INC(i
));
325 if (dss_has_feature(FEAT_PRELOAD
))
327 if (i
== OMAP_DSS_GFX
) {
328 SR(OVL_WINDOW_SKIP(i
));
333 SR(OVL_PICTURE_SIZE(i
));
337 for (j
= 0; j
< 8; j
++)
338 SR(OVL_FIR_COEF_H(i
, j
));
340 for (j
= 0; j
< 8; j
++)
341 SR(OVL_FIR_COEF_HV(i
, j
));
343 for (j
= 0; j
< 5; j
++)
344 SR(OVL_CONV_COEF(i
, j
));
346 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
347 for (j
= 0; j
< 8; j
++)
348 SR(OVL_FIR_COEF_V(i
, j
));
351 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
358 for (j
= 0; j
< 8; j
++)
359 SR(OVL_FIR_COEF_H2(i
, j
));
361 for (j
= 0; j
< 8; j
++)
362 SR(OVL_FIR_COEF_HV2(i
, j
));
364 for (j
= 0; j
< 8; j
++)
365 SR(OVL_FIR_COEF_V2(i
, j
));
367 if (dss_has_feature(FEAT_ATTR2
))
368 SR(OVL_ATTRIBUTES2(i
));
371 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
374 dispc
.ctx_valid
= true;
376 DSSDBG("context saved\n");
379 static void dispc_restore_context(void)
383 DSSDBG("dispc_restore_context\n");
385 if (!dispc
.ctx_valid
)
392 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
393 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
395 if (dss_has_feature(FEAT_MGR_LCD2
))
397 if (dss_has_feature(FEAT_MGR_LCD3
))
400 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
401 RR(DEFAULT_COLOR(i
));
404 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
415 if (dss_has_feature(FEAT_CPR
)) {
422 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
427 RR(OVL_ATTRIBUTES(i
));
428 RR(OVL_FIFO_THRESHOLD(i
));
430 RR(OVL_PIXEL_INC(i
));
431 if (dss_has_feature(FEAT_PRELOAD
))
433 if (i
== OMAP_DSS_GFX
) {
434 RR(OVL_WINDOW_SKIP(i
));
439 RR(OVL_PICTURE_SIZE(i
));
443 for (j
= 0; j
< 8; j
++)
444 RR(OVL_FIR_COEF_H(i
, j
));
446 for (j
= 0; j
< 8; j
++)
447 RR(OVL_FIR_COEF_HV(i
, j
));
449 for (j
= 0; j
< 5; j
++)
450 RR(OVL_CONV_COEF(i
, j
));
452 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
453 for (j
= 0; j
< 8; j
++)
454 RR(OVL_FIR_COEF_V(i
, j
));
457 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
464 for (j
= 0; j
< 8; j
++)
465 RR(OVL_FIR_COEF_H2(i
, j
));
467 for (j
= 0; j
< 8; j
++)
468 RR(OVL_FIR_COEF_HV2(i
, j
));
470 for (j
= 0; j
< 8; j
++)
471 RR(OVL_FIR_COEF_V2(i
, j
));
473 if (dss_has_feature(FEAT_ATTR2
))
474 RR(OVL_ATTRIBUTES2(i
));
477 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
480 /* enable last, because LCD & DIGIT enable are here */
482 if (dss_has_feature(FEAT_MGR_LCD2
))
484 if (dss_has_feature(FEAT_MGR_LCD3
))
486 /* clear spurious SYNC_LOST_DIGIT interrupts */
487 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT
);
490 * enable last so IRQs won't trigger before
491 * the context is fully restored
495 DSSDBG("context restored\n");
501 int dispc_runtime_get(void)
505 DSSDBG("dispc_runtime_get\n");
507 r
= pm_runtime_get_sync(&dispc
.pdev
->dev
);
509 return r
< 0 ? r
: 0;
511 EXPORT_SYMBOL(dispc_runtime_get
);
513 void dispc_runtime_put(void)
517 DSSDBG("dispc_runtime_put\n");
519 r
= pm_runtime_put_sync(&dispc
.pdev
->dev
);
520 WARN_ON(r
< 0 && r
!= -ENOSYS
);
522 EXPORT_SYMBOL(dispc_runtime_put
);
524 u32
dispc_mgr_get_vsync_irq(enum omap_channel channel
)
526 return mgr_desc
[channel
].vsync_irq
;
528 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq
);
530 u32
dispc_mgr_get_framedone_irq(enum omap_channel channel
)
532 if (channel
== OMAP_DSS_CHANNEL_DIGIT
&& dispc
.feat
->no_framedone_tv
)
535 return mgr_desc
[channel
].framedone_irq
;
537 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq
);
539 u32
dispc_mgr_get_sync_lost_irq(enum omap_channel channel
)
541 return mgr_desc
[channel
].sync_lost_irq
;
543 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq
);
545 u32
dispc_wb_get_framedone_irq(void)
547 return DISPC_IRQ_FRAMEDONEWB
;
550 bool dispc_mgr_go_busy(enum omap_channel channel
)
552 return mgr_fld_read(channel
, DISPC_MGR_FLD_GO
) == 1;
554 EXPORT_SYMBOL(dispc_mgr_go_busy
);
556 void dispc_mgr_go(enum omap_channel channel
)
558 WARN_ON(dispc_mgr_is_enabled(channel
) == false);
559 WARN_ON(dispc_mgr_go_busy(channel
));
561 DSSDBG("GO %s\n", mgr_desc
[channel
].name
);
563 mgr_fld_write(channel
, DISPC_MGR_FLD_GO
, 1);
565 EXPORT_SYMBOL(dispc_mgr_go
);
567 bool dispc_wb_go_busy(void)
569 return REG_GET(DISPC_CONTROL2
, 6, 6) == 1;
572 void dispc_wb_go(void)
574 enum omap_plane plane
= OMAP_DSS_WB
;
577 enable
= REG_GET(DISPC_OVL_ATTRIBUTES(plane
), 0, 0) == 1;
582 go
= REG_GET(DISPC_CONTROL2
, 6, 6) == 1;
584 DSSERR("GO bit not down for WB\n");
588 REG_FLD_MOD(DISPC_CONTROL2
, 1, 6, 6);
591 static void dispc_ovl_write_firh_reg(enum omap_plane plane
, int reg
, u32 value
)
593 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane
, reg
), value
);
596 static void dispc_ovl_write_firhv_reg(enum omap_plane plane
, int reg
, u32 value
)
598 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane
, reg
), value
);
601 static void dispc_ovl_write_firv_reg(enum omap_plane plane
, int reg
, u32 value
)
603 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane
, reg
), value
);
606 static void dispc_ovl_write_firh2_reg(enum omap_plane plane
, int reg
, u32 value
)
608 BUG_ON(plane
== OMAP_DSS_GFX
);
610 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane
, reg
), value
);
613 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane
, int reg
,
616 BUG_ON(plane
== OMAP_DSS_GFX
);
618 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane
, reg
), value
);
621 static void dispc_ovl_write_firv2_reg(enum omap_plane plane
, int reg
, u32 value
)
623 BUG_ON(plane
== OMAP_DSS_GFX
);
625 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane
, reg
), value
);
628 static void dispc_ovl_set_scale_coef(enum omap_plane plane
, int fir_hinc
,
629 int fir_vinc
, int five_taps
,
630 enum omap_color_component color_comp
)
632 const struct dispc_coef
*h_coef
, *v_coef
;
635 h_coef
= dispc_ovl_get_scale_coef(fir_hinc
, true);
636 v_coef
= dispc_ovl_get_scale_coef(fir_vinc
, five_taps
);
638 for (i
= 0; i
< 8; i
++) {
641 h
= FLD_VAL(h_coef
[i
].hc0_vc00
, 7, 0)
642 | FLD_VAL(h_coef
[i
].hc1_vc0
, 15, 8)
643 | FLD_VAL(h_coef
[i
].hc2_vc1
, 23, 16)
644 | FLD_VAL(h_coef
[i
].hc3_vc2
, 31, 24);
645 hv
= FLD_VAL(h_coef
[i
].hc4_vc22
, 7, 0)
646 | FLD_VAL(v_coef
[i
].hc1_vc0
, 15, 8)
647 | FLD_VAL(v_coef
[i
].hc2_vc1
, 23, 16)
648 | FLD_VAL(v_coef
[i
].hc3_vc2
, 31, 24);
650 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
) {
651 dispc_ovl_write_firh_reg(plane
, i
, h
);
652 dispc_ovl_write_firhv_reg(plane
, i
, hv
);
654 dispc_ovl_write_firh2_reg(plane
, i
, h
);
655 dispc_ovl_write_firhv2_reg(plane
, i
, hv
);
661 for (i
= 0; i
< 8; i
++) {
663 v
= FLD_VAL(v_coef
[i
].hc0_vc00
, 7, 0)
664 | FLD_VAL(v_coef
[i
].hc4_vc22
, 15, 8);
665 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
)
666 dispc_ovl_write_firv_reg(plane
, i
, v
);
668 dispc_ovl_write_firv2_reg(plane
, i
, v
);
674 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane
,
675 const struct color_conv_coef
*ct
)
677 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
679 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 0), CVAL(ct
->rcr
, ct
->ry
));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 1), CVAL(ct
->gy
, ct
->rcb
));
681 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 2), CVAL(ct
->gcb
, ct
->gcr
));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 3), CVAL(ct
->bcr
, ct
->by
));
683 dispc_write_reg(DISPC_OVL_CONV_COEF(plane
, 4), CVAL(0, ct
->bcb
));
685 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), ct
->full_range
, 11, 11);
690 static void dispc_setup_color_conv_coef(void)
693 int num_ovl
= dss_feat_get_num_ovls();
694 int num_wb
= dss_feat_get_num_wbs();
695 const struct color_conv_coef ctbl_bt601_5_ovl
= {
696 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
698 const struct color_conv_coef ctbl_bt601_5_wb
= {
699 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
702 for (i
= 1; i
< num_ovl
; i
++)
703 dispc_ovl_write_color_conv_coef(i
, &ctbl_bt601_5_ovl
);
705 for (; i
< num_wb
; i
++)
706 dispc_ovl_write_color_conv_coef(i
, &ctbl_bt601_5_wb
);
709 static void dispc_ovl_set_ba0(enum omap_plane plane
, u32 paddr
)
711 dispc_write_reg(DISPC_OVL_BA0(plane
), paddr
);
714 static void dispc_ovl_set_ba1(enum omap_plane plane
, u32 paddr
)
716 dispc_write_reg(DISPC_OVL_BA1(plane
), paddr
);
719 static void dispc_ovl_set_ba0_uv(enum omap_plane plane
, u32 paddr
)
721 dispc_write_reg(DISPC_OVL_BA0_UV(plane
), paddr
);
724 static void dispc_ovl_set_ba1_uv(enum omap_plane plane
, u32 paddr
)
726 dispc_write_reg(DISPC_OVL_BA1_UV(plane
), paddr
);
729 static void dispc_ovl_set_pos(enum omap_plane plane
,
730 enum omap_overlay_caps caps
, int x
, int y
)
734 if ((caps
& OMAP_DSS_OVL_CAP_POS
) == 0)
737 val
= FLD_VAL(y
, 26, 16) | FLD_VAL(x
, 10, 0);
739 dispc_write_reg(DISPC_OVL_POSITION(plane
), val
);
742 static void dispc_ovl_set_input_size(enum omap_plane plane
, int width
,
745 u32 val
= FLD_VAL(height
- 1, 26, 16) | FLD_VAL(width
- 1, 10, 0);
747 if (plane
== OMAP_DSS_GFX
|| plane
== OMAP_DSS_WB
)
748 dispc_write_reg(DISPC_OVL_SIZE(plane
), val
);
750 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane
), val
);
753 static void dispc_ovl_set_output_size(enum omap_plane plane
, int width
,
758 BUG_ON(plane
== OMAP_DSS_GFX
);
760 val
= FLD_VAL(height
- 1, 26, 16) | FLD_VAL(width
- 1, 10, 0);
762 if (plane
== OMAP_DSS_WB
)
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane
), val
);
765 dispc_write_reg(DISPC_OVL_SIZE(plane
), val
);
768 static void dispc_ovl_set_zorder(enum omap_plane plane
,
769 enum omap_overlay_caps caps
, u8 zorder
)
771 if ((caps
& OMAP_DSS_OVL_CAP_ZORDER
) == 0)
774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), zorder
, 27, 26);
777 static void dispc_ovl_enable_zorder_planes(void)
781 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
784 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++)
785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i
), 1, 25, 25);
788 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane
,
789 enum omap_overlay_caps caps
, bool enable
)
791 if ((caps
& OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
) == 0)
794 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
? 1 : 0, 28, 28);
797 static void dispc_ovl_setup_global_alpha(enum omap_plane plane
,
798 enum omap_overlay_caps caps
, u8 global_alpha
)
800 static const unsigned shifts
[] = { 0, 8, 16, 24, };
803 if ((caps
& OMAP_DSS_OVL_CAP_GLOBAL_ALPHA
) == 0)
806 shift
= shifts
[plane
];
807 REG_FLD_MOD(DISPC_GLOBAL_ALPHA
, global_alpha
, shift
+ 7, shift
);
810 static void dispc_ovl_set_pix_inc(enum omap_plane plane
, s32 inc
)
812 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane
), inc
);
815 static void dispc_ovl_set_row_inc(enum omap_plane plane
, s32 inc
)
817 dispc_write_reg(DISPC_OVL_ROW_INC(plane
), inc
);
820 static void dispc_ovl_set_color_mode(enum omap_plane plane
,
821 enum omap_color_mode color_mode
)
824 if (plane
!= OMAP_DSS_GFX
) {
825 switch (color_mode
) {
826 case OMAP_DSS_COLOR_NV12
:
828 case OMAP_DSS_COLOR_RGBX16
:
830 case OMAP_DSS_COLOR_RGBA16
:
832 case OMAP_DSS_COLOR_RGB12U
:
834 case OMAP_DSS_COLOR_ARGB16
:
836 case OMAP_DSS_COLOR_RGB16
:
838 case OMAP_DSS_COLOR_ARGB16_1555
:
840 case OMAP_DSS_COLOR_RGB24U
:
842 case OMAP_DSS_COLOR_RGB24P
:
844 case OMAP_DSS_COLOR_YUV2
:
846 case OMAP_DSS_COLOR_UYVY
:
848 case OMAP_DSS_COLOR_ARGB32
:
850 case OMAP_DSS_COLOR_RGBA32
:
852 case OMAP_DSS_COLOR_RGBX32
:
854 case OMAP_DSS_COLOR_XRGB16_1555
:
860 switch (color_mode
) {
861 case OMAP_DSS_COLOR_CLUT1
:
863 case OMAP_DSS_COLOR_CLUT2
:
865 case OMAP_DSS_COLOR_CLUT4
:
867 case OMAP_DSS_COLOR_CLUT8
:
869 case OMAP_DSS_COLOR_RGB12U
:
871 case OMAP_DSS_COLOR_ARGB16
:
873 case OMAP_DSS_COLOR_RGB16
:
875 case OMAP_DSS_COLOR_ARGB16_1555
:
877 case OMAP_DSS_COLOR_RGB24U
:
879 case OMAP_DSS_COLOR_RGB24P
:
881 case OMAP_DSS_COLOR_RGBX16
:
883 case OMAP_DSS_COLOR_RGBA16
:
885 case OMAP_DSS_COLOR_ARGB32
:
887 case OMAP_DSS_COLOR_RGBA32
:
889 case OMAP_DSS_COLOR_RGBX32
:
891 case OMAP_DSS_COLOR_XRGB16_1555
:
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), m
, 4, 1);
901 static void dispc_ovl_configure_burst_type(enum omap_plane plane
,
902 enum omap_dss_rotation_type rotation_type
)
904 if (dss_has_feature(FEAT_BURST_2D
) == 0)
907 if (rotation_type
== OMAP_DSS_ROT_TILER
)
908 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), 1, 29, 29);
910 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), 0, 29, 29);
913 void dispc_ovl_set_channel_out(enum omap_plane plane
, enum omap_channel channel
)
917 int chan
= 0, chan2
= 0;
923 case OMAP_DSS_VIDEO1
:
924 case OMAP_DSS_VIDEO2
:
925 case OMAP_DSS_VIDEO3
:
933 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
934 if (dss_has_feature(FEAT_MGR_LCD2
)) {
936 case OMAP_DSS_CHANNEL_LCD
:
940 case OMAP_DSS_CHANNEL_DIGIT
:
944 case OMAP_DSS_CHANNEL_LCD2
:
948 case OMAP_DSS_CHANNEL_LCD3
:
949 if (dss_has_feature(FEAT_MGR_LCD3
)) {
962 val
= FLD_MOD(val
, chan
, shift
, shift
);
963 val
= FLD_MOD(val
, chan2
, 31, 30);
965 val
= FLD_MOD(val
, channel
, shift
, shift
);
967 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), val
);
969 EXPORT_SYMBOL(dispc_ovl_set_channel_out
);
971 static enum omap_channel
dispc_ovl_get_channel_out(enum omap_plane plane
)
975 enum omap_channel channel
;
981 case OMAP_DSS_VIDEO1
:
982 case OMAP_DSS_VIDEO2
:
983 case OMAP_DSS_VIDEO3
:
991 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
993 if (dss_has_feature(FEAT_MGR_LCD3
)) {
994 if (FLD_GET(val
, 31, 30) == 0)
995 channel
= FLD_GET(val
, shift
, shift
);
996 else if (FLD_GET(val
, 31, 30) == 1)
997 channel
= OMAP_DSS_CHANNEL_LCD2
;
999 channel
= OMAP_DSS_CHANNEL_LCD3
;
1000 } else if (dss_has_feature(FEAT_MGR_LCD2
)) {
1001 if (FLD_GET(val
, 31, 30) == 0)
1002 channel
= FLD_GET(val
, shift
, shift
);
1004 channel
= OMAP_DSS_CHANNEL_LCD2
;
1006 channel
= FLD_GET(val
, shift
, shift
);
1012 void dispc_wb_set_channel_in(enum dss_writeback_channel channel
)
1014 enum omap_plane plane
= OMAP_DSS_WB
;
1016 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), channel
, 18, 16);
1019 static void dispc_ovl_set_burst_size(enum omap_plane plane
,
1020 enum omap_burst_size burst_size
)
1022 static const unsigned shifts
[] = { 6, 14, 14, 14, 14, };
1025 shift
= shifts
[plane
];
1026 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), burst_size
, shift
+ 1, shift
);
1029 static void dispc_configure_burst_sizes(void)
1032 const int burst_size
= BURST_SIZE_X8
;
1034 /* Configure burst size always to maximum size */
1035 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
)
1036 dispc_ovl_set_burst_size(i
, burst_size
);
1039 static u32
dispc_ovl_get_burst_size(enum omap_plane plane
)
1041 unsigned unit
= dss_feat_get_burst_size_unit();
1042 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1046 void dispc_enable_gamma_table(bool enable
)
1049 * This is partially implemented to support only disabling of
1053 DSSWARN("Gamma table enabling for TV not yet supported");
1057 REG_FLD_MOD(DISPC_CONFIG
, enable
, 9, 9);
1060 static void dispc_mgr_enable_cpr(enum omap_channel channel
, bool enable
)
1062 if (channel
== OMAP_DSS_CHANNEL_DIGIT
)
1065 mgr_fld_write(channel
, DISPC_MGR_FLD_CPR
, enable
);
1068 static void dispc_mgr_set_cpr_coef(enum omap_channel channel
,
1069 const struct omap_dss_cpr_coefs
*coefs
)
1071 u32 coef_r
, coef_g
, coef_b
;
1073 if (!dss_mgr_is_lcd(channel
))
1076 coef_r
= FLD_VAL(coefs
->rr
, 31, 22) | FLD_VAL(coefs
->rg
, 20, 11) |
1077 FLD_VAL(coefs
->rb
, 9, 0);
1078 coef_g
= FLD_VAL(coefs
->gr
, 31, 22) | FLD_VAL(coefs
->gg
, 20, 11) |
1079 FLD_VAL(coefs
->gb
, 9, 0);
1080 coef_b
= FLD_VAL(coefs
->br
, 31, 22) | FLD_VAL(coefs
->bg
, 20, 11) |
1081 FLD_VAL(coefs
->bb
, 9, 0);
1083 dispc_write_reg(DISPC_CPR_COEF_R(channel
), coef_r
);
1084 dispc_write_reg(DISPC_CPR_COEF_G(channel
), coef_g
);
1085 dispc_write_reg(DISPC_CPR_COEF_B(channel
), coef_b
);
1088 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane
, bool enable
)
1092 BUG_ON(plane
== OMAP_DSS_GFX
);
1094 val
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1095 val
= FLD_MOD(val
, enable
, 9, 9);
1096 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), val
);
1099 static void dispc_ovl_enable_replication(enum omap_plane plane
,
1100 enum omap_overlay_caps caps
, bool enable
)
1102 static const unsigned shifts
[] = { 5, 10, 10, 10 };
1105 if ((caps
& OMAP_DSS_OVL_CAP_REPLICATION
) == 0)
1108 shift
= shifts
[plane
];
1109 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
, shift
, shift
);
1112 static void dispc_mgr_set_size(enum omap_channel channel
, u16 width
,
1117 val
= FLD_VAL(height
- 1, dispc
.feat
->mgr_height_start
, 16) |
1118 FLD_VAL(width
- 1, dispc
.feat
->mgr_width_start
, 0);
1120 dispc_write_reg(DISPC_SIZE_MGR(channel
), val
);
1123 static void dispc_init_fifos(void)
1130 unit
= dss_feat_get_buffer_size_unit();
1132 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE
, &start
, &end
);
1134 for (fifo
= 0; fifo
< dispc
.feat
->num_fifos
; ++fifo
) {
1135 size
= REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo
), start
, end
);
1137 dispc
.fifo_size
[fifo
] = size
;
1140 * By default fifos are mapped directly to overlays, fifo 0 to
1141 * ovl 0, fifo 1 to ovl 1, etc.
1143 dispc
.fifo_assignment
[fifo
] = fifo
;
1147 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1148 * causes problems with certain use cases, like using the tiler in 2D
1149 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1150 * giving GFX plane a larger fifo. WB but should work fine with a
1153 if (dispc
.feat
->gfx_fifo_workaround
) {
1156 v
= dispc_read_reg(DISPC_GLOBAL_BUFFER
);
1158 v
= FLD_MOD(v
, 4, 2, 0); /* GFX BUF top to WB */
1159 v
= FLD_MOD(v
, 4, 5, 3); /* GFX BUF bottom to WB */
1160 v
= FLD_MOD(v
, 0, 26, 24); /* WB BUF top to GFX */
1161 v
= FLD_MOD(v
, 0, 29, 27); /* WB BUF bottom to GFX */
1163 dispc_write_reg(DISPC_GLOBAL_BUFFER
, v
);
1165 dispc
.fifo_assignment
[OMAP_DSS_GFX
] = OMAP_DSS_WB
;
1166 dispc
.fifo_assignment
[OMAP_DSS_WB
] = OMAP_DSS_GFX
;
1170 static u32
dispc_ovl_get_fifo_size(enum omap_plane plane
)
1175 for (fifo
= 0; fifo
< dispc
.feat
->num_fifos
; ++fifo
) {
1176 if (dispc
.fifo_assignment
[fifo
] == plane
)
1177 size
+= dispc
.fifo_size
[fifo
];
1183 void dispc_ovl_set_fifo_threshold(enum omap_plane plane
, u32 low
, u32 high
)
1185 u8 hi_start
, hi_end
, lo_start
, lo_end
;
1188 unit
= dss_feat_get_buffer_size_unit();
1190 WARN_ON(low
% unit
!= 0);
1191 WARN_ON(high
% unit
!= 0);
1196 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD
, &hi_start
, &hi_end
);
1197 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD
, &lo_start
, &lo_end
);
1199 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1201 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane
),
1202 lo_start
, lo_end
) * unit
,
1203 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane
),
1204 hi_start
, hi_end
) * unit
,
1205 low
* unit
, high
* unit
);
1207 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane
),
1208 FLD_VAL(high
, hi_start
, hi_end
) |
1209 FLD_VAL(low
, lo_start
, lo_end
));
1212 * configure the preload to the pipeline's high threhold, if HT it's too
1213 * large for the preload field, set the threshold to the maximum value
1214 * that can be held by the preload register
1216 if (dss_has_feature(FEAT_PRELOAD
) && dispc
.feat
->set_max_preload
&&
1217 plane
!= OMAP_DSS_WB
)
1218 dispc_write_reg(DISPC_OVL_PRELOAD(plane
), min(high
, 0xfffu
));
1220 EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold
);
1222 void dispc_enable_fifomerge(bool enable
)
1224 if (!dss_has_feature(FEAT_FIFO_MERGE
)) {
1229 DSSDBG("FIFO merge %s\n", enable
? "enabled" : "disabled");
1230 REG_FLD_MOD(DISPC_CONFIG
, enable
? 1 : 0, 14, 14);
1233 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane
,
1234 u32
*fifo_low
, u32
*fifo_high
, bool use_fifomerge
,
1238 * All sizes are in bytes. Both the buffer and burst are made of
1239 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242 unsigned buf_unit
= dss_feat_get_buffer_size_unit();
1243 unsigned ovl_fifo_size
, total_fifo_size
, burst_size
;
1246 burst_size
= dispc_ovl_get_burst_size(plane
);
1247 ovl_fifo_size
= dispc_ovl_get_fifo_size(plane
);
1249 if (use_fifomerge
) {
1250 total_fifo_size
= 0;
1251 for (i
= 0; i
< dss_feat_get_num_ovls(); ++i
)
1252 total_fifo_size
+= dispc_ovl_get_fifo_size(i
);
1254 total_fifo_size
= ovl_fifo_size
;
1258 * We use the same low threshold for both fifomerge and non-fifomerge
1259 * cases, but for fifomerge we calculate the high threshold using the
1260 * combined fifo size
1263 if (manual_update
&& dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG
)) {
1264 *fifo_low
= ovl_fifo_size
- burst_size
* 2;
1265 *fifo_high
= total_fifo_size
- burst_size
;
1266 } else if (plane
== OMAP_DSS_WB
) {
1268 * Most optimal configuration for writeback is to push out data
1269 * to the interconnect the moment writeback pushes enough pixels
1270 * in the FIFO to form a burst
1273 *fifo_high
= burst_size
;
1275 *fifo_low
= ovl_fifo_size
- burst_size
;
1276 *fifo_high
= total_fifo_size
- buf_unit
;
1279 EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds
);
1281 static void dispc_ovl_set_fir(enum omap_plane plane
,
1283 enum omap_color_component color_comp
)
1287 if (color_comp
== DISPC_COLOR_COMPONENT_RGB_Y
) {
1288 u8 hinc_start
, hinc_end
, vinc_start
, vinc_end
;
1290 dss_feat_get_reg_field(FEAT_REG_FIRHINC
,
1291 &hinc_start
, &hinc_end
);
1292 dss_feat_get_reg_field(FEAT_REG_FIRVINC
,
1293 &vinc_start
, &vinc_end
);
1294 val
= FLD_VAL(vinc
, vinc_start
, vinc_end
) |
1295 FLD_VAL(hinc
, hinc_start
, hinc_end
);
1297 dispc_write_reg(DISPC_OVL_FIR(plane
), val
);
1299 val
= FLD_VAL(vinc
, 28, 16) | FLD_VAL(hinc
, 12, 0);
1300 dispc_write_reg(DISPC_OVL_FIR2(plane
), val
);
1304 static void dispc_ovl_set_vid_accu0(enum omap_plane plane
, int haccu
, int vaccu
)
1307 u8 hor_start
, hor_end
, vert_start
, vert_end
;
1309 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU
, &hor_start
, &hor_end
);
1310 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU
, &vert_start
, &vert_end
);
1312 val
= FLD_VAL(vaccu
, vert_start
, vert_end
) |
1313 FLD_VAL(haccu
, hor_start
, hor_end
);
1315 dispc_write_reg(DISPC_OVL_ACCU0(plane
), val
);
1318 static void dispc_ovl_set_vid_accu1(enum omap_plane plane
, int haccu
, int vaccu
)
1321 u8 hor_start
, hor_end
, vert_start
, vert_end
;
1323 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU
, &hor_start
, &hor_end
);
1324 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU
, &vert_start
, &vert_end
);
1326 val
= FLD_VAL(vaccu
, vert_start
, vert_end
) |
1327 FLD_VAL(haccu
, hor_start
, hor_end
);
1329 dispc_write_reg(DISPC_OVL_ACCU1(plane
), val
);
1332 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane
, int haccu
,
1337 val
= FLD_VAL(vaccu
, 26, 16) | FLD_VAL(haccu
, 10, 0);
1338 dispc_write_reg(DISPC_OVL_ACCU2_0(plane
), val
);
1341 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane
, int haccu
,
1346 val
= FLD_VAL(vaccu
, 26, 16) | FLD_VAL(haccu
, 10, 0);
1347 dispc_write_reg(DISPC_OVL_ACCU2_1(plane
), val
);
1350 static void dispc_ovl_set_scale_param(enum omap_plane plane
,
1351 u16 orig_width
, u16 orig_height
,
1352 u16 out_width
, u16 out_height
,
1353 bool five_taps
, u8 rotation
,
1354 enum omap_color_component color_comp
)
1356 int fir_hinc
, fir_vinc
;
1358 fir_hinc
= 1024 * orig_width
/ out_width
;
1359 fir_vinc
= 1024 * orig_height
/ out_height
;
1361 dispc_ovl_set_scale_coef(plane
, fir_hinc
, fir_vinc
, five_taps
,
1363 dispc_ovl_set_fir(plane
, fir_hinc
, fir_vinc
, color_comp
);
1366 static void dispc_ovl_set_accu_uv(enum omap_plane plane
,
1367 u16 orig_width
, u16 orig_height
, u16 out_width
, u16 out_height
,
1368 bool ilace
, enum omap_color_mode color_mode
, u8 rotation
)
1370 int h_accu2_0
, h_accu2_1
;
1371 int v_accu2_0
, v_accu2_1
;
1372 int chroma_hinc
, chroma_vinc
;
1382 const struct accu
*accu_table
;
1383 const struct accu
*accu_val
;
1385 static const struct accu accu_nv12
[4] = {
1386 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1387 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1388 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1389 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1392 static const struct accu accu_nv12_ilace
[4] = {
1393 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1394 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1395 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1396 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1399 static const struct accu accu_yuv
[4] = {
1400 { 0, 1, 0, 1, 0, 1, 0, 1 },
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { -1, 1, 0, 1, 0, 1, 0, 1 },
1403 { 0, 1, 0, 1, -1, 1, 0, 1 },
1407 case OMAP_DSS_ROT_0
:
1410 case OMAP_DSS_ROT_90
:
1413 case OMAP_DSS_ROT_180
:
1416 case OMAP_DSS_ROT_270
:
1424 switch (color_mode
) {
1425 case OMAP_DSS_COLOR_NV12
:
1427 accu_table
= accu_nv12_ilace
;
1429 accu_table
= accu_nv12
;
1431 case OMAP_DSS_COLOR_YUV2
:
1432 case OMAP_DSS_COLOR_UYVY
:
1433 accu_table
= accu_yuv
;
1440 accu_val
= &accu_table
[idx
];
1442 chroma_hinc
= 1024 * orig_width
/ out_width
;
1443 chroma_vinc
= 1024 * orig_height
/ out_height
;
1445 h_accu2_0
= (accu_val
->h0_m
* chroma_hinc
/ accu_val
->h0_n
) % 1024;
1446 h_accu2_1
= (accu_val
->h1_m
* chroma_hinc
/ accu_val
->h1_n
) % 1024;
1447 v_accu2_0
= (accu_val
->v0_m
* chroma_vinc
/ accu_val
->v0_n
) % 1024;
1448 v_accu2_1
= (accu_val
->v1_m
* chroma_vinc
/ accu_val
->v1_n
) % 1024;
1450 dispc_ovl_set_vid_accu2_0(plane
, h_accu2_0
, v_accu2_0
);
1451 dispc_ovl_set_vid_accu2_1(plane
, h_accu2_1
, v_accu2_1
);
1454 static void dispc_ovl_set_scaling_common(enum omap_plane plane
,
1455 u16 orig_width
, u16 orig_height
,
1456 u16 out_width
, u16 out_height
,
1457 bool ilace
, bool five_taps
,
1458 bool fieldmode
, enum omap_color_mode color_mode
,
1465 dispc_ovl_set_scale_param(plane
, orig_width
, orig_height
,
1466 out_width
, out_height
, five_taps
,
1467 rotation
, DISPC_COLOR_COMPONENT_RGB_Y
);
1468 l
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
1470 /* RESIZEENABLE and VERTICALTAPS */
1471 l
&= ~((0x3 << 5) | (0x1 << 21));
1472 l
|= (orig_width
!= out_width
) ? (1 << 5) : 0;
1473 l
|= (orig_height
!= out_height
) ? (1 << 6) : 0;
1474 l
|= five_taps
? (1 << 21) : 0;
1476 /* VRESIZECONF and HRESIZECONF */
1477 if (dss_has_feature(FEAT_RESIZECONF
)) {
1479 l
|= (orig_width
<= out_width
) ? 0 : (1 << 7);
1480 l
|= (orig_height
<= out_height
) ? 0 : (1 << 8);
1483 /* LINEBUFFERSPLIT */
1484 if (dss_has_feature(FEAT_LINEBUFFERSPLIT
)) {
1486 l
|= five_taps
? (1 << 22) : 0;
1489 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), l
);
1492 * field 0 = even field = bottom field
1493 * field 1 = odd field = top field
1495 if (ilace
&& !fieldmode
) {
1497 accu0
= ((1024 * orig_height
/ out_height
) / 2) & 0x3ff;
1498 if (accu0
>= 1024/2) {
1504 dispc_ovl_set_vid_accu0(plane
, 0, accu0
);
1505 dispc_ovl_set_vid_accu1(plane
, 0, accu1
);
1508 static void dispc_ovl_set_scaling_uv(enum omap_plane plane
,
1509 u16 orig_width
, u16 orig_height
,
1510 u16 out_width
, u16 out_height
,
1511 bool ilace
, bool five_taps
,
1512 bool fieldmode
, enum omap_color_mode color_mode
,
1515 int scale_x
= out_width
!= orig_width
;
1516 int scale_y
= out_height
!= orig_height
;
1517 bool chroma_upscale
= plane
!= OMAP_DSS_WB
? true : false;
1519 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE
))
1521 if ((color_mode
!= OMAP_DSS_COLOR_YUV2
&&
1522 color_mode
!= OMAP_DSS_COLOR_UYVY
&&
1523 color_mode
!= OMAP_DSS_COLOR_NV12
)) {
1524 /* reset chroma resampling for RGB formats */
1525 if (plane
!= OMAP_DSS_WB
)
1526 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
), 0, 8, 8);
1530 dispc_ovl_set_accu_uv(plane
, orig_width
, orig_height
, out_width
,
1531 out_height
, ilace
, color_mode
, rotation
);
1533 switch (color_mode
) {
1534 case OMAP_DSS_COLOR_NV12
:
1535 if (chroma_upscale
) {
1536 /* UV is subsampled by 2 horizontally and vertically */
1540 /* UV is downsampled by 2 horizontally and vertically */
1546 case OMAP_DSS_COLOR_YUV2
:
1547 case OMAP_DSS_COLOR_UYVY
:
1548 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1549 if (rotation
== OMAP_DSS_ROT_0
||
1550 rotation
== OMAP_DSS_ROT_180
) {
1552 /* UV is subsampled by 2 horizontally */
1555 /* UV is downsampled by 2 horizontally */
1559 /* must use FIR for YUV422 if rotated */
1560 if (rotation
!= OMAP_DSS_ROT_0
)
1561 scale_x
= scale_y
= true;
1569 if (out_width
!= orig_width
)
1571 if (out_height
!= orig_height
)
1574 dispc_ovl_set_scale_param(plane
, orig_width
, orig_height
,
1575 out_width
, out_height
, five_taps
,
1576 rotation
, DISPC_COLOR_COMPONENT_UV
);
1578 if (plane
!= OMAP_DSS_WB
)
1579 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane
),
1580 (scale_x
|| scale_y
) ? 1 : 0, 8, 8);
1583 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), scale_x
? 1 : 0, 5, 5);
1585 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), scale_y
? 1 : 0, 6, 6);
1588 static void dispc_ovl_set_scaling(enum omap_plane plane
,
1589 u16 orig_width
, u16 orig_height
,
1590 u16 out_width
, u16 out_height
,
1591 bool ilace
, bool five_taps
,
1592 bool fieldmode
, enum omap_color_mode color_mode
,
1595 BUG_ON(plane
== OMAP_DSS_GFX
);
1597 dispc_ovl_set_scaling_common(plane
,
1598 orig_width
, orig_height
,
1599 out_width
, out_height
,
1601 fieldmode
, color_mode
,
1604 dispc_ovl_set_scaling_uv(plane
,
1605 orig_width
, orig_height
,
1606 out_width
, out_height
,
1608 fieldmode
, color_mode
,
1612 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane
, u8 rotation
,
1613 enum omap_dss_rotation_type rotation_type
,
1614 bool mirroring
, enum omap_color_mode color_mode
)
1616 bool row_repeat
= false;
1619 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1620 color_mode
== OMAP_DSS_COLOR_UYVY
) {
1624 case OMAP_DSS_ROT_0
:
1627 case OMAP_DSS_ROT_90
:
1630 case OMAP_DSS_ROT_180
:
1633 case OMAP_DSS_ROT_270
:
1639 case OMAP_DSS_ROT_0
:
1642 case OMAP_DSS_ROT_90
:
1645 case OMAP_DSS_ROT_180
:
1648 case OMAP_DSS_ROT_270
:
1654 if (rotation
== OMAP_DSS_ROT_90
|| rotation
== OMAP_DSS_ROT_270
)
1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), vidrot
, 13, 12);
1661 if (dss_has_feature(FEAT_ROWREPEATENABLE
))
1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
),
1663 row_repeat
? 1 : 0, 18, 18);
1665 if (color_mode
== OMAP_DSS_COLOR_NV12
) {
1666 bool doublestride
= (rotation_type
== OMAP_DSS_ROT_TILER
) &&
1667 (rotation
== OMAP_DSS_ROT_0
||
1668 rotation
== OMAP_DSS_ROT_180
);
1670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), doublestride
, 22, 22);
1675 static int color_mode_to_bpp(enum omap_color_mode color_mode
)
1677 switch (color_mode
) {
1678 case OMAP_DSS_COLOR_CLUT1
:
1680 case OMAP_DSS_COLOR_CLUT2
:
1682 case OMAP_DSS_COLOR_CLUT4
:
1684 case OMAP_DSS_COLOR_CLUT8
:
1685 case OMAP_DSS_COLOR_NV12
:
1687 case OMAP_DSS_COLOR_RGB12U
:
1688 case OMAP_DSS_COLOR_RGB16
:
1689 case OMAP_DSS_COLOR_ARGB16
:
1690 case OMAP_DSS_COLOR_YUV2
:
1691 case OMAP_DSS_COLOR_UYVY
:
1692 case OMAP_DSS_COLOR_RGBA16
:
1693 case OMAP_DSS_COLOR_RGBX16
:
1694 case OMAP_DSS_COLOR_ARGB16_1555
:
1695 case OMAP_DSS_COLOR_XRGB16_1555
:
1697 case OMAP_DSS_COLOR_RGB24P
:
1699 case OMAP_DSS_COLOR_RGB24U
:
1700 case OMAP_DSS_COLOR_ARGB32
:
1701 case OMAP_DSS_COLOR_RGBA32
:
1702 case OMAP_DSS_COLOR_RGBX32
:
1710 static s32
pixinc(int pixels
, u8 ps
)
1714 else if (pixels
> 1)
1715 return 1 + (pixels
- 1) * ps
;
1716 else if (pixels
< 0)
1717 return 1 - (-pixels
+ 1) * ps
;
1723 static void calc_vrfb_rotation_offset(u8 rotation
, bool mirror
,
1725 u16 width
, u16 height
,
1726 enum omap_color_mode color_mode
, bool fieldmode
,
1727 unsigned int field_offset
,
1728 unsigned *offset0
, unsigned *offset1
,
1729 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
1733 /* FIXME CLUT formats */
1734 switch (color_mode
) {
1735 case OMAP_DSS_COLOR_CLUT1
:
1736 case OMAP_DSS_COLOR_CLUT2
:
1737 case OMAP_DSS_COLOR_CLUT4
:
1738 case OMAP_DSS_COLOR_CLUT8
:
1741 case OMAP_DSS_COLOR_YUV2
:
1742 case OMAP_DSS_COLOR_UYVY
:
1746 ps
= color_mode_to_bpp(color_mode
) / 8;
1750 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation
, screen_width
,
1754 * field 0 = even field = bottom field
1755 * field 1 = odd field = top field
1757 switch (rotation
+ mirror
* 4) {
1758 case OMAP_DSS_ROT_0
:
1759 case OMAP_DSS_ROT_180
:
1761 * If the pixel format is YUV or UYVY divide the width
1762 * of the image by 2 for 0 and 180 degree rotation.
1764 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1765 color_mode
== OMAP_DSS_COLOR_UYVY
)
1767 case OMAP_DSS_ROT_90
:
1768 case OMAP_DSS_ROT_270
:
1771 *offset0
= field_offset
* screen_width
* ps
;
1775 *row_inc
= pixinc(1 +
1776 (y_predecim
* screen_width
- x_predecim
* width
) +
1777 (fieldmode
? screen_width
: 0), ps
);
1778 *pix_inc
= pixinc(x_predecim
, ps
);
1781 case OMAP_DSS_ROT_0
+ 4:
1782 case OMAP_DSS_ROT_180
+ 4:
1783 /* If the pixel format is YUV or UYVY divide the width
1784 * of the image by 2 for 0 degree and 180 degree
1786 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1787 color_mode
== OMAP_DSS_COLOR_UYVY
)
1789 case OMAP_DSS_ROT_90
+ 4:
1790 case OMAP_DSS_ROT_270
+ 4:
1793 *offset0
= field_offset
* screen_width
* ps
;
1796 *row_inc
= pixinc(1 -
1797 (y_predecim
* screen_width
+ x_predecim
* width
) -
1798 (fieldmode
? screen_width
: 0), ps
);
1799 *pix_inc
= pixinc(x_predecim
, ps
);
1808 static void calc_dma_rotation_offset(u8 rotation
, bool mirror
,
1810 u16 width
, u16 height
,
1811 enum omap_color_mode color_mode
, bool fieldmode
,
1812 unsigned int field_offset
,
1813 unsigned *offset0
, unsigned *offset1
,
1814 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
1819 /* FIXME CLUT formats */
1820 switch (color_mode
) {
1821 case OMAP_DSS_COLOR_CLUT1
:
1822 case OMAP_DSS_COLOR_CLUT2
:
1823 case OMAP_DSS_COLOR_CLUT4
:
1824 case OMAP_DSS_COLOR_CLUT8
:
1828 ps
= color_mode_to_bpp(color_mode
) / 8;
1832 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation
, screen_width
,
1835 /* width & height are overlay sizes, convert to fb sizes */
1837 if (rotation
== OMAP_DSS_ROT_0
|| rotation
== OMAP_DSS_ROT_180
) {
1846 * field 0 = even field = bottom field
1847 * field 1 = odd field = top field
1849 switch (rotation
+ mirror
* 4) {
1850 case OMAP_DSS_ROT_0
:
1853 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
1855 *offset0
= *offset1
;
1856 *row_inc
= pixinc(1 +
1857 (y_predecim
* screen_width
- fbw
* x_predecim
) +
1858 (fieldmode
? screen_width
: 0), ps
);
1859 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1860 color_mode
== OMAP_DSS_COLOR_UYVY
)
1861 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
1863 *pix_inc
= pixinc(x_predecim
, ps
);
1865 case OMAP_DSS_ROT_90
:
1866 *offset1
= screen_width
* (fbh
- 1) * ps
;
1868 *offset0
= *offset1
+ field_offset
* ps
;
1870 *offset0
= *offset1
;
1871 *row_inc
= pixinc(screen_width
* (fbh
* x_predecim
- 1) +
1872 y_predecim
+ (fieldmode
? 1 : 0), ps
);
1873 *pix_inc
= pixinc(-x_predecim
* screen_width
, ps
);
1875 case OMAP_DSS_ROT_180
:
1876 *offset1
= (screen_width
* (fbh
- 1) + fbw
- 1) * ps
;
1878 *offset0
= *offset1
- field_offset
* screen_width
* ps
;
1880 *offset0
= *offset1
;
1881 *row_inc
= pixinc(-1 -
1882 (y_predecim
* screen_width
- fbw
* x_predecim
) -
1883 (fieldmode
? screen_width
: 0), ps
);
1884 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1885 color_mode
== OMAP_DSS_COLOR_UYVY
)
1886 *pix_inc
= pixinc(-x_predecim
, 2 * ps
);
1888 *pix_inc
= pixinc(-x_predecim
, ps
);
1890 case OMAP_DSS_ROT_270
:
1891 *offset1
= (fbw
- 1) * ps
;
1893 *offset0
= *offset1
- field_offset
* ps
;
1895 *offset0
= *offset1
;
1896 *row_inc
= pixinc(-screen_width
* (fbh
* x_predecim
- 1) -
1897 y_predecim
- (fieldmode
? 1 : 0), ps
);
1898 *pix_inc
= pixinc(x_predecim
* screen_width
, ps
);
1902 case OMAP_DSS_ROT_0
+ 4:
1903 *offset1
= (fbw
- 1) * ps
;
1905 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
1907 *offset0
= *offset1
;
1908 *row_inc
= pixinc(y_predecim
* screen_width
* 2 - 1 +
1909 (fieldmode
? screen_width
: 0),
1911 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1912 color_mode
== OMAP_DSS_COLOR_UYVY
)
1913 *pix_inc
= pixinc(-x_predecim
, 2 * ps
);
1915 *pix_inc
= pixinc(-x_predecim
, ps
);
1918 case OMAP_DSS_ROT_90
+ 4:
1921 *offset0
= *offset1
+ field_offset
* ps
;
1923 *offset0
= *offset1
;
1924 *row_inc
= pixinc(-screen_width
* (fbh
* x_predecim
- 1) +
1925 y_predecim
+ (fieldmode
? 1 : 0),
1927 *pix_inc
= pixinc(x_predecim
* screen_width
, ps
);
1930 case OMAP_DSS_ROT_180
+ 4:
1931 *offset1
= screen_width
* (fbh
- 1) * ps
;
1933 *offset0
= *offset1
- field_offset
* screen_width
* ps
;
1935 *offset0
= *offset1
;
1936 *row_inc
= pixinc(1 - y_predecim
* screen_width
* 2 -
1937 (fieldmode
? screen_width
: 0),
1939 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1940 color_mode
== OMAP_DSS_COLOR_UYVY
)
1941 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
1943 *pix_inc
= pixinc(x_predecim
, ps
);
1946 case OMAP_DSS_ROT_270
+ 4:
1947 *offset1
= (screen_width
* (fbh
- 1) + fbw
- 1) * ps
;
1949 *offset0
= *offset1
- field_offset
* ps
;
1951 *offset0
= *offset1
;
1952 *row_inc
= pixinc(screen_width
* (fbh
* x_predecim
- 1) -
1953 y_predecim
- (fieldmode
? 1 : 0),
1955 *pix_inc
= pixinc(-x_predecim
* screen_width
, ps
);
1964 static void calc_tiler_rotation_offset(u16 screen_width
, u16 width
,
1965 enum omap_color_mode color_mode
, bool fieldmode
,
1966 unsigned int field_offset
, unsigned *offset0
, unsigned *offset1
,
1967 s32
*row_inc
, s32
*pix_inc
, int x_predecim
, int y_predecim
)
1971 switch (color_mode
) {
1972 case OMAP_DSS_COLOR_CLUT1
:
1973 case OMAP_DSS_COLOR_CLUT2
:
1974 case OMAP_DSS_COLOR_CLUT4
:
1975 case OMAP_DSS_COLOR_CLUT8
:
1979 ps
= color_mode_to_bpp(color_mode
) / 8;
1983 DSSDBG("scrw %d, width %d\n", screen_width
, width
);
1986 * field 0 = even field = bottom field
1987 * field 1 = odd field = top field
1991 *offset0
= *offset1
+ field_offset
* screen_width
* ps
;
1993 *offset0
= *offset1
;
1994 *row_inc
= pixinc(1 + (y_predecim
* screen_width
- width
* x_predecim
) +
1995 (fieldmode
? screen_width
: 0), ps
);
1996 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
1997 color_mode
== OMAP_DSS_COLOR_UYVY
)
1998 *pix_inc
= pixinc(x_predecim
, 2 * ps
);
2000 *pix_inc
= pixinc(x_predecim
, ps
);
2004 * This function is used to avoid synclosts in OMAP3, because of some
2005 * undocumented horizontal position and timing related limitations.
2007 static int check_horiz_timing_omap3(unsigned long pclk
, unsigned long lclk
,
2008 const struct omap_video_timings
*t
, u16 pos_x
,
2009 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2012 const int ds
= DIV_ROUND_UP(height
, out_height
);
2013 unsigned long nonactive
;
2014 static const u8 limits
[3] = { 8, 10, 20 };
2018 nonactive
= t
->x_res
+ t
->hfp
+ t
->hsw
+ t
->hbp
- out_width
;
2021 if (out_height
< height
)
2023 if (out_width
< width
)
2025 blank
= div_u64((u64
)(t
->hbp
+ t
->hsw
+ t
->hfp
) * lclk
, pclk
);
2026 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank
, limits
[i
]);
2027 if (blank
<= limits
[i
])
2030 /* FIXME add checks for 3-tap filter once the limitations are known */
2035 * Pixel data should be prepared before visible display point starts.
2036 * So, atleast DS-2 lines must have already been fetched by DISPC
2037 * during nonactive - pos_x period.
2039 val
= div_u64((u64
)(nonactive
- pos_x
) * lclk
, pclk
);
2040 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2041 val
, max(0, ds
- 2) * width
);
2042 if (val
< max(0, ds
- 2) * width
)
2046 * All lines need to be refilled during the nonactive period of which
2047 * only one line can be loaded during the active period. So, atleast
2048 * DS - 1 lines should be loaded during nonactive period.
2050 val
= div_u64((u64
)nonactive
* lclk
, pclk
);
2051 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2052 val
, max(0, ds
- 1) * width
);
2053 if (val
< max(0, ds
- 1) * width
)
2059 static unsigned long calc_core_clk_five_taps(unsigned long pclk
,
2060 const struct omap_video_timings
*mgr_timings
, u16 width
,
2061 u16 height
, u16 out_width
, u16 out_height
,
2062 enum omap_color_mode color_mode
)
2067 if (height
<= out_height
&& width
<= out_width
)
2068 return (unsigned long) pclk
;
2070 if (height
> out_height
) {
2071 unsigned int ppl
= mgr_timings
->x_res
;
2073 tmp
= pclk
* height
* out_width
;
2074 do_div(tmp
, 2 * out_height
* ppl
);
2077 if (height
> 2 * out_height
) {
2078 if (ppl
== out_width
)
2081 tmp
= pclk
* (height
- 2 * out_height
) * out_width
;
2082 do_div(tmp
, 2 * out_height
* (ppl
- out_width
));
2083 core_clk
= max_t(u32
, core_clk
, tmp
);
2087 if (width
> out_width
) {
2089 do_div(tmp
, out_width
);
2090 core_clk
= max_t(u32
, core_clk
, tmp
);
2092 if (color_mode
== OMAP_DSS_COLOR_RGB24U
)
2099 static unsigned long calc_core_clk_24xx(unsigned long pclk
, u16 width
,
2100 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2102 if (height
> out_height
&& width
> out_width
)
2108 static unsigned long calc_core_clk_34xx(unsigned long pclk
, u16 width
,
2109 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2111 unsigned int hf
, vf
;
2114 * FIXME how to determine the 'A' factor
2115 * for the no downscaling case ?
2118 if (width
> 3 * out_width
)
2120 else if (width
> 2 * out_width
)
2122 else if (width
> out_width
)
2126 if (height
> out_height
)
2131 return pclk
* vf
* hf
;
2134 static unsigned long calc_core_clk_44xx(unsigned long pclk
, u16 width
,
2135 u16 height
, u16 out_width
, u16 out_height
, bool mem_to_mem
)
2138 * If the overlay/writeback is in mem to mem mode, there are no
2139 * downscaling limitations with respect to pixel clock, return 1 as
2140 * required core clock to represent that we have sufficient enough
2141 * core clock to do maximum downscaling
2146 if (width
> out_width
)
2147 return DIV_ROUND_UP(pclk
, out_width
) * width
;
2152 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk
, unsigned long lclk
,
2153 const struct omap_video_timings
*mgr_timings
,
2154 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2155 enum omap_color_mode color_mode
, bool *five_taps
,
2156 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2157 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2160 u16 in_width
, in_height
;
2161 int min_factor
= min(*decim_x
, *decim_y
);
2162 const int maxsinglelinewidth
=
2163 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2168 in_height
= height
/ *decim_y
;
2169 in_width
= width
/ *decim_x
;
2170 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
,
2171 in_height
, out_width
, out_height
, mem_to_mem
);
2172 error
= (in_width
> maxsinglelinewidth
|| !*core_clk
||
2173 *core_clk
> dispc_core_clk_rate());
2175 if (*decim_x
== *decim_y
) {
2176 *decim_x
= min_factor
;
2179 swap(*decim_x
, *decim_y
);
2180 if (*decim_x
< *decim_y
)
2184 } while (*decim_x
<= *x_predecim
&& *decim_y
<= *y_predecim
&& error
);
2186 if (in_width
> maxsinglelinewidth
) {
2187 DSSERR("Cannot scale max input width exceeded");
2193 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk
, unsigned long lclk
,
2194 const struct omap_video_timings
*mgr_timings
,
2195 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2196 enum omap_color_mode color_mode
, bool *five_taps
,
2197 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2198 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2201 u16 in_width
, in_height
;
2202 int min_factor
= min(*decim_x
, *decim_y
);
2203 const int maxsinglelinewidth
=
2204 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2207 in_height
= height
/ *decim_y
;
2208 in_width
= width
/ *decim_x
;
2209 *five_taps
= in_height
> out_height
;
2211 if (in_width
> maxsinglelinewidth
)
2212 if (in_height
> out_height
&&
2213 in_height
< out_height
* 2)
2217 *core_clk
= calc_core_clk_five_taps(pclk
, mgr_timings
,
2218 in_width
, in_height
, out_width
,
2219 out_height
, color_mode
);
2221 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
,
2222 in_height
, out_width
, out_height
,
2225 error
= check_horiz_timing_omap3(pclk
, lclk
, mgr_timings
,
2226 pos_x
, in_width
, in_height
, out_width
,
2227 out_height
, *five_taps
);
2228 if (error
&& *five_taps
) {
2233 error
= (error
|| in_width
> maxsinglelinewidth
* 2 ||
2234 (in_width
> maxsinglelinewidth
&& *five_taps
) ||
2235 !*core_clk
|| *core_clk
> dispc_core_clk_rate());
2237 if (*decim_x
== *decim_y
) {
2238 *decim_x
= min_factor
;
2241 swap(*decim_x
, *decim_y
);
2242 if (*decim_x
< *decim_y
)
2246 } while (*decim_x
<= *x_predecim
&& *decim_y
<= *y_predecim
&& error
);
2248 if (check_horiz_timing_omap3(pclk
, lclk
, mgr_timings
, pos_x
, width
,
2249 height
, out_width
, out_height
, *five_taps
)) {
2250 DSSERR("horizontal timing too tight\n");
2254 if (in_width
> (maxsinglelinewidth
* 2)) {
2255 DSSERR("Cannot setup scaling");
2256 DSSERR("width exceeds maximum width possible");
2260 if (in_width
> maxsinglelinewidth
&& *five_taps
) {
2261 DSSERR("cannot setup scaling with five taps");
2267 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk
, unsigned long lclk
,
2268 const struct omap_video_timings
*mgr_timings
,
2269 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2270 enum omap_color_mode color_mode
, bool *five_taps
,
2271 int *x_predecim
, int *y_predecim
, int *decim_x
, int *decim_y
,
2272 u16 pos_x
, unsigned long *core_clk
, bool mem_to_mem
)
2274 u16 in_width
, in_width_max
;
2275 int decim_x_min
= *decim_x
;
2276 u16 in_height
= height
/ *decim_y
;
2277 const int maxsinglelinewidth
=
2278 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH
);
2279 const int maxdownscale
= dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE
);
2282 in_width_max
= out_width
* maxdownscale
;
2284 in_width_max
= dispc_core_clk_rate() /
2285 DIV_ROUND_UP(pclk
, out_width
);
2288 *decim_x
= DIV_ROUND_UP(width
, in_width_max
);
2290 *decim_x
= *decim_x
> decim_x_min
? *decim_x
: decim_x_min
;
2291 if (*decim_x
> *x_predecim
)
2295 in_width
= width
/ *decim_x
;
2296 } while (*decim_x
<= *x_predecim
&&
2297 in_width
> maxsinglelinewidth
&& ++*decim_x
);
2299 if (in_width
> maxsinglelinewidth
) {
2300 DSSERR("Cannot scale width exceeds max line width");
2304 *core_clk
= dispc
.feat
->calc_core_clk(pclk
, in_width
, in_height
,
2305 out_width
, out_height
, mem_to_mem
);
2309 static int dispc_ovl_calc_scaling(unsigned long pclk
, unsigned long lclk
,
2310 enum omap_overlay_caps caps
,
2311 const struct omap_video_timings
*mgr_timings
,
2312 u16 width
, u16 height
, u16 out_width
, u16 out_height
,
2313 enum omap_color_mode color_mode
, bool *five_taps
,
2314 int *x_predecim
, int *y_predecim
, u16 pos_x
,
2315 enum omap_dss_rotation_type rotation_type
, bool mem_to_mem
)
2317 const int maxdownscale
= dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE
);
2318 const int max_decim_limit
= 16;
2319 unsigned long core_clk
= 0;
2320 int decim_x
, decim_y
, ret
;
2322 if (width
== out_width
&& height
== out_height
)
2325 if ((caps
& OMAP_DSS_OVL_CAP_SCALE
) == 0)
2329 *x_predecim
= *y_predecim
= 1;
2331 *x_predecim
= max_decim_limit
;
2332 *y_predecim
= (rotation_type
== OMAP_DSS_ROT_TILER
&&
2333 dss_has_feature(FEAT_BURST_2D
)) ?
2334 2 : max_decim_limit
;
2337 if (color_mode
== OMAP_DSS_COLOR_CLUT1
||
2338 color_mode
== OMAP_DSS_COLOR_CLUT2
||
2339 color_mode
== OMAP_DSS_COLOR_CLUT4
||
2340 color_mode
== OMAP_DSS_COLOR_CLUT8
) {
2347 decim_x
= DIV_ROUND_UP(DIV_ROUND_UP(width
, out_width
), maxdownscale
);
2348 decim_y
= DIV_ROUND_UP(DIV_ROUND_UP(height
, out_height
), maxdownscale
);
2350 if (decim_x
> *x_predecim
|| out_width
> width
* 8)
2353 if (decim_y
> *y_predecim
|| out_height
> height
* 8)
2356 ret
= dispc
.feat
->calc_scaling(pclk
, lclk
, mgr_timings
, width
, height
,
2357 out_width
, out_height
, color_mode
, five_taps
,
2358 x_predecim
, y_predecim
, &decim_x
, &decim_y
, pos_x
, &core_clk
,
2363 DSSDBG("required core clk rate = %lu Hz\n", core_clk
);
2364 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2366 if (!core_clk
|| core_clk
> dispc_core_clk_rate()) {
2367 DSSERR("failed to set up scaling, "
2368 "required core clk rate = %lu Hz, "
2369 "current core clk rate = %lu Hz\n",
2370 core_clk
, dispc_core_clk_rate());
2374 *x_predecim
= decim_x
;
2375 *y_predecim
= decim_y
;
2379 int dispc_ovl_check(enum omap_plane plane
, enum omap_channel channel
,
2380 const struct omap_overlay_info
*oi
,
2381 const struct omap_video_timings
*timings
,
2382 int *x_predecim
, int *y_predecim
)
2384 enum omap_overlay_caps caps
= dss_feat_get_overlay_caps(plane
);
2385 bool five_taps
= true;
2386 bool fieldmode
= false;
2387 u16 in_height
= oi
->height
;
2388 u16 in_width
= oi
->width
;
2389 bool ilace
= timings
->interlace
;
2390 u16 out_width
, out_height
;
2391 int pos_x
= oi
->pos_x
;
2392 unsigned long pclk
= dispc_mgr_pclk_rate(channel
);
2393 unsigned long lclk
= dispc_mgr_lclk_rate(channel
);
2395 out_width
= oi
->out_width
== 0 ? oi
->width
: oi
->out_width
;
2396 out_height
= oi
->out_height
== 0 ? oi
->height
: oi
->out_height
;
2398 if (ilace
&& oi
->height
== out_height
)
2406 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2407 in_height
, out_height
);
2410 if (!dss_feat_color_mode_supported(plane
, oi
->color_mode
))
2413 return dispc_ovl_calc_scaling(pclk
, lclk
, caps
, timings
, in_width
,
2414 in_height
, out_width
, out_height
, oi
->color_mode
,
2415 &five_taps
, x_predecim
, y_predecim
, pos_x
,
2416 oi
->rotation_type
, false);
2418 EXPORT_SYMBOL(dispc_ovl_check
);
2420 static int dispc_ovl_setup_common(enum omap_plane plane
,
2421 enum omap_overlay_caps caps
, u32 paddr
, u32 p_uv_addr
,
2422 u16 screen_width
, int pos_x
, int pos_y
, u16 width
, u16 height
,
2423 u16 out_width
, u16 out_height
, enum omap_color_mode color_mode
,
2424 u8 rotation
, bool mirror
, u8 zorder
, u8 pre_mult_alpha
,
2425 u8 global_alpha
, enum omap_dss_rotation_type rotation_type
,
2426 bool replication
, const struct omap_video_timings
*mgr_timings
,
2429 bool five_taps
= true;
2430 bool fieldmode
= false;
2432 unsigned offset0
, offset1
;
2435 u16 frame_width
, frame_height
;
2436 unsigned int field_offset
= 0;
2437 u16 in_height
= height
;
2438 u16 in_width
= width
;
2439 int x_predecim
= 1, y_predecim
= 1;
2440 bool ilace
= mgr_timings
->interlace
;
2441 unsigned long pclk
= dispc_plane_pclk_rate(plane
);
2442 unsigned long lclk
= dispc_plane_lclk_rate(plane
);
2447 out_width
= out_width
== 0 ? width
: out_width
;
2448 out_height
= out_height
== 0 ? height
: out_height
;
2450 if (ilace
&& height
== out_height
)
2459 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2460 "out_height %d\n", in_height
, pos_y
,
2464 if (!dss_feat_color_mode_supported(plane
, color_mode
))
2467 r
= dispc_ovl_calc_scaling(pclk
, lclk
, caps
, mgr_timings
, in_width
,
2468 in_height
, out_width
, out_height
, color_mode
,
2469 &five_taps
, &x_predecim
, &y_predecim
, pos_x
,
2470 rotation_type
, mem_to_mem
);
2474 in_width
= in_width
/ x_predecim
;
2475 in_height
= in_height
/ y_predecim
;
2477 if (color_mode
== OMAP_DSS_COLOR_YUV2
||
2478 color_mode
== OMAP_DSS_COLOR_UYVY
||
2479 color_mode
== OMAP_DSS_COLOR_NV12
)
2482 if (ilace
&& !fieldmode
) {
2484 * when downscaling the bottom field may have to start several
2485 * source lines below the top field. Unfortunately ACCUI
2486 * registers will only hold the fractional part of the offset
2487 * so the integer part must be added to the base address of the
2490 if (!in_height
|| in_height
== out_height
)
2493 field_offset
= in_height
/ out_height
/ 2;
2496 /* Fields are independent but interleaved in memory. */
2505 if (plane
== OMAP_DSS_WB
) {
2506 frame_width
= out_width
;
2507 frame_height
= out_height
;
2509 frame_width
= in_width
;
2510 frame_height
= height
;
2513 if (rotation_type
== OMAP_DSS_ROT_TILER
)
2514 calc_tiler_rotation_offset(screen_width
, frame_width
,
2515 color_mode
, fieldmode
, field_offset
,
2516 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2517 x_predecim
, y_predecim
);
2518 else if (rotation_type
== OMAP_DSS_ROT_DMA
)
2519 calc_dma_rotation_offset(rotation
, mirror
, screen_width
,
2520 frame_width
, frame_height
,
2521 color_mode
, fieldmode
, field_offset
,
2522 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2523 x_predecim
, y_predecim
);
2525 calc_vrfb_rotation_offset(rotation
, mirror
,
2526 screen_width
, frame_width
, frame_height
,
2527 color_mode
, fieldmode
, field_offset
,
2528 &offset0
, &offset1
, &row_inc
, &pix_inc
,
2529 x_predecim
, y_predecim
);
2531 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2532 offset0
, offset1
, row_inc
, pix_inc
);
2534 dispc_ovl_set_color_mode(plane
, color_mode
);
2536 dispc_ovl_configure_burst_type(plane
, rotation_type
);
2538 dispc_ovl_set_ba0(plane
, paddr
+ offset0
);
2539 dispc_ovl_set_ba1(plane
, paddr
+ offset1
);
2541 if (OMAP_DSS_COLOR_NV12
== color_mode
) {
2542 dispc_ovl_set_ba0_uv(plane
, p_uv_addr
+ offset0
);
2543 dispc_ovl_set_ba1_uv(plane
, p_uv_addr
+ offset1
);
2546 dispc_ovl_set_row_inc(plane
, row_inc
);
2547 dispc_ovl_set_pix_inc(plane
, pix_inc
);
2549 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x
, pos_y
, in_width
,
2550 in_height
, out_width
, out_height
);
2552 dispc_ovl_set_pos(plane
, caps
, pos_x
, pos_y
);
2554 dispc_ovl_set_input_size(plane
, in_width
, in_height
);
2556 if (caps
& OMAP_DSS_OVL_CAP_SCALE
) {
2557 dispc_ovl_set_scaling(plane
, in_width
, in_height
, out_width
,
2558 out_height
, ilace
, five_taps
, fieldmode
,
2559 color_mode
, rotation
);
2560 dispc_ovl_set_output_size(plane
, out_width
, out_height
);
2561 dispc_ovl_set_vid_color_conv(plane
, cconv
);
2564 dispc_ovl_set_rotation_attrs(plane
, rotation
, rotation_type
, mirror
,
2567 dispc_ovl_set_zorder(plane
, caps
, zorder
);
2568 dispc_ovl_set_pre_mult_alpha(plane
, caps
, pre_mult_alpha
);
2569 dispc_ovl_setup_global_alpha(plane
, caps
, global_alpha
);
2571 dispc_ovl_enable_replication(plane
, caps
, replication
);
2576 int dispc_ovl_setup(enum omap_plane plane
, const struct omap_overlay_info
*oi
,
2577 bool replication
, const struct omap_video_timings
*mgr_timings
,
2581 enum omap_overlay_caps caps
= dss_feat_get_overlay_caps(plane
);
2582 enum omap_channel channel
;
2584 channel
= dispc_ovl_get_channel_out(plane
);
2586 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2587 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2588 plane
, &oi
->paddr
, &oi
->p_uv_addr
, oi
->screen_width
, oi
->pos_x
,
2589 oi
->pos_y
, oi
->width
, oi
->height
, oi
->out_width
, oi
->out_height
,
2590 oi
->color_mode
, oi
->rotation
, oi
->mirror
, channel
, replication
);
2592 r
= dispc_ovl_setup_common(plane
, caps
, oi
->paddr
, oi
->p_uv_addr
,
2593 oi
->screen_width
, oi
->pos_x
, oi
->pos_y
, oi
->width
, oi
->height
,
2594 oi
->out_width
, oi
->out_height
, oi
->color_mode
, oi
->rotation
,
2595 oi
->mirror
, oi
->zorder
, oi
->pre_mult_alpha
, oi
->global_alpha
,
2596 oi
->rotation_type
, replication
, mgr_timings
, mem_to_mem
);
2600 EXPORT_SYMBOL(dispc_ovl_setup
);
2602 int dispc_wb_setup(const struct omap_dss_writeback_info
*wi
,
2603 bool mem_to_mem
, const struct omap_video_timings
*mgr_timings
)
2607 enum omap_plane plane
= OMAP_DSS_WB
;
2608 const int pos_x
= 0, pos_y
= 0;
2609 const u8 zorder
= 0, global_alpha
= 0;
2610 const bool replication
= false;
2612 int in_width
= mgr_timings
->x_res
;
2613 int in_height
= mgr_timings
->y_res
;
2614 enum omap_overlay_caps caps
=
2615 OMAP_DSS_OVL_CAP_SCALE
| OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA
;
2617 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2618 "rot %d, mir %d\n", wi
->paddr
, wi
->p_uv_addr
, in_width
,
2619 in_height
, wi
->width
, wi
->height
, wi
->color_mode
, wi
->rotation
,
2622 r
= dispc_ovl_setup_common(plane
, caps
, wi
->paddr
, wi
->p_uv_addr
,
2623 wi
->buf_width
, pos_x
, pos_y
, in_width
, in_height
, wi
->width
,
2624 wi
->height
, wi
->color_mode
, wi
->rotation
, wi
->mirror
, zorder
,
2625 wi
->pre_mult_alpha
, global_alpha
, wi
->rotation_type
,
2626 replication
, mgr_timings
, mem_to_mem
);
2628 switch (wi
->color_mode
) {
2629 case OMAP_DSS_COLOR_RGB16
:
2630 case OMAP_DSS_COLOR_RGB24P
:
2631 case OMAP_DSS_COLOR_ARGB16
:
2632 case OMAP_DSS_COLOR_RGBA16
:
2633 case OMAP_DSS_COLOR_RGB12U
:
2634 case OMAP_DSS_COLOR_ARGB16_1555
:
2635 case OMAP_DSS_COLOR_XRGB16_1555
:
2636 case OMAP_DSS_COLOR_RGBX16
:
2644 /* setup extra DISPC_WB_ATTRIBUTES */
2645 l
= dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane
));
2646 l
= FLD_MOD(l
, truncation
, 10, 10); /* TRUNCATIONENABLE */
2647 l
= FLD_MOD(l
, mem_to_mem
, 19, 19); /* WRITEBACKMODE */
2648 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane
), l
);
2653 int dispc_ovl_enable(enum omap_plane plane
, bool enable
)
2655 DSSDBG("dispc_enable_plane %d, %d\n", plane
, enable
);
2657 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane
), enable
? 1 : 0, 0, 0);
2661 EXPORT_SYMBOL(dispc_ovl_enable
);
2663 bool dispc_ovl_enabled(enum omap_plane plane
)
2665 return REG_GET(DISPC_OVL_ATTRIBUTES(plane
), 0, 0);
2667 EXPORT_SYMBOL(dispc_ovl_enabled
);
2669 void dispc_mgr_enable(enum omap_channel channel
, bool enable
)
2671 mgr_fld_write(channel
, DISPC_MGR_FLD_ENABLE
, enable
);
2672 /* flush posted write */
2673 mgr_fld_read(channel
, DISPC_MGR_FLD_ENABLE
);
2675 EXPORT_SYMBOL(dispc_mgr_enable
);
2677 bool dispc_mgr_is_enabled(enum omap_channel channel
)
2679 return !!mgr_fld_read(channel
, DISPC_MGR_FLD_ENABLE
);
2681 EXPORT_SYMBOL(dispc_mgr_is_enabled
);
2683 void dispc_wb_enable(bool enable
)
2685 dispc_ovl_enable(OMAP_DSS_WB
, enable
);
2688 bool dispc_wb_is_enabled(void)
2690 return dispc_ovl_enabled(OMAP_DSS_WB
);
2693 static void dispc_lcd_enable_signal_polarity(bool act_high
)
2695 if (!dss_has_feature(FEAT_LCDENABLEPOL
))
2698 REG_FLD_MOD(DISPC_CONTROL
, act_high
? 1 : 0, 29, 29);
2701 void dispc_lcd_enable_signal(bool enable
)
2703 if (!dss_has_feature(FEAT_LCDENABLESIGNAL
))
2706 REG_FLD_MOD(DISPC_CONTROL
, enable
? 1 : 0, 28, 28);
2709 void dispc_pck_free_enable(bool enable
)
2711 if (!dss_has_feature(FEAT_PCKFREEENABLE
))
2714 REG_FLD_MOD(DISPC_CONTROL
, enable
? 1 : 0, 27, 27);
2717 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel
, bool enable
)
2719 mgr_fld_write(channel
, DISPC_MGR_FLD_FIFOHANDCHECK
, enable
);
2723 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel
)
2725 mgr_fld_write(channel
, DISPC_MGR_FLD_STNTFT
, 1);
2728 void dispc_set_loadmode(enum omap_dss_load_mode mode
)
2730 REG_FLD_MOD(DISPC_CONFIG
, mode
, 2, 1);
2734 static void dispc_mgr_set_default_color(enum omap_channel channel
, u32 color
)
2736 dispc_write_reg(DISPC_DEFAULT_COLOR(channel
), color
);
2739 static void dispc_mgr_set_trans_key(enum omap_channel ch
,
2740 enum omap_dss_trans_key_type type
,
2743 mgr_fld_write(ch
, DISPC_MGR_FLD_TCKSELECTION
, type
);
2745 dispc_write_reg(DISPC_TRANS_COLOR(ch
), trans_key
);
2748 static void dispc_mgr_enable_trans_key(enum omap_channel ch
, bool enable
)
2750 mgr_fld_write(ch
, DISPC_MGR_FLD_TCKENABLE
, enable
);
2753 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch
,
2756 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
))
2759 if (ch
== OMAP_DSS_CHANNEL_LCD
)
2760 REG_FLD_MOD(DISPC_CONFIG
, enable
, 18, 18);
2761 else if (ch
== OMAP_DSS_CHANNEL_DIGIT
)
2762 REG_FLD_MOD(DISPC_CONFIG
, enable
, 19, 19);
2765 void dispc_mgr_setup(enum omap_channel channel
,
2766 const struct omap_overlay_manager_info
*info
)
2768 dispc_mgr_set_default_color(channel
, info
->default_color
);
2769 dispc_mgr_set_trans_key(channel
, info
->trans_key_type
, info
->trans_key
);
2770 dispc_mgr_enable_trans_key(channel
, info
->trans_enabled
);
2771 dispc_mgr_enable_alpha_fixed_zorder(channel
,
2772 info
->partial_alpha_enabled
);
2773 if (dss_has_feature(FEAT_CPR
)) {
2774 dispc_mgr_enable_cpr(channel
, info
->cpr_enable
);
2775 dispc_mgr_set_cpr_coef(channel
, &info
->cpr_coefs
);
2778 EXPORT_SYMBOL(dispc_mgr_setup
);
2780 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel
, u8 data_lines
)
2784 switch (data_lines
) {
2802 mgr_fld_write(channel
, DISPC_MGR_FLD_TFTDATALINES
, code
);
2805 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode
)
2811 case DSS_IO_PAD_MODE_RESET
:
2815 case DSS_IO_PAD_MODE_RFBI
:
2819 case DSS_IO_PAD_MODE_BYPASS
:
2828 l
= dispc_read_reg(DISPC_CONTROL
);
2829 l
= FLD_MOD(l
, gpout0
, 15, 15);
2830 l
= FLD_MOD(l
, gpout1
, 16, 16);
2831 dispc_write_reg(DISPC_CONTROL
, l
);
2834 static void dispc_mgr_enable_stallmode(enum omap_channel channel
, bool enable
)
2836 mgr_fld_write(channel
, DISPC_MGR_FLD_STALLMODE
, enable
);
2839 void dispc_mgr_set_lcd_config(enum omap_channel channel
,
2840 const struct dss_lcd_mgr_config
*config
)
2842 dispc_mgr_set_io_pad_mode(config
->io_pad_mode
);
2844 dispc_mgr_enable_stallmode(channel
, config
->stallmode
);
2845 dispc_mgr_enable_fifohandcheck(channel
, config
->fifohandcheck
);
2847 dispc_mgr_set_clock_div(channel
, &config
->clock_info
);
2849 dispc_mgr_set_tft_data_lines(channel
, config
->video_port_width
);
2851 dispc_lcd_enable_signal_polarity(config
->lcden_sig_polarity
);
2853 dispc_mgr_set_lcd_type_tft(channel
);
2855 EXPORT_SYMBOL(dispc_mgr_set_lcd_config
);
2857 static bool _dispc_mgr_size_ok(u16 width
, u16 height
)
2859 return width
<= dispc
.feat
->mgr_width_max
&&
2860 height
<= dispc
.feat
->mgr_height_max
;
2863 static bool _dispc_lcd_timings_ok(int hsw
, int hfp
, int hbp
,
2864 int vsw
, int vfp
, int vbp
)
2866 if (hsw
< 1 || hsw
> dispc
.feat
->sw_max
||
2867 hfp
< 1 || hfp
> dispc
.feat
->hp_max
||
2868 hbp
< 1 || hbp
> dispc
.feat
->hp_max
||
2869 vsw
< 1 || vsw
> dispc
.feat
->sw_max
||
2870 vfp
< 0 || vfp
> dispc
.feat
->vp_max
||
2871 vbp
< 0 || vbp
> dispc
.feat
->vp_max
)
2876 static bool _dispc_mgr_pclk_ok(enum omap_channel channel
,
2879 if (dss_mgr_is_lcd(channel
))
2880 return pclk
<= dispc
.feat
->max_lcd_pclk
? true : false;
2882 return pclk
<= dispc
.feat
->max_tv_pclk
? true : false;
2885 bool dispc_mgr_timings_ok(enum omap_channel channel
,
2886 const struct omap_video_timings
*timings
)
2888 if (!_dispc_mgr_size_ok(timings
->x_res
, timings
->y_res
))
2891 if (!_dispc_mgr_pclk_ok(channel
, timings
->pixelclock
))
2894 if (dss_mgr_is_lcd(channel
)) {
2895 /* TODO: OMAP4+ supports interlace for LCD outputs */
2896 if (timings
->interlace
)
2899 if (!_dispc_lcd_timings_ok(timings
->hsw
, timings
->hfp
,
2900 timings
->hbp
, timings
->vsw
, timings
->vfp
,
2908 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel
, int hsw
,
2909 int hfp
, int hbp
, int vsw
, int vfp
, int vbp
,
2910 enum omap_dss_signal_level vsync_level
,
2911 enum omap_dss_signal_level hsync_level
,
2912 enum omap_dss_signal_edge data_pclk_edge
,
2913 enum omap_dss_signal_level de_level
,
2914 enum omap_dss_signal_edge sync_pclk_edge
)
2917 u32 timing_h
, timing_v
, l
;
2918 bool onoff
, rf
, ipc
;
2920 timing_h
= FLD_VAL(hsw
-1, dispc
.feat
->sw_start
, 0) |
2921 FLD_VAL(hfp
-1, dispc
.feat
->fp_start
, 8) |
2922 FLD_VAL(hbp
-1, dispc
.feat
->bp_start
, 20);
2923 timing_v
= FLD_VAL(vsw
-1, dispc
.feat
->sw_start
, 0) |
2924 FLD_VAL(vfp
, dispc
.feat
->fp_start
, 8) |
2925 FLD_VAL(vbp
, dispc
.feat
->bp_start
, 20);
2927 dispc_write_reg(DISPC_TIMING_H(channel
), timing_h
);
2928 dispc_write_reg(DISPC_TIMING_V(channel
), timing_v
);
2930 switch (data_pclk_edge
) {
2931 case OMAPDSS_DRIVE_SIG_RISING_EDGE
:
2934 case OMAPDSS_DRIVE_SIG_FALLING_EDGE
:
2937 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES
:
2942 switch (sync_pclk_edge
) {
2943 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES
:
2947 case OMAPDSS_DRIVE_SIG_FALLING_EDGE
:
2951 case OMAPDSS_DRIVE_SIG_RISING_EDGE
:
2959 l
= FLD_VAL(onoff
, 17, 17) |
2960 FLD_VAL(rf
, 16, 16) |
2961 FLD_VAL(de_level
, 15, 15) |
2962 FLD_VAL(ipc
, 14, 14) |
2963 FLD_VAL(hsync_level
, 13, 13) |
2964 FLD_VAL(vsync_level
, 12, 12);
2966 dispc_write_reg(DISPC_POL_FREQ(channel
), l
);
2968 if (dispc
.syscon_pol
) {
2969 const int shifts
[] = {
2970 [OMAP_DSS_CHANNEL_LCD
] = 0,
2971 [OMAP_DSS_CHANNEL_LCD2
] = 1,
2972 [OMAP_DSS_CHANNEL_LCD3
] = 2,
2977 mask
= (1 << 0) | (1 << 3) | (1 << 6);
2978 val
= (rf
<< 0) | (ipc
<< 3) | (onoff
<< 6);
2980 mask
<<= 16 + shifts
[channel
];
2981 val
<<= 16 + shifts
[channel
];
2983 regmap_update_bits(dispc
.syscon_pol
, dispc
.syscon_pol_offset
,
2988 /* change name to mode? */
2989 void dispc_mgr_set_timings(enum omap_channel channel
,
2990 const struct omap_video_timings
*timings
)
2992 unsigned xtot
, ytot
;
2993 unsigned long ht
, vt
;
2994 struct omap_video_timings t
= *timings
;
2996 DSSDBG("channel %d xres %u yres %u\n", channel
, t
.x_res
, t
.y_res
);
2998 if (!dispc_mgr_timings_ok(channel
, &t
)) {
3003 if (dss_mgr_is_lcd(channel
)) {
3004 _dispc_mgr_set_lcd_timings(channel
, t
.hsw
, t
.hfp
, t
.hbp
, t
.vsw
,
3005 t
.vfp
, t
.vbp
, t
.vsync_level
, t
.hsync_level
,
3006 t
.data_pclk_edge
, t
.de_level
, t
.sync_pclk_edge
);
3008 xtot
= t
.x_res
+ t
.hfp
+ t
.hsw
+ t
.hbp
;
3009 ytot
= t
.y_res
+ t
.vfp
+ t
.vsw
+ t
.vbp
;
3011 ht
= timings
->pixelclock
/ xtot
;
3012 vt
= timings
->pixelclock
/ xtot
/ ytot
;
3014 DSSDBG("pck %u\n", timings
->pixelclock
);
3015 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3016 t
.hsw
, t
.hfp
, t
.hbp
, t
.vsw
, t
.vfp
, t
.vbp
);
3017 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3018 t
.vsync_level
, t
.hsync_level
, t
.data_pclk_edge
,
3019 t
.de_level
, t
.sync_pclk_edge
);
3021 DSSDBG("hsync %luHz, vsync %luHz\n", ht
, vt
);
3023 if (t
.interlace
== true)
3027 dispc_mgr_set_size(channel
, t
.x_res
, t
.y_res
);
3029 EXPORT_SYMBOL(dispc_mgr_set_timings
);
3031 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel
, u16 lck_div
,
3034 BUG_ON(lck_div
< 1);
3035 BUG_ON(pck_div
< 1);
3037 dispc_write_reg(DISPC_DIVISORo(channel
),
3038 FLD_VAL(lck_div
, 23, 16) | FLD_VAL(pck_div
, 7, 0));
3040 if (dss_has_feature(FEAT_CORE_CLK_DIV
) == false &&
3041 channel
== OMAP_DSS_CHANNEL_LCD
)
3042 dispc
.core_clk_rate
= dispc_fclk_rate() / lck_div
;
3045 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel
, int *lck_div
,
3049 l
= dispc_read_reg(DISPC_DIVISORo(channel
));
3050 *lck_div
= FLD_GET(l
, 23, 16);
3051 *pck_div
= FLD_GET(l
, 7, 0);
3054 unsigned long dispc_fclk_rate(void)
3056 struct dss_pll
*pll
;
3057 unsigned long r
= 0;
3059 switch (dss_get_dispc_clk_source()) {
3060 case OMAP_DSS_CLK_SRC_FCK
:
3061 r
= dss_get_dispc_clk_rate();
3063 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
3064 pll
= dss_pll_find("dsi0");
3066 pll
= dss_pll_find("video0");
3068 r
= pll
->cinfo
.clkout
[0];
3070 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
:
3071 pll
= dss_pll_find("dsi1");
3073 pll
= dss_pll_find("video1");
3075 r
= pll
->cinfo
.clkout
[0];
3085 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel
)
3087 struct dss_pll
*pll
;
3092 if (dss_mgr_is_lcd(channel
)) {
3093 l
= dispc_read_reg(DISPC_DIVISORo(channel
));
3095 lcd
= FLD_GET(l
, 23, 16);
3097 switch (dss_get_lcd_clk_source(channel
)) {
3098 case OMAP_DSS_CLK_SRC_FCK
:
3099 r
= dss_get_dispc_clk_rate();
3101 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
3102 pll
= dss_pll_find("dsi0");
3104 pll
= dss_pll_find("video0");
3106 r
= pll
->cinfo
.clkout
[0];
3108 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
:
3109 pll
= dss_pll_find("dsi1");
3111 pll
= dss_pll_find("video1");
3113 r
= pll
->cinfo
.clkout
[0];
3122 return dispc_fclk_rate();
3126 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel
)
3130 if (dss_mgr_is_lcd(channel
)) {
3134 l
= dispc_read_reg(DISPC_DIVISORo(channel
));
3136 pcd
= FLD_GET(l
, 7, 0);
3138 r
= dispc_mgr_lclk_rate(channel
);
3142 return dispc
.tv_pclk_rate
;
3146 void dispc_set_tv_pclk(unsigned long pclk
)
3148 dispc
.tv_pclk_rate
= pclk
;
3151 unsigned long dispc_core_clk_rate(void)
3153 return dispc
.core_clk_rate
;
3156 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane
)
3158 enum omap_channel channel
;
3160 if (plane
== OMAP_DSS_WB
)
3163 channel
= dispc_ovl_get_channel_out(plane
);
3165 return dispc_mgr_pclk_rate(channel
);
3168 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane
)
3170 enum omap_channel channel
;
3172 if (plane
== OMAP_DSS_WB
)
3175 channel
= dispc_ovl_get_channel_out(plane
);
3177 return dispc_mgr_lclk_rate(channel
);
3180 static void dispc_dump_clocks_channel(struct seq_file
*s
, enum omap_channel channel
)
3183 enum omap_dss_clk_source lcd_clk_src
;
3185 seq_printf(s
, "- %s -\n", mgr_desc
[channel
].name
);
3187 lcd_clk_src
= dss_get_lcd_clk_source(channel
);
3189 seq_printf(s
, "%s clk source = %s (%s)\n", mgr_desc
[channel
].name
,
3190 dss_get_generic_clk_source_name(lcd_clk_src
),
3191 dss_feat_get_clk_source_name(lcd_clk_src
));
3193 dispc_mgr_get_lcd_divisor(channel
, &lcd
, &pcd
);
3195 seq_printf(s
, "lck\t\t%-16lulck div\t%u\n",
3196 dispc_mgr_lclk_rate(channel
), lcd
);
3197 seq_printf(s
, "pck\t\t%-16lupck div\t%u\n",
3198 dispc_mgr_pclk_rate(channel
), pcd
);
3201 void dispc_dump_clocks(struct seq_file
*s
)
3205 enum omap_dss_clk_source dispc_clk_src
= dss_get_dispc_clk_source();
3207 if (dispc_runtime_get())
3210 seq_printf(s
, "- DISPC -\n");
3212 seq_printf(s
, "dispc fclk source = %s (%s)\n",
3213 dss_get_generic_clk_source_name(dispc_clk_src
),
3214 dss_feat_get_clk_source_name(dispc_clk_src
));
3216 seq_printf(s
, "fck\t\t%-16lu\n", dispc_fclk_rate());
3218 if (dss_has_feature(FEAT_CORE_CLK_DIV
)) {
3219 seq_printf(s
, "- DISPC-CORE-CLK -\n");
3220 l
= dispc_read_reg(DISPC_DIVISOR
);
3221 lcd
= FLD_GET(l
, 23, 16);
3223 seq_printf(s
, "lck\t\t%-16lulck div\t%u\n",
3224 (dispc_fclk_rate()/lcd
), lcd
);
3227 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD
);
3229 if (dss_has_feature(FEAT_MGR_LCD2
))
3230 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD2
);
3231 if (dss_has_feature(FEAT_MGR_LCD3
))
3232 dispc_dump_clocks_channel(s
, OMAP_DSS_CHANNEL_LCD3
);
3234 dispc_runtime_put();
3237 static void dispc_dump_regs(struct seq_file
*s
)
3240 const char *mgr_names
[] = {
3241 [OMAP_DSS_CHANNEL_LCD
] = "LCD",
3242 [OMAP_DSS_CHANNEL_DIGIT
] = "TV",
3243 [OMAP_DSS_CHANNEL_LCD2
] = "LCD2",
3244 [OMAP_DSS_CHANNEL_LCD3
] = "LCD3",
3246 const char *ovl_names
[] = {
3247 [OMAP_DSS_GFX
] = "GFX",
3248 [OMAP_DSS_VIDEO1
] = "VID1",
3249 [OMAP_DSS_VIDEO2
] = "VID2",
3250 [OMAP_DSS_VIDEO3
] = "VID3",
3252 const char **p_names
;
3254 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3256 if (dispc_runtime_get())
3259 /* DISPC common registers */
3260 DUMPREG(DISPC_REVISION
);
3261 DUMPREG(DISPC_SYSCONFIG
);
3262 DUMPREG(DISPC_SYSSTATUS
);
3263 DUMPREG(DISPC_IRQSTATUS
);
3264 DUMPREG(DISPC_IRQENABLE
);
3265 DUMPREG(DISPC_CONTROL
);
3266 DUMPREG(DISPC_CONFIG
);
3267 DUMPREG(DISPC_CAPABLE
);
3268 DUMPREG(DISPC_LINE_STATUS
);
3269 DUMPREG(DISPC_LINE_NUMBER
);
3270 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER
) ||
3271 dss_has_feature(FEAT_ALPHA_FREE_ZORDER
))
3272 DUMPREG(DISPC_GLOBAL_ALPHA
);
3273 if (dss_has_feature(FEAT_MGR_LCD2
)) {
3274 DUMPREG(DISPC_CONTROL2
);
3275 DUMPREG(DISPC_CONFIG2
);
3277 if (dss_has_feature(FEAT_MGR_LCD3
)) {
3278 DUMPREG(DISPC_CONTROL3
);
3279 DUMPREG(DISPC_CONFIG3
);
3281 if (dss_has_feature(FEAT_MFLAG
))
3282 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE
);
3286 #define DISPC_REG(i, name) name(i)
3287 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3288 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3289 dispc_read_reg(DISPC_REG(i, r)))
3291 p_names
= mgr_names
;
3293 /* DISPC channel specific registers */
3294 for (i
= 0; i
< dss_feat_get_num_mgrs(); i
++) {
3295 DUMPREG(i
, DISPC_DEFAULT_COLOR
);
3296 DUMPREG(i
, DISPC_TRANS_COLOR
);
3297 DUMPREG(i
, DISPC_SIZE_MGR
);
3299 if (i
== OMAP_DSS_CHANNEL_DIGIT
)
3302 DUMPREG(i
, DISPC_TIMING_H
);
3303 DUMPREG(i
, DISPC_TIMING_V
);
3304 DUMPREG(i
, DISPC_POL_FREQ
);
3305 DUMPREG(i
, DISPC_DIVISORo
);
3307 DUMPREG(i
, DISPC_DATA_CYCLE1
);
3308 DUMPREG(i
, DISPC_DATA_CYCLE2
);
3309 DUMPREG(i
, DISPC_DATA_CYCLE3
);
3311 if (dss_has_feature(FEAT_CPR
)) {
3312 DUMPREG(i
, DISPC_CPR_COEF_R
);
3313 DUMPREG(i
, DISPC_CPR_COEF_G
);
3314 DUMPREG(i
, DISPC_CPR_COEF_B
);
3318 p_names
= ovl_names
;
3320 for (i
= 0; i
< dss_feat_get_num_ovls(); i
++) {
3321 DUMPREG(i
, DISPC_OVL_BA0
);
3322 DUMPREG(i
, DISPC_OVL_BA1
);
3323 DUMPREG(i
, DISPC_OVL_POSITION
);
3324 DUMPREG(i
, DISPC_OVL_SIZE
);
3325 DUMPREG(i
, DISPC_OVL_ATTRIBUTES
);
3326 DUMPREG(i
, DISPC_OVL_FIFO_THRESHOLD
);
3327 DUMPREG(i
, DISPC_OVL_FIFO_SIZE_STATUS
);
3328 DUMPREG(i
, DISPC_OVL_ROW_INC
);
3329 DUMPREG(i
, DISPC_OVL_PIXEL_INC
);
3331 if (dss_has_feature(FEAT_PRELOAD
))
3332 DUMPREG(i
, DISPC_OVL_PRELOAD
);
3333 if (dss_has_feature(FEAT_MFLAG
))
3334 DUMPREG(i
, DISPC_OVL_MFLAG_THRESHOLD
);
3336 if (i
== OMAP_DSS_GFX
) {
3337 DUMPREG(i
, DISPC_OVL_WINDOW_SKIP
);
3338 DUMPREG(i
, DISPC_OVL_TABLE_BA
);
3342 DUMPREG(i
, DISPC_OVL_FIR
);
3343 DUMPREG(i
, DISPC_OVL_PICTURE_SIZE
);
3344 DUMPREG(i
, DISPC_OVL_ACCU0
);
3345 DUMPREG(i
, DISPC_OVL_ACCU1
);
3346 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
3347 DUMPREG(i
, DISPC_OVL_BA0_UV
);
3348 DUMPREG(i
, DISPC_OVL_BA1_UV
);
3349 DUMPREG(i
, DISPC_OVL_FIR2
);
3350 DUMPREG(i
, DISPC_OVL_ACCU2_0
);
3351 DUMPREG(i
, DISPC_OVL_ACCU2_1
);
3353 if (dss_has_feature(FEAT_ATTR2
))
3354 DUMPREG(i
, DISPC_OVL_ATTRIBUTES2
);
3360 #define DISPC_REG(plane, name, i) name(plane, i)
3361 #define DUMPREG(plane, name, i) \
3362 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3363 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3364 dispc_read_reg(DISPC_REG(plane, name, i)))
3366 /* Video pipeline coefficient registers */
3368 /* start from OMAP_DSS_VIDEO1 */
3369 for (i
= 1; i
< dss_feat_get_num_ovls(); i
++) {
3370 for (j
= 0; j
< 8; j
++)
3371 DUMPREG(i
, DISPC_OVL_FIR_COEF_H
, j
);
3373 for (j
= 0; j
< 8; j
++)
3374 DUMPREG(i
, DISPC_OVL_FIR_COEF_HV
, j
);
3376 for (j
= 0; j
< 5; j
++)
3377 DUMPREG(i
, DISPC_OVL_CONV_COEF
, j
);
3379 if (dss_has_feature(FEAT_FIR_COEF_V
)) {
3380 for (j
= 0; j
< 8; j
++)
3381 DUMPREG(i
, DISPC_OVL_FIR_COEF_V
, j
);
3384 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE
)) {
3385 for (j
= 0; j
< 8; j
++)
3386 DUMPREG(i
, DISPC_OVL_FIR_COEF_H2
, j
);
3388 for (j
= 0; j
< 8; j
++)
3389 DUMPREG(i
, DISPC_OVL_FIR_COEF_HV2
, j
);
3391 for (j
= 0; j
< 8; j
++)
3392 DUMPREG(i
, DISPC_OVL_FIR_COEF_V2
, j
);
3396 dispc_runtime_put();
3402 /* calculate clock rates using dividers in cinfo */
3403 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate
,
3404 struct dispc_clock_info
*cinfo
)
3406 if (cinfo
->lck_div
> 255 || cinfo
->lck_div
== 0)
3408 if (cinfo
->pck_div
< 1 || cinfo
->pck_div
> 255)
3411 cinfo
->lck
= dispc_fclk_rate
/ cinfo
->lck_div
;
3412 cinfo
->pck
= cinfo
->lck
/ cinfo
->pck_div
;
3417 bool dispc_div_calc(unsigned long dispc
,
3418 unsigned long pck_min
, unsigned long pck_max
,
3419 dispc_div_calc_func func
, void *data
)
3421 int lckd
, lckd_start
, lckd_stop
;
3422 int pckd
, pckd_start
, pckd_stop
;
3423 unsigned long pck
, lck
;
3424 unsigned long lck_max
;
3425 unsigned long pckd_hw_min
, pckd_hw_max
;
3426 unsigned min_fck_per_pck
;
3429 #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3430 min_fck_per_pck
= CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
;
3432 min_fck_per_pck
= 0;
3435 pckd_hw_min
= dss_feat_get_param_min(FEAT_PARAM_DSS_PCD
);
3436 pckd_hw_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_PCD
);
3438 lck_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
3440 pck_min
= pck_min
? pck_min
: 1;
3441 pck_max
= pck_max
? pck_max
: ULONG_MAX
;
3443 lckd_start
= max(DIV_ROUND_UP(dispc
, lck_max
), 1ul);
3444 lckd_stop
= min(dispc
/ pck_min
, 255ul);
3446 for (lckd
= lckd_start
; lckd
<= lckd_stop
; ++lckd
) {
3449 pckd_start
= max(DIV_ROUND_UP(lck
, pck_max
), pckd_hw_min
);
3450 pckd_stop
= min(lck
/ pck_min
, pckd_hw_max
);
3452 for (pckd
= pckd_start
; pckd
<= pckd_stop
; ++pckd
) {
3456 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3457 * clock, which means we're configuring DISPC fclk here
3458 * also. Thus we need to use the calculated lck. For
3459 * OMAP4+ the DISPC fclk is a separate clock.
3461 if (dss_has_feature(FEAT_CORE_CLK_DIV
))
3462 fck
= dispc_core_clk_rate();
3466 if (fck
< pck
* min_fck_per_pck
)
3469 if (func(lckd
, pckd
, lck
, pck
, data
))
3477 void dispc_mgr_set_clock_div(enum omap_channel channel
,
3478 const struct dispc_clock_info
*cinfo
)
3480 DSSDBG("lck = %lu (%u)\n", cinfo
->lck
, cinfo
->lck_div
);
3481 DSSDBG("pck = %lu (%u)\n", cinfo
->pck
, cinfo
->pck_div
);
3483 dispc_mgr_set_lcd_divisor(channel
, cinfo
->lck_div
, cinfo
->pck_div
);
3486 int dispc_mgr_get_clock_div(enum omap_channel channel
,
3487 struct dispc_clock_info
*cinfo
)
3491 fck
= dispc_fclk_rate();
3493 cinfo
->lck_div
= REG_GET(DISPC_DIVISORo(channel
), 23, 16);
3494 cinfo
->pck_div
= REG_GET(DISPC_DIVISORo(channel
), 7, 0);
3496 cinfo
->lck
= fck
/ cinfo
->lck_div
;
3497 cinfo
->pck
= cinfo
->lck
/ cinfo
->pck_div
;
3502 u32
dispc_read_irqstatus(void)
3504 return dispc_read_reg(DISPC_IRQSTATUS
);
3506 EXPORT_SYMBOL(dispc_read_irqstatus
);
3508 void dispc_clear_irqstatus(u32 mask
)
3510 dispc_write_reg(DISPC_IRQSTATUS
, mask
);
3512 EXPORT_SYMBOL(dispc_clear_irqstatus
);
3514 u32
dispc_read_irqenable(void)
3516 return dispc_read_reg(DISPC_IRQENABLE
);
3518 EXPORT_SYMBOL(dispc_read_irqenable
);
3520 void dispc_write_irqenable(u32 mask
)
3522 u32 old_mask
= dispc_read_reg(DISPC_IRQENABLE
);
3524 /* clear the irqstatus for newly enabled irqs */
3525 dispc_clear_irqstatus((mask
^ old_mask
) & mask
);
3527 dispc_write_reg(DISPC_IRQENABLE
, mask
);
3529 EXPORT_SYMBOL(dispc_write_irqenable
);
3531 void dispc_enable_sidle(void)
3533 REG_FLD_MOD(DISPC_SYSCONFIG
, 2, 4, 3); /* SIDLEMODE: smart idle */
3536 void dispc_disable_sidle(void)
3538 REG_FLD_MOD(DISPC_SYSCONFIG
, 1, 4, 3); /* SIDLEMODE: no idle */
3541 static void _omap_dispc_initial_config(void)
3545 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3546 if (dss_has_feature(FEAT_CORE_CLK_DIV
)) {
3547 l
= dispc_read_reg(DISPC_DIVISOR
);
3548 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3549 l
= FLD_MOD(l
, 1, 0, 0);
3550 l
= FLD_MOD(l
, 1, 23, 16);
3551 dispc_write_reg(DISPC_DIVISOR
, l
);
3553 dispc
.core_clk_rate
= dispc_fclk_rate();
3557 if (dss_has_feature(FEAT_FUNCGATED
))
3558 REG_FLD_MOD(DISPC_CONFIG
, 1, 9, 9);
3560 dispc_setup_color_conv_coef();
3562 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY
);
3566 dispc_configure_burst_sizes();
3568 dispc_ovl_enable_zorder_planes();
3570 if (dispc
.feat
->mstandby_workaround
)
3571 REG_FLD_MOD(DISPC_MSTANDBY_CTRL
, 1, 0, 0);
3574 static const struct dispc_features omap24xx_dispc_feats __initconst
= {
3581 .mgr_width_start
= 10,
3582 .mgr_height_start
= 26,
3583 .mgr_width_max
= 2048,
3584 .mgr_height_max
= 2048,
3585 .max_lcd_pclk
= 66500000,
3586 .calc_scaling
= dispc_ovl_calc_scaling_24xx
,
3587 .calc_core_clk
= calc_core_clk_24xx
,
3589 .no_framedone_tv
= true,
3590 .set_max_preload
= false,
3593 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst
= {
3600 .mgr_width_start
= 10,
3601 .mgr_height_start
= 26,
3602 .mgr_width_max
= 2048,
3603 .mgr_height_max
= 2048,
3604 .max_lcd_pclk
= 173000000,
3605 .max_tv_pclk
= 59000000,
3606 .calc_scaling
= dispc_ovl_calc_scaling_34xx
,
3607 .calc_core_clk
= calc_core_clk_34xx
,
3609 .no_framedone_tv
= true,
3610 .set_max_preload
= false,
3613 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst
= {
3620 .mgr_width_start
= 10,
3621 .mgr_height_start
= 26,
3622 .mgr_width_max
= 2048,
3623 .mgr_height_max
= 2048,
3624 .max_lcd_pclk
= 173000000,
3625 .max_tv_pclk
= 59000000,
3626 .calc_scaling
= dispc_ovl_calc_scaling_34xx
,
3627 .calc_core_clk
= calc_core_clk_34xx
,
3629 .no_framedone_tv
= true,
3630 .set_max_preload
= false,
3633 static const struct dispc_features omap44xx_dispc_feats __initconst
= {
3640 .mgr_width_start
= 10,
3641 .mgr_height_start
= 26,
3642 .mgr_width_max
= 2048,
3643 .mgr_height_max
= 2048,
3644 .max_lcd_pclk
= 170000000,
3645 .max_tv_pclk
= 185625000,
3646 .calc_scaling
= dispc_ovl_calc_scaling_44xx
,
3647 .calc_core_clk
= calc_core_clk_44xx
,
3649 .gfx_fifo_workaround
= true,
3650 .set_max_preload
= true,
3653 static const struct dispc_features omap54xx_dispc_feats __initconst
= {
3660 .mgr_width_start
= 11,
3661 .mgr_height_start
= 27,
3662 .mgr_width_max
= 4096,
3663 .mgr_height_max
= 4096,
3664 .max_lcd_pclk
= 170000000,
3665 .max_tv_pclk
= 186000000,
3666 .calc_scaling
= dispc_ovl_calc_scaling_44xx
,
3667 .calc_core_clk
= calc_core_clk_44xx
,
3669 .gfx_fifo_workaround
= true,
3670 .mstandby_workaround
= true,
3671 .set_max_preload
= true,
3674 static int __init
dispc_init_features(struct platform_device
*pdev
)
3676 const struct dispc_features
*src
;
3677 struct dispc_features
*dst
;
3679 dst
= devm_kzalloc(&pdev
->dev
, sizeof(*dst
), GFP_KERNEL
);
3681 dev_err(&pdev
->dev
, "Failed to allocate DISPC Features\n");
3685 switch (omapdss_get_version()) {
3686 case OMAPDSS_VER_OMAP24xx
:
3687 src
= &omap24xx_dispc_feats
;
3690 case OMAPDSS_VER_OMAP34xx_ES1
:
3691 src
= &omap34xx_rev1_0_dispc_feats
;
3694 case OMAPDSS_VER_OMAP34xx_ES3
:
3695 case OMAPDSS_VER_OMAP3630
:
3696 case OMAPDSS_VER_AM35xx
:
3697 case OMAPDSS_VER_AM43xx
:
3698 src
= &omap34xx_rev3_0_dispc_feats
;
3701 case OMAPDSS_VER_OMAP4430_ES1
:
3702 case OMAPDSS_VER_OMAP4430_ES2
:
3703 case OMAPDSS_VER_OMAP4
:
3704 src
= &omap44xx_dispc_feats
;
3707 case OMAPDSS_VER_OMAP5
:
3708 case OMAPDSS_VER_DRA7xx
:
3709 src
= &omap54xx_dispc_feats
;
3716 memcpy(dst
, src
, sizeof(*dst
));
3722 static irqreturn_t
dispc_irq_handler(int irq
, void *arg
)
3724 if (!dispc
.is_enabled
)
3727 return dispc
.user_handler(irq
, dispc
.user_data
);
3730 int dispc_request_irq(irq_handler_t handler
, void *dev_id
)
3734 if (dispc
.user_handler
!= NULL
)
3737 dispc
.user_handler
= handler
;
3738 dispc
.user_data
= dev_id
;
3740 /* ensure the dispc_irq_handler sees the values above */
3743 r
= devm_request_irq(&dispc
.pdev
->dev
, dispc
.irq
, dispc_irq_handler
,
3744 IRQF_SHARED
, "OMAP DISPC", &dispc
);
3746 dispc
.user_handler
= NULL
;
3747 dispc
.user_data
= NULL
;
3752 EXPORT_SYMBOL(dispc_request_irq
);
3754 void dispc_free_irq(void *dev_id
)
3756 devm_free_irq(&dispc
.pdev
->dev
, dispc
.irq
, &dispc
);
3758 dispc
.user_handler
= NULL
;
3759 dispc
.user_data
= NULL
;
3761 EXPORT_SYMBOL(dispc_free_irq
);
3763 /* DISPC HW IP initialisation */
3764 static int __init
omap_dispchw_probe(struct platform_device
*pdev
)
3768 struct resource
*dispc_mem
;
3769 struct device_node
*np
= pdev
->dev
.of_node
;
3773 r
= dispc_init_features(dispc
.pdev
);
3777 dispc_mem
= platform_get_resource(dispc
.pdev
, IORESOURCE_MEM
, 0);
3779 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3783 dispc
.base
= devm_ioremap(&pdev
->dev
, dispc_mem
->start
,
3784 resource_size(dispc_mem
));
3786 DSSERR("can't ioremap DISPC\n");
3790 dispc
.irq
= platform_get_irq(dispc
.pdev
, 0);
3791 if (dispc
.irq
< 0) {
3792 DSSERR("platform_get_irq failed\n");
3796 if (np
&& of_property_read_bool(np
, "syscon-pol")) {
3797 dispc
.syscon_pol
= syscon_regmap_lookup_by_phandle(np
, "syscon-pol");
3798 if (IS_ERR(dispc
.syscon_pol
)) {
3799 dev_err(&pdev
->dev
, "failed to get syscon-pol regmap\n");
3800 return PTR_ERR(dispc
.syscon_pol
);
3803 if (of_property_read_u32_index(np
, "syscon-pol", 1,
3804 &dispc
.syscon_pol_offset
)) {
3805 dev_err(&pdev
->dev
, "failed to get syscon-pol offset\n");
3810 pm_runtime_enable(&pdev
->dev
);
3812 r
= dispc_runtime_get();
3814 goto err_runtime_get
;
3816 _omap_dispc_initial_config();
3818 rev
= dispc_read_reg(DISPC_REVISION
);
3819 dev_dbg(&pdev
->dev
, "OMAP DISPC rev %d.%d\n",
3820 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
3822 dispc_runtime_put();
3824 dss_init_overlay_managers();
3826 dss_debugfs_create_file("dispc", dispc_dump_regs
);
3831 pm_runtime_disable(&pdev
->dev
);
3835 static int __exit
omap_dispchw_remove(struct platform_device
*pdev
)
3837 pm_runtime_disable(&pdev
->dev
);
3839 dss_uninit_overlay_managers();
3844 static int dispc_runtime_suspend(struct device
*dev
)
3846 dispc
.is_enabled
= false;
3847 /* ensure the dispc_irq_handler sees the is_enabled value */
3849 /* wait for current handler to finish before turning the DISPC off */
3850 synchronize_irq(dispc
.irq
);
3852 dispc_save_context();
3857 static int dispc_runtime_resume(struct device
*dev
)
3860 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3861 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3862 * _omap_dispc_initial_config(). We can thus use it to detect if
3863 * we have lost register context.
3865 if (REG_GET(DISPC_CONFIG
, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY
) {
3866 _omap_dispc_initial_config();
3868 dispc_restore_context();
3871 dispc
.is_enabled
= true;
3872 /* ensure the dispc_irq_handler sees the is_enabled value */
3878 static const struct dev_pm_ops dispc_pm_ops
= {
3879 .runtime_suspend
= dispc_runtime_suspend
,
3880 .runtime_resume
= dispc_runtime_resume
,
3883 static const struct of_device_id dispc_of_match
[] = {
3884 { .compatible
= "ti,omap2-dispc", },
3885 { .compatible
= "ti,omap3-dispc", },
3886 { .compatible
= "ti,omap4-dispc", },
3887 { .compatible
= "ti,omap5-dispc", },
3888 { .compatible
= "ti,dra7-dispc", },
3892 static struct platform_driver omap_dispchw_driver
= {
3893 .remove
= __exit_p(omap_dispchw_remove
),
3895 .name
= "omapdss_dispc",
3896 .pm
= &dispc_pm_ops
,
3897 .of_match_table
= dispc_of_match
,
3898 .suppress_bind_attrs
= true,
3902 int __init
dispc_init_platform_driver(void)
3904 return platform_driver_probe(&omap_dispchw_driver
, omap_dispchw_probe
);
3907 void __exit
dispc_uninit_platform_driver(void)
3909 platform_driver_unregister(&omap_dispchw_driver
);