2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/export.h>
29 #include <linux/err.h>
30 #include <linux/delay.h>
31 #include <linux/seq_file.h>
32 #include <linux/clk.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/gfp.h>
36 #include <linux/sizes.h>
37 #include <linux/mfd/syscon.h>
38 #include <linux/regmap.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/suspend.h>
43 #include <video/omapdss.h>
46 #include "dss_features.h"
48 #define DSS_SZ_REGS SZ_512
54 #define DSS_REG(idx) ((const struct dss_reg) { idx })
56 #define DSS_REVISION DSS_REG(0x0000)
57 #define DSS_SYSCONFIG DSS_REG(0x0010)
58 #define DSS_SYSSTATUS DSS_REG(0x0014)
59 #define DSS_CONTROL DSS_REG(0x0040)
60 #define DSS_SDI_CONTROL DSS_REG(0x0044)
61 #define DSS_PLL_CONTROL DSS_REG(0x0048)
62 #define DSS_SDI_STATUS DSS_REG(0x005C)
64 #define REG_GET(idx, start, end) \
65 FLD_GET(dss_read_reg(idx), start, end)
67 #define REG_FLD_MOD(idx, val, start, end) \
68 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
72 u8 dss_fck_multiplier
;
73 const char *parent_clk_name
;
74 const enum omap_display_type
*ports
;
76 int (*dpi_select_source
)(int port
, enum omap_channel channel
);
80 struct platform_device
*pdev
;
82 struct regmap
*syscon_pll_ctrl
;
83 u32 syscon_pll_ctrl_offset
;
85 struct clk
*parent_clk
;
87 unsigned long dss_clk_rate
;
89 unsigned long cache_req_pck
;
90 unsigned long cache_prate
;
91 struct dispc_clock_info cache_dispc_cinfo
;
93 enum omap_dss_clk_source dsi_clk_source
[MAX_NUM_DSI
];
94 enum omap_dss_clk_source dispc_clk_source
;
95 enum omap_dss_clk_source lcd_clk_source
[MAX_DSS_LCD_MANAGERS
];
98 u32 ctx
[DSS_SZ_REGS
/ sizeof(u32
)];
100 const struct dss_features
*feat
;
102 struct dss_pll
*video1_pll
;
103 struct dss_pll
*video2_pll
;
106 static const char * const dss_generic_clk_source_names
[] = {
107 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
] = "DSI_PLL_HSDIV_DISPC",
108 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
] = "DSI_PLL_HSDIV_DSI",
109 [OMAP_DSS_CLK_SRC_FCK
] = "DSS_FCK",
110 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
] = "DSI_PLL2_HSDIV_DISPC",
111 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
] = "DSI_PLL2_HSDIV_DSI",
114 static bool dss_initialized
;
116 bool omapdss_is_initialized(void)
118 return dss_initialized
;
120 EXPORT_SYMBOL(omapdss_is_initialized
);
122 static inline void dss_write_reg(const struct dss_reg idx
, u32 val
)
124 __raw_writel(val
, dss
.base
+ idx
.idx
);
127 static inline u32
dss_read_reg(const struct dss_reg idx
)
129 return __raw_readl(dss
.base
+ idx
.idx
);
133 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
135 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
137 static void dss_save_context(void)
139 DSSDBG("dss_save_context\n");
143 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
144 OMAP_DISPLAY_TYPE_SDI
) {
149 dss
.ctx_valid
= true;
151 DSSDBG("context saved\n");
154 static void dss_restore_context(void)
156 DSSDBG("dss_restore_context\n");
163 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
164 OMAP_DISPLAY_TYPE_SDI
) {
169 DSSDBG("context restored\n");
175 void dss_ctrl_pll_enable(enum dss_pll_id pll_id
, bool enable
)
180 if (!dss
.syscon_pll_ctrl
)
196 DSSERR("illegal DSS PLL ID %d\n", pll_id
);
200 regmap_update_bits(dss
.syscon_pll_ctrl
, dss
.syscon_pll_ctrl_offset
,
201 1 << shift
, val
<< shift
);
204 void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id
,
205 enum omap_channel channel
)
209 if (!dss
.syscon_pll_ctrl
)
213 case OMAP_DSS_CHANNEL_LCD
:
222 DSSERR("error in PLL mux config for LCD\n");
227 case OMAP_DSS_CHANNEL_LCD2
:
238 DSSERR("error in PLL mux config for LCD2\n");
243 case OMAP_DSS_CHANNEL_LCD3
:
254 DSSERR("error in PLL mux config for LCD3\n");
260 DSSERR("error in PLL mux config\n");
264 regmap_update_bits(dss
.syscon_pll_ctrl
, dss
.syscon_pll_ctrl_offset
,
265 0x3 << shift
, val
<< shift
);
268 void dss_sdi_init(int datapairs
)
272 BUG_ON(datapairs
> 3 || datapairs
< 1);
274 l
= dss_read_reg(DSS_SDI_CONTROL
);
275 l
= FLD_MOD(l
, 0xf, 19, 15); /* SDI_PDIV */
276 l
= FLD_MOD(l
, datapairs
-1, 3, 2); /* SDI_PRSEL */
277 l
= FLD_MOD(l
, 2, 1, 0); /* SDI_BWSEL */
278 dss_write_reg(DSS_SDI_CONTROL
, l
);
280 l
= dss_read_reg(DSS_PLL_CONTROL
);
281 l
= FLD_MOD(l
, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
282 l
= FLD_MOD(l
, 0xb, 16, 11); /* SDI_PLL_REGN */
283 l
= FLD_MOD(l
, 0xb4, 10, 1); /* SDI_PLL_REGM */
284 dss_write_reg(DSS_PLL_CONTROL
, l
);
287 int dss_sdi_enable(void)
289 unsigned long timeout
;
291 dispc_pck_free_enable(1);
294 REG_FLD_MOD(DSS_PLL_CONTROL
, 1, 18, 18); /* SDI_PLL_SYSRESET */
295 udelay(1); /* wait 2x PCLK */
298 REG_FLD_MOD(DSS_PLL_CONTROL
, 1, 28, 28); /* SDI_PLL_GOBIT */
300 /* Waiting for PLL lock request to complete */
301 timeout
= jiffies
+ msecs_to_jiffies(500);
302 while (dss_read_reg(DSS_SDI_STATUS
) & (1 << 6)) {
303 if (time_after_eq(jiffies
, timeout
)) {
304 DSSERR("PLL lock request timed out\n");
309 /* Clearing PLL_GO bit */
310 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 28, 28);
312 /* Waiting for PLL to lock */
313 timeout
= jiffies
+ msecs_to_jiffies(500);
314 while (!(dss_read_reg(DSS_SDI_STATUS
) & (1 << 5))) {
315 if (time_after_eq(jiffies
, timeout
)) {
316 DSSERR("PLL lock timed out\n");
321 dispc_lcd_enable_signal(1);
323 /* Waiting for SDI reset to complete */
324 timeout
= jiffies
+ msecs_to_jiffies(500);
325 while (!(dss_read_reg(DSS_SDI_STATUS
) & (1 << 2))) {
326 if (time_after_eq(jiffies
, timeout
)) {
327 DSSERR("SDI reset timed out\n");
335 dispc_lcd_enable_signal(0);
338 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 18, 18); /* SDI_PLL_SYSRESET */
340 dispc_pck_free_enable(0);
345 void dss_sdi_disable(void)
347 dispc_lcd_enable_signal(0);
349 dispc_pck_free_enable(0);
352 REG_FLD_MOD(DSS_PLL_CONTROL
, 0, 18, 18); /* SDI_PLL_SYSRESET */
355 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src
)
357 return dss_generic_clk_source_names
[clk_src
];
360 void dss_dump_clocks(struct seq_file
*s
)
362 const char *fclk_name
, *fclk_real_name
;
363 unsigned long fclk_rate
;
365 if (dss_runtime_get())
368 seq_printf(s
, "- DSS -\n");
370 fclk_name
= dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK
);
371 fclk_real_name
= dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK
);
372 fclk_rate
= clk_get_rate(dss
.dss_clk
);
374 seq_printf(s
, "%s (%s) = %lu\n",
375 fclk_name
, fclk_real_name
,
381 static void dss_dump_regs(struct seq_file
*s
)
383 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
385 if (dss_runtime_get())
388 DUMPREG(DSS_REVISION
);
389 DUMPREG(DSS_SYSCONFIG
);
390 DUMPREG(DSS_SYSSTATUS
);
391 DUMPREG(DSS_CONTROL
);
393 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD
) &
394 OMAP_DISPLAY_TYPE_SDI
) {
395 DUMPREG(DSS_SDI_CONTROL
);
396 DUMPREG(DSS_PLL_CONTROL
);
397 DUMPREG(DSS_SDI_STATUS
);
404 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src
)
410 case OMAP_DSS_CLK_SRC_FCK
:
413 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
416 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
:
424 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH
, &start
, &end
);
426 REG_FLD_MOD(DSS_CONTROL
, b
, start
, end
); /* DISPC_CLK_SWITCH */
428 dss
.dispc_clk_source
= clk_src
;
431 void dss_select_dsi_clk_source(int dsi_module
,
432 enum omap_dss_clk_source clk_src
)
437 case OMAP_DSS_CLK_SRC_FCK
:
440 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
:
441 BUG_ON(dsi_module
!= 0);
444 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
:
445 BUG_ON(dsi_module
!= 1);
453 pos
= dsi_module
== 0 ? 1 : 10;
454 REG_FLD_MOD(DSS_CONTROL
, b
, pos
, pos
); /* DSIx_CLK_SWITCH */
456 dss
.dsi_clk_source
[dsi_module
] = clk_src
;
459 void dss_select_lcd_clk_source(enum omap_channel channel
,
460 enum omap_dss_clk_source clk_src
)
464 if (!dss_has_feature(FEAT_LCD_CLK_SRC
)) {
465 dss_select_dispc_clk_source(clk_src
);
470 case OMAP_DSS_CLK_SRC_FCK
:
473 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
474 BUG_ON(channel
!= OMAP_DSS_CHANNEL_LCD
);
477 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
:
478 BUG_ON(channel
!= OMAP_DSS_CHANNEL_LCD2
&&
479 channel
!= OMAP_DSS_CHANNEL_LCD3
);
487 pos
= channel
== OMAP_DSS_CHANNEL_LCD
? 0 :
488 (channel
== OMAP_DSS_CHANNEL_LCD2
? 12 : 19);
489 REG_FLD_MOD(DSS_CONTROL
, b
, pos
, pos
); /* LCDx_CLK_SWITCH */
491 ix
= channel
== OMAP_DSS_CHANNEL_LCD
? 0 :
492 (channel
== OMAP_DSS_CHANNEL_LCD2
? 1 : 2);
493 dss
.lcd_clk_source
[ix
] = clk_src
;
496 enum omap_dss_clk_source
dss_get_dispc_clk_source(void)
498 return dss
.dispc_clk_source
;
501 enum omap_dss_clk_source
dss_get_dsi_clk_source(int dsi_module
)
503 return dss
.dsi_clk_source
[dsi_module
];
506 enum omap_dss_clk_source
dss_get_lcd_clk_source(enum omap_channel channel
)
508 if (dss_has_feature(FEAT_LCD_CLK_SRC
)) {
509 int ix
= channel
== OMAP_DSS_CHANNEL_LCD
? 0 :
510 (channel
== OMAP_DSS_CHANNEL_LCD2
? 1 : 2);
511 return dss
.lcd_clk_source
[ix
];
513 /* LCD_CLK source is the same as DISPC_FCLK source for
515 return dss
.dispc_clk_source
;
519 bool dss_div_calc(unsigned long pck
, unsigned long fck_min
,
520 dss_div_calc_func func
, void *data
)
522 int fckd
, fckd_start
, fckd_stop
;
524 unsigned long fck_hw_max
;
525 unsigned long fckd_hw_max
;
529 fck_hw_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
531 if (dss
.parent_clk
== NULL
) {
534 pckd
= fck_hw_max
/ pck
;
538 fck
= clk_round_rate(dss
.dss_clk
, fck
);
540 return func(fck
, data
);
543 fckd_hw_max
= dss
.feat
->fck_div_max
;
545 m
= dss
.feat
->dss_fck_multiplier
;
546 prate
= clk_get_rate(dss
.parent_clk
);
548 fck_min
= fck_min
? fck_min
: 1;
550 fckd_start
= min(prate
* m
/ fck_min
, fckd_hw_max
);
551 fckd_stop
= max(DIV_ROUND_UP(prate
* m
, fck_hw_max
), 1ul);
553 for (fckd
= fckd_start
; fckd
>= fckd_stop
; --fckd
) {
554 fck
= DIV_ROUND_UP(prate
, fckd
) * m
;
563 int dss_set_fck_rate(unsigned long rate
)
567 DSSDBG("set fck to %lu\n", rate
);
569 r
= clk_set_rate(dss
.dss_clk
, rate
);
573 dss
.dss_clk_rate
= clk_get_rate(dss
.dss_clk
);
575 WARN_ONCE(dss
.dss_clk_rate
!= rate
,
576 "clk rate mismatch: %lu != %lu", dss
.dss_clk_rate
,
582 unsigned long dss_get_dispc_clk_rate(void)
584 return dss
.dss_clk_rate
;
587 static int dss_setup_default_clock(void)
589 unsigned long max_dss_fck
, prate
;
594 max_dss_fck
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
596 if (dss
.parent_clk
== NULL
) {
597 fck
= clk_round_rate(dss
.dss_clk
, max_dss_fck
);
599 prate
= clk_get_rate(dss
.parent_clk
);
601 fck_div
= DIV_ROUND_UP(prate
* dss
.feat
->dss_fck_multiplier
,
603 fck
= DIV_ROUND_UP(prate
, fck_div
) * dss
.feat
->dss_fck_multiplier
;
606 r
= dss_set_fck_rate(fck
);
613 void dss_set_venc_output(enum omap_dss_venc_type type
)
617 if (type
== OMAP_DSS_VENC_TYPE_COMPOSITE
)
619 else if (type
== OMAP_DSS_VENC_TYPE_SVIDEO
)
624 /* venc out selection. 0 = comp, 1 = svideo */
625 REG_FLD_MOD(DSS_CONTROL
, l
, 6, 6);
628 void dss_set_dac_pwrdn_bgz(bool enable
)
630 REG_FLD_MOD(DSS_CONTROL
, enable
, 5, 5); /* DAC Power-Down Control */
633 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src
)
635 enum omap_display_type dp
;
636 dp
= dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT
);
638 /* Complain about invalid selections */
639 WARN_ON((src
== DSS_VENC_TV_CLK
) && !(dp
& OMAP_DISPLAY_TYPE_VENC
));
640 WARN_ON((src
== DSS_HDMI_M_PCLK
) && !(dp
& OMAP_DISPLAY_TYPE_HDMI
));
642 /* Select only if we have options */
643 if ((dp
& OMAP_DISPLAY_TYPE_VENC
) && (dp
& OMAP_DISPLAY_TYPE_HDMI
))
644 REG_FLD_MOD(DSS_CONTROL
, src
, 15, 15); /* VENC_HDMI_SWITCH */
647 enum dss_hdmi_venc_clk_source_select
dss_get_hdmi_venc_clk_source(void)
649 enum omap_display_type displays
;
651 displays
= dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT
);
652 if ((displays
& OMAP_DISPLAY_TYPE_HDMI
) == 0)
653 return DSS_VENC_TV_CLK
;
655 if ((displays
& OMAP_DISPLAY_TYPE_VENC
) == 0)
656 return DSS_HDMI_M_PCLK
;
658 return REG_GET(DSS_CONTROL
, 15, 15);
661 static int dss_dpi_select_source_omap2_omap3(int port
, enum omap_channel channel
)
663 if (channel
!= OMAP_DSS_CHANNEL_LCD
)
669 static int dss_dpi_select_source_omap4(int port
, enum omap_channel channel
)
674 case OMAP_DSS_CHANNEL_LCD2
:
677 case OMAP_DSS_CHANNEL_DIGIT
:
684 REG_FLD_MOD(DSS_CONTROL
, val
, 17, 17);
689 static int dss_dpi_select_source_omap5(int port
, enum omap_channel channel
)
694 case OMAP_DSS_CHANNEL_LCD
:
697 case OMAP_DSS_CHANNEL_LCD2
:
700 case OMAP_DSS_CHANNEL_LCD3
:
703 case OMAP_DSS_CHANNEL_DIGIT
:
710 REG_FLD_MOD(DSS_CONTROL
, val
, 17, 16);
715 static int dss_dpi_select_source_dra7xx(int port
, enum omap_channel channel
)
719 return dss_dpi_select_source_omap5(port
, channel
);
721 if (channel
!= OMAP_DSS_CHANNEL_LCD2
)
725 if (channel
!= OMAP_DSS_CHANNEL_LCD3
)
735 int dss_dpi_select_source(int port
, enum omap_channel channel
)
737 return dss
.feat
->dpi_select_source(port
, channel
);
740 static int dss_get_clocks(void)
744 clk
= devm_clk_get(&dss
.pdev
->dev
, "fck");
746 DSSERR("can't get clock fck\n");
752 if (dss
.feat
->parent_clk_name
) {
753 clk
= clk_get(NULL
, dss
.feat
->parent_clk_name
);
755 DSSERR("Failed to get %s\n", dss
.feat
->parent_clk_name
);
762 dss
.parent_clk
= clk
;
767 static void dss_put_clocks(void)
770 clk_put(dss
.parent_clk
);
773 int dss_runtime_get(void)
777 DSSDBG("dss_runtime_get\n");
779 r
= pm_runtime_get_sync(&dss
.pdev
->dev
);
781 return r
< 0 ? r
: 0;
784 void dss_runtime_put(void)
788 DSSDBG("dss_runtime_put\n");
790 r
= pm_runtime_put_sync(&dss
.pdev
->dev
);
791 WARN_ON(r
< 0 && r
!= -ENOSYS
&& r
!= -EBUSY
);
795 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
796 void dss_debug_dump_clocks(struct seq_file
*s
)
799 dispc_dump_clocks(s
);
800 #ifdef CONFIG_OMAP2_DSS_DSI
807 static const enum omap_display_type omap2plus_ports
[] = {
808 OMAP_DISPLAY_TYPE_DPI
,
811 static const enum omap_display_type omap34xx_ports
[] = {
812 OMAP_DISPLAY_TYPE_DPI
,
813 OMAP_DISPLAY_TYPE_SDI
,
816 static const enum omap_display_type dra7xx_ports
[] = {
817 OMAP_DISPLAY_TYPE_DPI
,
818 OMAP_DISPLAY_TYPE_DPI
,
819 OMAP_DISPLAY_TYPE_DPI
,
822 static const struct dss_features omap24xx_dss_feats __initconst
= {
824 * fck div max is really 16, but the divider range has gaps. The range
825 * from 1 to 6 has no gaps, so let's use that as a max.
828 .dss_fck_multiplier
= 2,
829 .parent_clk_name
= "core_ck",
830 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
831 .ports
= omap2plus_ports
,
832 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
835 static const struct dss_features omap34xx_dss_feats __initconst
= {
837 .dss_fck_multiplier
= 2,
838 .parent_clk_name
= "dpll4_ck",
839 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
840 .ports
= omap34xx_ports
,
841 .num_ports
= ARRAY_SIZE(omap34xx_ports
),
844 static const struct dss_features omap3630_dss_feats __initconst
= {
846 .dss_fck_multiplier
= 1,
847 .parent_clk_name
= "dpll4_ck",
848 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
849 .ports
= omap2plus_ports
,
850 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
853 static const struct dss_features omap44xx_dss_feats __initconst
= {
855 .dss_fck_multiplier
= 1,
856 .parent_clk_name
= "dpll_per_x2_ck",
857 .dpi_select_source
= &dss_dpi_select_source_omap4
,
858 .ports
= omap2plus_ports
,
859 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
862 static const struct dss_features omap54xx_dss_feats __initconst
= {
864 .dss_fck_multiplier
= 1,
865 .parent_clk_name
= "dpll_per_x2_ck",
866 .dpi_select_source
= &dss_dpi_select_source_omap5
,
867 .ports
= omap2plus_ports
,
868 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
871 static const struct dss_features am43xx_dss_feats __initconst
= {
873 .dss_fck_multiplier
= 0,
874 .parent_clk_name
= NULL
,
875 .dpi_select_source
= &dss_dpi_select_source_omap2_omap3
,
876 .ports
= omap2plus_ports
,
877 .num_ports
= ARRAY_SIZE(omap2plus_ports
),
880 static const struct dss_features dra7xx_dss_feats __initconst
= {
882 .dss_fck_multiplier
= 1,
883 .parent_clk_name
= "dpll_per_x2_ck",
884 .dpi_select_source
= &dss_dpi_select_source_dra7xx
,
885 .ports
= dra7xx_ports
,
886 .num_ports
= ARRAY_SIZE(dra7xx_ports
),
889 static int __init
dss_init_features(struct platform_device
*pdev
)
891 const struct dss_features
*src
;
892 struct dss_features
*dst
;
894 dst
= devm_kzalloc(&pdev
->dev
, sizeof(*dst
), GFP_KERNEL
);
896 dev_err(&pdev
->dev
, "Failed to allocate local DSS Features\n");
900 switch (omapdss_get_version()) {
901 case OMAPDSS_VER_OMAP24xx
:
902 src
= &omap24xx_dss_feats
;
905 case OMAPDSS_VER_OMAP34xx_ES1
:
906 case OMAPDSS_VER_OMAP34xx_ES3
:
907 case OMAPDSS_VER_AM35xx
:
908 src
= &omap34xx_dss_feats
;
911 case OMAPDSS_VER_OMAP3630
:
912 src
= &omap3630_dss_feats
;
915 case OMAPDSS_VER_OMAP4430_ES1
:
916 case OMAPDSS_VER_OMAP4430_ES2
:
917 case OMAPDSS_VER_OMAP4
:
918 src
= &omap44xx_dss_feats
;
921 case OMAPDSS_VER_OMAP5
:
922 src
= &omap54xx_dss_feats
;
925 case OMAPDSS_VER_AM43xx
:
926 src
= &am43xx_dss_feats
;
929 case OMAPDSS_VER_DRA7xx
:
930 src
= &dra7xx_dss_feats
;
937 memcpy(dst
, src
, sizeof(*dst
));
943 static int __init
dss_init_ports(struct platform_device
*pdev
)
945 struct device_node
*parent
= pdev
->dev
.of_node
;
946 struct device_node
*port
;
952 port
= omapdss_of_get_next_port(parent
, NULL
);
956 if (dss
.feat
->num_ports
== 0)
960 enum omap_display_type port_type
;
963 r
= of_property_read_u32(port
, "reg", ®
);
967 if (reg
>= dss
.feat
->num_ports
)
970 port_type
= dss
.feat
->ports
[reg
];
973 case OMAP_DISPLAY_TYPE_DPI
:
974 dpi_init_port(pdev
, port
);
976 case OMAP_DISPLAY_TYPE_SDI
:
977 sdi_init_port(pdev
, port
);
982 } while ((port
= omapdss_of_get_next_port(parent
, port
)) != NULL
);
987 static void __exit
dss_uninit_ports(struct platform_device
*pdev
)
989 struct device_node
*parent
= pdev
->dev
.of_node
;
990 struct device_node
*port
;
995 port
= omapdss_of_get_next_port(parent
, NULL
);
999 if (dss
.feat
->num_ports
== 0)
1003 enum omap_display_type port_type
;
1007 r
= of_property_read_u32(port
, "reg", ®
);
1011 if (reg
>= dss
.feat
->num_ports
)
1014 port_type
= dss
.feat
->ports
[reg
];
1016 switch (port_type
) {
1017 case OMAP_DISPLAY_TYPE_DPI
:
1018 dpi_uninit_port(port
);
1020 case OMAP_DISPLAY_TYPE_SDI
:
1021 sdi_uninit_port(port
);
1026 } while ((port
= omapdss_of_get_next_port(parent
, port
)) != NULL
);
1029 static int dss_video_pll_probe(struct platform_device
*pdev
)
1031 struct device_node
*np
= pdev
->dev
.of_node
;
1032 struct regulator
*pll_regulator
;
1038 if (of_property_read_bool(np
, "syscon-pll-ctrl")) {
1039 dss
.syscon_pll_ctrl
= syscon_regmap_lookup_by_phandle(np
,
1041 if (IS_ERR(dss
.syscon_pll_ctrl
)) {
1043 "failed to get syscon-pll-ctrl regmap\n");
1044 return PTR_ERR(dss
.syscon_pll_ctrl
);
1047 if (of_property_read_u32_index(np
, "syscon-pll-ctrl", 1,
1048 &dss
.syscon_pll_ctrl_offset
)) {
1050 "failed to get syscon-pll-ctrl offset\n");
1055 pll_regulator
= devm_regulator_get(&pdev
->dev
, "vdda_video");
1056 if (IS_ERR(pll_regulator
)) {
1057 r
= PTR_ERR(pll_regulator
);
1061 pll_regulator
= NULL
;
1065 return -EPROBE_DEFER
;
1068 DSSERR("can't get DPLL VDDA regulator\n");
1073 if (of_property_match_string(np
, "reg-names", "pll1") >= 0) {
1074 dss
.video1_pll
= dss_video_pll_init(pdev
, 0, pll_regulator
);
1075 if (IS_ERR(dss
.video1_pll
))
1076 return PTR_ERR(dss
.video1_pll
);
1079 if (of_property_match_string(np
, "reg-names", "pll2") >= 0) {
1080 dss
.video2_pll
= dss_video_pll_init(pdev
, 1, pll_regulator
);
1081 if (IS_ERR(dss
.video2_pll
)) {
1082 dss_video_pll_uninit(dss
.video1_pll
);
1083 return PTR_ERR(dss
.video2_pll
);
1090 /* DSS HW IP initialisation */
1091 static int __init
omap_dsshw_probe(struct platform_device
*pdev
)
1093 struct resource
*dss_mem
;
1099 r
= dss_init_features(dss
.pdev
);
1103 dss_mem
= platform_get_resource(dss
.pdev
, IORESOURCE_MEM
, 0);
1105 DSSERR("can't get IORESOURCE_MEM DSS\n");
1109 dss
.base
= devm_ioremap(&pdev
->dev
, dss_mem
->start
,
1110 resource_size(dss_mem
));
1112 DSSERR("can't ioremap DSS\n");
1116 r
= dss_get_clocks();
1120 r
= dss_setup_default_clock();
1122 goto err_setup_clocks
;
1124 r
= dss_video_pll_probe(pdev
);
1128 r
= dss_init_ports(pdev
);
1130 goto err_init_ports
;
1132 pm_runtime_enable(&pdev
->dev
);
1134 r
= dss_runtime_get();
1136 goto err_runtime_get
;
1138 dss
.dss_clk_rate
= clk_get_rate(dss
.dss_clk
);
1141 REG_FLD_MOD(DSS_CONTROL
, 0, 0, 0);
1143 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK
);
1145 #ifdef CONFIG_OMAP2_DSS_VENC
1146 REG_FLD_MOD(DSS_CONTROL
, 1, 4, 4); /* venc dac demen */
1147 REG_FLD_MOD(DSS_CONTROL
, 1, 3, 3); /* venc clock 4x enable */
1148 REG_FLD_MOD(DSS_CONTROL
, 0, 2, 2); /* venc clock mode = normal */
1150 dss
.dsi_clk_source
[0] = OMAP_DSS_CLK_SRC_FCK
;
1151 dss
.dsi_clk_source
[1] = OMAP_DSS_CLK_SRC_FCK
;
1152 dss
.dispc_clk_source
= OMAP_DSS_CLK_SRC_FCK
;
1153 dss
.lcd_clk_source
[0] = OMAP_DSS_CLK_SRC_FCK
;
1154 dss
.lcd_clk_source
[1] = OMAP_DSS_CLK_SRC_FCK
;
1156 rev
= dss_read_reg(DSS_REVISION
);
1157 printk(KERN_INFO
"OMAP DSS rev %d.%d\n",
1158 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
1162 dss_debugfs_create_file("dss", dss_dump_regs
);
1164 pm_set_vt_switch(0);
1166 dss_initialized
= true;
1171 pm_runtime_disable(&pdev
->dev
);
1172 dss_uninit_ports(pdev
);
1175 dss_video_pll_uninit(dss
.video1_pll
);
1178 dss_video_pll_uninit(dss
.video2_pll
);
1185 static int __exit
omap_dsshw_remove(struct platform_device
*pdev
)
1187 dss_initialized
= false;
1190 dss_video_pll_uninit(dss
.video1_pll
);
1193 dss_video_pll_uninit(dss
.video2_pll
);
1195 dss_uninit_ports(pdev
);
1197 pm_runtime_disable(&pdev
->dev
);
1204 static int dss_runtime_suspend(struct device
*dev
)
1207 dss_set_min_bus_tput(dev
, 0);
1211 static int dss_runtime_resume(struct device
*dev
)
1215 * Set an arbitrarily high tput request to ensure OPP100.
1216 * What we should really do is to make a request to stay in OPP100,
1217 * without any tput requirements, but that is not currently possible
1221 r
= dss_set_min_bus_tput(dev
, 1000000000);
1225 dss_restore_context();
1229 static const struct dev_pm_ops dss_pm_ops
= {
1230 .runtime_suspend
= dss_runtime_suspend
,
1231 .runtime_resume
= dss_runtime_resume
,
1234 static const struct of_device_id dss_of_match
[] = {
1235 { .compatible
= "ti,omap2-dss", },
1236 { .compatible
= "ti,omap3-dss", },
1237 { .compatible
= "ti,omap4-dss", },
1238 { .compatible
= "ti,omap5-dss", },
1239 { .compatible
= "ti,dra7-dss", },
1243 MODULE_DEVICE_TABLE(of
, dss_of_match
);
1245 static struct platform_driver omap_dsshw_driver
= {
1246 .remove
= __exit_p(omap_dsshw_remove
),
1248 .name
= "omapdss_dss",
1250 .of_match_table
= dss_of_match
,
1251 .suppress_bind_attrs
= true,
1255 int __init
dss_init_platform_driver(void)
1257 return platform_driver_probe(&omap_dsshw_driver
, omap_dsshw_probe
);
1260 void dss_uninit_platform_driver(void)
1262 platform_driver_unregister(&omap_dsshw_driver
);