drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c

   1 /*
   2  * HDMI PLL
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #define DSS_SUBSYS_NAME "HDMIPLL"
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19
  20 #include <video/omapdss.h>
  21
  22 #include "dss.h"
  23 #include "hdmi.h"
  24
  25 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
  26 {
  27 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
  28                 hdmi_read_reg(pll->base, r))
  29
  30         DUMPPLL(PLLCTRL_PLL_CONTROL);
  31         DUMPPLL(PLLCTRL_PLL_STATUS);
  32         DUMPPLL(PLLCTRL_PLL_GO);
  33         DUMPPLL(PLLCTRL_CFG1);
  34         DUMPPLL(PLLCTRL_CFG2);
  35         DUMPPLL(PLLCTRL_CFG3);
  36         DUMPPLL(PLLCTRL_SSC_CFG1);
  37         DUMPPLL(PLLCTRL_SSC_CFG2);
  38         DUMPPLL(PLLCTRL_CFG4);
  39 }
  40
  41 void hdmi_pll_compute(struct hdmi_pll_data *pll,
  42         unsigned long target_tmds, struct dss_pll_clock_info *pi)
  43 {
  44         unsigned long fint, clkdco, clkout;
  45         unsigned long target_bitclk, target_clkdco;
  46         unsigned long min_dco;
  47         unsigned n, m, mf, m2, sd;
  48         unsigned long clkin;
  49         const struct dss_pll_hw *hw = pll->pll.hw;
  50
  51         clkin = clk_get_rate(pll->pll.clkin);
  52
  53         DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
  54
  55         target_bitclk = target_tmds * 10;
  56
  57         /* Fint */
  58         n = DIV_ROUND_UP(clkin, hw->fint_max);
  59         fint = clkin / n;
  60
  61         /* adjust m2 so that the clkdco will be high enough */
  62         min_dco = roundup(hw->clkdco_min, fint);
  63         m2 = DIV_ROUND_UP(min_dco, target_bitclk);
  64         if (m2 == 0)
  65                 m2 = 1;
  66
  67         target_clkdco = target_bitclk * m2;
  68         m = target_clkdco / fint;
  69
  70         clkdco = fint * m;
  71
  72         /* adjust clkdco with fractional mf */
  73         if (WARN_ON(target_clkdco - clkdco > fint))
  74                 mf = 0;
  75         else
  76                 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
  77
  78         if (mf > 0)
  79                 clkdco += (u32)div_u64((u64)mf * fint, 262144);
  80
  81         clkout = clkdco / m2;
  82
  83         /* sigma-delta */
  84         sd = DIV_ROUND_UP(fint * m, 250000000);
  85
  86         DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
  87                 n, m, mf, m2, sd);
  88         DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
  89
  90         pi->n = n;
  91         pi->m = m;
  92         pi->mf = mf;
  93         pi->mX[0] = m2;
  94         pi->sd = sd;
  95
  96         pi->fint = fint;
  97         pi->clkdco = clkdco;
  98         pi->clkout[0] = clkout;
  99 }
 100
 101 static int hdmi_pll_enable(struct dss_pll *dsspll)
 102 {
 103         struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
 104         struct hdmi_wp_data *wp = pll->wp;
 105         u16 r = 0;
 106
 107         dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
 108
 109         r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 110         if (r)
 111                 return r;
 112
 113         return 0;
 114 }
 115
 116 static void hdmi_pll_disable(struct dss_pll *dsspll)
 117 {
 118         struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
 119         struct hdmi_wp_data *wp = pll->wp;
 120
 121         hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 122
 123         dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
 124 }
 125
 126 static const struct dss_pll_ops dsi_pll_ops = {
 127         .enable = hdmi_pll_enable,
 128         .disable = hdmi_pll_disable,
 129         .set_config = dss_pll_write_config_type_b,
 130 };
 131
 132 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
 133         .n_max = 255,
 134         .m_min = 20,
 135         .m_max = 4095,
 136         .mX_max = 127,
 137         .fint_min = 500000,
 138         .fint_max = 2500000,
 139
 140         .clkdco_min = 500000000,
 141         .clkdco_low = 1000000000,
 142         .clkdco_max = 2000000000,
 143
 144         .n_msb = 8,
 145         .n_lsb = 1,
 146         .m_msb = 20,
 147         .m_lsb = 9,
 148
 149         .mX_msb[0] = 24,
 150         .mX_lsb[0] = 18,
 151
 152         .has_selfreqdco = true,
 153 };
 154
 155 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
 156         .n_max = 255,
 157         .m_min = 20,
 158         .m_max = 2045,
 159         .mX_max = 127,
 160         .fint_min = 620000,
 161         .fint_max = 2500000,
 162
 163         .clkdco_min = 750000000,
 164         .clkdco_low = 1500000000,
 165         .clkdco_max = 2500000000UL,
 166
 167         .n_msb = 8,
 168         .n_lsb = 1,
 169         .m_msb = 20,
 170         .m_lsb = 9,
 171
 172         .mX_msb[0] = 24,
 173         .mX_lsb[0] = 18,
 174
 175         .has_selfreqdco = true,
 176         .has_refsel = true,
 177 };
 178
 179 static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
 180 {
 181         struct dss_pll *pll = &hpll->pll;
 182         struct clk *clk;
 183         int r;
 184
 185         clk = devm_clk_get(&pdev->dev, "sys_clk");
 186         if (IS_ERR(clk)) {
 187                 DSSERR("can't get sys_clk\n");
 188                 return PTR_ERR(clk);
 189         }
 190
 191         pll->name = "hdmi";
 192         pll->id = DSS_PLL_HDMI;
 193         pll->base = hpll->base;
 194         pll->clkin = clk;
 195
 196         switch (omapdss_get_version()) {
 197         case OMAPDSS_VER_OMAP4430_ES1:
 198         case OMAPDSS_VER_OMAP4430_ES2:
 199         case OMAPDSS_VER_OMAP4:
 200                 pll->hw = &dss_omap4_hdmi_pll_hw;
 201                 break;
 202
 203         case OMAPDSS_VER_OMAP5:
 204         case OMAPDSS_VER_DRA7xx:
 205                 pll->hw = &dss_omap5_hdmi_pll_hw;
 206                 break;
 207
 208         default:
 209                 return -ENODEV;
 210         }
 211
 212         pll->ops = &dsi_pll_ops;
 213
 214         r = dss_pll_register(pll);
 215         if (r)
 216                 return r;
 217
 218         return 0;
 219 }
 220
 221 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
 222         struct hdmi_wp_data *wp)
 223 {
 224         int r;
 225         struct resource *res;
 226
 227         pll->wp = wp;
 228
 229         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
 230         if (!res) {
 231                 DSSERR("can't get PLL mem resource\n");
 232                 return -EINVAL;
 233         }
 234
 235         pll->base = devm_ioremap_resource(&pdev->dev, res);
 236         if (IS_ERR(pll->base)) {
 237                 DSSERR("can't ioremap PLLCTRL\n");
 238                 return PTR_ERR(pll->base);
 239         }
 240
 241         r = dsi_init_pll_data(pdev, pll);
 242         if (r) {
 243                 DSSERR("failed to init HDMI PLL\n");
 244                 return r;
 245         }
 246
 247         return 0;
 248 }
 249
 250 void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
 251 {
 252         struct dss_pll *pll = &hpll->pll;
 253
 254         dss_pll_unregister(pll);
 255 }