projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[PATCH] nvidiafb: Add support for Geforce4 MX 4000
[deliverable/linux.git] / drivers / video / nvidia / nvidia.c
1 /*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #ifdef CONFIG_MTRR
25 #include <asm/mtrr.h>
26 #endif
27 #ifdef CONFIG_PPC_OF
28 #include <asm/prom.h>
29 #include <asm/pci-bridge.h>
30 #endif
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
33 #endif
34
35 #include "nv_local.h"
36 #include "nv_type.h"
37 #include "nv_proto.h"
38 #include "nv_dma.h"
39
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
42 #endif
43
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
47 #else
48 #define NVTRACE if (0) printk
49 #endif
50
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
53
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
59 BUG(); \
60 }
61 #else
62 #define assert(expr)
63 #endif
64
65 #define PFX "nvidiafb: "
66
67 /* HW cursor parameters */
68 #define MAX_CURS 32
69
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x0252,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0313,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x0316,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0317,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x031D,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x031E,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x031F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x0329,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, 0x032F,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, 0x0345,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, 0x0349,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, 0x034B,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, 0x034F,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0142,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0143,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x0144,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x0145,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x0146,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0147,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, 0x0148,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0149,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x014b,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, 0x14c,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x014d,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, 0x0160,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, 0x0162,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0163,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x0165,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, 0x0169,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, 0x016b,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, 0x016c,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, 0x016d,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, 0x016e,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, 0x0210,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
401 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
403 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
405 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
407 {PCI_VENDOR_ID_NVIDIA, 0x021d,
408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
409 {PCI_VENDOR_ID_NVIDIA, 0x021e,
410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
411 {PCI_VENDOR_ID_NVIDIA, 0x0220,
412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
413 {PCI_VENDOR_ID_NVIDIA, 0x0221,
414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
415 {PCI_VENDOR_ID_NVIDIA, 0x0222,
416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
417 {PCI_VENDOR_ID_NVIDIA, 0x0228,
418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
419 {0,} /* terminate list */
420 };
421
422 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
423
424 /* command line data, set in nvidiafb_setup() */
425 static int flatpanel __devinitdata = -1; /* Autodetect later */
426 static int fpdither __devinitdata = -1;
427 static int forceCRTC __devinitdata = -1;
428 static int hwcur __devinitdata = 0;
429 static int noaccel __devinitdata = 0;
430 static int noscale __devinitdata = 0;
431 static int paneltweak __devinitdata = 0;
432 static int vram __devinitdata = 0;
433 static int bpp __devinitdata = 8;
434 #ifdef CONFIG_MTRR
435 static int nomtrr __devinitdata = 0;
436 #endif
437
438 static char *mode_option __devinitdata = NULL;
439
440 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
441 .type = FB_TYPE_PACKED_PIXELS,
442 .xpanstep = 8,
443 .ypanstep = 1,
444 };
445
446 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
447 .xres = 640,
448 .yres = 480,
449 .xres_virtual = 640,
450 .yres_virtual = 480,
451 .bits_per_pixel = 8,
452 .red = {0, 8, 0},
453 .green = {0, 8, 0},
454 .blue = {0, 8, 0},
455 .transp = {0, 0, 0},
456 .activate = FB_ACTIVATE_NOW,
457 .height = -1,
458 .width = -1,
459 .pixclock = 39721,
460 .left_margin = 40,
461 .right_margin = 24,
462 .upper_margin = 32,
463 .lower_margin = 11,
464 .hsync_len = 96,
465 .vsync_len = 2,
466 .vmode = FB_VMODE_NONINTERLACED
467 };
468
469 /*
470 * Backlight control
471 */
472 #ifdef CONFIG_PMAC_BACKLIGHT
473
474 static int nvidia_backlight_levels[] = {
475 0x158,
476 0x192,
477 0x1c6,
478 0x200,
479 0x234,
480 0x268,
481 0x2a2,
482 0x2d6,
483 0x310,
484 0x344,
485 0x378,
486 0x3b2,
487 0x3e6,
488 0x41a,
489 0x454,
490 0x534,
491 };
492
493 /* ------------------------------------------------------------------------- *
494 *
495 * Backlight operations
496 *
497 * ------------------------------------------------------------------------- */
498
499 static int nvidia_set_backlight_enable(int on, int level, void *data)
500 {
501 struct nvidia_par *par = data;
502 u32 tmp_pcrt, tmp_pmc, fpcontrol;
503
504 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
505 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
506 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
507
508 if (on && (level > BACKLIGHT_OFF)) {
509 tmp_pcrt |= 0x1;
510 tmp_pmc |= (1 << 31); // backlight bit
511 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
512 }
513
514 if (on)
515 fpcontrol |= par->fpSyncs;
516 else
517 fpcontrol |= 0x20000022;
518
519 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
520 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
521 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
522
523 return 0;
524 }
525
526 static int nvidia_set_backlight_level(int level, void *data)
527 {
528 return nvidia_set_backlight_enable(1, level, data);
529 }
530
531 static struct backlight_controller nvidia_backlight_controller = {
532 nvidia_set_backlight_enable,
533 nvidia_set_backlight_level
534 };
535
536 #endif /* CONFIG_PMAC_BACKLIGHT */
537
538 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
539 u16 bg, u16 fg, u32 w, u32 h)
540 {
541 u32 *data = (u32 *) data8;
542 int i, j, k = 0;
543 u32 b, tmp;
544
545 w = (w + 1) & ~1;
546
547 for (i = 0; i < h; i++) {
548 b = *data++;
549 reverse_order(&b);
550
551 for (j = 0; j < w / 2; j++) {
552 tmp = 0;
553 #if defined (__BIG_ENDIAN)
554 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
555 b <<= 1;
556 tmp |= (b & (1 << 31)) ? fg : bg;
557 b <<= 1;
558 #else
559 tmp = (b & 1) ? fg : bg;
560 b >>= 1;
561 tmp |= (b & 1) ? fg << 16 : bg << 16;
562 b >>= 1;
563 #endif
564 NV_WR32(&par->CURSOR[k++], 0, tmp);
565 }
566 k += (MAX_CURS - w) / 2;
567 }
568 }
569
570 static void nvidia_write_clut(struct nvidia_par *par,
571 u8 regnum, u8 red, u8 green, u8 blue)
572 {
573 NVWriteDacMask(par, 0xff);
574 NVWriteDacWriteAddr(par, regnum);
575 NVWriteDacData(par, red);
576 NVWriteDacData(par, green);
577 NVWriteDacData(par, blue);
578 }
579
580 static void nvidia_read_clut(struct nvidia_par *par,
581 u8 regnum, u8 * red, u8 * green, u8 * blue)
582 {
583 NVWriteDacMask(par, 0xff);
584 NVWriteDacReadAddr(par, regnum);
585 *red = NVReadDacData(par);
586 *green = NVReadDacData(par);
587 *blue = NVReadDacData(par);
588 }
589
590 static int nvidia_panel_tweak(struct nvidia_par *par,
591 struct _riva_hw_state *state)
592 {
593 int tweak = 0;
594
595 if (par->paneltweak) {
596 tweak = par->paneltweak;
597 } else {
598 /* begin flat panel hacks */
599 /* This is unfortunate, but some chips need this register
600 tweaked or else you get artifacts where adjacent pixels are
601 swapped. There are no hard rules for what to set here so all
602 we can do is experiment and apply hacks. */
603
604 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
605 /* At least one NV34 laptop needs this workaround. */
606 tweak = -1;
607 }
608
609 if((par->Chipset & 0xfff0) == 0x0310) {
610 tweak = 1;
611 }
612 /* end flat panel hacks */
613 }
614
615 return tweak;
616 }
617
618 static void nvidia_save_vga(struct nvidia_par *par,
619 struct _riva_hw_state *state)
620 {
621 int i;
622
623 NVTRACE_ENTER();
624 NVLockUnlock(par, 0);
625
626 NVUnloadStateExt(par, state);
627
628 state->misc_output = NVReadMiscOut(par);
629
630 for (i = 0; i < NUM_CRT_REGS; i++)
631 state->crtc[i] = NVReadCrtc(par, i);
632
633 for (i = 0; i < NUM_ATC_REGS; i++)
634 state->attr[i] = NVReadAttr(par, i);
635
636 for (i = 0; i < NUM_GRC_REGS; i++)
637 state->gra[i] = NVReadGr(par, i);
638
639 for (i = 0; i < NUM_SEQ_REGS; i++)
640 state->seq[i] = NVReadSeq(par, i);
641 NVTRACE_LEAVE();
642 }
643
644 #undef DUMP_REG
645
646 static void nvidia_write_regs(struct nvidia_par *par)
647 {
648 struct _riva_hw_state *state = &par->ModeReg;
649 int i;
650
651 NVTRACE_ENTER();
652
653 NVLoadStateExt(par, state);
654
655 NVWriteMiscOut(par, state->misc_output);
656
657 for (i = 1; i < NUM_SEQ_REGS; i++) {
658 #ifdef DUMP_REG
659 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
660 #endif
661 NVWriteSeq(par, i, state->seq[i]);
662 }
663
664 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
665 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
666
667 for (i = 0; i < NUM_CRT_REGS; i++) {
668 switch (i) {
669 case 0x19:
670 case 0x20 ... 0x40:
671 break;
672 default:
673 #ifdef DUMP_REG
674 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
675 #endif
676 NVWriteCrtc(par, i, state->crtc[i]);
677 }
678 }
679
680 for (i = 0; i < NUM_GRC_REGS; i++) {
681 #ifdef DUMP_REG
682 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
683 #endif
684 NVWriteGr(par, i, state->gra[i]);
685 }
686
687 for (i = 0; i < NUM_ATC_REGS; i++) {
688 #ifdef DUMP_REG
689 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
690 #endif
691 NVWriteAttr(par, i, state->attr[i]);
692 }
693
694 NVTRACE_LEAVE();
695 }
696
697 static void nvidia_vga_protect(struct nvidia_par *par, int on)
698 {
699 unsigned char tmp;
700
701 if (on) {
702 /*
703 * Turn off screen and disable sequencer.
704 */
705 tmp = NVReadSeq(par, 0x01);
706
707 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
708 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
709 } else {
710 /*
711 * Reenable sequencer, then turn on screen.
712 */
713
714 tmp = NVReadSeq(par, 0x01);
715
716 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
717 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
718 }
719 }
720
721
722
723 static int nvidia_calc_regs(struct fb_info *info)
724 {
725 struct nvidia_par *par = info->par;
726 struct _riva_hw_state *state = &par->ModeReg;
727 int i, depth = fb_get_color_depth(&info->var, &info->fix);
728 int h_display = info->var.xres / 8 - 1;
729 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
730 int h_end = (info->var.xres + info->var.right_margin +
731 info->var.hsync_len) / 8 - 1;
732 int h_total = (info->var.xres + info->var.right_margin +
733 info->var.hsync_len + info->var.left_margin) / 8 - 5;
734 int h_blank_s = h_display;
735 int h_blank_e = h_total + 4;
736 int v_display = info->var.yres - 1;
737 int v_start = info->var.yres + info->var.lower_margin - 1;
738 int v_end = (info->var.yres + info->var.lower_margin +
739 info->var.vsync_len) - 1;
740 int v_total = (info->var.yres + info->var.lower_margin +
741 info->var.vsync_len + info->var.upper_margin) - 2;
742 int v_blank_s = v_display;
743 int v_blank_e = v_total + 1;
744
745 /*
746 * Set all CRTC values.
747 */
748
749 if (info->var.vmode & FB_VMODE_INTERLACED)
750 v_total |= 1;
751
752 if (par->FlatPanel == 1) {
753 v_start = v_total - 3;
754 v_end = v_total - 2;
755 v_blank_s = v_start;
756 h_start = h_total - 5;
757 h_end = h_total - 2;
758 h_blank_e = h_total + 4;
759 }
760
761 state->crtc[0x0] = Set8Bits(h_total);
762 state->crtc[0x1] = Set8Bits(h_display);
763 state->crtc[0x2] = Set8Bits(h_blank_s);
764 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
765 | SetBit(7);
766 state->crtc[0x4] = Set8Bits(h_start);
767 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
768 | SetBitField(h_end, 4: 0, 4:0);
769 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
770 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
771 | SetBitField(v_display, 8: 8, 1:1)
772 | SetBitField(v_start, 8: 8, 2:2)
773 | SetBitField(v_blank_s, 8: 8, 3:3)
774 | SetBit(4)
775 | SetBitField(v_total, 9: 9, 5:5)
776 | SetBitField(v_display, 9: 9, 6:6)
777 | SetBitField(v_start, 9: 9, 7:7);
778 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
779 | SetBit(6)
780 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
781 state->crtc[0x10] = Set8Bits(v_start);
782 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
783 state->crtc[0x12] = Set8Bits(v_display);
784 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
785 (info->var.bits_per_pixel / 8));
786 state->crtc[0x15] = Set8Bits(v_blank_s);
787 state->crtc[0x16] = Set8Bits(v_blank_e);
788
789 state->attr[0x10] = 0x01;
790
791 if (par->Television)
792 state->attr[0x11] = 0x00;
793
794 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
795 | SetBitField(v_blank_s, 10: 10, 3:3)
796 | SetBitField(v_start, 10: 10, 2:2)
797 | SetBitField(v_display, 10: 10, 1:1)
798 | SetBitField(v_total, 10: 10, 0:0);
799
800 state->horiz = SetBitField(h_total, 8: 8, 0:0)
801 | SetBitField(h_display, 8: 8, 1:1)
802 | SetBitField(h_blank_s, 8: 8, 2:2)
803 | SetBitField(h_start, 8: 8, 3:3);
804
805 state->extra = SetBitField(v_total, 11: 11, 0:0)
806 | SetBitField(v_display, 11: 11, 2:2)
807 | SetBitField(v_start, 11: 11, 4:4)
808 | SetBitField(v_blank_s, 11: 11, 6:6);
809
810 if (info->var.vmode & FB_VMODE_INTERLACED) {
811 h_total = (h_total >> 1) & ~1;
812 state->interlace = Set8Bits(h_total);
813 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
814 } else {
815 state->interlace = 0xff; /* interlace off */
816 }
817
818 /*
819 * Calculate the extended registers.
820 */
821
822 if (depth < 24)
823 i = depth;
824 else
825 i = 32;
826
827 if (par->Architecture >= NV_ARCH_10)
828 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
829 par->CursorStart);
830
831 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
832 state->misc_output &= ~0x40;
833 else
834 state->misc_output |= 0x40;
835 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
836 state->misc_output &= ~0x80;
837 else
838 state->misc_output |= 0x80;
839
840 NVCalcStateExt(par, state, i, info->var.xres_virtual,
841 info->var.xres, info->var.yres_virtual,
842 1000000000 / info->var.pixclock, info->var.vmode);
843
844 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
845 if (par->FlatPanel == 1) {
846 state->pixel |= (1 << 7);
847
848 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
849 || (par->fpHeight <= info->var.yres)) {
850 state->scale |= (1 << 8);
851 }
852
853 if (!par->crtcSync_read) {
854 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
855 par->crtcSync_read = 1;
856 }
857
858 par->PanelTweak = nvidia_panel_tweak(par, state);
859 }
860
861 state->vpll = state->pll;
862 state->vpll2 = state->pll;
863 state->vpllB = state->pllB;
864 state->vpll2B = state->pllB;
865
866 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
867 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
868
869 if (par->CRTCnumber) {
870 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
871 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
872 state->crtcOwner = 3;
873 state->pllsel |= 0x20000800;
874 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
875 if (par->twoStagePLL)
876 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
877 } else if (par->twoHeads) {
878 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
879 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
880 state->crtcOwner = 0;
881 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
882 if (par->twoStagePLL)
883 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
884 }
885
886 state->cursorConfig = 0x00000100;
887
888 if (info->var.vmode & FB_VMODE_DOUBLE)
889 state->cursorConfig |= (1 << 4);
890
891 if (par->alphaCursor) {
892 if ((par->Chipset & 0x0ff0) != 0x0110)
893 state->cursorConfig |= 0x04011000;
894 else
895 state->cursorConfig |= 0x14011000;
896 state->general |= (1 << 29);
897 } else
898 state->cursorConfig |= 0x02000000;
899
900 if (par->twoHeads) {
901 if ((par->Chipset & 0x0ff0) == 0x0110) {
902 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
903 ~0x00010000;
904 if (par->FPDither)
905 state->dither |= 0x00010000;
906 } else {
907 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
908 if (par->FPDither)
909 state->dither |= 1;
910 }
911 }
912
913 state->timingH = 0;
914 state->timingV = 0;
915 state->displayV = info->var.xres;
916
917 return 0;
918 }
919
920 static void nvidia_init_vga(struct fb_info *info)
921 {
922 struct nvidia_par *par = info->par;
923 struct _riva_hw_state *state = &par->ModeReg;
924 int i;
925
926 for (i = 0; i < 0x10; i++)
927 state->attr[i] = i;
928 state->attr[0x10] = 0x41;
929 state->attr[0x11] = 0xff;
930 state->attr[0x12] = 0x0f;
931 state->attr[0x13] = 0x00;
932 state->attr[0x14] = 0x00;
933
934 memset(state->crtc, 0x00, NUM_CRT_REGS);
935 state->crtc[0x0a] = 0x20;
936 state->crtc[0x17] = 0xe3;
937 state->crtc[0x18] = 0xff;
938 state->crtc[0x28] = 0x40;
939
940 memset(state->gra, 0x00, NUM_GRC_REGS);
941 state->gra[0x05] = 0x40;
942 state->gra[0x06] = 0x05;
943 state->gra[0x07] = 0x0f;
944 state->gra[0x08] = 0xff;
945
946 state->seq[0x00] = 0x03;
947 state->seq[0x01] = 0x01;
948 state->seq[0x02] = 0x0f;
949 state->seq[0x03] = 0x00;
950 state->seq[0x04] = 0x0e;
951
952 state->misc_output = 0xeb;
953 }
954
955 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
956 {
957 struct nvidia_par *par = info->par;
958 u8 data[MAX_CURS * MAX_CURS / 8];
959 int i, set = cursor->set;
960 u16 fg, bg;
961
962 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
963 return -ENXIO;
964
965 NVShowHideCursor(par, 0);
966
967 if (par->cursor_reset) {
968 set = FB_CUR_SETALL;
969 par->cursor_reset = 0;
970 }
971
972 if (set & FB_CUR_SETSIZE)
973 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
974
975 if (set & FB_CUR_SETPOS) {
976 u32 xx, yy, temp;
977
978 yy = cursor->image.dy - info->var.yoffset;
979 xx = cursor->image.dx - info->var.xoffset;
980 temp = xx & 0xFFFF;
981 temp |= yy << 16;
982
983 NV_WR32(par->PRAMDAC, 0x0000300, temp);
984 }
985
986 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
987 u32 bg_idx = cursor->image.bg_color;
988 u32 fg_idx = cursor->image.fg_color;
989 u32 s_pitch = (cursor->image.width + 7) >> 3;
990 u32 d_pitch = MAX_CURS / 8;
991 u8 *dat = (u8 *) cursor->image.data;
992 u8 *msk = (u8 *) cursor->mask;
993 u8 *src;
994
995 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
996
997 if (src) {
998 switch (cursor->rop) {
999 case ROP_XOR:
1000 for (i = 0; i < s_pitch * cursor->image.height; i++)
1001 src[i] = dat[i] ^ msk[i];
1002 break;
1003 case ROP_COPY:
1004 default:
1005 for (i = 0; i < s_pitch * cursor->image.height; i++)
1006 src[i] = dat[i] & msk[i];
1007 break;
1008 }
1009
1010 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1011 cursor->image.height);
1012
1013 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1014 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1015 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1016
1017 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1018 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1019 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1020
1021 NVLockUnlock(par, 0);
1022
1023 nvidiafb_load_cursor_image(par, data, bg, fg,
1024 cursor->image.width,
1025 cursor->image.height);
1026 kfree(src);
1027 }
1028 }
1029
1030 if (cursor->enable)
1031 NVShowHideCursor(par, 1);
1032
1033 return 0;
1034 }
1035
1036 static int nvidiafb_set_par(struct fb_info *info)
1037 {
1038 struct nvidia_par *par = info->par;
1039
1040 NVTRACE_ENTER();
1041
1042 NVLockUnlock(par, 1);
1043 if (!par->FlatPanel || !par->twoHeads)
1044 par->FPDither = 0;
1045
1046 if (par->FPDither < 0) {
1047 if ((par->Chipset & 0x0ff0) == 0x0110)
1048 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
1049 & 0x00010000);
1050 else
1051 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
1052 printk(KERN_INFO PFX "Flat panel dithering %s\n",
1053 par->FPDither ? "enabled" : "disabled");
1054 }
1055
1056 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1057 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1058
1059 nvidia_init_vga(info);
1060 nvidia_calc_regs(info);
1061
1062 NVLockUnlock(par, 0);
1063 if (par->twoHeads) {
1064 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1065 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1066 NVLockUnlock(par, 0);
1067 }
1068
1069 nvidia_vga_protect(par, 1);
1070
1071 nvidia_write_regs(par);
1072
1073 #if defined (__BIG_ENDIAN)
1074 /* turn on LFB swapping */
1075 {
1076 unsigned char tmp;
1077
1078 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1079 tmp = VGA_RD08(par->PCIO, 0x3d5);
1080 tmp |= (1 << 7);
1081 VGA_WR08(par->PCIO, 0x3d5, tmp);
1082 }
1083 #endif
1084
1085 info->fix.line_length = (info->var.xres_virtual *
1086 info->var.bits_per_pixel) >> 3;
1087 if (info->var.accel_flags) {
1088 info->fbops->fb_imageblit = nvidiafb_imageblit;
1089 info->fbops->fb_fillrect = nvidiafb_fillrect;
1090 info->fbops->fb_copyarea = nvidiafb_copyarea;
1091 info->fbops->fb_sync = nvidiafb_sync;
1092 info->pixmap.scan_align = 4;
1093 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1094 NVResetGraphics(info);
1095 } else {
1096 info->fbops->fb_imageblit = cfb_imageblit;
1097 info->fbops->fb_fillrect = cfb_fillrect;
1098 info->fbops->fb_copyarea = cfb_copyarea;
1099 info->fbops->fb_sync = NULL;
1100 info->pixmap.scan_align = 1;
1101 info->flags |= FBINFO_HWACCEL_DISABLED;
1102 }
1103
1104 par->cursor_reset = 1;
1105
1106 nvidia_vga_protect(par, 0);
1107
1108 NVTRACE_LEAVE();
1109 return 0;
1110 }
1111
1112 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1113 unsigned blue, unsigned transp,
1114 struct fb_info *info)
1115 {
1116 struct nvidia_par *par = info->par;
1117 int i;
1118
1119 NVTRACE_ENTER();
1120 if (regno >= (1 << info->var.green.length))
1121 return -EINVAL;
1122
1123 if (info->var.grayscale) {
1124 /* gray = 0.30*R + 0.59*G + 0.11*B */
1125 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1126 }
1127
1128 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1129 ((u32 *) info->pseudo_palette)[regno] =
1130 (regno << info->var.red.offset) |
1131 (regno << info->var.green.offset) |
1132 (regno << info->var.blue.offset);
1133 }
1134
1135 switch (info->var.bits_per_pixel) {
1136 case 8:
1137 /* "transparent" stuff is completely ignored. */
1138 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1139 break;
1140 case 16:
1141 if (info->var.green.length == 5) {
1142 for (i = 0; i < 8; i++) {
1143 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1144 green >> 8, blue >> 8);
1145 }
1146 } else {
1147 u8 r, g, b;
1148
1149 if (regno < 32) {
1150 for (i = 0; i < 8; i++) {
1151 nvidia_write_clut(par, regno * 8 + i,
1152 red >> 8, green >> 8,
1153 blue >> 8);
1154 }
1155 }
1156
1157 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1158
1159 for (i = 0; i < 4; i++)
1160 nvidia_write_clut(par, regno * 4 + i, r,
1161 green >> 8, b);
1162 }
1163 break;
1164 case 32:
1165 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1166 break;
1167 default:
1168 /* do nothing */
1169 break;
1170 }
1171
1172 NVTRACE_LEAVE();
1173 return 0;
1174 }
1175
1176 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1177 struct fb_info *info)
1178 {
1179 struct nvidia_par *par = info->par;
1180 int memlen, vramlen, mode_valid = 0;
1181 int pitch, err = 0;
1182
1183 NVTRACE_ENTER();
1184
1185 var->transp.offset = 0;
1186 var->transp.length = 0;
1187
1188 var->xres &= ~7;
1189
1190 if (var->bits_per_pixel <= 8)
1191 var->bits_per_pixel = 8;
1192 else if (var->bits_per_pixel <= 16)
1193 var->bits_per_pixel = 16;
1194 else
1195 var->bits_per_pixel = 32;
1196
1197 switch (var->bits_per_pixel) {
1198 case 8:
1199 var->red.offset = 0;
1200 var->red.length = 8;
1201 var->green.offset = 0;
1202 var->green.length = 8;
1203 var->blue.offset = 0;
1204 var->blue.length = 8;
1205 var->transp.offset = 0;
1206 var->transp.length = 0;
1207 break;
1208 case 16:
1209 var->green.length = (var->green.length < 6) ? 5 : 6;
1210 var->red.length = 5;
1211 var->blue.length = 5;
1212 var->transp.length = 6 - var->green.length;
1213 var->blue.offset = 0;
1214 var->green.offset = 5;
1215 var->red.offset = 5 + var->green.length;
1216 var->transp.offset = (5 + var->red.offset) & 15;
1217 break;
1218 case 32: /* RGBA 8888 */
1219 var->red.offset = 16;
1220 var->red.length = 8;
1221 var->green.offset = 8;
1222 var->green.length = 8;
1223 var->blue.offset = 0;
1224 var->blue.length = 8;
1225 var->transp.length = 8;
1226 var->transp.offset = 24;
1227 break;
1228 }
1229
1230 var->red.msb_right = 0;
1231 var->green.msb_right = 0;
1232 var->blue.msb_right = 0;
1233 var->transp.msb_right = 0;
1234
1235 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1236 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1237 mode_valid = 1;
1238
1239 /* calculate modeline if supported by monitor */
1240 if (!mode_valid && info->monspecs.gtf) {
1241 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1242 mode_valid = 1;
1243 }
1244
1245 if (!mode_valid) {
1246 struct fb_videomode *mode;
1247
1248 mode = fb_find_best_mode(var, &info->modelist);
1249 if (mode) {
1250 fb_videomode_to_var(var, mode);
1251 mode_valid = 1;
1252 }
1253 }
1254
1255 if (!mode_valid && info->monspecs.modedb_len)
1256 return -EINVAL;
1257
1258 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1259 par->fpHeight < var->yres))
1260 return -EINVAL;
1261
1262 if (var->yres_virtual < var->yres)
1263 var->yres_virtual = var->yres;
1264
1265 if (var->xres_virtual < var->xres)
1266 var->xres_virtual = var->xres;
1267
1268 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1269
1270 vramlen = info->screen_size;
1271 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1272 memlen = pitch * var->yres_virtual;
1273
1274 if (memlen > vramlen) {
1275 var->yres_virtual = vramlen / pitch;
1276
1277 if (var->yres_virtual < var->yres) {
1278 var->yres_virtual = var->yres;
1279 var->xres_virtual = vramlen / var->yres_virtual;
1280 var->xres_virtual /= var->bits_per_pixel / 8;
1281 var->xres_virtual &= ~63;
1282 pitch = (var->xres_virtual *
1283 var->bits_per_pixel + 7) / 8;
1284 memlen = pitch * var->yres;
1285
1286 if (var->xres_virtual < var->xres) {
1287 printk("nvidiafb: required video memory, "
1288 "%d bytes, for %dx%d-%d (virtual) "
1289 "is out of range\n",
1290 memlen, var->xres_virtual,
1291 var->yres_virtual, var->bits_per_pixel);
1292 err = -ENOMEM;
1293 }
1294 }
1295 }
1296
1297 if (var->accel_flags) {
1298 if (var->yres_virtual > 0x7fff)
1299 var->yres_virtual = 0x7fff;
1300 if (var->xres_virtual > 0x7fff)
1301 var->xres_virtual = 0x7fff;
1302 }
1303
1304 var->xres_virtual &= ~63;
1305
1306 NVTRACE_LEAVE();
1307
1308 return err;
1309 }
1310
1311 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1312 struct fb_info *info)
1313 {
1314 struct nvidia_par *par = info->par;
1315 u32 total;
1316
1317 total = var->yoffset * info->fix.line_length + var->xoffset;
1318
1319 NVSetStartAddress(par, total);
1320
1321 return 0;
1322 }
1323
1324 static int nvidiafb_blank(int blank, struct fb_info *info)
1325 {
1326 struct nvidia_par *par = info->par;
1327 unsigned char tmp, vesa;
1328
1329 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1330 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1331
1332 NVTRACE_ENTER();
1333
1334 if (blank)
1335 tmp |= 0x20;
1336
1337 switch (blank) {
1338 case FB_BLANK_UNBLANK:
1339 case FB_BLANK_NORMAL:
1340 break;
1341 case FB_BLANK_VSYNC_SUSPEND:
1342 vesa |= 0x80;
1343 break;
1344 case FB_BLANK_HSYNC_SUSPEND:
1345 vesa |= 0x40;
1346 break;
1347 case FB_BLANK_POWERDOWN:
1348 vesa |= 0xc0;
1349 break;
1350 }
1351
1352 NVWriteSeq(par, 0x01, tmp);
1353 NVWriteCrtc(par, 0x1a, vesa);
1354
1355 #ifdef CONFIG_PMAC_BACKLIGHT
1356 if (par->FlatPanel && _machine == _MACH_Pmac) {
1357 set_backlight_enable(!blank);
1358 }
1359 #endif
1360
1361 NVTRACE_LEAVE();
1362
1363 return 0;
1364 }
1365
1366 static struct fb_ops nvidia_fb_ops = {
1367 .owner = THIS_MODULE,
1368 .fb_check_var = nvidiafb_check_var,
1369 .fb_set_par = nvidiafb_set_par,
1370 .fb_setcolreg = nvidiafb_setcolreg,
1371 .fb_pan_display = nvidiafb_pan_display,
1372 .fb_blank = nvidiafb_blank,
1373 .fb_fillrect = nvidiafb_fillrect,
1374 .fb_copyarea = nvidiafb_copyarea,
1375 .fb_imageblit = nvidiafb_imageblit,
1376 .fb_cursor = nvidiafb_cursor,
1377 .fb_sync = nvidiafb_sync,
1378 };
1379
1380 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1381 {
1382 struct fb_monspecs *specs = &info->monspecs;
1383 struct fb_videomode modedb;
1384 struct nvidia_par *par = info->par;
1385 int lpitch;
1386
1387 NVTRACE_ENTER();
1388 info->flags = FBINFO_DEFAULT
1389 | FBINFO_HWACCEL_IMAGEBLIT
1390 | FBINFO_HWACCEL_FILLRECT
1391 | FBINFO_HWACCEL_COPYAREA
1392 | FBINFO_HWACCEL_YPAN;
1393
1394 fb_videomode_to_modelist(info->monspecs.modedb,
1395 info->monspecs.modedb_len, &info->modelist);
1396 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1397
1398 switch (bpp) {
1399 case 0 ... 8:
1400 bpp = 8;
1401 break;
1402 case 9 ... 16:
1403 bpp = 16;
1404 break;
1405 default:
1406 bpp = 32;
1407 break;
1408 }
1409
1410 if (specs->modedb != NULL) {
1411 struct fb_videomode *modedb;
1412
1413 modedb = fb_find_best_display(specs, &info->modelist);
1414 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1415 nvidiafb_default_var.bits_per_pixel = bpp;
1416 } else if (par->fpWidth && par->fpHeight) {
1417 char buf[16];
1418
1419 memset(buf, 0, 16);
1420 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1421 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1422 specs->modedb_len, &modedb, bpp);
1423 }
1424
1425 if (mode_option)
1426 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1427 specs->modedb, specs->modedb_len, &modedb, bpp);
1428
1429 info->var = nvidiafb_default_var;
1430 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1431 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1432 info->pseudo_palette = par->pseudo_palette;
1433 fb_alloc_cmap(&info->cmap, 256, 0);
1434 fb_destroy_modedb(info->monspecs.modedb);
1435 info->monspecs.modedb = NULL;
1436
1437 /* maximize virtual vertical length */
1438 lpitch = info->var.xres_virtual *
1439 ((info->var.bits_per_pixel + 7) >> 3);
1440 info->var.yres_virtual = info->screen_size / lpitch;
1441
1442 info->pixmap.scan_align = 4;
1443 info->pixmap.buf_align = 4;
1444 info->pixmap.access_align = 32;
1445 info->pixmap.size = 8 * 1024;
1446 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1447
1448 if (!hwcur)
1449 info->fbops->fb_cursor = NULL;
1450
1451 info->var.accel_flags = (!noaccel);
1452
1453 switch (par->Architecture) {
1454 case NV_ARCH_04:
1455 info->fix.accel = FB_ACCEL_NV4;
1456 break;
1457 case NV_ARCH_10:
1458 info->fix.accel = FB_ACCEL_NV_10;
1459 break;
1460 case NV_ARCH_20:
1461 info->fix.accel = FB_ACCEL_NV_20;
1462 break;
1463 case NV_ARCH_30:
1464 info->fix.accel = FB_ACCEL_NV_30;
1465 break;
1466 case NV_ARCH_40:
1467 info->fix.accel = FB_ACCEL_NV_40;
1468 break;
1469 }
1470
1471 NVTRACE_LEAVE();
1472
1473 return nvidiafb_check_var(&info->var, info);
1474 }
1475
1476 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1477 {
1478 struct nvidia_par *par = info->par;
1479 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1480
1481 printk("nvidiafb: PCI id - %x\n", id);
1482 if ((id & 0xfff0) == 0x00f0) {
1483 /* pci-e */
1484 printk("nvidiafb: PCI-E card\n");
1485 id = NV_RD32(par->REGS, 0x1800);
1486
1487 if ((id & 0x0000ffff) == 0x000010DE)
1488 id = 0x10DE0000 | (id >> 16);
1489 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1490 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1491 ((id >> 8) & 0x000000ff);
1492 }
1493
1494 printk("nvidiafb: Actual id - %x\n", id);
1495 return id;
1496 }
1497
1498 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1499 {
1500 struct nvidia_par *par = info->par;
1501 u32 arch = 0;
1502
1503 switch (par->Chipset & 0x0ff0) {
1504 case 0x0100: /* GeForce 256 */
1505 case 0x0110: /* GeForce2 MX */
1506 case 0x0150: /* GeForce2 */
1507 case 0x0170: /* GeForce4 MX */
1508 case 0x0180: /* GeForce4 MX (8x AGP) */
1509 case 0x01A0: /* nForce */
1510 case 0x01F0: /* nForce2 */
1511 arch = NV_ARCH_10;
1512 break;
1513 case 0x0200: /* GeForce3 */
1514 case 0x0250: /* GeForce4 Ti */
1515 case 0x0280: /* GeForce4 Ti (8x AGP) */
1516 arch = NV_ARCH_20;
1517 break;
1518 case 0x0300: /* GeForceFX 5800 */
1519 case 0x0310: /* GeForceFX 5600 */
1520 case 0x0320: /* GeForceFX 5200 */
1521 case 0x0330: /* GeForceFX 5900 */
1522 case 0x0340: /* GeForceFX 5700 */
1523 arch = NV_ARCH_30;
1524 break;
1525 case 0x0040:
1526 case 0x00C0:
1527 case 0x0120:
1528 case 0x0130:
1529 case 0x0140:
1530 case 0x0160:
1531 case 0x01D0:
1532 case 0x0090:
1533 case 0x0210:
1534 case 0x0220:
1535 case 0x0230:
1536 case 0x0290:
1537 case 0x0390:
1538 arch = NV_ARCH_40;
1539 break;
1540 case 0x0020: /* TNT, TNT2 */
1541 arch = NV_ARCH_04;
1542 break;
1543 default: /* unknown architecture */
1544 break;
1545 }
1546
1547 return arch;
1548 }
1549
1550 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1551 const struct pci_device_id *ent)
1552 {
1553 struct nvidia_par *par;
1554 struct fb_info *info;
1555 unsigned short cmd;
1556
1557
1558 NVTRACE_ENTER();
1559 assert(pd != NULL);
1560
1561 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1562
1563 if (!info)
1564 goto err_out;
1565
1566 par = info->par;
1567 par->pci_dev = pd;
1568
1569 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1570
1571 if (info->pixmap.addr == NULL)
1572 goto err_out_kfree;
1573
1574 memset(info->pixmap.addr, 0, 8 * 1024);
1575
1576 if (pci_enable_device(pd)) {
1577 printk(KERN_ERR PFX "cannot enable PCI device\n");
1578 goto err_out_enable;
1579 }
1580
1581 if (pci_request_regions(pd, "nvidiafb")) {
1582 printk(KERN_ERR PFX "cannot request PCI regions\n");
1583 goto err_out_request;
1584 }
1585
1586 par->FlatPanel = flatpanel;
1587 if (flatpanel == 1)
1588 printk(KERN_INFO PFX "flatpanel support enabled\n");
1589 par->FPDither = fpdither;
1590
1591 par->CRTCnumber = forceCRTC;
1592 par->FpScale = (!noscale);
1593 par->paneltweak = paneltweak;
1594
1595 /* enable IO and mem if not already done */
1596 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1597 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1598 pci_write_config_word(pd, PCI_COMMAND, cmd);
1599
1600 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1601 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1602 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1603
1604 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1605
1606 if (!par->REGS) {
1607 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1608 goto err_out_free_base0;
1609 }
1610
1611 par->Chipset = nvidia_get_chipset(info);
1612 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1613 par->Architecture = nvidia_get_arch(info);
1614
1615 if (par->Architecture == 0) {
1616 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1617 goto err_out_arch;
1618 }
1619
1620 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1621
1622 if (NVCommonSetup(info))
1623 goto err_out_arch;
1624
1625 par->FbAddress = nvidiafb_fix.smem_start;
1626 par->FbMapSize = par->RamAmountKBytes * 1024;
1627 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1628 par->FbMapSize = vram * 1024 * 1024;
1629
1630 /* Limit amount of vram to 64 MB */
1631 if (par->FbMapSize > 64 * 1024 * 1024)
1632 par->FbMapSize = 64 * 1024 * 1024;
1633
1634 if(par->Architecture >= NV_ARCH_40)
1635 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1636 else
1637 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1638 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1639 16 * 1024;
1640 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1641 par->CursorStart = par->FbUsableSize + (32 * 1024);
1642
1643 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1644 info->screen_size = par->FbUsableSize;
1645 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1646
1647 if (!info->screen_base) {
1648 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1649 goto err_out_free_base1;
1650 }
1651
1652 par->FbStart = info->screen_base;
1653
1654 #ifdef CONFIG_MTRR
1655 if (!nomtrr) {
1656 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1657 par->RamAmountKBytes * 1024,
1658 MTRR_TYPE_WRCOMB, 1);
1659 if (par->mtrr.vram < 0) {
1660 printk(KERN_ERR PFX "unable to setup MTRR\n");
1661 } else {
1662 par->mtrr.vram_valid = 1;
1663 /* let there be speed */
1664 printk(KERN_INFO PFX "MTRR set to ON\n");
1665 }
1666 }
1667 #endif /* CONFIG_MTRR */
1668
1669 info->fbops = &nvidia_fb_ops;
1670 info->fix = nvidiafb_fix;
1671
1672 if (nvidia_set_fbinfo(info) < 0) {
1673 printk(KERN_ERR PFX "error setting initial video mode\n");
1674 goto err_out_iounmap_fb;
1675 }
1676
1677 nvidia_save_vga(par, &par->SavedReg);
1678
1679 if (register_framebuffer(info) < 0) {
1680 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1681 goto err_out_iounmap_fb;
1682 }
1683
1684 pci_set_drvdata(pd, info);
1685
1686 printk(KERN_INFO PFX
1687 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1688 info->fix.id,
1689 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1690 #ifdef CONFIG_PMAC_BACKLIGHT
1691 if (par->FlatPanel && _machine == _MACH_Pmac)
1692 register_backlight_controller(&nvidia_backlight_controller,
1693 par, "mnca");
1694 #endif
1695 NVTRACE_LEAVE();
1696 return 0;
1697
1698 err_out_iounmap_fb:
1699 iounmap(info->screen_base);
1700 err_out_free_base1:
1701 fb_destroy_modedb(info->monspecs.modedb);
1702 nvidia_delete_i2c_busses(par);
1703 err_out_arch:
1704 iounmap(par->REGS);
1705 err_out_free_base0:
1706 pci_release_regions(pd);
1707 err_out_request:
1708 pci_disable_device(pd);
1709 err_out_enable:
1710 kfree(info->pixmap.addr);
1711 err_out_kfree:
1712 framebuffer_release(info);
1713 err_out:
1714 return -ENODEV;
1715 }
1716
1717 static void __exit nvidiafb_remove(struct pci_dev *pd)
1718 {
1719 struct fb_info *info = pci_get_drvdata(pd);
1720 struct nvidia_par *par = info->par;
1721
1722 NVTRACE_ENTER();
1723 if (!info)
1724 return;
1725
1726 unregister_framebuffer(info);
1727 #ifdef CONFIG_MTRR
1728 if (par->mtrr.vram_valid)
1729 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1730 info->fix.smem_len);
1731 #endif /* CONFIG_MTRR */
1732
1733 iounmap(info->screen_base);
1734 fb_destroy_modedb(info->monspecs.modedb);
1735 nvidia_delete_i2c_busses(par);
1736 iounmap(par->REGS);
1737 pci_release_regions(pd);
1738 pci_disable_device(pd);
1739 kfree(info->pixmap.addr);
1740 framebuffer_release(info);
1741 pci_set_drvdata(pd, NULL);
1742 NVTRACE_LEAVE();
1743 }
1744
1745 /* ------------------------------------------------------------------------- *
1746 *
1747 * initialization
1748 *
1749 * ------------------------------------------------------------------------- */
1750
1751 #ifndef MODULE
1752 static int __devinit nvidiafb_setup(char *options)
1753 {
1754 char *this_opt;
1755
1756 NVTRACE_ENTER();
1757 if (!options || !*options)
1758 return 0;
1759
1760 while ((this_opt = strsep(&options, ",")) != NULL) {
1761 if (!strncmp(this_opt, "forceCRTC", 9)) {
1762 char *p;
1763
1764 p = this_opt + 9;
1765 if (!*p || !*(++p))
1766 continue;
1767 forceCRTC = *p - '0';
1768 if (forceCRTC < 0 || forceCRTC > 1)
1769 forceCRTC = -1;
1770 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1771 flatpanel = 1;
1772 } else if (!strncmp(this_opt, "hwcur", 5)) {
1773 hwcur = 1;
1774 } else if (!strncmp(this_opt, "noaccel", 6)) {
1775 noaccel = 1;
1776 } else if (!strncmp(this_opt, "noscale", 7)) {
1777 noscale = 1;
1778 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1779 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1780 } else if (!strncmp(this_opt, "vram:", 5)) {
1781 vram = simple_strtoul(this_opt+5, NULL, 0);
1782 #ifdef CONFIG_MTRR
1783 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1784 nomtrr = 1;
1785 #endif
1786 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1787 fpdither = simple_strtol(this_opt+9, NULL, 0);
1788 } else if (!strncmp(this_opt, "bpp:", 4)) {
1789 bpp = simple_strtoul(this_opt+4, NULL, 0);
1790 } else
1791 mode_option = this_opt;
1792 }
1793 NVTRACE_LEAVE();
1794 return 0;
1795 }
1796 #endif /* !MODULE */
1797
1798 static struct pci_driver nvidiafb_driver = {
1799 .name = "nvidiafb",
1800 .id_table = nvidiafb_pci_tbl,
1801 .probe = nvidiafb_probe,
1802 .remove = __exit_p(nvidiafb_remove),
1803 };
1804
1805 /* ------------------------------------------------------------------------- *
1806 *
1807 * modularization
1808 *
1809 * ------------------------------------------------------------------------- */
1810
1811 static int __devinit nvidiafb_init(void)
1812 {
1813 #ifndef MODULE
1814 char *option = NULL;
1815
1816 if (fb_get_options("nvidiafb", &option))
1817 return -ENODEV;
1818 nvidiafb_setup(option);
1819 #endif
1820 return pci_register_driver(&nvidiafb_driver);
1821 }
1822
1823 module_init(nvidiafb_init);
1824
1825 #ifdef MODULE
1826 static void __exit nvidiafb_exit(void)
1827 {
1828 pci_unregister_driver(&nvidiafb_driver);
1829 }
1830
1831 module_exit(nvidiafb_exit);
1832
1833 module_param(flatpanel, int, 0);
1834 MODULE_PARM_DESC(flatpanel,
1835 "Enables experimental flat panel support for some chipsets. "
1836 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1837 module_param(fpdither, int, 0);
1838 MODULE_PARM_DESC(fpdither,
1839 "Enables dithering of flat panel for 6 bits panels. "
1840 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1841 module_param(hwcur, int, 0);
1842 MODULE_PARM_DESC(hwcur,
1843 "Enables hardware cursor implementation. (0 or 1=enabled) "
1844 "(default=0)");
1845 module_param(noaccel, int, 0);
1846 MODULE_PARM_DESC(noaccel,
1847 "Disables hardware acceleration. (0 or 1=disable) "
1848 "(default=0)");
1849 module_param(noscale, int, 0);
1850 MODULE_PARM_DESC(noscale,
1851 "Disables screen scaleing. (0 or 1=disable) "
1852 "(default=0, do scaling)");
1853 module_param(paneltweak, int, 0);
1854 MODULE_PARM_DESC(paneltweak,
1855 "Tweak display settings for flatpanels. "
1856 "(default=0, no tweaks)");
1857 module_param(forceCRTC, int, 0);
1858 MODULE_PARM_DESC(forceCRTC,
1859 "Forces usage of a particular CRTC in case autodetection "
1860 "fails. (0 or 1) (default=autodetect)");
1861 module_param(vram, int, 0);
1862 MODULE_PARM_DESC(vram,
1863 "amount of framebuffer memory to remap in MiB"
1864 "(default=0 - remap entire memory)");
1865 module_param(mode_option, charp, 0);
1866 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1867 module_param(bpp, int, 0);
1868 MODULE_PARM_DESC(bpp, "pixel width in bits"
1869 "(default=8)");
1870 #ifdef CONFIG_MTRR
1871 module_param(nomtrr, bool, 0);
1872 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1873 "(default=0)");
1874 #endif
1875
1876 MODULE_AUTHOR("Antonino Daplas");
1877 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1878 MODULE_LICENSE("GPL");
1879 #endif /* MODULE */
1880
Linux kernel - Deliverables
This page took 0.117286 seconds and 5 git commands to generate.