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Merge branch 'master'
[deliverable/linux.git] / drivers / video / nvidia / nvidia.c
1 /*
2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
3 *
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 *
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
17 #include <linux/mm.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/fb.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
24 #ifdef CONFIG_MTRR
25 #include <asm/mtrr.h>
26 #endif
27 #ifdef CONFIG_PPC_OF
28 #include <asm/prom.h>
29 #include <asm/pci-bridge.h>
30 #endif
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
33 #endif
34
35 #include "nv_local.h"
36 #include "nv_type.h"
37 #include "nv_proto.h"
38 #include "nv_dma.h"
39
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
42 #endif
43
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
47 #else
48 #define NVTRACE if (0) printk
49 #endif
50
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
53
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
56 if (!(expr)) { \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
59 BUG(); \
60 }
61 #else
62 #define assert(expr)
63 #endif
64
65 #define PFX "nvidiafb: "
66
67 /* HW cursor parameters */
68 #define MAX_CURS 32
69
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x021d,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x021e,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {PCI_VENDOR_ID_NVIDIA, 0x0220,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
401 {PCI_VENDOR_ID_NVIDIA, 0x0221,
402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
403 {PCI_VENDOR_ID_NVIDIA, 0x0222,
404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
405 {PCI_VENDOR_ID_NVIDIA, 0x0228,
406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
407 {0,} /* terminate list */
408 };
409
410 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
411
412 /* command line data, set in nvidiafb_setup() */
413 static int flatpanel __devinitdata = -1; /* Autodetect later */
414 static int forceCRTC __devinitdata = -1;
415 static int hwcur __devinitdata = 0;
416 static int noaccel __devinitdata = 0;
417 static int noscale __devinitdata = 0;
418 static int paneltweak __devinitdata = 0;
419 static int vram __devinitdata = 0;
420 #ifdef CONFIG_MTRR
421 static int nomtrr __devinitdata = 0;
422 #endif
423
424 static char *mode_option __devinitdata = NULL;
425
426 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
427 .type = FB_TYPE_PACKED_PIXELS,
428 .xpanstep = 8,
429 .ypanstep = 1,
430 };
431
432 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
433 .xres = 640,
434 .yres = 480,
435 .xres_virtual = 640,
436 .yres_virtual = 480,
437 .bits_per_pixel = 8,
438 .red = {0, 8, 0},
439 .green = {0, 8, 0},
440 .blue = {0, 8, 0},
441 .transp = {0, 0, 0},
442 .activate = FB_ACTIVATE_NOW,
443 .height = -1,
444 .width = -1,
445 .pixclock = 39721,
446 .left_margin = 40,
447 .right_margin = 24,
448 .upper_margin = 32,
449 .lower_margin = 11,
450 .hsync_len = 96,
451 .vsync_len = 2,
452 .vmode = FB_VMODE_NONINTERLACED
453 };
454
455 /*
456 * Backlight control
457 */
458 #ifdef CONFIG_PMAC_BACKLIGHT
459
460 static int nvidia_backlight_levels[] = {
461 0x158,
462 0x192,
463 0x1c6,
464 0x200,
465 0x234,
466 0x268,
467 0x2a2,
468 0x2d6,
469 0x310,
470 0x344,
471 0x378,
472 0x3b2,
473 0x3e6,
474 0x41a,
475 0x454,
476 0x534,
477 };
478
479 /* ------------------------------------------------------------------------- *
480 *
481 * Backlight operations
482 *
483 * ------------------------------------------------------------------------- */
484
485 static int nvidia_set_backlight_enable(int on, int level, void *data)
486 {
487 struct nvidia_par *par = (struct nvidia_par *)data;
488 u32 tmp_pcrt, tmp_pmc, fpcontrol;
489
490 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
491 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
492 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
493
494 if (on && (level > BACKLIGHT_OFF)) {
495 tmp_pcrt |= 0x1;
496 tmp_pmc |= (1 << 31); // backlight bit
497 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
498 }
499
500 if (on)
501 fpcontrol |= par->fpSyncs;
502 else
503 fpcontrol |= 0x20000022;
504
505 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
506 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
507 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
508
509 return 0;
510 }
511
512 static int nvidia_set_backlight_level(int level, void *data)
513 {
514 return nvidia_set_backlight_enable(1, level, data);
515 }
516
517 static struct backlight_controller nvidia_backlight_controller = {
518 nvidia_set_backlight_enable,
519 nvidia_set_backlight_level
520 };
521
522 #endif /* CONFIG_PMAC_BACKLIGHT */
523
524 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
525 u16 bg, u16 fg, u32 w, u32 h)
526 {
527 u32 *data = (u32 *) data8;
528 int i, j, k = 0;
529 u32 b, tmp;
530
531 w = (w + 1) & ~1;
532
533 for (i = 0; i < h; i++) {
534 b = *data++;
535 reverse_order(&b);
536
537 for (j = 0; j < w / 2; j++) {
538 tmp = 0;
539 #if defined (__BIG_ENDIAN)
540 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
541 b <<= 1;
542 tmp |= (b & (1 << 31)) ? fg : bg;
543 b <<= 1;
544 #else
545 tmp = (b & 1) ? fg : bg;
546 b >>= 1;
547 tmp |= (b & 1) ? fg << 16 : bg << 16;
548 b >>= 1;
549 #endif
550 NV_WR32(&par->CURSOR[k++], 0, tmp);
551 }
552 k += (MAX_CURS - w) / 2;
553 }
554 }
555
556 static void nvidia_write_clut(struct nvidia_par *par,
557 u8 regnum, u8 red, u8 green, u8 blue)
558 {
559 NVWriteDacMask(par, 0xff);
560 NVWriteDacWriteAddr(par, regnum);
561 NVWriteDacData(par, red);
562 NVWriteDacData(par, green);
563 NVWriteDacData(par, blue);
564 }
565
566 static void nvidia_read_clut(struct nvidia_par *par,
567 u8 regnum, u8 * red, u8 * green, u8 * blue)
568 {
569 NVWriteDacMask(par, 0xff);
570 NVWriteDacReadAddr(par, regnum);
571 *red = NVReadDacData(par);
572 *green = NVReadDacData(par);
573 *blue = NVReadDacData(par);
574 }
575
576 static int nvidia_panel_tweak(struct nvidia_par *par,
577 struct _riva_hw_state *state)
578 {
579 int tweak = 0;
580
581 if (par->paneltweak) {
582 tweak = par->paneltweak;
583 } else {
584 /* begin flat panel hacks */
585 /* This is unfortunate, but some chips need this register
586 tweaked or else you get artifacts where adjacent pixels are
587 swapped. There are no hard rules for what to set here so all
588 we can do is experiment and apply hacks. */
589
590 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
591 /* At least one NV34 laptop needs this workaround. */
592 tweak = -1;
593 }
594
595 if((par->Chipset & 0xfff0) == 0x0310) {
596 tweak = 1;
597 }
598 /* end flat panel hacks */
599 }
600
601 return tweak;
602 }
603
604 static void nvidia_save_vga(struct nvidia_par *par,
605 struct _riva_hw_state *state)
606 {
607 int i;
608
609 NVTRACE_ENTER();
610 NVLockUnlock(par, 0);
611
612 NVUnloadStateExt(par, state);
613
614 state->misc_output = NVReadMiscOut(par);
615
616 for (i = 0; i < NUM_CRT_REGS; i++)
617 state->crtc[i] = NVReadCrtc(par, i);
618
619 for (i = 0; i < NUM_ATC_REGS; i++)
620 state->attr[i] = NVReadAttr(par, i);
621
622 for (i = 0; i < NUM_GRC_REGS; i++)
623 state->gra[i] = NVReadGr(par, i);
624
625 for (i = 0; i < NUM_SEQ_REGS; i++)
626 state->seq[i] = NVReadSeq(par, i);
627 NVTRACE_LEAVE();
628 }
629
630 static void nvidia_write_regs(struct nvidia_par *par)
631 {
632 struct _riva_hw_state *state = &par->ModeReg;
633 int i;
634
635 NVTRACE_ENTER();
636 NVWriteCrtc(par, 0x11, 0x00);
637
638 NVLockUnlock(par, 0);
639
640 NVLoadStateExt(par, state);
641
642 NVWriteMiscOut(par, state->misc_output);
643
644 for (i = 0; i < NUM_CRT_REGS; i++) {
645 switch (i) {
646 case 0x19:
647 case 0x20 ... 0x40:
648 break;
649 default:
650 NVWriteCrtc(par, i, state->crtc[i]);
651 }
652 }
653
654 for (i = 0; i < NUM_ATC_REGS; i++)
655 NVWriteAttr(par, i, state->attr[i]);
656
657 for (i = 0; i < NUM_GRC_REGS; i++)
658 NVWriteGr(par, i, state->gra[i]);
659
660 for (i = 0; i < NUM_SEQ_REGS; i++)
661 NVWriteSeq(par, i, state->seq[i]);
662 NVTRACE_LEAVE();
663 }
664
665 static int nvidia_calc_regs(struct fb_info *info)
666 {
667 struct nvidia_par *par = info->par;
668 struct _riva_hw_state *state = &par->ModeReg;
669 int i, depth = fb_get_color_depth(&info->var, &info->fix);
670 int h_display = info->var.xres / 8 - 1;
671 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
672 int h_end = (info->var.xres + info->var.right_margin +
673 info->var.hsync_len) / 8 - 1;
674 int h_total = (info->var.xres + info->var.right_margin +
675 info->var.hsync_len + info->var.left_margin) / 8 - 5;
676 int h_blank_s = h_display;
677 int h_blank_e = h_total + 4;
678 int v_display = info->var.yres - 1;
679 int v_start = info->var.yres + info->var.lower_margin - 1;
680 int v_end = (info->var.yres + info->var.lower_margin +
681 info->var.vsync_len) - 1;
682 int v_total = (info->var.yres + info->var.lower_margin +
683 info->var.vsync_len + info->var.upper_margin) - 2;
684 int v_blank_s = v_display;
685 int v_blank_e = v_total + 1;
686
687 /*
688 * Set all CRTC values.
689 */
690
691 if (info->var.vmode & FB_VMODE_INTERLACED)
692 v_total |= 1;
693
694 if (par->FlatPanel == 1) {
695 v_start = v_total - 3;
696 v_end = v_total - 2;
697 v_blank_s = v_start;
698 h_start = h_total - 5;
699 h_end = h_total - 2;
700 h_blank_e = h_total + 4;
701 }
702
703 state->crtc[0x0] = Set8Bits(h_total);
704 state->crtc[0x1] = Set8Bits(h_display);
705 state->crtc[0x2] = Set8Bits(h_blank_s);
706 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
707 | SetBit(7);
708 state->crtc[0x4] = Set8Bits(h_start);
709 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
710 | SetBitField(h_end, 4: 0, 4:0);
711 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
712 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
713 | SetBitField(v_display, 8: 8, 1:1)
714 | SetBitField(v_start, 8: 8, 2:2)
715 | SetBitField(v_blank_s, 8: 8, 3:3)
716 | SetBit(4)
717 | SetBitField(v_total, 9: 9, 5:5)
718 | SetBitField(v_display, 9: 9, 6:6)
719 | SetBitField(v_start, 9: 9, 7:7);
720 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
721 | SetBit(6)
722 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
723 state->crtc[0x10] = Set8Bits(v_start);
724 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
725 state->crtc[0x12] = Set8Bits(v_display);
726 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
727 (info->var.bits_per_pixel / 8));
728 state->crtc[0x15] = Set8Bits(v_blank_s);
729 state->crtc[0x16] = Set8Bits(v_blank_e);
730
731 state->attr[0x10] = 0x01;
732
733 if (par->Television)
734 state->attr[0x11] = 0x00;
735
736 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
737 | SetBitField(v_blank_s, 10: 10, 3:3)
738 | SetBitField(v_start, 10: 10, 2:2)
739 | SetBitField(v_display, 10: 10, 1:1)
740 | SetBitField(v_total, 10: 10, 0:0);
741
742 state->horiz = SetBitField(h_total, 8: 8, 0:0)
743 | SetBitField(h_display, 8: 8, 1:1)
744 | SetBitField(h_blank_s, 8: 8, 2:2)
745 | SetBitField(h_start, 8: 8, 3:3);
746
747 state->extra = SetBitField(v_total, 11: 11, 0:0)
748 | SetBitField(v_display, 11: 11, 2:2)
749 | SetBitField(v_start, 11: 11, 4:4)
750 | SetBitField(v_blank_s, 11: 11, 6:6);
751
752 if (info->var.vmode & FB_VMODE_INTERLACED) {
753 h_total = (h_total >> 1) & ~1;
754 state->interlace = Set8Bits(h_total);
755 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
756 } else {
757 state->interlace = 0xff; /* interlace off */
758 }
759
760 /*
761 * Calculate the extended registers.
762 */
763
764 if (depth < 24)
765 i = depth;
766 else
767 i = 32;
768
769 if (par->Architecture >= NV_ARCH_10)
770 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
771 par->CursorStart);
772
773 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
774 state->misc_output &= ~0x40;
775 else
776 state->misc_output |= 0x40;
777 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
778 state->misc_output &= ~0x80;
779 else
780 state->misc_output |= 0x80;
781
782 NVCalcStateExt(par, state, i, info->var.xres_virtual,
783 info->var.xres, info->var.yres_virtual,
784 1000000000 / info->var.pixclock, info->var.vmode);
785
786 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
787 if (par->FlatPanel == 1) {
788 state->pixel |= (1 << 7);
789
790 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
791 || (par->fpHeight <= info->var.yres)) {
792 state->scale |= (1 << 8);
793 }
794
795 if (!par->crtcSync_read) {
796 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
797 par->crtcSync_read = 1;
798 }
799
800 par->PanelTweak = nvidia_panel_tweak(par, state);
801 }
802
803 state->vpll = state->pll;
804 state->vpll2 = state->pll;
805 state->vpllB = state->pllB;
806 state->vpll2B = state->pllB;
807
808 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
809 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
810
811 if (par->CRTCnumber) {
812 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
813 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
814 state->crtcOwner = 3;
815 state->pllsel |= 0x20000800;
816 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
817 if (par->twoStagePLL)
818 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
819 } else if (par->twoHeads) {
820 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
821 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
822 state->crtcOwner = 0;
823 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
824 if (par->twoStagePLL)
825 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
826 }
827
828 state->cursorConfig = 0x00000100;
829
830 if (info->var.vmode & FB_VMODE_DOUBLE)
831 state->cursorConfig |= (1 << 4);
832
833 if (par->alphaCursor) {
834 if ((par->Chipset & 0x0ff0) != 0x0110)
835 state->cursorConfig |= 0x04011000;
836 else
837 state->cursorConfig |= 0x14011000;
838 state->general |= (1 << 29);
839 } else
840 state->cursorConfig |= 0x02000000;
841
842 if (par->twoHeads) {
843 if ((par->Chipset & 0x0ff0) == 0x0110) {
844 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
845 ~0x00010000;
846 if (par->FPDither)
847 state->dither |= 0x00010000;
848 } else {
849 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
850 if (par->FPDither)
851 state->dither |= 1;
852 }
853 }
854
855 state->timingH = 0;
856 state->timingV = 0;
857 state->displayV = info->var.xres;
858
859 return 0;
860 }
861
862 static void nvidia_init_vga(struct fb_info *info)
863 {
864 struct nvidia_par *par = info->par;
865 struct _riva_hw_state *state = &par->ModeReg;
866 int i;
867
868 for (i = 0; i < 0x10; i++)
869 state->attr[i] = i;
870 state->attr[0x10] = 0x41;
871 state->attr[0x11] = 0x01;
872 state->attr[0x12] = 0x0f;
873 state->attr[0x13] = 0x00;
874 state->attr[0x14] = 0x00;
875
876 memset(state->crtc, 0x00, NUM_CRT_REGS);
877 state->crtc[0x0a] = 0x20;
878 state->crtc[0x17] = 0xe3;
879 state->crtc[0x18] = 0xff;
880 state->crtc[0x28] = 0x40;
881
882 memset(state->gra, 0x00, NUM_GRC_REGS);
883 state->gra[0x05] = 0x40;
884 state->gra[0x06] = 0x05;
885 state->gra[0x07] = 0x0f;
886 state->gra[0x08] = 0xff;
887
888 state->seq[0x00] = 0x03;
889 state->seq[0x01] = 0x01;
890 state->seq[0x02] = 0x0f;
891 state->seq[0x03] = 0x00;
892 state->seq[0x04] = 0x0e;
893
894 state->misc_output = 0xeb;
895 }
896
897 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
898 {
899 struct nvidia_par *par = info->par;
900 u8 data[MAX_CURS * MAX_CURS / 8];
901 int i, set = cursor->set;
902 u16 fg, bg;
903
904 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
905 return -ENXIO;
906
907 NVShowHideCursor(par, 0);
908
909 if (par->cursor_reset) {
910 set = FB_CUR_SETALL;
911 par->cursor_reset = 0;
912 }
913
914 if (set & FB_CUR_SETSIZE)
915 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
916
917 if (set & FB_CUR_SETPOS) {
918 u32 xx, yy, temp;
919
920 yy = cursor->image.dy - info->var.yoffset;
921 xx = cursor->image.dx - info->var.xoffset;
922 temp = xx & 0xFFFF;
923 temp |= yy << 16;
924
925 NV_WR32(par->PRAMDAC, 0x0000300, temp);
926 }
927
928 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
929 u32 bg_idx = cursor->image.bg_color;
930 u32 fg_idx = cursor->image.fg_color;
931 u32 s_pitch = (cursor->image.width + 7) >> 3;
932 u32 d_pitch = MAX_CURS / 8;
933 u8 *dat = (u8 *) cursor->image.data;
934 u8 *msk = (u8 *) cursor->mask;
935 u8 *src;
936
937 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
938
939 if (src) {
940 switch (cursor->rop) {
941 case ROP_XOR:
942 for (i = 0; i < s_pitch * cursor->image.height; i++)
943 src[i] = dat[i] ^ msk[i];
944 break;
945 case ROP_COPY:
946 default:
947 for (i = 0; i < s_pitch * cursor->image.height; i++)
948 src[i] = dat[i] & msk[i];
949 break;
950 }
951
952 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
953 cursor->image.height);
954
955 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
956 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
957 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
958
959 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
960 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
961 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
962
963 NVLockUnlock(par, 0);
964
965 nvidiafb_load_cursor_image(par, data, bg, fg,
966 cursor->image.width,
967 cursor->image.height);
968 kfree(src);
969 }
970 }
971
972 if (cursor->enable)
973 NVShowHideCursor(par, 1);
974
975 return 0;
976 }
977
978 static int nvidiafb_set_par(struct fb_info *info)
979 {
980 struct nvidia_par *par = info->par;
981
982 NVTRACE_ENTER();
983
984 NVLockUnlock(par, 1);
985 if (!par->FlatPanel || (info->var.bits_per_pixel != 24) ||
986 !par->twoHeads)
987 par->FPDither = 0;
988
989 info->fix.visual = (info->var.bits_per_pixel == 8) ?
990 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
991
992 nvidia_init_vga(info);
993 nvidia_calc_regs(info);
994 nvidia_write_regs(par);
995
996 NVLockUnlock(par, 0);
997 if (par->twoHeads) {
998 VGA_WR08(par->PCIO, 0x03D4, 0x44);
999 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1000 NVLockUnlock(par, 0);
1001 }
1002
1003 NVWriteCrtc(par, 0x11, 0x00);
1004 info->fix.line_length = (info->var.xres_virtual *
1005 info->var.bits_per_pixel) >> 3;
1006 if (info->var.accel_flags) {
1007 info->fbops->fb_imageblit = nvidiafb_imageblit;
1008 info->fbops->fb_fillrect = nvidiafb_fillrect;
1009 info->fbops->fb_copyarea = nvidiafb_copyarea;
1010 info->fbops->fb_sync = nvidiafb_sync;
1011 info->pixmap.scan_align = 4;
1012 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1013 NVResetGraphics(info);
1014 } else {
1015 info->fbops->fb_imageblit = cfb_imageblit;
1016 info->fbops->fb_fillrect = cfb_fillrect;
1017 info->fbops->fb_copyarea = cfb_copyarea;
1018 info->fbops->fb_sync = NULL;
1019 info->pixmap.scan_align = 1;
1020 info->flags |= FBINFO_HWACCEL_DISABLED;
1021 }
1022
1023 par->cursor_reset = 1;
1024
1025 NVWriteCrtc(par, 0x11, 0xff);
1026
1027 NVTRACE_LEAVE();
1028 return 0;
1029 }
1030
1031 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1032 unsigned blue, unsigned transp,
1033 struct fb_info *info)
1034 {
1035 struct nvidia_par *par = info->par;
1036 int i;
1037
1038 NVTRACE_ENTER();
1039 if (regno >= (1 << info->var.green.length))
1040 return -EINVAL;
1041
1042 if (info->var.grayscale) {
1043 /* gray = 0.30*R + 0.59*G + 0.11*B */
1044 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1045 }
1046
1047 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1048 ((u32 *) info->pseudo_palette)[regno] =
1049 (regno << info->var.red.offset) |
1050 (regno << info->var.green.offset) |
1051 (regno << info->var.blue.offset);
1052 }
1053
1054 switch (info->var.bits_per_pixel) {
1055 case 8:
1056 /* "transparent" stuff is completely ignored. */
1057 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1058 break;
1059 case 16:
1060 if (info->var.green.length == 5) {
1061 for (i = 0; i < 8; i++) {
1062 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1063 green >> 8, blue >> 8);
1064 }
1065 } else {
1066 u8 r, g, b;
1067
1068 if (regno < 32) {
1069 for (i = 0; i < 8; i++) {
1070 nvidia_write_clut(par, regno * 8 + i,
1071 red >> 8, green >> 8,
1072 blue >> 8);
1073 }
1074 }
1075
1076 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1077
1078 for (i = 0; i < 4; i++)
1079 nvidia_write_clut(par, regno * 4 + i, r,
1080 green >> 8, b);
1081 }
1082 break;
1083 case 32:
1084 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1085 break;
1086 default:
1087 /* do nothing */
1088 break;
1089 }
1090
1091 NVTRACE_LEAVE();
1092 return 0;
1093 }
1094
1095 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1096 struct fb_info *info)
1097 {
1098 struct nvidia_par *par = info->par;
1099 int memlen, vramlen, mode_valid = 0;
1100 int pitch, err = 0;
1101
1102 NVTRACE_ENTER();
1103
1104 var->transp.offset = 0;
1105 var->transp.length = 0;
1106
1107 var->xres &= ~7;
1108
1109 if (var->bits_per_pixel <= 8)
1110 var->bits_per_pixel = 8;
1111 else if (var->bits_per_pixel <= 16)
1112 var->bits_per_pixel = 16;
1113 else
1114 var->bits_per_pixel = 32;
1115
1116 switch (var->bits_per_pixel) {
1117 case 8:
1118 var->red.offset = 0;
1119 var->red.length = 8;
1120 var->green.offset = 0;
1121 var->green.length = 8;
1122 var->blue.offset = 0;
1123 var->blue.length = 8;
1124 var->transp.offset = 0;
1125 var->transp.length = 0;
1126 break;
1127 case 16:
1128 var->green.length = (var->green.length < 6) ? 5 : 6;
1129 var->red.length = 5;
1130 var->blue.length = 5;
1131 var->transp.length = 6 - var->green.length;
1132 var->blue.offset = 0;
1133 var->green.offset = 5;
1134 var->red.offset = 5 + var->green.length;
1135 var->transp.offset = (5 + var->red.offset) & 15;
1136 break;
1137 case 32: /* RGBA 8888 */
1138 var->red.offset = 16;
1139 var->red.length = 8;
1140 var->green.offset = 8;
1141 var->green.length = 8;
1142 var->blue.offset = 0;
1143 var->blue.length = 8;
1144 var->transp.length = 8;
1145 var->transp.offset = 24;
1146 break;
1147 }
1148
1149 var->red.msb_right = 0;
1150 var->green.msb_right = 0;
1151 var->blue.msb_right = 0;
1152 var->transp.msb_right = 0;
1153
1154 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1155 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1156 mode_valid = 1;
1157
1158 /* calculate modeline if supported by monitor */
1159 if (!mode_valid && info->monspecs.gtf) {
1160 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1161 mode_valid = 1;
1162 }
1163
1164 if (!mode_valid) {
1165 struct fb_videomode *mode;
1166
1167 mode = fb_find_best_mode(var, &info->modelist);
1168 if (mode) {
1169 fb_videomode_to_var(var, mode);
1170 mode_valid = 1;
1171 }
1172 }
1173
1174 if (!mode_valid && info->monspecs.modedb_len)
1175 return -EINVAL;
1176
1177 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1178 par->fpHeight < var->yres))
1179 return -EINVAL;
1180
1181 if (var->yres_virtual < var->yres)
1182 var->yres_virtual = var->yres;
1183
1184 if (var->xres_virtual < var->xres)
1185 var->xres_virtual = var->xres;
1186
1187 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1188
1189 vramlen = info->screen_size;
1190 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1191 memlen = pitch * var->yres_virtual;
1192
1193 if (memlen > vramlen) {
1194 var->yres_virtual = vramlen / pitch;
1195
1196 if (var->yres_virtual < var->yres) {
1197 var->yres_virtual = var->yres;
1198 var->xres_virtual = vramlen / var->yres_virtual;
1199 var->xres_virtual /= var->bits_per_pixel / 8;
1200 var->xres_virtual &= ~63;
1201 pitch = (var->xres_virtual *
1202 var->bits_per_pixel + 7) / 8;
1203 memlen = pitch * var->yres;
1204
1205 if (var->xres_virtual < var->xres) {
1206 printk("nvidiafb: required video memory, "
1207 "%d bytes, for %dx%d-%d (virtual) "
1208 "is out of range\n",
1209 memlen, var->xres_virtual,
1210 var->yres_virtual, var->bits_per_pixel);
1211 err = -ENOMEM;
1212 }
1213 }
1214 }
1215
1216 if (var->accel_flags) {
1217 if (var->yres_virtual > 0x7fff)
1218 var->yres_virtual = 0x7fff;
1219 if (var->xres_virtual > 0x7fff)
1220 var->xres_virtual = 0x7fff;
1221 }
1222
1223 var->xres_virtual &= ~63;
1224
1225 NVTRACE_LEAVE();
1226
1227 return err;
1228 }
1229
1230 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1231 struct fb_info *info)
1232 {
1233 struct nvidia_par *par = info->par;
1234 u32 total;
1235
1236 total = info->var.yoffset * info->fix.line_length + info->var.xoffset;
1237
1238 NVSetStartAddress(par, total);
1239
1240 return 0;
1241 }
1242
1243 static int nvidiafb_blank(int blank, struct fb_info *info)
1244 {
1245 struct nvidia_par *par = info->par;
1246 unsigned char tmp, vesa;
1247
1248 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1249 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1250
1251 NVTRACE_ENTER();
1252
1253 if (blank)
1254 tmp |= 0x20;
1255
1256 switch (blank) {
1257 case FB_BLANK_UNBLANK:
1258 case FB_BLANK_NORMAL:
1259 break;
1260 case FB_BLANK_VSYNC_SUSPEND:
1261 vesa |= 0x80;
1262 break;
1263 case FB_BLANK_HSYNC_SUSPEND:
1264 vesa |= 0x40;
1265 break;
1266 case FB_BLANK_POWERDOWN:
1267 vesa |= 0xc0;
1268 break;
1269 }
1270
1271 NVWriteSeq(par, 0x01, tmp);
1272 NVWriteCrtc(par, 0x1a, vesa);
1273
1274 #ifdef CONFIG_PMAC_BACKLIGHT
1275 if (par->FlatPanel && _machine == _MACH_Pmac) {
1276 set_backlight_enable(!blank);
1277 }
1278 #endif
1279
1280 NVTRACE_LEAVE();
1281
1282 return 0;
1283 }
1284
1285 static struct fb_ops nvidia_fb_ops = {
1286 .owner = THIS_MODULE,
1287 .fb_check_var = nvidiafb_check_var,
1288 .fb_set_par = nvidiafb_set_par,
1289 .fb_setcolreg = nvidiafb_setcolreg,
1290 .fb_pan_display = nvidiafb_pan_display,
1291 .fb_blank = nvidiafb_blank,
1292 .fb_fillrect = nvidiafb_fillrect,
1293 .fb_copyarea = nvidiafb_copyarea,
1294 .fb_imageblit = nvidiafb_imageblit,
1295 .fb_cursor = nvidiafb_cursor,
1296 .fb_sync = nvidiafb_sync,
1297 };
1298
1299 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1300 {
1301 struct fb_monspecs *specs = &info->monspecs;
1302 struct fb_videomode modedb;
1303 struct nvidia_par *par = info->par;
1304 int lpitch;
1305
1306 NVTRACE_ENTER();
1307 info->flags = FBINFO_DEFAULT
1308 | FBINFO_HWACCEL_IMAGEBLIT
1309 | FBINFO_HWACCEL_FILLRECT
1310 | FBINFO_HWACCEL_COPYAREA
1311 | FBINFO_HWACCEL_YPAN;
1312
1313 fb_videomode_to_modelist(info->monspecs.modedb,
1314 info->monspecs.modedb_len, &info->modelist);
1315 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1316
1317 if (specs->modedb != NULL) {
1318 /* get preferred timing */
1319 if (specs->misc & FB_MISC_1ST_DETAIL) {
1320 int i;
1321
1322 for (i = 0; i < specs->modedb_len; i++) {
1323 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1324 modedb = specs->modedb[i];
1325 break;
1326 }
1327 }
1328 } else {
1329 /* otherwise, get first mode in database */
1330 modedb = specs->modedb[0];
1331 }
1332
1333 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1334 nvidiafb_default_var.bits_per_pixel = 8;
1335 } else if (par->fpWidth && par->fpHeight) {
1336 char buf[16];
1337
1338 memset(buf, 0, 16);
1339 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1340 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1341 specs->modedb_len, &modedb, 8);
1342 }
1343
1344 if (mode_option)
1345 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1346 specs->modedb, specs->modedb_len, &modedb, 8);
1347
1348 info->var = nvidiafb_default_var;
1349 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1350 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1351 info->pseudo_palette = par->pseudo_palette;
1352 fb_alloc_cmap(&info->cmap, 256, 0);
1353 fb_destroy_modedb(info->monspecs.modedb);
1354 info->monspecs.modedb = NULL;
1355
1356 /* maximize virtual vertical length */
1357 lpitch = info->var.xres_virtual *
1358 ((info->var.bits_per_pixel + 7) >> 3);
1359 info->var.yres_virtual = info->screen_size / lpitch;
1360
1361 info->pixmap.scan_align = 4;
1362 info->pixmap.buf_align = 4;
1363 info->pixmap.access_align = 32;
1364 info->pixmap.size = 8 * 1024;
1365 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1366
1367 if (!hwcur)
1368 info->fbops->fb_cursor = soft_cursor;
1369
1370 info->var.accel_flags = (!noaccel);
1371
1372 switch (par->Architecture) {
1373 case NV_ARCH_04:
1374 info->fix.accel = FB_ACCEL_NV4;
1375 break;
1376 case NV_ARCH_10:
1377 info->fix.accel = FB_ACCEL_NV_10;
1378 break;
1379 case NV_ARCH_20:
1380 info->fix.accel = FB_ACCEL_NV_20;
1381 break;
1382 case NV_ARCH_30:
1383 info->fix.accel = FB_ACCEL_NV_30;
1384 break;
1385 case NV_ARCH_40:
1386 info->fix.accel = FB_ACCEL_NV_40;
1387 break;
1388 }
1389
1390 NVTRACE_LEAVE();
1391
1392 return nvidiafb_check_var(&info->var, info);
1393 }
1394
1395 static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1396 {
1397 u32 arch = 0;
1398
1399 switch (pd->device & 0x0ff0) {
1400 case 0x0100: /* GeForce 256 */
1401 case 0x0110: /* GeForce2 MX */
1402 case 0x0150: /* GeForce2 */
1403 case 0x0170: /* GeForce4 MX */
1404 case 0x0180: /* GeForce4 MX (8x AGP) */
1405 case 0x01A0: /* nForce */
1406 case 0x01F0: /* nForce2 */
1407 arch = NV_ARCH_10;
1408 break;
1409 case 0x0200: /* GeForce3 */
1410 case 0x0250: /* GeForce4 Ti */
1411 case 0x0280: /* GeForce4 Ti (8x AGP) */
1412 arch = NV_ARCH_20;
1413 break;
1414 case 0x0300: /* GeForceFX 5800 */
1415 case 0x0310: /* GeForceFX 5600 */
1416 case 0x0320: /* GeForceFX 5200 */
1417 case 0x0330: /* GeForceFX 5900 */
1418 case 0x0340: /* GeForceFX 5700 */
1419 arch = NV_ARCH_30;
1420 break;
1421 case 0x0040:
1422 case 0x00C0:
1423 case 0x0120:
1424 case 0x0130:
1425 case 0x0140:
1426 case 0x0160:
1427 case 0x01D0:
1428 case 0x0090:
1429 case 0x0210:
1430 case 0x0220:
1431 case 0x0230:
1432 arch = NV_ARCH_40;
1433 break;
1434 case 0x0020: /* TNT, TNT2 */
1435 arch = NV_ARCH_04;
1436 break;
1437 default: /* unknown architecture */
1438 break;
1439 }
1440
1441 return arch;
1442 }
1443
1444 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1445 const struct pci_device_id *ent)
1446 {
1447 struct nvidia_par *par;
1448 struct fb_info *info;
1449 unsigned short cmd;
1450
1451
1452 NVTRACE_ENTER();
1453 assert(pd != NULL);
1454
1455 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1456
1457 if (!info)
1458 goto err_out;
1459
1460 par = (struct nvidia_par *)info->par;
1461 par->pci_dev = pd;
1462
1463 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1464
1465 if (info->pixmap.addr == NULL)
1466 goto err_out_kfree;
1467
1468 memset(info->pixmap.addr, 0, 8 * 1024);
1469
1470 if (pci_enable_device(pd)) {
1471 printk(KERN_ERR PFX "cannot enable PCI device\n");
1472 goto err_out_enable;
1473 }
1474
1475 if (pci_request_regions(pd, "nvidiafb")) {
1476 printk(KERN_ERR PFX "cannot request PCI regions\n");
1477 goto err_out_request;
1478 }
1479
1480 par->Architecture = nvidia_get_arch(pd);
1481
1482 par->Chipset = (pd->vendor << 16) | pd->device;
1483 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1484
1485 if (par->Architecture == 0) {
1486 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1487 goto err_out_free_base0;
1488 }
1489
1490 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1491
1492 par->FlatPanel = flatpanel;
1493
1494 if (flatpanel == 1)
1495 printk(KERN_INFO PFX "flatpanel support enabled\n");
1496
1497 par->CRTCnumber = forceCRTC;
1498 par->FpScale = (!noscale);
1499 par->paneltweak = paneltweak;
1500
1501 /* enable IO and mem if not already done */
1502 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1503 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1504 pci_write_config_word(pd, PCI_COMMAND, cmd);
1505
1506 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1507 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1508 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1509
1510 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1511
1512 if (!par->REGS) {
1513 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1514 goto err_out_free_base0;
1515 }
1516
1517 NVCommonSetup(info);
1518
1519 par->FbAddress = nvidiafb_fix.smem_start;
1520 par->FbMapSize = par->RamAmountKBytes * 1024;
1521 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1522 par->FbMapSize = vram * 1024 * 1024;
1523
1524 /* Limit amount of vram to 64 MB */
1525 if (par->FbMapSize > 64 * 1024 * 1024)
1526 par->FbMapSize = 64 * 1024 * 1024;
1527
1528 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1529 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1530 16 * 1024;
1531 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1532 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1533 info->screen_size = par->FbUsableSize;
1534 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1535
1536 if (!info->screen_base) {
1537 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1538 goto err_out_free_base1;
1539 }
1540
1541 par->FbStart = info->screen_base;
1542
1543 #ifdef CONFIG_MTRR
1544 if (!nomtrr) {
1545 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1546 par->RamAmountKBytes * 1024,
1547 MTRR_TYPE_WRCOMB, 1);
1548 if (par->mtrr.vram < 0) {
1549 printk(KERN_ERR PFX "unable to setup MTRR\n");
1550 } else {
1551 par->mtrr.vram_valid = 1;
1552 /* let there be speed */
1553 printk(KERN_INFO PFX "MTRR set to ON\n");
1554 }
1555 }
1556 #endif /* CONFIG_MTRR */
1557
1558 info->fbops = &nvidia_fb_ops;
1559 info->fix = nvidiafb_fix;
1560
1561 if (nvidia_set_fbinfo(info) < 0) {
1562 printk(KERN_ERR PFX "error setting initial video mode\n");
1563 goto err_out_iounmap_fb;
1564 }
1565
1566 nvidia_save_vga(par, &par->SavedReg);
1567
1568 if (register_framebuffer(info) < 0) {
1569 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1570 goto err_out_iounmap_fb;
1571 }
1572
1573 pci_set_drvdata(pd, info);
1574
1575 printk(KERN_INFO PFX
1576 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1577 info->fix.id,
1578 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1579 #ifdef CONFIG_PMAC_BACKLIGHT
1580 if (par->FlatPanel && _machine == _MACH_Pmac)
1581 register_backlight_controller(&nvidia_backlight_controller,
1582 par, "mnca");
1583 #endif
1584 NVTRACE_LEAVE();
1585 return 0;
1586
1587 err_out_iounmap_fb:
1588 iounmap(info->screen_base);
1589 err_out_free_base1:
1590 fb_destroy_modedb(info->monspecs.modedb);
1591 nvidia_delete_i2c_busses(par);
1592 iounmap(par->REGS);
1593 err_out_free_base0:
1594 pci_release_regions(pd);
1595 err_out_request:
1596 pci_disable_device(pd);
1597 err_out_enable:
1598 kfree(info->pixmap.addr);
1599 err_out_kfree:
1600 framebuffer_release(info);
1601 err_out:
1602 return -ENODEV;
1603 }
1604
1605 static void __exit nvidiafb_remove(struct pci_dev *pd)
1606 {
1607 struct fb_info *info = pci_get_drvdata(pd);
1608 struct nvidia_par *par = info->par;
1609
1610 NVTRACE_ENTER();
1611 if (!info)
1612 return;
1613
1614 unregister_framebuffer(info);
1615 #ifdef CONFIG_MTRR
1616 if (par->mtrr.vram_valid)
1617 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1618 info->fix.smem_len);
1619 #endif /* CONFIG_MTRR */
1620
1621 iounmap(info->screen_base);
1622 fb_destroy_modedb(info->monspecs.modedb);
1623 nvidia_delete_i2c_busses(par);
1624 iounmap(par->REGS);
1625 pci_release_regions(pd);
1626 pci_disable_device(pd);
1627 kfree(info->pixmap.addr);
1628 framebuffer_release(info);
1629 pci_set_drvdata(pd, NULL);
1630 NVTRACE_LEAVE();
1631 }
1632
1633 /* ------------------------------------------------------------------------- *
1634 *
1635 * initialization
1636 *
1637 * ------------------------------------------------------------------------- */
1638
1639 #ifndef MODULE
1640 static int __devinit nvidiafb_setup(char *options)
1641 {
1642 char *this_opt;
1643
1644 NVTRACE_ENTER();
1645 if (!options || !*options)
1646 return 0;
1647
1648 while ((this_opt = strsep(&options, ",")) != NULL) {
1649 if (!strncmp(this_opt, "forceCRTC", 9)) {
1650 char *p;
1651
1652 p = this_opt + 9;
1653 if (!*p || !*(++p))
1654 continue;
1655 forceCRTC = *p - '0';
1656 if (forceCRTC < 0 || forceCRTC > 1)
1657 forceCRTC = -1;
1658 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1659 flatpanel = 1;
1660 } else if (!strncmp(this_opt, "hwcur", 5)) {
1661 hwcur = 1;
1662 } else if (!strncmp(this_opt, "noaccel", 6)) {
1663 noaccel = 1;
1664 } else if (!strncmp(this_opt, "noscale", 7)) {
1665 noscale = 1;
1666 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1667 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1668 } else if (!strncmp(this_opt, "vram:", 5)) {
1669 vram = simple_strtoul(this_opt+5, NULL, 0);
1670 #ifdef CONFIG_MTRR
1671 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1672 nomtrr = 1;
1673 #endif
1674 } else
1675 mode_option = this_opt;
1676 }
1677 NVTRACE_LEAVE();
1678 return 0;
1679 }
1680 #endif /* !MODULE */
1681
1682 static struct pci_driver nvidiafb_driver = {
1683 .name = "nvidiafb",
1684 .id_table = nvidiafb_pci_tbl,
1685 .probe = nvidiafb_probe,
1686 .remove = __exit_p(nvidiafb_remove),
1687 };
1688
1689 /* ------------------------------------------------------------------------- *
1690 *
1691 * modularization
1692 *
1693 * ------------------------------------------------------------------------- */
1694
1695 static int __devinit nvidiafb_init(void)
1696 {
1697 #ifndef MODULE
1698 char *option = NULL;
1699
1700 if (fb_get_options("nvidiafb", &option))
1701 return -ENODEV;
1702 nvidiafb_setup(option);
1703 #endif
1704 return pci_register_driver(&nvidiafb_driver);
1705 }
1706
1707 module_init(nvidiafb_init);
1708
1709 #ifdef MODULE
1710 static void __exit nvidiafb_exit(void)
1711 {
1712 pci_unregister_driver(&nvidiafb_driver);
1713 }
1714
1715 module_exit(nvidiafb_exit);
1716
1717 module_param(flatpanel, int, 0);
1718 MODULE_PARM_DESC(flatpanel,
1719 "Enables experimental flat panel support for some chipsets. "
1720 "(0 or 1=enabled) (default=0)");
1721 module_param(hwcur, int, 0);
1722 MODULE_PARM_DESC(hwcur,
1723 "Enables hardware cursor implementation. (0 or 1=enabled) "
1724 "(default=0)");
1725 module_param(noaccel, int, 0);
1726 MODULE_PARM_DESC(noaccel,
1727 "Disables hardware acceleration. (0 or 1=disable) "
1728 "(default=0)");
1729 module_param(noscale, int, 0);
1730 MODULE_PARM_DESC(noscale,
1731 "Disables screen scaleing. (0 or 1=disable) "
1732 "(default=0, do scaling)");
1733 module_param(paneltweak, int, 0);
1734 MODULE_PARM_DESC(paneltweak,
1735 "Tweak display settings for flatpanels. "
1736 "(default=0, no tweaks)");
1737 module_param(forceCRTC, int, 0);
1738 MODULE_PARM_DESC(forceCRTC,
1739 "Forces usage of a particular CRTC in case autodetection "
1740 "fails. (0 or 1) (default=autodetect)");
1741 module_param(vram, int, 0);
1742 MODULE_PARM_DESC(vram,
1743 "amount of framebuffer memory to remap in MiB"
1744 "(default=0 - remap entire memory)");
1745 #ifdef CONFIG_MTRR
1746 module_param(nomtrr, bool, 0);
1747 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1748 "(default=0)");
1749 #endif
1750
1751 MODULE_AUTHOR("Antonino Daplas");
1752 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1753 MODULE_LICENSE("GPL");
1754 #endif /* MODULE */
1755
Linux kernel - Deliverables
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