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OMAP: OMAPFB: split omapfb.h
[deliverable/linux.git] / drivers / video / omap / lcdc.c
1 /*
2 * OMAP1 internal LCD controller
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/err.h>
26 #include <linux/mm.h>
27 #include <linux/fb.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/vmalloc.h>
30 #include <linux/clk.h>
31
32 #include <plat/dma.h>
33
34 #include <asm/mach-types.h>
35
36 #include "omapfb.h"
37
38 #include "lcdc.h"
39
40 #define MODULE_NAME "lcdc"
41
42 #define OMAP_LCDC_BASE 0xfffec000
43 #define OMAP_LCDC_SIZE 256
44 #define OMAP_LCDC_IRQ INT_LCD_CTRL
45
46 #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
47 #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
48 #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
49 #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
50 #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
51 #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
52 #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
53 #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
54
55 #define OMAP_LCDC_STAT_DONE (1 << 0)
56 #define OMAP_LCDC_STAT_VSYNC (1 << 1)
57 #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
58 #define OMAP_LCDC_STAT_ABC (1 << 3)
59 #define OMAP_LCDC_STAT_LINE_INT (1 << 4)
60 #define OMAP_LCDC_STAT_FUF (1 << 5)
61 #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
62
63 #define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
64 #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
65 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
66
67 #define OMAP_LCDC_IRQ_VSYNC (1 << 2)
68 #define OMAP_LCDC_IRQ_DONE (1 << 3)
69 #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
70 #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
71 #define OMAP_LCDC_IRQ_LINE (1 << 6)
72 #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
73
74 #define MAX_PALETTE_SIZE PAGE_SIZE
75
76 enum lcdc_load_mode {
77 OMAP_LCDC_LOAD_PALETTE,
78 OMAP_LCDC_LOAD_FRAME,
79 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
80 };
81
82 static struct omap_lcd_controller {
83 enum omapfb_update_mode update_mode;
84 int ext_mode;
85
86 unsigned long frame_offset;
87 int screen_width;
88 int xres;
89 int yres;
90
91 enum omapfb_color_format color_mode;
92 int bpp;
93 void *palette_virt;
94 dma_addr_t palette_phys;
95 int palette_code;
96 int palette_size;
97
98 unsigned int irq_mask;
99 struct completion last_frame_complete;
100 struct completion palette_load_complete;
101 struct clk *lcd_ck;
102 struct omapfb_device *fbdev;
103
104 void (*dma_callback)(void *data);
105 void *dma_callback_data;
106
107 int fbmem_allocated;
108 dma_addr_t vram_phys;
109 void *vram_virt;
110 unsigned long vram_size;
111 } lcdc;
112
113 static void inline enable_irqs(int mask)
114 {
115 lcdc.irq_mask |= mask;
116 }
117
118 static void inline disable_irqs(int mask)
119 {
120 lcdc.irq_mask &= ~mask;
121 }
122
123 static void set_load_mode(enum lcdc_load_mode mode)
124 {
125 u32 l;
126
127 l = omap_readl(OMAP_LCDC_CONTROL);
128 l &= ~(3 << 20);
129 switch (mode) {
130 case OMAP_LCDC_LOAD_PALETTE:
131 l |= 1 << 20;
132 break;
133 case OMAP_LCDC_LOAD_FRAME:
134 l |= 2 << 20;
135 break;
136 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
137 break;
138 default:
139 BUG();
140 }
141 omap_writel(l, OMAP_LCDC_CONTROL);
142 }
143
144 static void enable_controller(void)
145 {
146 u32 l;
147
148 l = omap_readl(OMAP_LCDC_CONTROL);
149 l |= OMAP_LCDC_CTRL_LCD_EN;
150 l &= ~OMAP_LCDC_IRQ_MASK;
151 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
152 omap_writel(l, OMAP_LCDC_CONTROL);
153 }
154
155 static void disable_controller_async(void)
156 {
157 u32 l;
158 u32 mask;
159
160 l = omap_readl(OMAP_LCDC_CONTROL);
161 mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
162 /*
163 * Preserve the DONE mask, since we still want to get the
164 * final DONE irq. It will be disabled in the IRQ handler.
165 */
166 mask &= ~OMAP_LCDC_IRQ_DONE;
167 l &= ~mask;
168 omap_writel(l, OMAP_LCDC_CONTROL);
169 }
170
171 static void disable_controller(void)
172 {
173 init_completion(&lcdc.last_frame_complete);
174 disable_controller_async();
175 if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
176 msecs_to_jiffies(500)))
177 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
178 }
179
180 static void reset_controller(u32 status)
181 {
182 static unsigned long reset_count;
183 static unsigned long last_jiffies;
184
185 disable_controller_async();
186 reset_count++;
187 if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
188 dev_err(lcdc.fbdev->dev,
189 "resetting (status %#010x,reset count %lu)\n",
190 status, reset_count);
191 last_jiffies = jiffies;
192 }
193 if (reset_count < 100) {
194 enable_controller();
195 } else {
196 reset_count = 0;
197 dev_err(lcdc.fbdev->dev,
198 "too many reset attempts, giving up.\n");
199 }
200 }
201
202 /*
203 * Configure the LCD DMA according to the current mode specified by parameters
204 * in lcdc.fbdev and fbdev->var.
205 */
206 static void setup_lcd_dma(void)
207 {
208 static const int dma_elem_type[] = {
209 0,
210 OMAP_DMA_DATA_TYPE_S8,
211 OMAP_DMA_DATA_TYPE_S16,
212 0,
213 OMAP_DMA_DATA_TYPE_S32,
214 };
215 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
216 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
217 unsigned long src;
218 int esize, xelem, yelem;
219
220 src = lcdc.vram_phys + lcdc.frame_offset;
221
222 switch (var->rotate) {
223 case 0:
224 if (plane->info.mirror || (src & 3) ||
225 lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
226 (lcdc.xres & 1))
227 esize = 2;
228 else
229 esize = 4;
230 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
231 yelem = lcdc.yres;
232 break;
233 case 90:
234 case 180:
235 case 270:
236 if (cpu_is_omap15xx()) {
237 BUG();
238 }
239 esize = 2;
240 xelem = lcdc.yres * lcdc.bpp / 16;
241 yelem = lcdc.xres;
242 break;
243 default:
244 BUG();
245 return;
246 }
247 #ifdef VERBOSE
248 dev_dbg(lcdc.fbdev->dev,
249 "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
250 src, esize, xelem, yelem);
251 #endif
252 omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
253 if (!cpu_is_omap15xx()) {
254 int bpp = lcdc.bpp;
255
256 /*
257 * YUV support is only for external mode when we have the
258 * YUV window embedded in a 16bpp frame buffer.
259 */
260 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
261 bpp = 16;
262 /* Set virtual xres elem size */
263 omap_set_lcd_dma_b1_vxres(
264 lcdc.screen_width * bpp / 8 / esize);
265 /* Setup transformations */
266 omap_set_lcd_dma_b1_rotation(var->rotate);
267 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
268 }
269 omap_setup_lcd_dma();
270 }
271
272 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
273 {
274 u32 status;
275
276 status = omap_readl(OMAP_LCDC_STATUS);
277
278 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
279 reset_controller(status);
280 else {
281 if (status & OMAP_LCDC_STAT_DONE) {
282 u32 l;
283
284 /*
285 * Disable IRQ_DONE. The status bit will be cleared
286 * only when the controller is reenabled and we don't
287 * want to get more interrupts.
288 */
289 l = omap_readl(OMAP_LCDC_CONTROL);
290 l &= ~OMAP_LCDC_IRQ_DONE;
291 omap_writel(l, OMAP_LCDC_CONTROL);
292 complete(&lcdc.last_frame_complete);
293 }
294 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
295 disable_controller_async();
296 complete(&lcdc.palette_load_complete);
297 }
298 }
299
300 /*
301 * Clear these interrupt status bits.
302 * Sync_lost, FUF bits were cleared by disabling the LCD controller
303 * LOADED_PALETTE can be cleared this way only in palette only
304 * load mode. In other load modes it's cleared by disabling the
305 * controller.
306 */
307 status &= ~(OMAP_LCDC_STAT_VSYNC |
308 OMAP_LCDC_STAT_LOADED_PALETTE |
309 OMAP_LCDC_STAT_ABC |
310 OMAP_LCDC_STAT_LINE_INT);
311 omap_writel(status, OMAP_LCDC_STATUS);
312 return IRQ_HANDLED;
313 }
314
315 /*
316 * Change to a new video mode. We defer this to a later time to avoid any
317 * flicker and not to mess up the current LCD DMA context. For this we disable
318 * the LCD controller, which will generate a DONE irq after the last frame has
319 * been transferred. Then it'll be safe to reconfigure both the LCD controller
320 * as well as the LCD DMA.
321 */
322 static int omap_lcdc_setup_plane(int plane, int channel_out,
323 unsigned long offset, int screen_width,
324 int pos_x, int pos_y, int width, int height,
325 int color_mode)
326 {
327 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
328 struct lcd_panel *panel = lcdc.fbdev->panel;
329 int rot_x, rot_y;
330
331 if (var->rotate == 0) {
332 rot_x = panel->x_res;
333 rot_y = panel->y_res;
334 } else {
335 rot_x = panel->y_res;
336 rot_y = panel->x_res;
337 }
338 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
339 width > rot_x || height > rot_y) {
340 #ifdef VERBOSE
341 dev_dbg(lcdc.fbdev->dev,
342 "invalid plane params plane %d pos_x %d pos_y %d "
343 "w %d h %d\n", plane, pos_x, pos_y, width, height);
344 #endif
345 return -EINVAL;
346 }
347
348 lcdc.frame_offset = offset;
349 lcdc.xres = width;
350 lcdc.yres = height;
351 lcdc.screen_width = screen_width;
352 lcdc.color_mode = color_mode;
353
354 switch (color_mode) {
355 case OMAPFB_COLOR_CLUT_8BPP:
356 lcdc.bpp = 8;
357 lcdc.palette_code = 0x3000;
358 lcdc.palette_size = 512;
359 break;
360 case OMAPFB_COLOR_RGB565:
361 lcdc.bpp = 16;
362 lcdc.palette_code = 0x4000;
363 lcdc.palette_size = 32;
364 break;
365 case OMAPFB_COLOR_RGB444:
366 lcdc.bpp = 16;
367 lcdc.palette_code = 0x4000;
368 lcdc.palette_size = 32;
369 break;
370 case OMAPFB_COLOR_YUV420:
371 if (lcdc.ext_mode) {
372 lcdc.bpp = 12;
373 break;
374 }
375 /* fallthrough */
376 case OMAPFB_COLOR_YUV422:
377 if (lcdc.ext_mode) {
378 lcdc.bpp = 16;
379 break;
380 }
381 /* fallthrough */
382 default:
383 /* FIXME: other BPPs.
384 * bpp1: code 0, size 256
385 * bpp2: code 0x1000 size 256
386 * bpp4: code 0x2000 size 256
387 * bpp12: code 0x4000 size 32
388 */
389 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
390 BUG();
391 return -1;
392 }
393
394 if (lcdc.ext_mode) {
395 setup_lcd_dma();
396 return 0;
397 }
398
399 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
400 disable_controller();
401 omap_stop_lcd_dma();
402 setup_lcd_dma();
403 enable_controller();
404 }
405
406 return 0;
407 }
408
409 static int omap_lcdc_enable_plane(int plane, int enable)
410 {
411 dev_dbg(lcdc.fbdev->dev,
412 "plane %d enable %d update_mode %d ext_mode %d\n",
413 plane, enable, lcdc.update_mode, lcdc.ext_mode);
414 if (plane != OMAPFB_PLANE_GFX)
415 return -EINVAL;
416
417 return 0;
418 }
419
420 /*
421 * Configure the LCD DMA for a palette load operation and do the palette
422 * downloading synchronously. We don't use the frame+palette load mode of
423 * the controller, since the palette can always be downloaded seperately.
424 */
425 static void load_palette(void)
426 {
427 u16 *palette;
428
429 palette = (u16 *)lcdc.palette_virt;
430
431 *(u16 *)palette &= 0x0fff;
432 *(u16 *)palette |= lcdc.palette_code;
433
434 omap_set_lcd_dma_b1(lcdc.palette_phys,
435 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
436
437 omap_set_lcd_dma_single_transfer(1);
438 omap_setup_lcd_dma();
439
440 init_completion(&lcdc.palette_load_complete);
441 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
442 set_load_mode(OMAP_LCDC_LOAD_PALETTE);
443 enable_controller();
444 if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
445 msecs_to_jiffies(500)))
446 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
447 /* The controller gets disabled in the irq handler */
448 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
449 omap_stop_lcd_dma();
450
451 omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
452 }
453
454 /* Used only in internal controller mode */
455 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
456 u16 transp, int update_hw_pal)
457 {
458 u16 *palette;
459
460 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
461 return -EINVAL;
462
463 palette = (u16 *)lcdc.palette_virt;
464
465 palette[regno] &= ~0x0fff;
466 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
467 (blue >> 12);
468
469 if (update_hw_pal) {
470 disable_controller();
471 omap_stop_lcd_dma();
472 load_palette();
473 setup_lcd_dma();
474 set_load_mode(OMAP_LCDC_LOAD_FRAME);
475 enable_controller();
476 }
477
478 return 0;
479 }
480
481 static void calc_ck_div(int is_tft, int pck, int *pck_div)
482 {
483 unsigned long lck;
484
485 pck = max(1, pck);
486 lck = clk_get_rate(lcdc.lcd_ck);
487 *pck_div = (lck + pck - 1) / pck;
488 if (is_tft)
489 *pck_div = max(2, *pck_div);
490 else
491 *pck_div = max(3, *pck_div);
492 if (*pck_div > 255) {
493 /* FIXME: try to adjust logic clock divider as well */
494 *pck_div = 255;
495 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
496 pck / 1000);
497 }
498 }
499
500 static void inline setup_regs(void)
501 {
502 u32 l;
503 struct lcd_panel *panel = lcdc.fbdev->panel;
504 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
505 unsigned long lck;
506 int pcd;
507
508 l = omap_readl(OMAP_LCDC_CONTROL);
509 l &= ~OMAP_LCDC_CTRL_LCD_TFT;
510 l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
511 #ifdef CONFIG_MACH_OMAP_PALMTE
512 /* FIXME:if (machine_is_omap_palmte()) { */
513 /* PalmTE uses alternate TFT setting in 8BPP mode */
514 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
515 /* } */
516 #endif
517 omap_writel(l, OMAP_LCDC_CONTROL);
518
519 l = omap_readl(OMAP_LCDC_TIMING2);
520 l &= ~(((1 << 6) - 1) << 20);
521 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
522 omap_writel(l, OMAP_LCDC_TIMING2);
523
524 l = panel->x_res - 1;
525 l |= (panel->hsw - 1) << 10;
526 l |= (panel->hfp - 1) << 16;
527 l |= (panel->hbp - 1) << 24;
528 omap_writel(l, OMAP_LCDC_TIMING0);
529
530 l = panel->y_res - 1;
531 l |= (panel->vsw - 1) << 10;
532 l |= panel->vfp << 16;
533 l |= panel->vbp << 24;
534 omap_writel(l, OMAP_LCDC_TIMING1);
535
536 l = omap_readl(OMAP_LCDC_TIMING2);
537 l &= ~0xff;
538
539 lck = clk_get_rate(lcdc.lcd_ck);
540
541 if (!panel->pcd)
542 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
543 else {
544 dev_warn(lcdc.fbdev->dev,
545 "Pixel clock divider value is obsolete.\n"
546 "Try to set pixel_clock to %lu and pcd to 0 "
547 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
548 lck / panel->pcd / 1000, panel->name);
549
550 pcd = panel->pcd;
551 }
552 l |= pcd & 0xff;
553 l |= panel->acb << 8;
554 omap_writel(l, OMAP_LCDC_TIMING2);
555
556 /* update panel info with the exact clock */
557 panel->pixel_clock = lck / pcd / 1000;
558 }
559
560 /*
561 * Configure the LCD controller, download the color palette and start a looped
562 * DMA transfer of the frame image data. Called only in internal
563 * controller mode.
564 */
565 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
566 {
567 int r = 0;
568
569 if (mode != lcdc.update_mode) {
570 switch (mode) {
571 case OMAPFB_AUTO_UPDATE:
572 setup_regs();
573 load_palette();
574
575 /* Setup and start LCD DMA */
576 setup_lcd_dma();
577
578 set_load_mode(OMAP_LCDC_LOAD_FRAME);
579 enable_irqs(OMAP_LCDC_IRQ_DONE);
580 /* This will start the actual DMA transfer */
581 enable_controller();
582 lcdc.update_mode = mode;
583 break;
584 case OMAPFB_UPDATE_DISABLED:
585 disable_controller();
586 omap_stop_lcd_dma();
587 lcdc.update_mode = mode;
588 break;
589 default:
590 r = -EINVAL;
591 }
592 }
593
594 return r;
595 }
596
597 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
598 {
599 return lcdc.update_mode;
600 }
601
602 /* PM code called only in internal controller mode */
603 static void omap_lcdc_suspend(void)
604 {
605 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
606 disable_controller();
607 omap_stop_lcd_dma();
608 }
609 }
610
611 static void omap_lcdc_resume(void)
612 {
613 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
614 setup_regs();
615 load_palette();
616 setup_lcd_dma();
617 set_load_mode(OMAP_LCDC_LOAD_FRAME);
618 enable_irqs(OMAP_LCDC_IRQ_DONE);
619 enable_controller();
620 }
621 }
622
623 static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
624 {
625 return;
626 }
627
628 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
629 {
630 BUG_ON(callback == NULL);
631
632 if (lcdc.dma_callback)
633 return -EBUSY;
634 else {
635 lcdc.dma_callback = callback;
636 lcdc.dma_callback_data = data;
637 }
638 return 0;
639 }
640 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
641
642 void omap_lcdc_free_dma_callback(void)
643 {
644 lcdc.dma_callback = NULL;
645 }
646 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
647
648 static void lcdc_dma_handler(u16 status, void *data)
649 {
650 if (lcdc.dma_callback)
651 lcdc.dma_callback(lcdc.dma_callback_data);
652 }
653
654 static int mmap_kern(void)
655 {
656 struct vm_struct *kvma;
657 struct vm_area_struct vma;
658 pgprot_t pgprot;
659 unsigned long vaddr;
660
661 kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
662 if (kvma == NULL) {
663 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
664 return -ENOMEM;
665 }
666 vma.vm_mm = &init_mm;
667
668 vaddr = (unsigned long)kvma->addr;
669 vma.vm_start = vaddr;
670 vma.vm_end = vaddr + lcdc.vram_size;
671
672 pgprot = pgprot_writecombine(pgprot_kernel);
673 if (io_remap_pfn_range(&vma, vaddr,
674 lcdc.vram_phys >> PAGE_SHIFT,
675 lcdc.vram_size, pgprot) < 0) {
676 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
677 return -EAGAIN;
678 }
679
680 lcdc.vram_virt = (void *)vaddr;
681
682 return 0;
683 }
684
685 static void unmap_kern(void)
686 {
687 vunmap(lcdc.vram_virt);
688 }
689
690 static int alloc_palette_ram(void)
691 {
692 lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
693 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
694 if (lcdc.palette_virt == NULL) {
695 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
696 return -ENOMEM;
697 }
698 memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
699
700 return 0;
701 }
702
703 static void free_palette_ram(void)
704 {
705 dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
706 lcdc.palette_virt, lcdc.palette_phys);
707 }
708
709 static int alloc_fbmem(struct omapfb_mem_region *region)
710 {
711 int bpp;
712 int frame_size;
713 struct lcd_panel *panel = lcdc.fbdev->panel;
714
715 bpp = panel->bpp;
716 if (bpp == 12)
717 bpp = 16;
718 frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
719 if (region->size > frame_size)
720 frame_size = region->size;
721 lcdc.vram_size = frame_size;
722 lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
723 lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
724 if (lcdc.vram_virt == NULL) {
725 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
726 return -ENOMEM;
727 }
728 region->size = frame_size;
729 region->paddr = lcdc.vram_phys;
730 region->vaddr = lcdc.vram_virt;
731 region->alloc = 1;
732
733 memset(lcdc.vram_virt, 0, lcdc.vram_size);
734
735 return 0;
736 }
737
738 static void free_fbmem(void)
739 {
740 dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
741 lcdc.vram_virt, lcdc.vram_phys);
742 }
743
744 static int setup_fbmem(struct omapfb_mem_desc *req_md)
745 {
746 int r;
747
748 if (!req_md->region_cnt) {
749 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
750 return -EINVAL;
751 }
752
753 if (req_md->region_cnt > 1) {
754 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
755 req_md->region_cnt = 1;
756 }
757
758 if (req_md->region[0].paddr == 0) {
759 lcdc.fbmem_allocated = 1;
760 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
761 return r;
762 return 0;
763 }
764
765 lcdc.vram_phys = req_md->region[0].paddr;
766 lcdc.vram_size = req_md->region[0].size;
767
768 if ((r = mmap_kern()) < 0)
769 return r;
770
771 dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
772 lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
773
774 return 0;
775 }
776
777 static void cleanup_fbmem(void)
778 {
779 if (lcdc.fbmem_allocated)
780 free_fbmem();
781 else
782 unmap_kern();
783 }
784
785 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
786 struct omapfb_mem_desc *req_vram)
787 {
788 int r;
789 u32 l;
790 int rate;
791 struct clk *tc_ck;
792
793 lcdc.irq_mask = 0;
794
795 lcdc.fbdev = fbdev;
796 lcdc.ext_mode = ext_mode;
797
798 l = 0;
799 omap_writel(l, OMAP_LCDC_CONTROL);
800
801 /* FIXME:
802 * According to errata some platforms have a clock rate limitiation
803 */
804 lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
805 if (IS_ERR(lcdc.lcd_ck)) {
806 dev_err(fbdev->dev, "unable to access LCD clock\n");
807 r = PTR_ERR(lcdc.lcd_ck);
808 goto fail0;
809 }
810
811 tc_ck = clk_get(fbdev->dev, "tc_ck");
812 if (IS_ERR(tc_ck)) {
813 dev_err(fbdev->dev, "unable to access TC clock\n");
814 r = PTR_ERR(tc_ck);
815 goto fail1;
816 }
817
818 rate = clk_get_rate(tc_ck);
819 clk_put(tc_ck);
820
821 if (machine_is_ams_delta())
822 rate /= 4;
823 if (machine_is_omap_h3())
824 rate /= 3;
825 r = clk_set_rate(lcdc.lcd_ck, rate);
826 if (r) {
827 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
828 goto fail1;
829 }
830 clk_enable(lcdc.lcd_ck);
831
832 r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
833 if (r) {
834 dev_err(fbdev->dev, "unable to get IRQ\n");
835 goto fail2;
836 }
837
838 r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
839 if (r) {
840 dev_err(fbdev->dev, "unable to get LCD DMA\n");
841 goto fail3;
842 }
843
844 omap_set_lcd_dma_single_transfer(ext_mode);
845 omap_set_lcd_dma_ext_controller(ext_mode);
846
847 if (!ext_mode)
848 if ((r = alloc_palette_ram()) < 0)
849 goto fail4;
850
851 if ((r = setup_fbmem(req_vram)) < 0)
852 goto fail5;
853
854 pr_info("omapfb: LCDC initialized\n");
855
856 return 0;
857 fail5:
858 if (!ext_mode)
859 free_palette_ram();
860 fail4:
861 omap_free_lcd_dma();
862 fail3:
863 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
864 fail2:
865 clk_disable(lcdc.lcd_ck);
866 fail1:
867 clk_put(lcdc.lcd_ck);
868 fail0:
869 return r;
870 }
871
872 static void omap_lcdc_cleanup(void)
873 {
874 if (!lcdc.ext_mode)
875 free_palette_ram();
876 cleanup_fbmem();
877 omap_free_lcd_dma();
878 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
879 clk_disable(lcdc.lcd_ck);
880 clk_put(lcdc.lcd_ck);
881 }
882
883 const struct lcd_ctrl omap1_int_ctrl = {
884 .name = "internal",
885 .init = omap_lcdc_init,
886 .cleanup = omap_lcdc_cleanup,
887 .get_caps = omap_lcdc_get_caps,
888 .set_update_mode = omap_lcdc_set_update_mode,
889 .get_update_mode = omap_lcdc_get_update_mode,
890 .update_window = NULL,
891 .suspend = omap_lcdc_suspend,
892 .resume = omap_lcdc_resume,
893 .setup_plane = omap_lcdc_setup_plane,
894 .enable_plane = omap_lcdc_enable_plane,
895 .setcolreg = omap_lcdc_setcolreg,
896 };
Linux kernel - Deliverables
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