OMAP: DSS2: Add Kconfig option for DPI display type
[deliverable/linux.git] / drivers / video / omap2 / dss / core.c
1 /*
2 * linux/drivers/video/omap2/dss/core.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "CORE"
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/clk.h>
28 #include <linux/err.h>
29 #include <linux/platform_device.h>
30 #include <linux/seq_file.h>
31 #include <linux/debugfs.h>
32 #include <linux/io.h>
33 #include <linux/device.h>
34 #include <linux/regulator/consumer.h>
35
36 #include <plat/display.h>
37 #include <plat/clock.h>
38
39 #include "dss.h"
40
41 static struct {
42 struct platform_device *pdev;
43 int ctx_id;
44
45 struct clk *dss_ick;
46 struct clk *dss1_fck;
47 struct clk *dss2_fck;
48 struct clk *dss_54m_fck;
49 struct clk *dss_96m_fck;
50 unsigned num_clks_enabled;
51
52 struct regulator *vdds_dsi_reg;
53 struct regulator *vdds_sdi_reg;
54 struct regulator *vdda_dac_reg;
55 } core;
56
57 static void dss_clk_enable_all_no_ctx(void);
58 static void dss_clk_disable_all_no_ctx(void);
59 static void dss_clk_enable_no_ctx(enum dss_clock clks);
60 static void dss_clk_disable_no_ctx(enum dss_clock clks);
61
62 static char *def_disp_name;
63 module_param_named(def_disp, def_disp_name, charp, 0);
64 MODULE_PARM_DESC(def_disp_name, "default display name");
65
66 #ifdef DEBUG
67 unsigned int dss_debug;
68 module_param_named(debug, dss_debug, bool, 0644);
69 #endif
70
71 /* CONTEXT */
72 static int dss_get_ctx_id(void)
73 {
74 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
75 int r;
76
77 if (!pdata->get_last_off_on_transaction_id)
78 return 0;
79 r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
80 if (r < 0) {
81 dev_err(&core.pdev->dev, "getting transaction ID failed, "
82 "will force context restore\n");
83 r = -1;
84 }
85 return r;
86 }
87
88 int dss_need_ctx_restore(void)
89 {
90 int id = dss_get_ctx_id();
91
92 if (id < 0 || id != core.ctx_id) {
93 DSSDBG("ctx id %d -> id %d\n",
94 core.ctx_id, id);
95 core.ctx_id = id;
96 return 1;
97 } else {
98 return 0;
99 }
100 }
101
102 static void save_all_ctx(void)
103 {
104 DSSDBG("save context\n");
105
106 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
107
108 dss_save_context();
109 dispc_save_context();
110 #ifdef CONFIG_OMAP2_DSS_DSI
111 dsi_save_context();
112 #endif
113
114 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
115 }
116
117 static void restore_all_ctx(void)
118 {
119 DSSDBG("restore context\n");
120
121 dss_clk_enable_all_no_ctx();
122
123 dss_restore_context();
124 dispc_restore_context();
125 #ifdef CONFIG_OMAP2_DSS_DSI
126 dsi_restore_context();
127 #endif
128
129 dss_clk_disable_all_no_ctx();
130 }
131
132 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
133 /* CLOCKS */
134 static void core_dump_clocks(struct seq_file *s)
135 {
136 int i;
137 struct clk *clocks[5] = {
138 core.dss_ick,
139 core.dss1_fck,
140 core.dss2_fck,
141 core.dss_54m_fck,
142 core.dss_96m_fck
143 };
144
145 seq_printf(s, "- CORE -\n");
146
147 seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
148
149 for (i = 0; i < 5; i++) {
150 if (!clocks[i])
151 continue;
152 seq_printf(s, "%-15s\t%lu\t%d\n",
153 clocks[i]->name,
154 clk_get_rate(clocks[i]),
155 clocks[i]->usecount);
156 }
157 }
158 #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
159
160 static int dss_get_clock(struct clk **clock, const char *clk_name)
161 {
162 struct clk *clk;
163
164 clk = clk_get(&core.pdev->dev, clk_name);
165
166 if (IS_ERR(clk)) {
167 DSSERR("can't get clock %s", clk_name);
168 return PTR_ERR(clk);
169 }
170
171 *clock = clk;
172
173 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
174
175 return 0;
176 }
177
178 static int dss_get_clocks(void)
179 {
180 int r;
181
182 core.dss_ick = NULL;
183 core.dss1_fck = NULL;
184 core.dss2_fck = NULL;
185 core.dss_54m_fck = NULL;
186 core.dss_96m_fck = NULL;
187
188 r = dss_get_clock(&core.dss_ick, "ick");
189 if (r)
190 goto err;
191
192 r = dss_get_clock(&core.dss1_fck, "dss1_fck");
193 if (r)
194 goto err;
195
196 r = dss_get_clock(&core.dss2_fck, "dss2_fck");
197 if (r)
198 goto err;
199
200 r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
201 if (r)
202 goto err;
203
204 r = dss_get_clock(&core.dss_96m_fck, "video_fck");
205 if (r)
206 goto err;
207
208 return 0;
209
210 err:
211 if (core.dss_ick)
212 clk_put(core.dss_ick);
213 if (core.dss1_fck)
214 clk_put(core.dss1_fck);
215 if (core.dss2_fck)
216 clk_put(core.dss2_fck);
217 if (core.dss_54m_fck)
218 clk_put(core.dss_54m_fck);
219 if (core.dss_96m_fck)
220 clk_put(core.dss_96m_fck);
221
222 return r;
223 }
224
225 static void dss_put_clocks(void)
226 {
227 if (core.dss_96m_fck)
228 clk_put(core.dss_96m_fck);
229 clk_put(core.dss_54m_fck);
230 clk_put(core.dss1_fck);
231 clk_put(core.dss2_fck);
232 clk_put(core.dss_ick);
233 }
234
235 unsigned long dss_clk_get_rate(enum dss_clock clk)
236 {
237 switch (clk) {
238 case DSS_CLK_ICK:
239 return clk_get_rate(core.dss_ick);
240 case DSS_CLK_FCK1:
241 return clk_get_rate(core.dss1_fck);
242 case DSS_CLK_FCK2:
243 return clk_get_rate(core.dss2_fck);
244 case DSS_CLK_54M:
245 return clk_get_rate(core.dss_54m_fck);
246 case DSS_CLK_96M:
247 return clk_get_rate(core.dss_96m_fck);
248 }
249
250 BUG();
251 return 0;
252 }
253
254 static unsigned count_clk_bits(enum dss_clock clks)
255 {
256 unsigned num_clks = 0;
257
258 if (clks & DSS_CLK_ICK)
259 ++num_clks;
260 if (clks & DSS_CLK_FCK1)
261 ++num_clks;
262 if (clks & DSS_CLK_FCK2)
263 ++num_clks;
264 if (clks & DSS_CLK_54M)
265 ++num_clks;
266 if (clks & DSS_CLK_96M)
267 ++num_clks;
268
269 return num_clks;
270 }
271
272 static void dss_clk_enable_no_ctx(enum dss_clock clks)
273 {
274 unsigned num_clks = count_clk_bits(clks);
275
276 if (clks & DSS_CLK_ICK)
277 clk_enable(core.dss_ick);
278 if (clks & DSS_CLK_FCK1)
279 clk_enable(core.dss1_fck);
280 if (clks & DSS_CLK_FCK2)
281 clk_enable(core.dss2_fck);
282 if (clks & DSS_CLK_54M)
283 clk_enable(core.dss_54m_fck);
284 if (clks & DSS_CLK_96M)
285 clk_enable(core.dss_96m_fck);
286
287 core.num_clks_enabled += num_clks;
288 }
289
290 void dss_clk_enable(enum dss_clock clks)
291 {
292 bool check_ctx = core.num_clks_enabled == 0;
293
294 dss_clk_enable_no_ctx(clks);
295
296 if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
297 restore_all_ctx();
298 }
299
300 static void dss_clk_disable_no_ctx(enum dss_clock clks)
301 {
302 unsigned num_clks = count_clk_bits(clks);
303
304 if (clks & DSS_CLK_ICK)
305 clk_disable(core.dss_ick);
306 if (clks & DSS_CLK_FCK1)
307 clk_disable(core.dss1_fck);
308 if (clks & DSS_CLK_FCK2)
309 clk_disable(core.dss2_fck);
310 if (clks & DSS_CLK_54M)
311 clk_disable(core.dss_54m_fck);
312 if (clks & DSS_CLK_96M)
313 clk_disable(core.dss_96m_fck);
314
315 core.num_clks_enabled -= num_clks;
316 }
317
318 void dss_clk_disable(enum dss_clock clks)
319 {
320 if (cpu_is_omap34xx()) {
321 unsigned num_clks = count_clk_bits(clks);
322
323 BUG_ON(core.num_clks_enabled < num_clks);
324
325 if (core.num_clks_enabled == num_clks)
326 save_all_ctx();
327 }
328
329 dss_clk_disable_no_ctx(clks);
330 }
331
332 static void dss_clk_enable_all_no_ctx(void)
333 {
334 enum dss_clock clks;
335
336 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
337 if (cpu_is_omap34xx())
338 clks |= DSS_CLK_96M;
339 dss_clk_enable_no_ctx(clks);
340 }
341
342 static void dss_clk_disable_all_no_ctx(void)
343 {
344 enum dss_clock clks;
345
346 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
347 if (cpu_is_omap34xx())
348 clks |= DSS_CLK_96M;
349 dss_clk_disable_no_ctx(clks);
350 }
351
352 static void dss_clk_disable_all(void)
353 {
354 enum dss_clock clks;
355
356 clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
357 if (cpu_is_omap34xx())
358 clks |= DSS_CLK_96M;
359 dss_clk_disable(clks);
360 }
361
362 /* REGULATORS */
363
364 struct regulator *dss_get_vdds_dsi(void)
365 {
366 struct regulator *reg;
367
368 if (core.vdds_dsi_reg != NULL)
369 return core.vdds_dsi_reg;
370
371 reg = regulator_get(&core.pdev->dev, "vdds_dsi");
372 if (!IS_ERR(reg))
373 core.vdds_dsi_reg = reg;
374
375 return reg;
376 }
377
378 struct regulator *dss_get_vdds_sdi(void)
379 {
380 struct regulator *reg;
381
382 if (core.vdds_sdi_reg != NULL)
383 return core.vdds_sdi_reg;
384
385 reg = regulator_get(&core.pdev->dev, "vdds_sdi");
386 if (!IS_ERR(reg))
387 core.vdds_sdi_reg = reg;
388
389 return reg;
390 }
391
392 struct regulator *dss_get_vdda_dac(void)
393 {
394 struct regulator *reg;
395
396 if (core.vdda_dac_reg != NULL)
397 return core.vdda_dac_reg;
398
399 reg = regulator_get(&core.pdev->dev, "vdda_dac");
400 if (!IS_ERR(reg))
401 core.vdda_dac_reg = reg;
402
403 return reg;
404 }
405
406 /* DEBUGFS */
407 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
408 static void dss_debug_dump_clocks(struct seq_file *s)
409 {
410 core_dump_clocks(s);
411 dss_dump_clocks(s);
412 dispc_dump_clocks(s);
413 #ifdef CONFIG_OMAP2_DSS_DSI
414 dsi_dump_clocks(s);
415 #endif
416 }
417
418 static int dss_debug_show(struct seq_file *s, void *unused)
419 {
420 void (*func)(struct seq_file *) = s->private;
421 func(s);
422 return 0;
423 }
424
425 static int dss_debug_open(struct inode *inode, struct file *file)
426 {
427 return single_open(file, dss_debug_show, inode->i_private);
428 }
429
430 static const struct file_operations dss_debug_fops = {
431 .open = dss_debug_open,
432 .read = seq_read,
433 .llseek = seq_lseek,
434 .release = single_release,
435 };
436
437 static struct dentry *dss_debugfs_dir;
438
439 static int dss_initialize_debugfs(void)
440 {
441 dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
442 if (IS_ERR(dss_debugfs_dir)) {
443 int err = PTR_ERR(dss_debugfs_dir);
444 dss_debugfs_dir = NULL;
445 return err;
446 }
447
448 debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
449 &dss_debug_dump_clocks, &dss_debug_fops);
450
451 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
452 debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
453 &dispc_dump_irqs, &dss_debug_fops);
454 #endif
455
456 #if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS)
457 debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
458 &dsi_dump_irqs, &dss_debug_fops);
459 #endif
460
461 debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
462 &dss_dump_regs, &dss_debug_fops);
463 debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
464 &dispc_dump_regs, &dss_debug_fops);
465 #ifdef CONFIG_OMAP2_DSS_RFBI
466 debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
467 &rfbi_dump_regs, &dss_debug_fops);
468 #endif
469 #ifdef CONFIG_OMAP2_DSS_DSI
470 debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
471 &dsi_dump_regs, &dss_debug_fops);
472 #endif
473 #ifdef CONFIG_OMAP2_DSS_VENC
474 debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
475 &venc_dump_regs, &dss_debug_fops);
476 #endif
477 return 0;
478 }
479
480 static void dss_uninitialize_debugfs(void)
481 {
482 if (dss_debugfs_dir)
483 debugfs_remove_recursive(dss_debugfs_dir);
484 }
485 #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
486
487 /* PLATFORM DEVICE */
488 static int omap_dss_probe(struct platform_device *pdev)
489 {
490 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
491 int skip_init = 0;
492 int r;
493 int i;
494
495 core.pdev = pdev;
496
497 dss_init_overlay_managers(pdev);
498 dss_init_overlays(pdev);
499
500 r = dss_get_clocks();
501 if (r)
502 goto fail0;
503
504 dss_clk_enable_all_no_ctx();
505
506 core.ctx_id = dss_get_ctx_id();
507 DSSDBG("initial ctx id %u\n", core.ctx_id);
508
509 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
510 /* DISPC_CONTROL */
511 if (omap_readl(0x48050440) & 1) /* LCD enabled? */
512 skip_init = 1;
513 #endif
514
515 r = dss_init(skip_init);
516 if (r) {
517 DSSERR("Failed to initialize DSS\n");
518 goto fail0;
519 }
520
521 #ifdef CONFIG_OMAP2_DSS_RFBI
522 r = rfbi_init();
523 if (r) {
524 DSSERR("Failed to initialize rfbi\n");
525 goto fail0;
526 }
527 #endif
528
529 #ifdef CONFIG_OMAP2_DSS_DPI
530 r = dpi_init(pdev);
531 if (r) {
532 DSSERR("Failed to initialize dpi\n");
533 goto fail0;
534 }
535 #endif
536
537 r = dispc_init();
538 if (r) {
539 DSSERR("Failed to initialize dispc\n");
540 goto fail0;
541 }
542 #ifdef CONFIG_OMAP2_DSS_VENC
543 r = venc_init(pdev);
544 if (r) {
545 DSSERR("Failed to initialize venc\n");
546 goto fail0;
547 }
548 #endif
549 if (cpu_is_omap34xx()) {
550 #ifdef CONFIG_OMAP2_DSS_SDI
551 r = sdi_init(skip_init);
552 if (r) {
553 DSSERR("Failed to initialize SDI\n");
554 goto fail0;
555 }
556 #endif
557 #ifdef CONFIG_OMAP2_DSS_DSI
558 r = dsi_init(pdev);
559 if (r) {
560 DSSERR("Failed to initialize DSI\n");
561 goto fail0;
562 }
563 #endif
564 }
565
566 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
567 r = dss_initialize_debugfs();
568 if (r)
569 goto fail0;
570 #endif
571
572 for (i = 0; i < pdata->num_devices; ++i) {
573 struct omap_dss_device *dssdev = pdata->devices[i];
574
575 r = omap_dss_register_device(dssdev);
576 if (r)
577 DSSERR("device reg failed %d\n", i);
578
579 if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
580 pdata->default_device = dssdev;
581 }
582
583 dss_clk_disable_all();
584
585 return 0;
586
587 /* XXX fail correctly */
588 fail0:
589 return r;
590 }
591
592 static int omap_dss_remove(struct platform_device *pdev)
593 {
594 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
595 int i;
596 int c;
597
598 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
599 dss_uninitialize_debugfs();
600 #endif
601
602 #ifdef CONFIG_OMAP2_DSS_VENC
603 venc_exit();
604 #endif
605 dispc_exit();
606 #ifdef CONFIG_OMAP2_DSS_DPI
607 dpi_exit();
608 #endif
609 #ifdef CONFIG_OMAP2_DSS_RFBI
610 rfbi_exit();
611 #endif
612 if (cpu_is_omap34xx()) {
613 #ifdef CONFIG_OMAP2_DSS_DSI
614 dsi_exit();
615 #endif
616 #ifdef CONFIG_OMAP2_DSS_SDI
617 sdi_exit();
618 #endif
619 }
620
621 dss_exit();
622
623 /* these should be removed at some point */
624 c = core.dss_ick->usecount;
625 if (c > 0) {
626 DSSERR("warning: dss_ick usecount %d, disabling\n", c);
627 while (c-- > 0)
628 clk_disable(core.dss_ick);
629 }
630
631 c = core.dss1_fck->usecount;
632 if (c > 0) {
633 DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
634 while (c-- > 0)
635 clk_disable(core.dss1_fck);
636 }
637
638 c = core.dss2_fck->usecount;
639 if (c > 0) {
640 DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
641 while (c-- > 0)
642 clk_disable(core.dss2_fck);
643 }
644
645 c = core.dss_54m_fck->usecount;
646 if (c > 0) {
647 DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
648 while (c-- > 0)
649 clk_disable(core.dss_54m_fck);
650 }
651
652 if (core.dss_96m_fck) {
653 c = core.dss_96m_fck->usecount;
654 if (c > 0) {
655 DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
656 c);
657 while (c-- > 0)
658 clk_disable(core.dss_96m_fck);
659 }
660 }
661
662 dss_put_clocks();
663
664 dss_uninit_overlays(pdev);
665 dss_uninit_overlay_managers(pdev);
666
667 for (i = 0; i < pdata->num_devices; ++i)
668 omap_dss_unregister_device(pdata->devices[i]);
669
670 return 0;
671 }
672
673 static void omap_dss_shutdown(struct platform_device *pdev)
674 {
675 DSSDBG("shutdown\n");
676 dss_disable_all_devices();
677 }
678
679 static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
680 {
681 DSSDBG("suspend %d\n", state.event);
682
683 return dss_suspend_all_devices();
684 }
685
686 static int omap_dss_resume(struct platform_device *pdev)
687 {
688 DSSDBG("resume\n");
689
690 return dss_resume_all_devices();
691 }
692
693 static struct platform_driver omap_dss_driver = {
694 .probe = omap_dss_probe,
695 .remove = omap_dss_remove,
696 .shutdown = omap_dss_shutdown,
697 .suspend = omap_dss_suspend,
698 .resume = omap_dss_resume,
699 .driver = {
700 .name = "omapdss",
701 .owner = THIS_MODULE,
702 },
703 };
704
705 /* BUS */
706 static int dss_bus_match(struct device *dev, struct device_driver *driver)
707 {
708 struct omap_dss_device *dssdev = to_dss_device(dev);
709
710 DSSDBG("bus_match. dev %s/%s, drv %s\n",
711 dev_name(dev), dssdev->driver_name, driver->name);
712
713 return strcmp(dssdev->driver_name, driver->name) == 0;
714 }
715
716 static ssize_t device_name_show(struct device *dev,
717 struct device_attribute *attr, char *buf)
718 {
719 struct omap_dss_device *dssdev = to_dss_device(dev);
720 return snprintf(buf, PAGE_SIZE, "%s\n",
721 dssdev->name ?
722 dssdev->name : "");
723 }
724
725 static struct device_attribute default_dev_attrs[] = {
726 __ATTR(name, S_IRUGO, device_name_show, NULL),
727 __ATTR_NULL,
728 };
729
730 static ssize_t driver_name_show(struct device_driver *drv, char *buf)
731 {
732 struct omap_dss_driver *dssdrv = to_dss_driver(drv);
733 return snprintf(buf, PAGE_SIZE, "%s\n",
734 dssdrv->driver.name ?
735 dssdrv->driver.name : "");
736 }
737 static struct driver_attribute default_drv_attrs[] = {
738 __ATTR(name, S_IRUGO, driver_name_show, NULL),
739 __ATTR_NULL,
740 };
741
742 static struct bus_type dss_bus_type = {
743 .name = "omapdss",
744 .match = dss_bus_match,
745 .dev_attrs = default_dev_attrs,
746 .drv_attrs = default_drv_attrs,
747 };
748
749 static void dss_bus_release(struct device *dev)
750 {
751 DSSDBG("bus_release\n");
752 }
753
754 static struct device dss_bus = {
755 .release = dss_bus_release,
756 };
757
758 struct bus_type *dss_get_bus(void)
759 {
760 return &dss_bus_type;
761 }
762
763 /* DRIVER */
764 static int dss_driver_probe(struct device *dev)
765 {
766 int r;
767 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
768 struct omap_dss_device *dssdev = to_dss_device(dev);
769 struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
770 bool force;
771
772 DSSDBG("driver_probe: dev %s/%s, drv %s\n",
773 dev_name(dev), dssdev->driver_name,
774 dssdrv->driver.name);
775
776 dss_init_device(core.pdev, dssdev);
777
778 force = pdata->default_device == dssdev;
779 dss_recheck_connections(dssdev, force);
780
781 r = dssdrv->probe(dssdev);
782
783 if (r) {
784 DSSERR("driver probe failed: %d\n", r);
785 dss_uninit_device(core.pdev, dssdev);
786 return r;
787 }
788
789 DSSDBG("probe done for device %s\n", dev_name(dev));
790
791 dssdev->driver = dssdrv;
792
793 return 0;
794 }
795
796 static int dss_driver_remove(struct device *dev)
797 {
798 struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
799 struct omap_dss_device *dssdev = to_dss_device(dev);
800
801 DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
802 dssdev->driver_name);
803
804 dssdrv->remove(dssdev);
805
806 dss_uninit_device(core.pdev, dssdev);
807
808 dssdev->driver = NULL;
809
810 return 0;
811 }
812
813 int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
814 {
815 dssdriver->driver.bus = &dss_bus_type;
816 dssdriver->driver.probe = dss_driver_probe;
817 dssdriver->driver.remove = dss_driver_remove;
818
819 if (dssdriver->get_resolution == NULL)
820 dssdriver->get_resolution = omapdss_default_get_resolution;
821 if (dssdriver->get_recommended_bpp == NULL)
822 dssdriver->get_recommended_bpp =
823 omapdss_default_get_recommended_bpp;
824
825 return driver_register(&dssdriver->driver);
826 }
827 EXPORT_SYMBOL(omap_dss_register_driver);
828
829 void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
830 {
831 driver_unregister(&dssdriver->driver);
832 }
833 EXPORT_SYMBOL(omap_dss_unregister_driver);
834
835 /* DEVICE */
836 static void reset_device(struct device *dev, int check)
837 {
838 u8 *dev_p = (u8 *)dev;
839 u8 *dev_end = dev_p + sizeof(*dev);
840 void *saved_pdata;
841
842 saved_pdata = dev->platform_data;
843 if (check) {
844 /*
845 * Check if there is any other setting than platform_data
846 * in struct device; warn that these will be reset by our
847 * init.
848 */
849 dev->platform_data = NULL;
850 while (dev_p < dev_end) {
851 if (*dev_p) {
852 WARN("%s: struct device fields will be "
853 "discarded\n",
854 __func__);
855 break;
856 }
857 dev_p++;
858 }
859 }
860 memset(dev, 0, sizeof(*dev));
861 dev->platform_data = saved_pdata;
862 }
863
864
865 static void omap_dss_dev_release(struct device *dev)
866 {
867 reset_device(dev, 0);
868 }
869
870 int omap_dss_register_device(struct omap_dss_device *dssdev)
871 {
872 static int dev_num;
873
874 WARN_ON(!dssdev->driver_name);
875
876 reset_device(&dssdev->dev, 1);
877 dssdev->dev.bus = &dss_bus_type;
878 dssdev->dev.parent = &dss_bus;
879 dssdev->dev.release = omap_dss_dev_release;
880 dev_set_name(&dssdev->dev, "display%d", dev_num++);
881 return device_register(&dssdev->dev);
882 }
883
884 void omap_dss_unregister_device(struct omap_dss_device *dssdev)
885 {
886 device_unregister(&dssdev->dev);
887 }
888
889 /* BUS */
890 static int omap_dss_bus_register(void)
891 {
892 int r;
893
894 r = bus_register(&dss_bus_type);
895 if (r) {
896 DSSERR("bus register failed\n");
897 return r;
898 }
899
900 dev_set_name(&dss_bus, "omapdss");
901 r = device_register(&dss_bus);
902 if (r) {
903 DSSERR("bus driver register failed\n");
904 bus_unregister(&dss_bus_type);
905 return r;
906 }
907
908 return 0;
909 }
910
911 /* INIT */
912
913 #ifdef CONFIG_OMAP2_DSS_MODULE
914 static void omap_dss_bus_unregister(void)
915 {
916 device_unregister(&dss_bus);
917
918 bus_unregister(&dss_bus_type);
919 }
920
921 static int __init omap_dss_init(void)
922 {
923 int r;
924
925 r = omap_dss_bus_register();
926 if (r)
927 return r;
928
929 r = platform_driver_register(&omap_dss_driver);
930 if (r) {
931 omap_dss_bus_unregister();
932 return r;
933 }
934
935 return 0;
936 }
937
938 static void __exit omap_dss_exit(void)
939 {
940 if (core.vdds_dsi_reg != NULL) {
941 regulator_put(core.vdds_dsi_reg);
942 core.vdds_dsi_reg = NULL;
943 }
944
945 if (core.vdds_sdi_reg != NULL) {
946 regulator_put(core.vdds_sdi_reg);
947 core.vdds_sdi_reg = NULL;
948 }
949
950 if (core.vdda_dac_reg != NULL) {
951 regulator_put(core.vdda_dac_reg);
952 core.vdda_dac_reg = NULL;
953 }
954
955 platform_driver_unregister(&omap_dss_driver);
956
957 omap_dss_bus_unregister();
958 }
959
960 module_init(omap_dss_init);
961 module_exit(omap_dss_exit);
962 #else
963 static int __init omap_dss_init(void)
964 {
965 return omap_dss_bus_register();
966 }
967
968 static int __init omap_dss_init2(void)
969 {
970 return platform_driver_register(&omap_dss_driver);
971 }
972
973 core_initcall(omap_dss_init);
974 device_initcall(omap_dss_init2);
975 #endif
976
977 MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
978 MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
979 MODULE_LICENSE("GPL v2");
980
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