OMAP: DSS2: check for manager when enabling display
[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c
1 /*
2 * linux/drivers/video/omap2/dss/dpi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DPI"
24
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
31
32 #include <video/omapdss.h>
33 #include <plat/cpu.h>
34
35 #include "dss.h"
36
37 static struct {
38 struct regulator *vdds_dsi_reg;
39 struct platform_device *dsidev;
40 } dpi;
41
42 static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
43 {
44 int dsi_module;
45
46 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
47
48 return dsi_get_dsidev_from_id(dsi_module);
49 }
50
51 static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
52 {
53 if (dssdev->clocks.dispc.dispc_fclk_src ==
54 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
55 dssdev->clocks.dispc.dispc_fclk_src ==
56 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
57 dssdev->clocks.dispc.channel.lcd_clk_src ==
58 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
59 dssdev->clocks.dispc.channel.lcd_clk_src ==
60 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
61 return true;
62 else
63 return false;
64 }
65
66 static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
67 unsigned long pck_req, unsigned long *fck, int *lck_div,
68 int *pck_div)
69 {
70 struct dsi_clock_info dsi_cinfo;
71 struct dispc_clock_info dispc_cinfo;
72 int r;
73
74 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
75 &dsi_cinfo, &dispc_cinfo);
76 if (r)
77 return r;
78
79 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
80 if (r)
81 return r;
82
83 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
84
85 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
86 if (r)
87 return r;
88
89 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
90 *lck_div = dispc_cinfo.lck_div;
91 *pck_div = dispc_cinfo.pck_div;
92
93 return 0;
94 }
95
96 static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
97 unsigned long pck_req, unsigned long *fck, int *lck_div,
98 int *pck_div)
99 {
100 struct dss_clock_info dss_cinfo;
101 struct dispc_clock_info dispc_cinfo;
102 int r;
103
104 r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
105 if (r)
106 return r;
107
108 r = dss_set_clock_div(&dss_cinfo);
109 if (r)
110 return r;
111
112 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
113 if (r)
114 return r;
115
116 *fck = dss_cinfo.fck;
117 *lck_div = dispc_cinfo.lck_div;
118 *pck_div = dispc_cinfo.pck_div;
119
120 return 0;
121 }
122
123 static int dpi_set_mode(struct omap_dss_device *dssdev)
124 {
125 struct omap_video_timings *t = &dssdev->panel.timings;
126 int lck_div = 0, pck_div = 0;
127 unsigned long fck = 0;
128 unsigned long pck;
129 bool is_tft;
130 int r = 0;
131
132 dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
133 dssdev->panel.acbi, dssdev->panel.acb);
134
135 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
136
137 if (dpi_use_dsi_pll(dssdev))
138 r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
139 &fck, &lck_div, &pck_div);
140 else
141 r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
142 &fck, &lck_div, &pck_div);
143 if (r)
144 return r;
145
146 pck = fck / lck_div / pck_div / 1000;
147
148 if (pck != t->pixel_clock) {
149 DSSWARN("Could not find exact pixel clock. "
150 "Requested %d kHz, got %lu kHz\n",
151 t->pixel_clock, pck);
152
153 t->pixel_clock = pck;
154 }
155
156 dispc_set_lcd_timings(dssdev->manager->id, t);
157
158 return 0;
159 }
160
161 static void dpi_basic_init(struct omap_dss_device *dssdev)
162 {
163 bool is_tft;
164
165 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
166
167 dispc_set_parallel_interface_mode(dssdev->manager->id,
168 OMAP_DSS_PARALLELMODE_BYPASS);
169 dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
170 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
171 dispc_set_tft_data_lines(dssdev->manager->id,
172 dssdev->phy.dpi.data_lines);
173 }
174
175 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
176 {
177 int r;
178
179 if (dssdev->manager == NULL) {
180 DSSERR("failed to enable display: no manager\n");
181 return -ENODEV;
182 }
183
184 r = omap_dss_start_device(dssdev);
185 if (r) {
186 DSSERR("failed to start device\n");
187 goto err_start_dev;
188 }
189
190 if (cpu_is_omap34xx()) {
191 r = regulator_enable(dpi.vdds_dsi_reg);
192 if (r)
193 goto err_reg_enable;
194 }
195
196 r = dss_runtime_get();
197 if (r)
198 goto err_get_dss;
199
200 r = dispc_runtime_get();
201 if (r)
202 goto err_get_dispc;
203
204 dpi_basic_init(dssdev);
205
206 if (dpi_use_dsi_pll(dssdev)) {
207 r = dsi_runtime_get(dpi.dsidev);
208 if (r)
209 goto err_get_dsi;
210
211 r = dsi_pll_init(dpi.dsidev, 0, 1);
212 if (r)
213 goto err_dsi_pll_init;
214 }
215
216 r = dpi_set_mode(dssdev);
217 if (r)
218 goto err_set_mode;
219
220 mdelay(2);
221
222 dssdev->manager->enable(dssdev->manager);
223
224 return 0;
225
226 err_set_mode:
227 if (dpi_use_dsi_pll(dssdev))
228 dsi_pll_uninit(dpi.dsidev, true);
229 err_dsi_pll_init:
230 if (dpi_use_dsi_pll(dssdev))
231 dsi_runtime_put(dpi.dsidev);
232 err_get_dsi:
233 dispc_runtime_put();
234 err_get_dispc:
235 dss_runtime_put();
236 err_get_dss:
237 if (cpu_is_omap34xx())
238 regulator_disable(dpi.vdds_dsi_reg);
239 err_reg_enable:
240 omap_dss_stop_device(dssdev);
241 err_start_dev:
242 return r;
243 }
244 EXPORT_SYMBOL(omapdss_dpi_display_enable);
245
246 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
247 {
248 dssdev->manager->disable(dssdev->manager);
249
250 if (dpi_use_dsi_pll(dssdev)) {
251 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
252 dsi_pll_uninit(dpi.dsidev, true);
253 dsi_runtime_put(dpi.dsidev);
254 }
255
256 dispc_runtime_put();
257 dss_runtime_put();
258
259 if (cpu_is_omap34xx())
260 regulator_disable(dpi.vdds_dsi_reg);
261
262 omap_dss_stop_device(dssdev);
263 }
264 EXPORT_SYMBOL(omapdss_dpi_display_disable);
265
266 void dpi_set_timings(struct omap_dss_device *dssdev,
267 struct omap_video_timings *timings)
268 {
269 int r;
270
271 DSSDBG("dpi_set_timings\n");
272 dssdev->panel.timings = *timings;
273 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
274 r = dss_runtime_get();
275 if (r)
276 return;
277
278 r = dispc_runtime_get();
279 if (r) {
280 dss_runtime_put();
281 return;
282 }
283
284 dpi_set_mode(dssdev);
285 dispc_go(dssdev->manager->id);
286
287 dispc_runtime_put();
288 dss_runtime_put();
289 }
290 }
291 EXPORT_SYMBOL(dpi_set_timings);
292
293 int dpi_check_timings(struct omap_dss_device *dssdev,
294 struct omap_video_timings *timings)
295 {
296 bool is_tft;
297 int r;
298 int lck_div, pck_div;
299 unsigned long fck;
300 unsigned long pck;
301 struct dispc_clock_info dispc_cinfo;
302
303 if (!dispc_lcd_timings_ok(timings))
304 return -EINVAL;
305
306 if (timings->pixel_clock == 0)
307 return -EINVAL;
308
309 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
310
311 if (dpi_use_dsi_pll(dssdev)) {
312 struct dsi_clock_info dsi_cinfo;
313 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
314 timings->pixel_clock * 1000,
315 &dsi_cinfo, &dispc_cinfo);
316
317 if (r)
318 return r;
319
320 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
321 } else {
322 struct dss_clock_info dss_cinfo;
323 r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
324 &dss_cinfo, &dispc_cinfo);
325
326 if (r)
327 return r;
328
329 fck = dss_cinfo.fck;
330 }
331
332 lck_div = dispc_cinfo.lck_div;
333 pck_div = dispc_cinfo.pck_div;
334
335 pck = fck / lck_div / pck_div / 1000;
336
337 timings->pixel_clock = pck;
338
339 return 0;
340 }
341 EXPORT_SYMBOL(dpi_check_timings);
342
343 int dpi_init_display(struct omap_dss_device *dssdev)
344 {
345 DSSDBG("init_display\n");
346
347 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
348 struct regulator *vdds_dsi;
349
350 vdds_dsi = dss_get_vdds_dsi();
351
352 if (IS_ERR(vdds_dsi)) {
353 DSSERR("can't get VDDS_DSI regulator\n");
354 return PTR_ERR(vdds_dsi);
355 }
356
357 dpi.vdds_dsi_reg = vdds_dsi;
358 }
359
360 if (dpi_use_dsi_pll(dssdev)) {
361 enum omap_dss_clk_source dispc_fclk_src =
362 dssdev->clocks.dispc.dispc_fclk_src;
363 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
364 }
365
366 return 0;
367 }
368
369 int dpi_init(void)
370 {
371 return 0;
372 }
373
374 void dpi_exit(void)
375 {
376 }
377
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