7411f2674e1682d702c5e3b2af38ffcb8794b24c
[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c
1 /*
2 * linux/drivers/video/omap2/dss/dpi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DPI"
24
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
33
34 #include <video/omapdss.h>
35
36 #include "dss.h"
37 #include "dss_features.h"
38
39 static struct {
40 struct platform_device *pdev;
41
42 struct regulator *vdds_dsi_reg;
43 struct platform_device *dsidev;
44
45 struct mutex lock;
46
47 struct omap_video_timings timings;
48 struct dss_lcd_mgr_config mgr_config;
49 int data_lines;
50
51 struct omap_dss_device output;
52 } dpi;
53
54 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
55 {
56 /*
57 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
58 * would also be used for DISPC fclk. Meaning, when the DPI output is
59 * disabled, DISPC clock will be disabled, and TV out will stop.
60 */
61 switch (omapdss_get_version()) {
62 case OMAPDSS_VER_OMAP24xx:
63 case OMAPDSS_VER_OMAP34xx_ES1:
64 case OMAPDSS_VER_OMAP34xx_ES3:
65 case OMAPDSS_VER_OMAP3630:
66 case OMAPDSS_VER_AM35xx:
67 return NULL;
68
69 case OMAPDSS_VER_OMAP4430_ES1:
70 case OMAPDSS_VER_OMAP4430_ES2:
71 case OMAPDSS_VER_OMAP4:
72 switch (channel) {
73 case OMAP_DSS_CHANNEL_LCD:
74 return dsi_get_dsidev_from_id(0);
75 case OMAP_DSS_CHANNEL_LCD2:
76 return dsi_get_dsidev_from_id(1);
77 default:
78 return NULL;
79 }
80
81 case OMAPDSS_VER_OMAP5:
82 switch (channel) {
83 case OMAP_DSS_CHANNEL_LCD:
84 return dsi_get_dsidev_from_id(0);
85 case OMAP_DSS_CHANNEL_LCD3:
86 return dsi_get_dsidev_from_id(1);
87 default:
88 return NULL;
89 }
90
91 default:
92 return NULL;
93 }
94 }
95
96 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
97 {
98 switch (channel) {
99 case OMAP_DSS_CHANNEL_LCD:
100 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
101 case OMAP_DSS_CHANNEL_LCD2:
102 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
103 default:
104 /* this shouldn't happen */
105 WARN_ON(1);
106 return OMAP_DSS_CLK_SRC_FCK;
107 }
108 }
109
110 struct dpi_clk_calc_ctx {
111 struct platform_device *dsidev;
112
113 /* inputs */
114
115 unsigned long pck_min, pck_max;
116
117 /* outputs */
118
119 struct dsi_clock_info dsi_cinfo;
120 unsigned long long fck;
121 struct dispc_clock_info dispc_cinfo;
122 };
123
124 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
125 unsigned long pck, void *data)
126 {
127 struct dpi_clk_calc_ctx *ctx = data;
128
129 /*
130 * Odd dividers give us uneven duty cycle, causing problem when level
131 * shifted. So skip all odd dividers when the pixel clock is on the
132 * higher side.
133 */
134 if (ctx->pck_min >= 100000000) {
135 if (lckd > 1 && lckd % 2 != 0)
136 return false;
137
138 if (pckd > 1 && pckd % 2 != 0)
139 return false;
140 }
141
142 ctx->dispc_cinfo.lck_div = lckd;
143 ctx->dispc_cinfo.pck_div = pckd;
144 ctx->dispc_cinfo.lck = lck;
145 ctx->dispc_cinfo.pck = pck;
146
147 return true;
148 }
149
150
151 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
152 void *data)
153 {
154 struct dpi_clk_calc_ctx *ctx = data;
155
156 /*
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
159 * higher side.
160 */
161 if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
162 return false;
163
164 ctx->dsi_cinfo.regm_dispc = regm_dispc;
165 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
166
167 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
168 dpi_calc_dispc_cb, ctx);
169 }
170
171
172 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
173 unsigned long pll,
174 void *data)
175 {
176 struct dpi_clk_calc_ctx *ctx = data;
177
178 ctx->dsi_cinfo.regn = regn;
179 ctx->dsi_cinfo.regm = regm;
180 ctx->dsi_cinfo.fint = fint;
181 ctx->dsi_cinfo.clkin4ddr = pll;
182
183 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
184 dpi_calc_hsdiv_cb, ctx);
185 }
186
187 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
188 {
189 struct dpi_clk_calc_ctx *ctx = data;
190
191 ctx->fck = fck;
192
193 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
194 dpi_calc_dispc_cb, ctx);
195 }
196
197 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
198 {
199 unsigned long clkin;
200 unsigned long pll_min, pll_max;
201
202 clkin = dsi_get_pll_clkin(dpi.dsidev);
203
204 memset(ctx, 0, sizeof(*ctx));
205 ctx->dsidev = dpi.dsidev;
206 ctx->pck_min = pck - 1000;
207 ctx->pck_max = pck + 1000;
208 ctx->dsi_cinfo.clkin = clkin;
209
210 pll_min = 0;
211 pll_max = 0;
212
213 return dsi_pll_calc(dpi.dsidev, clkin,
214 pll_min, pll_max,
215 dpi_calc_pll_cb, ctx);
216 }
217
218 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
219 {
220 int i;
221
222 /*
223 * DSS fck gives us very few possibilities, so finding a good pixel
224 * clock may not be possible. We try multiple times to find the clock,
225 * each time widening the pixel clock range we look for, up to
226 * +/- ~15MHz.
227 */
228
229 for (i = 0; i < 25; ++i) {
230 bool ok;
231
232 memset(ctx, 0, sizeof(*ctx));
233 if (pck > 1000 * i * i * i)
234 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
235 else
236 ctx->pck_min = 0;
237 ctx->pck_max = pck + 1000 * i * i * i;
238
239 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
240 if (ok)
241 return ok;
242 }
243
244 return false;
245 }
246
247
248
249 static int dpi_set_dsi_clk(enum omap_channel channel,
250 unsigned long pck_req, unsigned long *fck, int *lck_div,
251 int *pck_div)
252 {
253 struct dpi_clk_calc_ctx ctx;
254 int r;
255 bool ok;
256
257 ok = dpi_dsi_clk_calc(pck_req, &ctx);
258 if (!ok)
259 return -EINVAL;
260
261 r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
262 if (r)
263 return r;
264
265 dss_select_lcd_clk_source(channel,
266 dpi_get_alt_clk_src(channel));
267
268 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
269
270 *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
271 *lck_div = ctx.dispc_cinfo.lck_div;
272 *pck_div = ctx.dispc_cinfo.pck_div;
273
274 return 0;
275 }
276
277 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
278 int *lck_div, int *pck_div)
279 {
280 struct dpi_clk_calc_ctx ctx;
281 int r;
282 bool ok;
283
284 ok = dpi_dss_clk_calc(pck_req, &ctx);
285 if (!ok)
286 return -EINVAL;
287
288 r = dss_set_fck_rate(ctx.fck);
289 if (r)
290 return r;
291
292 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
293
294 *fck = ctx.fck;
295 *lck_div = ctx.dispc_cinfo.lck_div;
296 *pck_div = ctx.dispc_cinfo.pck_div;
297
298 return 0;
299 }
300
301 static int dpi_set_mode(struct omap_overlay_manager *mgr)
302 {
303 struct omap_video_timings *t = &dpi.timings;
304 int lck_div = 0, pck_div = 0;
305 unsigned long fck = 0;
306 unsigned long pck;
307 int r = 0;
308
309 if (dpi.dsidev)
310 r = dpi_set_dsi_clk(mgr->id, t->pixel_clock * 1000, &fck,
311 &lck_div, &pck_div);
312 else
313 r = dpi_set_dispc_clk(t->pixel_clock * 1000, &fck,
314 &lck_div, &pck_div);
315 if (r)
316 return r;
317
318 pck = fck / lck_div / pck_div / 1000;
319
320 if (pck != t->pixel_clock) {
321 DSSWARN("Could not find exact pixel clock. "
322 "Requested %d kHz, got %lu kHz\n",
323 t->pixel_clock, pck);
324
325 t->pixel_clock = pck;
326 }
327
328 dss_mgr_set_timings(mgr, t);
329
330 return 0;
331 }
332
333 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
334 {
335 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
336
337 dpi.mgr_config.stallmode = false;
338 dpi.mgr_config.fifohandcheck = false;
339
340 dpi.mgr_config.video_port_width = dpi.data_lines;
341
342 dpi.mgr_config.lcden_sig_polarity = 0;
343
344 dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
345 }
346
347 static int dpi_display_enable(struct omap_dss_device *dssdev)
348 {
349 struct omap_dss_device *out = &dpi.output;
350 int r;
351
352 mutex_lock(&dpi.lock);
353
354 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
355 DSSERR("no VDSS_DSI regulator\n");
356 r = -ENODEV;
357 goto err_no_reg;
358 }
359
360 if (out == NULL || out->manager == NULL) {
361 DSSERR("failed to enable display: no output/manager\n");
362 r = -ENODEV;
363 goto err_no_out_mgr;
364 }
365
366 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
367 r = regulator_enable(dpi.vdds_dsi_reg);
368 if (r)
369 goto err_reg_enable;
370 }
371
372 r = dispc_runtime_get();
373 if (r)
374 goto err_get_dispc;
375
376 r = dss_dpi_select_source(out->manager->id);
377 if (r)
378 goto err_src_sel;
379
380 if (dpi.dsidev) {
381 r = dsi_runtime_get(dpi.dsidev);
382 if (r)
383 goto err_get_dsi;
384
385 r = dsi_pll_init(dpi.dsidev, 0, 1);
386 if (r)
387 goto err_dsi_pll_init;
388 }
389
390 r = dpi_set_mode(out->manager);
391 if (r)
392 goto err_set_mode;
393
394 dpi_config_lcd_manager(out->manager);
395
396 mdelay(2);
397
398 r = dss_mgr_enable(out->manager);
399 if (r)
400 goto err_mgr_enable;
401
402 mutex_unlock(&dpi.lock);
403
404 return 0;
405
406 err_mgr_enable:
407 err_set_mode:
408 if (dpi.dsidev)
409 dsi_pll_uninit(dpi.dsidev, true);
410 err_dsi_pll_init:
411 if (dpi.dsidev)
412 dsi_runtime_put(dpi.dsidev);
413 err_get_dsi:
414 err_src_sel:
415 dispc_runtime_put();
416 err_get_dispc:
417 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
418 regulator_disable(dpi.vdds_dsi_reg);
419 err_reg_enable:
420 err_no_out_mgr:
421 err_no_reg:
422 mutex_unlock(&dpi.lock);
423 return r;
424 }
425
426 static void dpi_display_disable(struct omap_dss_device *dssdev)
427 {
428 struct omap_overlay_manager *mgr = dpi.output.manager;
429
430 mutex_lock(&dpi.lock);
431
432 dss_mgr_disable(mgr);
433
434 if (dpi.dsidev) {
435 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
436 dsi_pll_uninit(dpi.dsidev, true);
437 dsi_runtime_put(dpi.dsidev);
438 }
439
440 dispc_runtime_put();
441
442 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
443 regulator_disable(dpi.vdds_dsi_reg);
444
445 mutex_unlock(&dpi.lock);
446 }
447
448 static void dpi_set_timings(struct omap_dss_device *dssdev,
449 struct omap_video_timings *timings)
450 {
451 DSSDBG("dpi_set_timings\n");
452
453 mutex_lock(&dpi.lock);
454
455 dpi.timings = *timings;
456
457 mutex_unlock(&dpi.lock);
458 }
459
460 static void dpi_get_timings(struct omap_dss_device *dssdev,
461 struct omap_video_timings *timings)
462 {
463 mutex_lock(&dpi.lock);
464
465 *timings = dpi.timings;
466
467 mutex_unlock(&dpi.lock);
468 }
469
470 static int dpi_check_timings(struct omap_dss_device *dssdev,
471 struct omap_video_timings *timings)
472 {
473 struct omap_overlay_manager *mgr = dpi.output.manager;
474 int lck_div, pck_div;
475 unsigned long fck;
476 unsigned long pck;
477 struct dpi_clk_calc_ctx ctx;
478 bool ok;
479
480 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
481 return -EINVAL;
482
483 if (timings->pixel_clock == 0)
484 return -EINVAL;
485
486 if (dpi.dsidev) {
487 ok = dpi_dsi_clk_calc(timings->pixel_clock * 1000, &ctx);
488 if (!ok)
489 return -EINVAL;
490
491 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
492 } else {
493 ok = dpi_dss_clk_calc(timings->pixel_clock * 1000, &ctx);
494 if (!ok)
495 return -EINVAL;
496
497 fck = ctx.fck;
498 }
499
500 lck_div = ctx.dispc_cinfo.lck_div;
501 pck_div = ctx.dispc_cinfo.pck_div;
502
503 pck = fck / lck_div / pck_div / 1000;
504
505 timings->pixel_clock = pck;
506
507 return 0;
508 }
509
510 static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
511 {
512 mutex_lock(&dpi.lock);
513
514 dpi.data_lines = data_lines;
515
516 mutex_unlock(&dpi.lock);
517 }
518
519 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
520 {
521 int r;
522
523 /* do initial setup with the PLL to see if it is operational */
524
525 r = dsi_runtime_get(dsidev);
526 if (r)
527 return r;
528
529 r = dsi_pll_init(dsidev, 0, 1);
530 if (r) {
531 dsi_runtime_put(dsidev);
532 return r;
533 }
534
535 dsi_pll_uninit(dsidev, true);
536 dsi_runtime_put(dsidev);
537
538 return 0;
539 }
540
541 static int dpi_init_regulator(void)
542 {
543 struct regulator *vdds_dsi;
544
545 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
546 return 0;
547
548 if (dpi.vdds_dsi_reg)
549 return 0;
550
551 vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
552 if (IS_ERR(vdds_dsi)) {
553 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
554 DSSERR("can't get VDDS_DSI regulator\n");
555 return PTR_ERR(vdds_dsi);
556 }
557
558 dpi.vdds_dsi_reg = vdds_dsi;
559
560 return 0;
561 }
562
563 static void dpi_init_pll(void)
564 {
565 struct platform_device *dsidev;
566
567 if (dpi.dsidev)
568 return;
569
570 dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
571 if (!dsidev)
572 return;
573
574 if (dpi_verify_dsi_pll(dsidev)) {
575 DSSWARN("DSI PLL not operational\n");
576 return;
577 }
578
579 dpi.dsidev = dsidev;
580 }
581
582 /*
583 * Return a hardcoded channel for the DPI output. This should work for
584 * current use cases, but this can be later expanded to either resolve
585 * the channel in some more dynamic manner, or get the channel as a user
586 * parameter.
587 */
588 static enum omap_channel dpi_get_channel(void)
589 {
590 switch (omapdss_get_version()) {
591 case OMAPDSS_VER_OMAP24xx:
592 case OMAPDSS_VER_OMAP34xx_ES1:
593 case OMAPDSS_VER_OMAP34xx_ES3:
594 case OMAPDSS_VER_OMAP3630:
595 case OMAPDSS_VER_AM35xx:
596 return OMAP_DSS_CHANNEL_LCD;
597
598 case OMAPDSS_VER_OMAP4430_ES1:
599 case OMAPDSS_VER_OMAP4430_ES2:
600 case OMAPDSS_VER_OMAP4:
601 return OMAP_DSS_CHANNEL_LCD2;
602
603 case OMAPDSS_VER_OMAP5:
604 return OMAP_DSS_CHANNEL_LCD3;
605
606 default:
607 DSSWARN("unsupported DSS version\n");
608 return OMAP_DSS_CHANNEL_LCD;
609 }
610 }
611
612 static int dpi_connect(struct omap_dss_device *dssdev,
613 struct omap_dss_device *dst)
614 {
615 struct omap_overlay_manager *mgr;
616 int r;
617
618 r = dpi_init_regulator();
619 if (r)
620 return r;
621
622 dpi_init_pll();
623
624 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
625 if (!mgr)
626 return -ENODEV;
627
628 r = dss_mgr_connect(mgr, dssdev);
629 if (r)
630 return r;
631
632 r = omapdss_output_set_device(dssdev, dst);
633 if (r) {
634 DSSERR("failed to connect output to new device: %s\n",
635 dst->name);
636 dss_mgr_disconnect(mgr, dssdev);
637 return r;
638 }
639
640 return 0;
641 }
642
643 static void dpi_disconnect(struct omap_dss_device *dssdev,
644 struct omap_dss_device *dst)
645 {
646 WARN_ON(dst != dssdev->dst);
647
648 if (dst != dssdev->dst)
649 return;
650
651 omapdss_output_unset_device(dssdev);
652
653 if (dssdev->manager)
654 dss_mgr_disconnect(dssdev->manager, dssdev);
655 }
656
657 static const struct omapdss_dpi_ops dpi_ops = {
658 .connect = dpi_connect,
659 .disconnect = dpi_disconnect,
660
661 .enable = dpi_display_enable,
662 .disable = dpi_display_disable,
663
664 .check_timings = dpi_check_timings,
665 .set_timings = dpi_set_timings,
666 .get_timings = dpi_get_timings,
667
668 .set_data_lines = dpi_set_data_lines,
669 };
670
671 static void dpi_init_output(struct platform_device *pdev)
672 {
673 struct omap_dss_device *out = &dpi.output;
674
675 out->dev = &pdev->dev;
676 out->id = OMAP_DSS_OUTPUT_DPI;
677 out->output_type = OMAP_DISPLAY_TYPE_DPI;
678 out->name = "dpi.0";
679 out->dispc_channel = dpi_get_channel();
680 out->ops.dpi = &dpi_ops;
681 out->owner = THIS_MODULE;
682
683 omapdss_register_output(out);
684 }
685
686 static void __exit dpi_uninit_output(struct platform_device *pdev)
687 {
688 struct omap_dss_device *out = &dpi.output;
689
690 omapdss_unregister_output(out);
691 }
692
693 static int omap_dpi_probe(struct platform_device *pdev)
694 {
695 dpi.pdev = pdev;
696
697 mutex_init(&dpi.lock);
698
699 dpi_init_output(pdev);
700
701 return 0;
702 }
703
704 static int __exit omap_dpi_remove(struct platform_device *pdev)
705 {
706 dpi_uninit_output(pdev);
707
708 return 0;
709 }
710
711 static struct platform_driver omap_dpi_driver = {
712 .probe = omap_dpi_probe,
713 .remove = __exit_p(omap_dpi_remove),
714 .driver = {
715 .name = "omapdss_dpi",
716 .owner = THIS_MODULE,
717 },
718 };
719
720 int __init dpi_init_platform_driver(void)
721 {
722 return platform_driver_register(&omap_dpi_driver);
723 }
724
725 void __exit dpi_uninit_platform_driver(void)
726 {
727 platform_driver_unregister(&omap_dpi_driver);
728 }
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