2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
34 #include <video/omapdss.h>
37 #include "dss_features.h"
40 struct platform_device
*pdev
;
42 struct regulator
*vdds_dsi_reg
;
43 struct platform_device
*dsidev
;
47 struct omap_video_timings timings
;
48 struct dss_lcd_mgr_config mgr_config
;
51 struct omap_dss_output output
;
54 static struct platform_device
*dpi_get_dsidev(enum omap_channel channel
)
57 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
58 * would also be used for DISPC fclk. Meaning, when the DPI output is
59 * disabled, DISPC clock will be disabled, and TV out will stop.
61 switch (omapdss_get_version()) {
62 case OMAPDSS_VER_OMAP24xx
:
63 case OMAPDSS_VER_OMAP34xx_ES1
:
64 case OMAPDSS_VER_OMAP34xx_ES3
:
65 case OMAPDSS_VER_OMAP3630
:
66 case OMAPDSS_VER_AM35xx
:
69 case OMAPDSS_VER_OMAP4430_ES1
:
70 case OMAPDSS_VER_OMAP4430_ES2
:
71 case OMAPDSS_VER_OMAP4
:
73 case OMAP_DSS_CHANNEL_LCD
:
74 return dsi_get_dsidev_from_id(0);
75 case OMAP_DSS_CHANNEL_LCD2
:
76 return dsi_get_dsidev_from_id(1);
81 case OMAPDSS_VER_OMAP5
:
83 case OMAP_DSS_CHANNEL_LCD
:
84 return dsi_get_dsidev_from_id(0);
85 case OMAP_DSS_CHANNEL_LCD3
:
86 return dsi_get_dsidev_from_id(1);
96 static enum omap_dss_clk_source
dpi_get_alt_clk_src(enum omap_channel channel
)
99 case OMAP_DSS_CHANNEL_LCD
:
100 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
;
101 case OMAP_DSS_CHANNEL_LCD2
:
102 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
;
104 /* this shouldn't happen */
106 return OMAP_DSS_CLK_SRC_FCK
;
110 struct dpi_clk_calc_ctx
{
111 struct platform_device
*dsidev
;
115 unsigned long pck_min
, pck_max
;
119 struct dsi_clock_info dsi_cinfo
;
120 struct dss_clock_info dss_cinfo
;
121 struct dispc_clock_info dispc_cinfo
;
124 static bool dpi_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
125 unsigned long pck
, void *data
)
127 struct dpi_clk_calc_ctx
*ctx
= data
;
130 * Odd dividers give us uneven duty cycle, causing problem when level
131 * shifted. So skip all odd dividers when the pixel clock is on the
134 if (ctx
->pck_min
>= 1000000) {
135 if (lckd
> 1 && lckd
% 2 != 0)
138 if (pckd
> 1 && pckd
% 2 != 0)
142 ctx
->dispc_cinfo
.lck_div
= lckd
;
143 ctx
->dispc_cinfo
.pck_div
= pckd
;
144 ctx
->dispc_cinfo
.lck
= lck
;
145 ctx
->dispc_cinfo
.pck
= pck
;
151 static bool dpi_calc_hsdiv_cb(int regm_dispc
, unsigned long dispc
,
154 struct dpi_clk_calc_ctx
*ctx
= data
;
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
161 if (regm_dispc
> 1 && regm_dispc
% 2 != 0 && ctx
->pck_min
>= 1000000)
164 ctx
->dsi_cinfo
.regm_dispc
= regm_dispc
;
165 ctx
->dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
= dispc
;
167 return dispc_div_calc(dispc
, ctx
->pck_min
, ctx
->pck_max
,
168 dpi_calc_dispc_cb
, ctx
);
172 static bool dpi_calc_pll_cb(int regn
, int regm
, unsigned long fint
,
176 struct dpi_clk_calc_ctx
*ctx
= data
;
178 ctx
->dsi_cinfo
.regn
= regn
;
179 ctx
->dsi_cinfo
.regm
= regm
;
180 ctx
->dsi_cinfo
.fint
= fint
;
181 ctx
->dsi_cinfo
.clkin4ddr
= pll
;
183 return dsi_hsdiv_calc(ctx
->dsidev
, pll
, ctx
->pck_min
,
184 dpi_calc_hsdiv_cb
, ctx
);
187 static bool dpi_calc_dss_cb(int fckd
, unsigned long fck
, void *data
)
189 struct dpi_clk_calc_ctx
*ctx
= data
;
191 ctx
->dss_cinfo
.fck
= fck
;
192 ctx
->dss_cinfo
.fck_div
= fckd
;
194 return dispc_div_calc(fck
, ctx
->pck_min
, ctx
->pck_max
,
195 dpi_calc_dispc_cb
, ctx
);
198 static bool dpi_dsi_clk_calc(unsigned long pck
, struct dpi_clk_calc_ctx
*ctx
)
201 unsigned long pll_min
, pll_max
;
203 clkin
= dsi_get_pll_clkin(dpi
.dsidev
);
205 memset(ctx
, 0, sizeof(*ctx
));
206 ctx
->dsidev
= dpi
.dsidev
;
207 ctx
->pck_min
= pck
- 1000;
208 ctx
->pck_max
= pck
+ 1000;
209 ctx
->dsi_cinfo
.clkin
= clkin
;
214 return dsi_pll_calc(dpi
.dsidev
, clkin
,
216 dpi_calc_pll_cb
, ctx
);
219 static bool dpi_dss_clk_calc(unsigned long pck
, struct dpi_clk_calc_ctx
*ctx
)
224 * DSS fck gives us very few possibilities, so finding a good pixel
225 * clock may not be possible. We try multiple times to find the clock,
226 * each time widening the pixel clock range we look for, up to
230 for (i
= 0; i
< 25; ++i
) {
233 memset(ctx
, 0, sizeof(*ctx
));
234 if (pck
> 1000 * i
* i
* i
)
235 ctx
->pck_min
= max(pck
- 1000 * i
* i
* i
, 0lu);
238 ctx
->pck_max
= pck
+ 1000 * i
* i
* i
;
240 ok
= dss_div_calc(ctx
->pck_min
, dpi_calc_dss_cb
, ctx
);
250 static int dpi_set_dsi_clk(enum omap_channel channel
,
251 unsigned long pck_req
, unsigned long *fck
, int *lck_div
,
254 struct dpi_clk_calc_ctx ctx
;
258 ok
= dpi_dsi_clk_calc(pck_req
, &ctx
);
262 r
= dsi_pll_set_clock_div(dpi
.dsidev
, &ctx
.dsi_cinfo
);
266 dss_select_lcd_clk_source(channel
,
267 dpi_get_alt_clk_src(channel
));
269 dpi
.mgr_config
.clock_info
= ctx
.dispc_cinfo
;
271 *fck
= ctx
.dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
;
272 *lck_div
= ctx
.dispc_cinfo
.lck_div
;
273 *pck_div
= ctx
.dispc_cinfo
.pck_div
;
278 static int dpi_set_dispc_clk(unsigned long pck_req
, unsigned long *fck
,
279 int *lck_div
, int *pck_div
)
281 struct dpi_clk_calc_ctx ctx
;
285 ok
= dpi_dss_clk_calc(pck_req
, &ctx
);
289 r
= dss_set_clock_div(&ctx
.dss_cinfo
);
293 dpi
.mgr_config
.clock_info
= ctx
.dispc_cinfo
;
295 *fck
= ctx
.dss_cinfo
.fck
;
296 *lck_div
= ctx
.dispc_cinfo
.lck_div
;
297 *pck_div
= ctx
.dispc_cinfo
.pck_div
;
302 static int dpi_set_mode(struct omap_overlay_manager
*mgr
)
304 struct omap_video_timings
*t
= &dpi
.timings
;
305 int lck_div
= 0, pck_div
= 0;
306 unsigned long fck
= 0;
311 r
= dpi_set_dsi_clk(mgr
->id
, t
->pixel_clock
* 1000, &fck
,
314 r
= dpi_set_dispc_clk(t
->pixel_clock
* 1000, &fck
,
319 pck
= fck
/ lck_div
/ pck_div
/ 1000;
321 if (pck
!= t
->pixel_clock
) {
322 DSSWARN("Could not find exact pixel clock. "
323 "Requested %d kHz, got %lu kHz\n",
324 t
->pixel_clock
, pck
);
326 t
->pixel_clock
= pck
;
329 dss_mgr_set_timings(mgr
, t
);
334 static void dpi_config_lcd_manager(struct omap_overlay_manager
*mgr
)
336 dpi
.mgr_config
.io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
;
338 dpi
.mgr_config
.stallmode
= false;
339 dpi
.mgr_config
.fifohandcheck
= false;
341 dpi
.mgr_config
.video_port_width
= dpi
.data_lines
;
343 dpi
.mgr_config
.lcden_sig_polarity
= 0;
345 dss_mgr_set_lcd_config(mgr
, &dpi
.mgr_config
);
348 int omapdss_dpi_display_enable(struct omap_dss_device
*dssdev
)
350 struct omap_dss_output
*out
= &dpi
.output
;
353 mutex_lock(&dpi
.lock
);
355 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI
) && !dpi
.vdds_dsi_reg
) {
356 DSSERR("no VDSS_DSI regulator\n");
361 if (out
== NULL
|| out
->manager
== NULL
) {
362 DSSERR("failed to enable display: no output/manager\n");
367 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI
)) {
368 r
= regulator_enable(dpi
.vdds_dsi_reg
);
373 r
= dispc_runtime_get();
377 r
= dss_dpi_select_source(out
->manager
->id
);
382 r
= dsi_runtime_get(dpi
.dsidev
);
386 r
= dsi_pll_init(dpi
.dsidev
, 0, 1);
388 goto err_dsi_pll_init
;
391 r
= dpi_set_mode(out
->manager
);
395 dpi_config_lcd_manager(out
->manager
);
399 r
= dss_mgr_enable(out
->manager
);
403 mutex_unlock(&dpi
.lock
);
410 dsi_pll_uninit(dpi
.dsidev
, true);
413 dsi_runtime_put(dpi
.dsidev
);
418 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI
))
419 regulator_disable(dpi
.vdds_dsi_reg
);
423 mutex_unlock(&dpi
.lock
);
426 EXPORT_SYMBOL(omapdss_dpi_display_enable
);
428 void omapdss_dpi_display_disable(struct omap_dss_device
*dssdev
)
430 struct omap_overlay_manager
*mgr
= dpi
.output
.manager
;
432 mutex_lock(&dpi
.lock
);
434 dss_mgr_disable(mgr
);
437 dss_select_lcd_clk_source(mgr
->id
, OMAP_DSS_CLK_SRC_FCK
);
438 dsi_pll_uninit(dpi
.dsidev
, true);
439 dsi_runtime_put(dpi
.dsidev
);
444 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI
))
445 regulator_disable(dpi
.vdds_dsi_reg
);
447 mutex_unlock(&dpi
.lock
);
449 EXPORT_SYMBOL(omapdss_dpi_display_disable
);
451 void omapdss_dpi_set_timings(struct omap_dss_device
*dssdev
,
452 struct omap_video_timings
*timings
)
454 DSSDBG("dpi_set_timings\n");
456 mutex_lock(&dpi
.lock
);
458 dpi
.timings
= *timings
;
460 mutex_unlock(&dpi
.lock
);
462 EXPORT_SYMBOL(omapdss_dpi_set_timings
);
464 int dpi_check_timings(struct omap_dss_device
*dssdev
,
465 struct omap_video_timings
*timings
)
467 struct omap_overlay_manager
*mgr
= dpi
.output
.manager
;
468 int lck_div
, pck_div
;
471 struct dpi_clk_calc_ctx ctx
;
474 if (mgr
&& !dispc_mgr_timings_ok(mgr
->id
, timings
))
477 if (timings
->pixel_clock
== 0)
481 ok
= dpi_dsi_clk_calc(timings
->pixel_clock
* 1000, &ctx
);
485 fck
= ctx
.dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
;
487 ok
= dpi_dss_clk_calc(timings
->pixel_clock
* 1000, &ctx
);
491 fck
= ctx
.dss_cinfo
.fck
;
494 lck_div
= ctx
.dispc_cinfo
.lck_div
;
495 pck_div
= ctx
.dispc_cinfo
.pck_div
;
497 pck
= fck
/ lck_div
/ pck_div
/ 1000;
499 timings
->pixel_clock
= pck
;
503 EXPORT_SYMBOL(dpi_check_timings
);
505 void omapdss_dpi_set_data_lines(struct omap_dss_device
*dssdev
, int data_lines
)
507 mutex_lock(&dpi
.lock
);
509 dpi
.data_lines
= data_lines
;
511 mutex_unlock(&dpi
.lock
);
513 EXPORT_SYMBOL(omapdss_dpi_set_data_lines
);
515 static int dpi_verify_dsi_pll(struct platform_device
*dsidev
)
519 /* do initial setup with the PLL to see if it is operational */
521 r
= dsi_runtime_get(dsidev
);
525 r
= dsi_pll_init(dsidev
, 0, 1);
527 dsi_runtime_put(dsidev
);
531 dsi_pll_uninit(dsidev
, true);
532 dsi_runtime_put(dsidev
);
537 static int dpi_init_regulator(void)
539 struct regulator
*vdds_dsi
;
541 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI
))
544 if (dpi
.vdds_dsi_reg
)
547 vdds_dsi
= dss_get_vdds_dsi();
549 if (IS_ERR(vdds_dsi
)) {
550 vdds_dsi
= devm_regulator_get(&dpi
.pdev
->dev
, "vdds_dsi");
551 if (IS_ERR(vdds_dsi
)) {
552 DSSERR("can't get VDDS_DSI regulator\n");
553 return PTR_ERR(vdds_dsi
);
557 dpi
.vdds_dsi_reg
= vdds_dsi
;
562 static void dpi_init_pll(void)
564 struct platform_device
*dsidev
;
569 dsidev
= dpi_get_dsidev(dpi
.output
.dispc_channel
);
573 if (dpi_verify_dsi_pll(dsidev
)) {
574 DSSWARN("DSI PLL not operational\n");
582 * Return a hardcoded channel for the DPI output. This should work for
583 * current use cases, but this can be later expanded to either resolve
584 * the channel in some more dynamic manner, or get the channel as a user
587 static enum omap_channel
dpi_get_channel(void)
589 switch (omapdss_get_version()) {
590 case OMAPDSS_VER_OMAP24xx
:
591 case OMAPDSS_VER_OMAP34xx_ES1
:
592 case OMAPDSS_VER_OMAP34xx_ES3
:
593 case OMAPDSS_VER_OMAP3630
:
594 case OMAPDSS_VER_AM35xx
:
595 return OMAP_DSS_CHANNEL_LCD
;
597 case OMAPDSS_VER_OMAP4430_ES1
:
598 case OMAPDSS_VER_OMAP4430_ES2
:
599 case OMAPDSS_VER_OMAP4
:
600 return OMAP_DSS_CHANNEL_LCD2
;
602 case OMAPDSS_VER_OMAP5
:
603 return OMAP_DSS_CHANNEL_LCD3
;
606 DSSWARN("unsupported DSS version\n");
607 return OMAP_DSS_CHANNEL_LCD
;
611 static struct omap_dss_device
*dpi_find_dssdev(struct platform_device
*pdev
)
613 struct omap_dss_board_info
*pdata
= pdev
->dev
.platform_data
;
614 const char *def_disp_name
= omapdss_get_default_display_name();
615 struct omap_dss_device
*def_dssdev
;
620 for (i
= 0; i
< pdata
->num_devices
; ++i
) {
621 struct omap_dss_device
*dssdev
= pdata
->devices
[i
];
623 if (dssdev
->type
!= OMAP_DISPLAY_TYPE_DPI
)
626 if (def_dssdev
== NULL
)
629 if (def_disp_name
!= NULL
&&
630 strcmp(dssdev
->name
, def_disp_name
) == 0) {
639 static int dpi_probe_pdata(struct platform_device
*dpidev
)
641 struct omap_dss_device
*plat_dssdev
;
642 struct omap_dss_device
*dssdev
;
645 plat_dssdev
= dpi_find_dssdev(dpidev
);
650 r
= dpi_init_regulator();
656 dssdev
= dss_alloc_and_init_device(&dpidev
->dev
);
660 dss_copy_device_pdata(dssdev
, plat_dssdev
);
662 r
= omapdss_output_set_device(&dpi
.output
, dssdev
);
664 DSSERR("failed to connect output to new device: %s\n",
666 dss_put_device(dssdev
);
670 r
= dss_add_device(dssdev
);
672 DSSERR("device %s register failed: %d\n", dssdev
->name
, r
);
673 omapdss_output_unset_device(&dpi
.output
);
674 dss_put_device(dssdev
);
681 static void dpi_init_output(struct platform_device
*pdev
)
683 struct omap_dss_output
*out
= &dpi
.output
;
686 out
->id
= OMAP_DSS_OUTPUT_DPI
;
687 out
->type
= OMAP_DISPLAY_TYPE_DPI
;
689 out
->dispc_channel
= dpi_get_channel();
691 dss_register_output(out
);
694 static void __exit
dpi_uninit_output(struct platform_device
*pdev
)
696 struct omap_dss_output
*out
= &dpi
.output
;
698 dss_unregister_output(out
);
701 static int omap_dpi_probe(struct platform_device
*pdev
)
707 mutex_init(&dpi
.lock
);
709 dpi_init_output(pdev
);
711 if (pdev
->dev
.platform_data
) {
712 r
= dpi_probe_pdata(pdev
);
720 dpi_uninit_output(pdev
);
724 static int __exit
omap_dpi_remove(struct platform_device
*pdev
)
726 dss_unregister_child_devices(&pdev
->dev
);
728 dpi_uninit_output(pdev
);
733 static struct platform_driver omap_dpi_driver
= {
734 .probe
= omap_dpi_probe
,
735 .remove
= __exit_p(omap_dpi_remove
),
737 .name
= "omapdss_dpi",
738 .owner
= THIS_MODULE
,
742 int __init
dpi_init_platform_driver(void)
744 return platform_driver_register(&omap_dpi_driver
);
747 void __exit
dpi_uninit_platform_driver(void)
749 platform_driver_unregister(&omap_dpi_driver
);