OMAPDSS: remove omap_dss_start/stop_device()
[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c
1 /*
2 * linux/drivers/video/omap2/dss/dpi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #define DSS_SUBSYS_NAME "DPI"
24
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
33
34 #include <video/omapdss.h>
35
36 #include "dss.h"
37 #include "dss_features.h"
38
39 static struct {
40 struct platform_device *pdev;
41
42 struct regulator *vdds_dsi_reg;
43 struct platform_device *dsidev;
44
45 struct mutex lock;
46
47 struct omap_video_timings timings;
48 struct dss_lcd_mgr_config mgr_config;
49 int data_lines;
50
51 struct omap_dss_output output;
52 } dpi;
53
54 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
55 {
56 /*
57 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
58 * would also be used for DISPC fclk. Meaning, when the DPI output is
59 * disabled, DISPC clock will be disabled, and TV out will stop.
60 */
61 switch (omapdss_get_version()) {
62 case OMAPDSS_VER_OMAP24xx:
63 case OMAPDSS_VER_OMAP34xx_ES1:
64 case OMAPDSS_VER_OMAP34xx_ES3:
65 case OMAPDSS_VER_OMAP3630:
66 case OMAPDSS_VER_AM35xx:
67 return NULL;
68
69 case OMAPDSS_VER_OMAP4430_ES1:
70 case OMAPDSS_VER_OMAP4430_ES2:
71 case OMAPDSS_VER_OMAP4:
72 switch (channel) {
73 case OMAP_DSS_CHANNEL_LCD:
74 return dsi_get_dsidev_from_id(0);
75 case OMAP_DSS_CHANNEL_LCD2:
76 return dsi_get_dsidev_from_id(1);
77 default:
78 return NULL;
79 }
80
81 case OMAPDSS_VER_OMAP5:
82 switch (channel) {
83 case OMAP_DSS_CHANNEL_LCD:
84 return dsi_get_dsidev_from_id(0);
85 case OMAP_DSS_CHANNEL_LCD3:
86 return dsi_get_dsidev_from_id(1);
87 default:
88 return NULL;
89 }
90
91 default:
92 return NULL;
93 }
94 }
95
96 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
97 {
98 switch (channel) {
99 case OMAP_DSS_CHANNEL_LCD:
100 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
101 case OMAP_DSS_CHANNEL_LCD2:
102 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
103 default:
104 /* this shouldn't happen */
105 WARN_ON(1);
106 return OMAP_DSS_CLK_SRC_FCK;
107 }
108 }
109
110 struct dpi_clk_calc_ctx {
111 struct platform_device *dsidev;
112
113 /* inputs */
114
115 unsigned long pck_min, pck_max;
116
117 /* outputs */
118
119 struct dsi_clock_info dsi_cinfo;
120 struct dss_clock_info dss_cinfo;
121 struct dispc_clock_info dispc_cinfo;
122 };
123
124 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
125 unsigned long pck, void *data)
126 {
127 struct dpi_clk_calc_ctx *ctx = data;
128
129 /*
130 * Odd dividers give us uneven duty cycle, causing problem when level
131 * shifted. So skip all odd dividers when the pixel clock is on the
132 * higher side.
133 */
134 if (ctx->pck_min >= 1000000) {
135 if (lckd > 1 && lckd % 2 != 0)
136 return false;
137
138 if (pckd > 1 && pckd % 2 != 0)
139 return false;
140 }
141
142 ctx->dispc_cinfo.lck_div = lckd;
143 ctx->dispc_cinfo.pck_div = pckd;
144 ctx->dispc_cinfo.lck = lck;
145 ctx->dispc_cinfo.pck = pck;
146
147 return true;
148 }
149
150
151 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
152 void *data)
153 {
154 struct dpi_clk_calc_ctx *ctx = data;
155
156 /*
157 * Odd dividers give us uneven duty cycle, causing problem when level
158 * shifted. So skip all odd dividers when the pixel clock is on the
159 * higher side.
160 */
161 if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 1000000)
162 return false;
163
164 ctx->dsi_cinfo.regm_dispc = regm_dispc;
165 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
166
167 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
168 dpi_calc_dispc_cb, ctx);
169 }
170
171
172 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
173 unsigned long pll,
174 void *data)
175 {
176 struct dpi_clk_calc_ctx *ctx = data;
177
178 ctx->dsi_cinfo.regn = regn;
179 ctx->dsi_cinfo.regm = regm;
180 ctx->dsi_cinfo.fint = fint;
181 ctx->dsi_cinfo.clkin4ddr = pll;
182
183 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
184 dpi_calc_hsdiv_cb, ctx);
185 }
186
187 static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
188 {
189 struct dpi_clk_calc_ctx *ctx = data;
190
191 ctx->dss_cinfo.fck = fck;
192 ctx->dss_cinfo.fck_div = fckd;
193
194 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
195 dpi_calc_dispc_cb, ctx);
196 }
197
198 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
199 {
200 unsigned long clkin;
201 unsigned long pll_min, pll_max;
202
203 clkin = dsi_get_pll_clkin(dpi.dsidev);
204
205 memset(ctx, 0, sizeof(*ctx));
206 ctx->dsidev = dpi.dsidev;
207 ctx->pck_min = pck - 1000;
208 ctx->pck_max = pck + 1000;
209 ctx->dsi_cinfo.clkin = clkin;
210
211 pll_min = 0;
212 pll_max = 0;
213
214 return dsi_pll_calc(dpi.dsidev, clkin,
215 pll_min, pll_max,
216 dpi_calc_pll_cb, ctx);
217 }
218
219 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
220 {
221 int i;
222
223 /*
224 * DSS fck gives us very few possibilities, so finding a good pixel
225 * clock may not be possible. We try multiple times to find the clock,
226 * each time widening the pixel clock range we look for, up to
227 * +/- ~15MHz.
228 */
229
230 for (i = 0; i < 25; ++i) {
231 bool ok;
232
233 memset(ctx, 0, sizeof(*ctx));
234 if (pck > 1000 * i * i * i)
235 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
236 else
237 ctx->pck_min = 0;
238 ctx->pck_max = pck + 1000 * i * i * i;
239
240 ok = dss_div_calc(ctx->pck_min, dpi_calc_dss_cb, ctx);
241 if (ok)
242 return ok;
243 }
244
245 return false;
246 }
247
248
249
250 static int dpi_set_dsi_clk(enum omap_channel channel,
251 unsigned long pck_req, unsigned long *fck, int *lck_div,
252 int *pck_div)
253 {
254 struct dpi_clk_calc_ctx ctx;
255 int r;
256 bool ok;
257
258 ok = dpi_dsi_clk_calc(pck_req, &ctx);
259 if (!ok)
260 return -EINVAL;
261
262 r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
263 if (r)
264 return r;
265
266 dss_select_lcd_clk_source(channel,
267 dpi_get_alt_clk_src(channel));
268
269 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
270
271 *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
272 *lck_div = ctx.dispc_cinfo.lck_div;
273 *pck_div = ctx.dispc_cinfo.pck_div;
274
275 return 0;
276 }
277
278 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
279 int *lck_div, int *pck_div)
280 {
281 struct dpi_clk_calc_ctx ctx;
282 int r;
283 bool ok;
284
285 ok = dpi_dss_clk_calc(pck_req, &ctx);
286 if (!ok)
287 return -EINVAL;
288
289 r = dss_set_clock_div(&ctx.dss_cinfo);
290 if (r)
291 return r;
292
293 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
294
295 *fck = ctx.dss_cinfo.fck;
296 *lck_div = ctx.dispc_cinfo.lck_div;
297 *pck_div = ctx.dispc_cinfo.pck_div;
298
299 return 0;
300 }
301
302 static int dpi_set_mode(struct omap_overlay_manager *mgr)
303 {
304 struct omap_video_timings *t = &dpi.timings;
305 int lck_div = 0, pck_div = 0;
306 unsigned long fck = 0;
307 unsigned long pck;
308 int r = 0;
309
310 if (dpi.dsidev)
311 r = dpi_set_dsi_clk(mgr->id, t->pixel_clock * 1000, &fck,
312 &lck_div, &pck_div);
313 else
314 r = dpi_set_dispc_clk(t->pixel_clock * 1000, &fck,
315 &lck_div, &pck_div);
316 if (r)
317 return r;
318
319 pck = fck / lck_div / pck_div / 1000;
320
321 if (pck != t->pixel_clock) {
322 DSSWARN("Could not find exact pixel clock. "
323 "Requested %d kHz, got %lu kHz\n",
324 t->pixel_clock, pck);
325
326 t->pixel_clock = pck;
327 }
328
329 dss_mgr_set_timings(mgr, t);
330
331 return 0;
332 }
333
334 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
335 {
336 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
337
338 dpi.mgr_config.stallmode = false;
339 dpi.mgr_config.fifohandcheck = false;
340
341 dpi.mgr_config.video_port_width = dpi.data_lines;
342
343 dpi.mgr_config.lcden_sig_polarity = 0;
344
345 dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
346 }
347
348 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
349 {
350 struct omap_dss_output *out = &dpi.output;
351 int r;
352
353 mutex_lock(&dpi.lock);
354
355 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
356 DSSERR("no VDSS_DSI regulator\n");
357 r = -ENODEV;
358 goto err_no_reg;
359 }
360
361 if (out == NULL || out->manager == NULL) {
362 DSSERR("failed to enable display: no output/manager\n");
363 r = -ENODEV;
364 goto err_no_out_mgr;
365 }
366
367 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
368 r = regulator_enable(dpi.vdds_dsi_reg);
369 if (r)
370 goto err_reg_enable;
371 }
372
373 r = dispc_runtime_get();
374 if (r)
375 goto err_get_dispc;
376
377 r = dss_dpi_select_source(out->manager->id);
378 if (r)
379 goto err_src_sel;
380
381 if (dpi.dsidev) {
382 r = dsi_runtime_get(dpi.dsidev);
383 if (r)
384 goto err_get_dsi;
385
386 r = dsi_pll_init(dpi.dsidev, 0, 1);
387 if (r)
388 goto err_dsi_pll_init;
389 }
390
391 r = dpi_set_mode(out->manager);
392 if (r)
393 goto err_set_mode;
394
395 dpi_config_lcd_manager(out->manager);
396
397 mdelay(2);
398
399 r = dss_mgr_enable(out->manager);
400 if (r)
401 goto err_mgr_enable;
402
403 mutex_unlock(&dpi.lock);
404
405 return 0;
406
407 err_mgr_enable:
408 err_set_mode:
409 if (dpi.dsidev)
410 dsi_pll_uninit(dpi.dsidev, true);
411 err_dsi_pll_init:
412 if (dpi.dsidev)
413 dsi_runtime_put(dpi.dsidev);
414 err_get_dsi:
415 err_src_sel:
416 dispc_runtime_put();
417 err_get_dispc:
418 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
419 regulator_disable(dpi.vdds_dsi_reg);
420 err_reg_enable:
421 err_no_out_mgr:
422 err_no_reg:
423 mutex_unlock(&dpi.lock);
424 return r;
425 }
426 EXPORT_SYMBOL(omapdss_dpi_display_enable);
427
428 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
429 {
430 struct omap_overlay_manager *mgr = dpi.output.manager;
431
432 mutex_lock(&dpi.lock);
433
434 dss_mgr_disable(mgr);
435
436 if (dpi.dsidev) {
437 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
438 dsi_pll_uninit(dpi.dsidev, true);
439 dsi_runtime_put(dpi.dsidev);
440 }
441
442 dispc_runtime_put();
443
444 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
445 regulator_disable(dpi.vdds_dsi_reg);
446
447 mutex_unlock(&dpi.lock);
448 }
449 EXPORT_SYMBOL(omapdss_dpi_display_disable);
450
451 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
452 struct omap_video_timings *timings)
453 {
454 DSSDBG("dpi_set_timings\n");
455
456 mutex_lock(&dpi.lock);
457
458 dpi.timings = *timings;
459
460 mutex_unlock(&dpi.lock);
461 }
462 EXPORT_SYMBOL(omapdss_dpi_set_timings);
463
464 int dpi_check_timings(struct omap_dss_device *dssdev,
465 struct omap_video_timings *timings)
466 {
467 struct omap_overlay_manager *mgr = dpi.output.manager;
468 int lck_div, pck_div;
469 unsigned long fck;
470 unsigned long pck;
471 struct dpi_clk_calc_ctx ctx;
472 bool ok;
473
474 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
475 return -EINVAL;
476
477 if (timings->pixel_clock == 0)
478 return -EINVAL;
479
480 if (dpi.dsidev) {
481 ok = dpi_dsi_clk_calc(timings->pixel_clock * 1000, &ctx);
482 if (!ok)
483 return -EINVAL;
484
485 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
486 } else {
487 ok = dpi_dss_clk_calc(timings->pixel_clock * 1000, &ctx);
488 if (!ok)
489 return -EINVAL;
490
491 fck = ctx.dss_cinfo.fck;
492 }
493
494 lck_div = ctx.dispc_cinfo.lck_div;
495 pck_div = ctx.dispc_cinfo.pck_div;
496
497 pck = fck / lck_div / pck_div / 1000;
498
499 timings->pixel_clock = pck;
500
501 return 0;
502 }
503 EXPORT_SYMBOL(dpi_check_timings);
504
505 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
506 {
507 mutex_lock(&dpi.lock);
508
509 dpi.data_lines = data_lines;
510
511 mutex_unlock(&dpi.lock);
512 }
513 EXPORT_SYMBOL(omapdss_dpi_set_data_lines);
514
515 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
516 {
517 int r;
518
519 /* do initial setup with the PLL to see if it is operational */
520
521 r = dsi_runtime_get(dsidev);
522 if (r)
523 return r;
524
525 r = dsi_pll_init(dsidev, 0, 1);
526 if (r) {
527 dsi_runtime_put(dsidev);
528 return r;
529 }
530
531 dsi_pll_uninit(dsidev, true);
532 dsi_runtime_put(dsidev);
533
534 return 0;
535 }
536
537 static int dpi_init_regulator(void)
538 {
539 struct regulator *vdds_dsi;
540
541 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
542 return 0;
543
544 if (dpi.vdds_dsi_reg)
545 return 0;
546
547 vdds_dsi = dss_get_vdds_dsi();
548
549 if (IS_ERR(vdds_dsi)) {
550 vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
551 if (IS_ERR(vdds_dsi)) {
552 DSSERR("can't get VDDS_DSI regulator\n");
553 return PTR_ERR(vdds_dsi);
554 }
555 }
556
557 dpi.vdds_dsi_reg = vdds_dsi;
558
559 return 0;
560 }
561
562 static void dpi_init_pll(void)
563 {
564 struct platform_device *dsidev;
565
566 if (dpi.dsidev)
567 return;
568
569 dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
570 if (!dsidev)
571 return;
572
573 if (dpi_verify_dsi_pll(dsidev)) {
574 DSSWARN("DSI PLL not operational\n");
575 return;
576 }
577
578 dpi.dsidev = dsidev;
579 }
580
581 /*
582 * Return a hardcoded channel for the DPI output. This should work for
583 * current use cases, but this can be later expanded to either resolve
584 * the channel in some more dynamic manner, or get the channel as a user
585 * parameter.
586 */
587 static enum omap_channel dpi_get_channel(void)
588 {
589 switch (omapdss_get_version()) {
590 case OMAPDSS_VER_OMAP24xx:
591 case OMAPDSS_VER_OMAP34xx_ES1:
592 case OMAPDSS_VER_OMAP34xx_ES3:
593 case OMAPDSS_VER_OMAP3630:
594 case OMAPDSS_VER_AM35xx:
595 return OMAP_DSS_CHANNEL_LCD;
596
597 case OMAPDSS_VER_OMAP4430_ES1:
598 case OMAPDSS_VER_OMAP4430_ES2:
599 case OMAPDSS_VER_OMAP4:
600 return OMAP_DSS_CHANNEL_LCD2;
601
602 case OMAPDSS_VER_OMAP5:
603 return OMAP_DSS_CHANNEL_LCD3;
604
605 default:
606 DSSWARN("unsupported DSS version\n");
607 return OMAP_DSS_CHANNEL_LCD;
608 }
609 }
610
611 static struct omap_dss_device *dpi_find_dssdev(struct platform_device *pdev)
612 {
613 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
614 const char *def_disp_name = omapdss_get_default_display_name();
615 struct omap_dss_device *def_dssdev;
616 int i;
617
618 def_dssdev = NULL;
619
620 for (i = 0; i < pdata->num_devices; ++i) {
621 struct omap_dss_device *dssdev = pdata->devices[i];
622
623 if (dssdev->type != OMAP_DISPLAY_TYPE_DPI)
624 continue;
625
626 if (def_dssdev == NULL)
627 def_dssdev = dssdev;
628
629 if (def_disp_name != NULL &&
630 strcmp(dssdev->name, def_disp_name) == 0) {
631 def_dssdev = dssdev;
632 break;
633 }
634 }
635
636 return def_dssdev;
637 }
638
639 static int dpi_probe_pdata(struct platform_device *dpidev)
640 {
641 struct omap_dss_device *plat_dssdev;
642 struct omap_dss_device *dssdev;
643 int r;
644
645 plat_dssdev = dpi_find_dssdev(dpidev);
646
647 if (!plat_dssdev)
648 return 0;
649
650 r = dpi_init_regulator();
651 if (r)
652 return r;
653
654 dpi_init_pll();
655
656 dssdev = dss_alloc_and_init_device(&dpidev->dev);
657 if (!dssdev)
658 return -ENOMEM;
659
660 dss_copy_device_pdata(dssdev, plat_dssdev);
661
662 r = omapdss_output_set_device(&dpi.output, dssdev);
663 if (r) {
664 DSSERR("failed to connect output to new device: %s\n",
665 dssdev->name);
666 dss_put_device(dssdev);
667 return r;
668 }
669
670 r = dss_add_device(dssdev);
671 if (r) {
672 DSSERR("device %s register failed: %d\n", dssdev->name, r);
673 omapdss_output_unset_device(&dpi.output);
674 dss_put_device(dssdev);
675 return r;
676 }
677
678 return 0;
679 }
680
681 static void dpi_init_output(struct platform_device *pdev)
682 {
683 struct omap_dss_output *out = &dpi.output;
684
685 out->pdev = pdev;
686 out->id = OMAP_DSS_OUTPUT_DPI;
687 out->type = OMAP_DISPLAY_TYPE_DPI;
688 out->name = "dpi.0";
689 out->dispc_channel = dpi_get_channel();
690
691 dss_register_output(out);
692 }
693
694 static void __exit dpi_uninit_output(struct platform_device *pdev)
695 {
696 struct omap_dss_output *out = &dpi.output;
697
698 dss_unregister_output(out);
699 }
700
701 static int omap_dpi_probe(struct platform_device *pdev)
702 {
703 int r;
704
705 dpi.pdev = pdev;
706
707 mutex_init(&dpi.lock);
708
709 dpi_init_output(pdev);
710
711 if (pdev->dev.platform_data) {
712 r = dpi_probe_pdata(pdev);
713 if (r)
714 goto err_probe;
715 }
716
717 return 0;
718
719 err_probe:
720 dpi_uninit_output(pdev);
721 return r;
722 }
723
724 static int __exit omap_dpi_remove(struct platform_device *pdev)
725 {
726 dss_unregister_child_devices(&pdev->dev);
727
728 dpi_uninit_output(pdev);
729
730 return 0;
731 }
732
733 static struct platform_driver omap_dpi_driver = {
734 .probe = omap_dpi_probe,
735 .remove = __exit_p(omap_dpi_remove),
736 .driver = {
737 .name = "omapdss_dpi",
738 .owner = THIS_MODULE,
739 },
740 };
741
742 int __init dpi_init_platform_driver(void)
743 {
744 return platform_driver_register(&omap_dpi_driver);
745 }
746
747 void __exit dpi_uninit_platform_driver(void)
748 {
749 platform_driver_unregister(&omap_dpi_driver);
750 }
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