2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
46 #include "dss_features.h"
48 #define DSI_CATCH_MISSING_TE
50 struct dsi_reg
{ u16 idx
; };
52 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
54 #define DSI_SZ_REGS SZ_1K
55 /* DSI Protocol Engine */
57 #define DSI_REVISION DSI_REG(0x0000)
58 #define DSI_SYSCONFIG DSI_REG(0x0010)
59 #define DSI_SYSSTATUS DSI_REG(0x0014)
60 #define DSI_IRQSTATUS DSI_REG(0x0018)
61 #define DSI_IRQENABLE DSI_REG(0x001C)
62 #define DSI_CTRL DSI_REG(0x0040)
63 #define DSI_GNQ DSI_REG(0x0044)
64 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
65 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
66 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
67 #define DSI_CLK_CTRL DSI_REG(0x0054)
68 #define DSI_TIMING1 DSI_REG(0x0058)
69 #define DSI_TIMING2 DSI_REG(0x005C)
70 #define DSI_VM_TIMING1 DSI_REG(0x0060)
71 #define DSI_VM_TIMING2 DSI_REG(0x0064)
72 #define DSI_VM_TIMING3 DSI_REG(0x0068)
73 #define DSI_CLK_TIMING DSI_REG(0x006C)
74 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
75 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
76 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
77 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
78 #define DSI_VM_TIMING4 DSI_REG(0x0080)
79 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
80 #define DSI_VM_TIMING5 DSI_REG(0x0088)
81 #define DSI_VM_TIMING6 DSI_REG(0x008C)
82 #define DSI_VM_TIMING7 DSI_REG(0x0090)
83 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
84 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
85 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
86 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
88 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
89 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
90 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
94 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
95 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
96 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
97 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
98 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
100 /* DSI_PLL_CTRL_SCP */
102 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
103 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
104 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
105 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
106 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
108 #define REG_GET(dsidev, idx, start, end) \
109 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
114 /* Global interrupts */
115 #define DSI_IRQ_VC0 (1 << 0)
116 #define DSI_IRQ_VC1 (1 << 1)
117 #define DSI_IRQ_VC2 (1 << 2)
118 #define DSI_IRQ_VC3 (1 << 3)
119 #define DSI_IRQ_WAKEUP (1 << 4)
120 #define DSI_IRQ_RESYNC (1 << 5)
121 #define DSI_IRQ_PLL_LOCK (1 << 7)
122 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
123 #define DSI_IRQ_PLL_RECALL (1 << 9)
124 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
125 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
126 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
127 #define DSI_IRQ_TE_TRIGGER (1 << 16)
128 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
129 #define DSI_IRQ_SYNC_LOST (1 << 18)
130 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
131 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
132 #define DSI_IRQ_ERROR_MASK \
133 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
134 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
135 #define DSI_IRQ_CHANNEL_MASK 0xf
137 /* Virtual channel interrupts */
138 #define DSI_VC_IRQ_CS (1 << 0)
139 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
140 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
141 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
142 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
143 #define DSI_VC_IRQ_BTA (1 << 5)
144 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
145 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
147 #define DSI_VC_IRQ_ERROR_MASK \
148 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
149 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
150 DSI_VC_IRQ_FIFO_TX_UDF)
152 /* ComplexIO interrupts */
153 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
154 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
155 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
156 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
157 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
158 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
159 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
160 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
161 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
162 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
163 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
164 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
165 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
166 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
167 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
168 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
169 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
170 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
171 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
172 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
185 #define DSI_CIO_IRQ_ERROR_MASK \
186 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
187 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
188 DSI_CIO_IRQ_ERRSYNCESC5 | \
189 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
190 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
191 DSI_CIO_IRQ_ERRESC5 | \
192 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
193 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
194 DSI_CIO_IRQ_ERRCONTROL5 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
201 typedef void (*omap_dsi_isr_t
) (void *arg
, u32 mask
);
203 static int dsi_display_init_dispc(struct platform_device
*dsidev
,
204 struct omap_overlay_manager
*mgr
);
205 static void dsi_display_uninit_dispc(struct platform_device
*dsidev
,
206 struct omap_overlay_manager
*mgr
);
208 #define DSI_MAX_NR_ISRS 2
209 #define DSI_MAX_NR_LANES 5
211 enum dsi_lane_function
{
220 struct dsi_lane_config
{
221 enum dsi_lane_function function
;
225 struct dsi_isr_data
{
233 DSI_FIFO_SIZE_32
= 1,
234 DSI_FIFO_SIZE_64
= 2,
235 DSI_FIFO_SIZE_96
= 3,
236 DSI_FIFO_SIZE_128
= 4,
240 DSI_VC_SOURCE_L4
= 0,
244 struct dsi_irq_stats
{
245 unsigned long last_reset
;
247 unsigned dsi_irqs
[32];
248 unsigned vc_irqs
[4][32];
249 unsigned cio_irqs
[32];
252 struct dsi_isr_tables
{
253 struct dsi_isr_data isr_table
[DSI_MAX_NR_ISRS
];
254 struct dsi_isr_data isr_table_vc
[4][DSI_MAX_NR_ISRS
];
255 struct dsi_isr_data isr_table_cio
[DSI_MAX_NR_ISRS
];
258 struct dsi_clk_calc_ctx
{
259 struct platform_device
*dsidev
;
263 const struct omap_dss_dsi_config
*config
;
265 unsigned long req_pck_min
, req_pck_nom
, req_pck_max
;
269 struct dsi_clock_info dsi_cinfo
;
270 struct dispc_clock_info dispc_cinfo
;
272 struct omap_video_timings dispc_vm
;
273 struct omap_dss_dsi_videomode_timings dsi_vm
;
277 struct platform_device
*pdev
;
287 struct dispc_clock_info user_dispc_cinfo
;
288 struct dsi_clock_info user_dsi_cinfo
;
290 struct dsi_clock_info current_cinfo
;
292 bool vdds_dsi_enabled
;
293 struct regulator
*vdds_dsi_reg
;
296 enum dsi_vc_source source
;
297 struct omap_dss_device
*dssdev
;
298 enum fifo_size fifo_size
;
303 struct semaphore bus_lock
;
308 struct dsi_isr_tables isr_tables
;
309 /* space for a copy used by the interrupt handler */
310 struct dsi_isr_tables isr_tables_copy
;
314 unsigned update_bytes
;
320 void (*framedone_callback
)(int, void *);
321 void *framedone_data
;
323 struct delayed_work framedone_timeout_work
;
325 #ifdef DSI_CATCH_MISSING_TE
326 struct timer_list te_timer
;
329 unsigned long cache_req_pck
;
330 unsigned long cache_clk_freq
;
331 struct dsi_clock_info cache_cinfo
;
334 spinlock_t errors_lock
;
336 ktime_t perf_setup_time
;
337 ktime_t perf_start_time
;
342 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
343 spinlock_t irq_stats_lock
;
344 struct dsi_irq_stats irq_stats
;
346 /* DSI PLL Parameter Ranges */
347 unsigned long regm_max
, regn_max
;
348 unsigned long regm_dispc_max
, regm_dsi_max
;
349 unsigned long fint_min
, fint_max
;
350 unsigned long lpdiv_max
;
352 unsigned num_lanes_supported
;
353 unsigned line_buffer_size
;
355 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
356 unsigned num_lanes_used
;
358 unsigned scp_clk_refcount
;
360 struct dss_lcd_mgr_config mgr_config
;
361 struct omap_video_timings timings
;
362 enum omap_dss_dsi_pixel_format pix_fmt
;
363 enum omap_dss_dsi_mode mode
;
364 struct omap_dss_dsi_videomode_timings vm_timings
;
366 struct omap_dss_output output
;
369 struct dsi_packet_sent_handler_data
{
370 struct platform_device
*dsidev
;
371 struct completion
*completion
;
375 static bool dsi_perf
;
376 module_param(dsi_perf
, bool, 0644);
379 static inline struct dsi_data
*dsi_get_dsidrv_data(struct platform_device
*dsidev
)
381 return dev_get_drvdata(&dsidev
->dev
);
384 static inline struct platform_device
*dsi_get_dsidev_from_dssdev(struct omap_dss_device
*dssdev
)
386 return dssdev
->output
->pdev
;
389 struct platform_device
*dsi_get_dsidev_from_id(int module
)
391 struct omap_dss_output
*out
;
392 enum omap_dss_output_id id
;
396 id
= OMAP_DSS_OUTPUT_DSI1
;
399 id
= OMAP_DSS_OUTPUT_DSI2
;
405 out
= omap_dss_get_output(id
);
407 return out
? out
->pdev
: NULL
;
410 static inline void dsi_write_reg(struct platform_device
*dsidev
,
411 const struct dsi_reg idx
, u32 val
)
413 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
415 __raw_writel(val
, dsi
->base
+ idx
.idx
);
418 static inline u32
dsi_read_reg(struct platform_device
*dsidev
,
419 const struct dsi_reg idx
)
421 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
423 return __raw_readl(dsi
->base
+ idx
.idx
);
426 void dsi_bus_lock(struct omap_dss_device
*dssdev
)
428 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
429 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
431 down(&dsi
->bus_lock
);
433 EXPORT_SYMBOL(dsi_bus_lock
);
435 void dsi_bus_unlock(struct omap_dss_device
*dssdev
)
437 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
438 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
442 EXPORT_SYMBOL(dsi_bus_unlock
);
444 static bool dsi_bus_is_locked(struct platform_device
*dsidev
)
446 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
448 return dsi
->bus_lock
.count
== 0;
451 static void dsi_completion_handler(void *data
, u32 mask
)
453 complete((struct completion
*)data
);
456 static inline int wait_for_bit_change(struct platform_device
*dsidev
,
457 const struct dsi_reg idx
, int bitnum
, int value
)
459 unsigned long timeout
;
463 /* first busyloop to see if the bit changes right away */
466 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
470 /* then loop for 500ms, sleeping for 1ms in between */
471 timeout
= jiffies
+ msecs_to_jiffies(500);
472 while (time_before(jiffies
, timeout
)) {
473 if (REG_GET(dsidev
, idx
, bitnum
, bitnum
) == value
)
476 wait
= ns_to_ktime(1000 * 1000);
477 set_current_state(TASK_UNINTERRUPTIBLE
);
478 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
484 u8
dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt
)
487 case OMAP_DSS_DSI_FMT_RGB888
:
488 case OMAP_DSS_DSI_FMT_RGB666
:
490 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
492 case OMAP_DSS_DSI_FMT_RGB565
:
501 static void dsi_perf_mark_setup(struct platform_device
*dsidev
)
503 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
504 dsi
->perf_setup_time
= ktime_get();
507 static void dsi_perf_mark_start(struct platform_device
*dsidev
)
509 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
510 dsi
->perf_start_time
= ktime_get();
513 static void dsi_perf_show(struct platform_device
*dsidev
, const char *name
)
515 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
516 ktime_t t
, setup_time
, trans_time
;
518 u32 setup_us
, trans_us
, total_us
;
525 setup_time
= ktime_sub(dsi
->perf_start_time
, dsi
->perf_setup_time
);
526 setup_us
= (u32
)ktime_to_us(setup_time
);
530 trans_time
= ktime_sub(t
, dsi
->perf_start_time
);
531 trans_us
= (u32
)ktime_to_us(trans_time
);
535 total_us
= setup_us
+ trans_us
;
537 total_bytes
= dsi
->update_bytes
;
539 printk(KERN_INFO
"DSI(%s): %u us + %u us = %u us (%uHz), "
540 "%u bytes, %u kbytes/sec\n",
545 1000*1000 / total_us
,
547 total_bytes
* 1000 / total_us
);
550 static inline void dsi_perf_mark_setup(struct platform_device
*dsidev
)
554 static inline void dsi_perf_mark_start(struct platform_device
*dsidev
)
558 static inline void dsi_perf_show(struct platform_device
*dsidev
,
564 static int verbose_irq
;
566 static void print_irq_status(u32 status
)
571 if (!verbose_irq
&& (status
& ~DSI_IRQ_CHANNEL_MASK
) == 0)
574 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
576 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
578 verbose_irq
? PIS(VC0
) : "",
579 verbose_irq
? PIS(VC1
) : "",
580 verbose_irq
? PIS(VC2
) : "",
581 verbose_irq
? PIS(VC3
) : "",
598 static void print_irq_status_vc(int channel
, u32 status
)
603 if (!verbose_irq
&& (status
& ~DSI_VC_IRQ_PACKET_SENT
) == 0)
606 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
608 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
614 verbose_irq
? PIS(PACKET_SENT
) : "",
619 PIS(PP_BUSY_CHANGE
));
623 static void print_irq_status_cio(u32 status
)
628 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
630 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
644 PIS(ERRCONTENTIONLP0_1
),
645 PIS(ERRCONTENTIONLP1_1
),
646 PIS(ERRCONTENTIONLP0_2
),
647 PIS(ERRCONTENTIONLP1_2
),
648 PIS(ERRCONTENTIONLP0_3
),
649 PIS(ERRCONTENTIONLP1_3
),
650 PIS(ULPSACTIVENOT_ALL0
),
651 PIS(ULPSACTIVENOT_ALL1
));
655 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
656 static void dsi_collect_irq_stats(struct platform_device
*dsidev
, u32 irqstatus
,
657 u32
*vcstatus
, u32 ciostatus
)
659 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
662 spin_lock(&dsi
->irq_stats_lock
);
664 dsi
->irq_stats
.irq_count
++;
665 dss_collect_irq_stats(irqstatus
, dsi
->irq_stats
.dsi_irqs
);
667 for (i
= 0; i
< 4; ++i
)
668 dss_collect_irq_stats(vcstatus
[i
], dsi
->irq_stats
.vc_irqs
[i
]);
670 dss_collect_irq_stats(ciostatus
, dsi
->irq_stats
.cio_irqs
);
672 spin_unlock(&dsi
->irq_stats_lock
);
675 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
678 static int debug_irq
;
680 static void dsi_handle_irq_errors(struct platform_device
*dsidev
, u32 irqstatus
,
681 u32
*vcstatus
, u32 ciostatus
)
683 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
686 if (irqstatus
& DSI_IRQ_ERROR_MASK
) {
687 DSSERR("DSI error, irqstatus %x\n", irqstatus
);
688 print_irq_status(irqstatus
);
689 spin_lock(&dsi
->errors_lock
);
690 dsi
->errors
|= irqstatus
& DSI_IRQ_ERROR_MASK
;
691 spin_unlock(&dsi
->errors_lock
);
692 } else if (debug_irq
) {
693 print_irq_status(irqstatus
);
696 for (i
= 0; i
< 4; ++i
) {
697 if (vcstatus
[i
] & DSI_VC_IRQ_ERROR_MASK
) {
698 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
700 print_irq_status_vc(i
, vcstatus
[i
]);
701 } else if (debug_irq
) {
702 print_irq_status_vc(i
, vcstatus
[i
]);
706 if (ciostatus
& DSI_CIO_IRQ_ERROR_MASK
) {
707 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus
);
708 print_irq_status_cio(ciostatus
);
709 } else if (debug_irq
) {
710 print_irq_status_cio(ciostatus
);
714 static void dsi_call_isrs(struct dsi_isr_data
*isr_array
,
715 unsigned isr_array_size
, u32 irqstatus
)
717 struct dsi_isr_data
*isr_data
;
720 for (i
= 0; i
< isr_array_size
; i
++) {
721 isr_data
= &isr_array
[i
];
722 if (isr_data
->isr
&& isr_data
->mask
& irqstatus
)
723 isr_data
->isr(isr_data
->arg
, irqstatus
);
727 static void dsi_handle_isrs(struct dsi_isr_tables
*isr_tables
,
728 u32 irqstatus
, u32
*vcstatus
, u32 ciostatus
)
732 dsi_call_isrs(isr_tables
->isr_table
,
733 ARRAY_SIZE(isr_tables
->isr_table
),
736 for (i
= 0; i
< 4; ++i
) {
737 if (vcstatus
[i
] == 0)
739 dsi_call_isrs(isr_tables
->isr_table_vc
[i
],
740 ARRAY_SIZE(isr_tables
->isr_table_vc
[i
]),
745 dsi_call_isrs(isr_tables
->isr_table_cio
,
746 ARRAY_SIZE(isr_tables
->isr_table_cio
),
750 static irqreturn_t
omap_dsi_irq_handler(int irq
, void *arg
)
752 struct platform_device
*dsidev
;
753 struct dsi_data
*dsi
;
754 u32 irqstatus
, vcstatus
[4], ciostatus
;
757 dsidev
= (struct platform_device
*) arg
;
758 dsi
= dsi_get_dsidrv_data(dsidev
);
760 spin_lock(&dsi
->irq_lock
);
762 irqstatus
= dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
764 /* IRQ is not for us */
766 spin_unlock(&dsi
->irq_lock
);
770 dsi_write_reg(dsidev
, DSI_IRQSTATUS
, irqstatus
& ~DSI_IRQ_CHANNEL_MASK
);
771 /* flush posted write */
772 dsi_read_reg(dsidev
, DSI_IRQSTATUS
);
774 for (i
= 0; i
< 4; ++i
) {
775 if ((irqstatus
& (1 << i
)) == 0) {
780 vcstatus
[i
] = dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
782 dsi_write_reg(dsidev
, DSI_VC_IRQSTATUS(i
), vcstatus
[i
]);
783 /* flush posted write */
784 dsi_read_reg(dsidev
, DSI_VC_IRQSTATUS(i
));
787 if (irqstatus
& DSI_IRQ_COMPLEXIO_ERR
) {
788 ciostatus
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
790 dsi_write_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
, ciostatus
);
791 /* flush posted write */
792 dsi_read_reg(dsidev
, DSI_COMPLEXIO_IRQ_STATUS
);
797 #ifdef DSI_CATCH_MISSING_TE
798 if (irqstatus
& DSI_IRQ_TE_TRIGGER
)
799 del_timer(&dsi
->te_timer
);
802 /* make a copy and unlock, so that isrs can unregister
804 memcpy(&dsi
->isr_tables_copy
, &dsi
->isr_tables
,
805 sizeof(dsi
->isr_tables
));
807 spin_unlock(&dsi
->irq_lock
);
809 dsi_handle_isrs(&dsi
->isr_tables_copy
, irqstatus
, vcstatus
, ciostatus
);
811 dsi_handle_irq_errors(dsidev
, irqstatus
, vcstatus
, ciostatus
);
813 dsi_collect_irq_stats(dsidev
, irqstatus
, vcstatus
, ciostatus
);
818 /* dsi->irq_lock has to be locked by the caller */
819 static void _omap_dsi_configure_irqs(struct platform_device
*dsidev
,
820 struct dsi_isr_data
*isr_array
,
821 unsigned isr_array_size
, u32 default_mask
,
822 const struct dsi_reg enable_reg
,
823 const struct dsi_reg status_reg
)
825 struct dsi_isr_data
*isr_data
;
832 for (i
= 0; i
< isr_array_size
; i
++) {
833 isr_data
= &isr_array
[i
];
835 if (isr_data
->isr
== NULL
)
838 mask
|= isr_data
->mask
;
841 old_mask
= dsi_read_reg(dsidev
, enable_reg
);
842 /* clear the irqstatus for newly enabled irqs */
843 dsi_write_reg(dsidev
, status_reg
, (mask
^ old_mask
) & mask
);
844 dsi_write_reg(dsidev
, enable_reg
, mask
);
846 /* flush posted writes */
847 dsi_read_reg(dsidev
, enable_reg
);
848 dsi_read_reg(dsidev
, status_reg
);
851 /* dsi->irq_lock has to be locked by the caller */
852 static void _omap_dsi_set_irqs(struct platform_device
*dsidev
)
854 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
855 u32 mask
= DSI_IRQ_ERROR_MASK
;
856 #ifdef DSI_CATCH_MISSING_TE
857 mask
|= DSI_IRQ_TE_TRIGGER
;
859 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table
,
860 ARRAY_SIZE(dsi
->isr_tables
.isr_table
), mask
,
861 DSI_IRQENABLE
, DSI_IRQSTATUS
);
864 /* dsi->irq_lock has to be locked by the caller */
865 static void _omap_dsi_set_irqs_vc(struct platform_device
*dsidev
, int vc
)
867 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
869 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_vc
[vc
],
870 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[vc
]),
871 DSI_VC_IRQ_ERROR_MASK
,
872 DSI_VC_IRQENABLE(vc
), DSI_VC_IRQSTATUS(vc
));
875 /* dsi->irq_lock has to be locked by the caller */
876 static void _omap_dsi_set_irqs_cio(struct platform_device
*dsidev
)
878 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
880 _omap_dsi_configure_irqs(dsidev
, dsi
->isr_tables
.isr_table_cio
,
881 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
),
882 DSI_CIO_IRQ_ERROR_MASK
,
883 DSI_COMPLEXIO_IRQ_ENABLE
, DSI_COMPLEXIO_IRQ_STATUS
);
886 static void _dsi_initialize_irq(struct platform_device
*dsidev
)
888 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
892 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
894 memset(&dsi
->isr_tables
, 0, sizeof(dsi
->isr_tables
));
896 _omap_dsi_set_irqs(dsidev
);
897 for (vc
= 0; vc
< 4; ++vc
)
898 _omap_dsi_set_irqs_vc(dsidev
, vc
);
899 _omap_dsi_set_irqs_cio(dsidev
);
901 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
904 static int _dsi_register_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
905 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
907 struct dsi_isr_data
*isr_data
;
913 /* check for duplicate entry and find a free slot */
915 for (i
= 0; i
< isr_array_size
; i
++) {
916 isr_data
= &isr_array
[i
];
918 if (isr_data
->isr
== isr
&& isr_data
->arg
== arg
&&
919 isr_data
->mask
== mask
) {
923 if (isr_data
->isr
== NULL
&& free_idx
== -1)
930 isr_data
= &isr_array
[free_idx
];
933 isr_data
->mask
= mask
;
938 static int _dsi_unregister_isr(omap_dsi_isr_t isr
, void *arg
, u32 mask
,
939 struct dsi_isr_data
*isr_array
, unsigned isr_array_size
)
941 struct dsi_isr_data
*isr_data
;
944 for (i
= 0; i
< isr_array_size
; i
++) {
945 isr_data
= &isr_array
[i
];
946 if (isr_data
->isr
!= isr
|| isr_data
->arg
!= arg
||
947 isr_data
->mask
!= mask
)
950 isr_data
->isr
= NULL
;
951 isr_data
->arg
= NULL
;
960 static int dsi_register_isr(struct platform_device
*dsidev
, omap_dsi_isr_t isr
,
963 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
967 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
969 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
970 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
973 _omap_dsi_set_irqs(dsidev
);
975 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
980 static int dsi_unregister_isr(struct platform_device
*dsidev
,
981 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
983 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
987 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
989 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table
,
990 ARRAY_SIZE(dsi
->isr_tables
.isr_table
));
993 _omap_dsi_set_irqs(dsidev
);
995 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1000 static int dsi_register_isr_vc(struct platform_device
*dsidev
, int channel
,
1001 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1003 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1004 unsigned long flags
;
1007 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1009 r
= _dsi_register_isr(isr
, arg
, mask
,
1010 dsi
->isr_tables
.isr_table_vc
[channel
],
1011 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
1014 _omap_dsi_set_irqs_vc(dsidev
, channel
);
1016 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1021 static int dsi_unregister_isr_vc(struct platform_device
*dsidev
, int channel
,
1022 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1024 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1025 unsigned long flags
;
1028 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1030 r
= _dsi_unregister_isr(isr
, arg
, mask
,
1031 dsi
->isr_tables
.isr_table_vc
[channel
],
1032 ARRAY_SIZE(dsi
->isr_tables
.isr_table_vc
[channel
]));
1035 _omap_dsi_set_irqs_vc(dsidev
, channel
);
1037 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1042 static int dsi_register_isr_cio(struct platform_device
*dsidev
,
1043 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1045 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1046 unsigned long flags
;
1049 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1051 r
= _dsi_register_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1052 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1055 _omap_dsi_set_irqs_cio(dsidev
);
1057 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1062 static int dsi_unregister_isr_cio(struct platform_device
*dsidev
,
1063 omap_dsi_isr_t isr
, void *arg
, u32 mask
)
1065 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1066 unsigned long flags
;
1069 spin_lock_irqsave(&dsi
->irq_lock
, flags
);
1071 r
= _dsi_unregister_isr(isr
, arg
, mask
, dsi
->isr_tables
.isr_table_cio
,
1072 ARRAY_SIZE(dsi
->isr_tables
.isr_table_cio
));
1075 _omap_dsi_set_irqs_cio(dsidev
);
1077 spin_unlock_irqrestore(&dsi
->irq_lock
, flags
);
1082 static u32
dsi_get_errors(struct platform_device
*dsidev
)
1084 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1085 unsigned long flags
;
1087 spin_lock_irqsave(&dsi
->errors_lock
, flags
);
1090 spin_unlock_irqrestore(&dsi
->errors_lock
, flags
);
1094 int dsi_runtime_get(struct platform_device
*dsidev
)
1097 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1099 DSSDBG("dsi_runtime_get\n");
1101 r
= pm_runtime_get_sync(&dsi
->pdev
->dev
);
1103 return r
< 0 ? r
: 0;
1106 void dsi_runtime_put(struct platform_device
*dsidev
)
1108 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1111 DSSDBG("dsi_runtime_put\n");
1113 r
= pm_runtime_put_sync(&dsi
->pdev
->dev
);
1114 WARN_ON(r
< 0 && r
!= -ENOSYS
);
1117 static int dsi_regulator_init(struct platform_device
*dsidev
)
1119 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1120 struct regulator
*vdds_dsi
;
1122 if (dsi
->vdds_dsi_reg
!= NULL
)
1125 vdds_dsi
= devm_regulator_get(&dsi
->pdev
->dev
, "vdds_dsi");
1127 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1128 if (IS_ERR(vdds_dsi
))
1129 vdds_dsi
= devm_regulator_get(&dsi
->pdev
->dev
, "VCXIO");
1131 if (IS_ERR(vdds_dsi
)) {
1132 DSSERR("can't get VDDS_DSI regulator\n");
1133 return PTR_ERR(vdds_dsi
);
1136 dsi
->vdds_dsi_reg
= vdds_dsi
;
1141 /* source clock for DSI PLL. this could also be PCLKFREE */
1142 static inline void dsi_enable_pll_clock(struct platform_device
*dsidev
,
1145 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1148 clk_prepare_enable(dsi
->sys_clk
);
1150 clk_disable_unprepare(dsi
->sys_clk
);
1152 if (enable
&& dsi
->pll_locked
) {
1153 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1)
1154 DSSERR("cannot lock PLL when enabling clocks\n");
1158 static void _dsi_print_reset_status(struct platform_device
*dsidev
)
1163 /* A dummy read using the SCP interface to any DSIPHY register is
1164 * required after DSIPHY reset to complete the reset of the DSI complex
1166 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
1168 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
)) {
1178 #define DSI_FLD_GET(fld, start, end)\
1179 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1181 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1182 DSI_FLD_GET(PLL_STATUS
, 0, 0),
1183 DSI_FLD_GET(COMPLEXIO_CFG1
, 29, 29),
1184 DSI_FLD_GET(DSIPHY_CFG5
, b0
, b0
),
1185 DSI_FLD_GET(DSIPHY_CFG5
, b1
, b1
),
1186 DSI_FLD_GET(DSIPHY_CFG5
, b2
, b2
),
1187 DSI_FLD_GET(DSIPHY_CFG5
, 29, 29),
1188 DSI_FLD_GET(DSIPHY_CFG5
, 30, 30),
1189 DSI_FLD_GET(DSIPHY_CFG5
, 31, 31));
1194 static inline int dsi_if_enable(struct platform_device
*dsidev
, bool enable
)
1196 DSSDBG("dsi_if_enable(%d)\n", enable
);
1198 enable
= enable
? 1 : 0;
1199 REG_FLD_MOD(dsidev
, DSI_CTRL
, enable
, 0, 0); /* IF_EN */
1201 if (wait_for_bit_change(dsidev
, DSI_CTRL
, 0, enable
) != enable
) {
1202 DSSERR("Failed to set dsi_if_enable to %d\n", enable
);
1209 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device
*dsidev
)
1211 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1213 return dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
;
1216 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device
*dsidev
)
1218 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1220 return dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
;
1223 static unsigned long dsi_get_txbyteclkhs(struct platform_device
*dsidev
)
1225 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1227 return dsi
->current_cinfo
.clkin4ddr
/ 16;
1230 static unsigned long dsi_fclk_rate(struct platform_device
*dsidev
)
1233 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1235 if (dss_get_dsi_clk_source(dsi
->module_id
) == OMAP_DSS_CLK_SRC_FCK
) {
1236 /* DSI FCLK source is DSS_CLK_FCK */
1237 r
= clk_get_rate(dsi
->dss_clk
);
1239 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1240 r
= dsi_get_pll_hsdiv_dsi_rate(dsidev
);
1246 static int dsi_lp_clock_calc(struct dsi_clock_info
*cinfo
,
1247 unsigned long lp_clk_min
, unsigned long lp_clk_max
)
1249 unsigned long dsi_fclk
= cinfo
->dsi_pll_hsdiv_dsi_clk
;
1250 unsigned lp_clk_div
;
1251 unsigned long lp_clk
;
1253 lp_clk_div
= DIV_ROUND_UP(dsi_fclk
, lp_clk_max
* 2);
1254 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1256 if (lp_clk
< lp_clk_min
|| lp_clk
> lp_clk_max
)
1259 cinfo
->lp_clk_div
= lp_clk_div
;
1260 cinfo
->lp_clk
= lp_clk
;
1265 static int dsi_set_lp_clk_divisor(struct platform_device
*dsidev
)
1267 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1268 unsigned long dsi_fclk
;
1269 unsigned lp_clk_div
;
1270 unsigned long lp_clk
;
1272 lp_clk_div
= dsi
->user_dsi_cinfo
.lp_clk_div
;
1274 if (lp_clk_div
== 0 || lp_clk_div
> dsi
->lpdiv_max
)
1277 dsi_fclk
= dsi_fclk_rate(dsidev
);
1279 lp_clk
= dsi_fclk
/ 2 / lp_clk_div
;
1281 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div
, lp_clk
);
1282 dsi
->current_cinfo
.lp_clk
= lp_clk
;
1283 dsi
->current_cinfo
.lp_clk_div
= lp_clk_div
;
1285 /* LP_CLK_DIVISOR */
1286 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, lp_clk_div
, 12, 0);
1288 /* LP_RX_SYNCHRO_ENABLE */
1289 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, dsi_fclk
> 30000000 ? 1 : 0, 21, 21);
1294 static void dsi_enable_scp_clk(struct platform_device
*dsidev
)
1296 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1298 if (dsi
->scp_clk_refcount
++ == 0)
1299 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 14, 14); /* CIO_CLK_ICG */
1302 static void dsi_disable_scp_clk(struct platform_device
*dsidev
)
1304 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1306 WARN_ON(dsi
->scp_clk_refcount
== 0);
1307 if (--dsi
->scp_clk_refcount
== 0)
1308 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 14, 14); /* CIO_CLK_ICG */
1311 enum dsi_pll_power_state
{
1312 DSI_PLL_POWER_OFF
= 0x0,
1313 DSI_PLL_POWER_ON_HSCLK
= 0x1,
1314 DSI_PLL_POWER_ON_ALL
= 0x2,
1315 DSI_PLL_POWER_ON_DIV
= 0x3,
1318 static int dsi_pll_power(struct platform_device
*dsidev
,
1319 enum dsi_pll_power_state state
)
1323 /* DSI-PLL power command 0x3 is not working */
1324 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG
) &&
1325 state
== DSI_PLL_POWER_ON_DIV
)
1326 state
= DSI_PLL_POWER_ON_ALL
;
1329 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, state
, 31, 30);
1331 /* PLL_PWR_STATUS */
1332 while (FLD_GET(dsi_read_reg(dsidev
, DSI_CLK_CTRL
), 29, 28) != state
) {
1334 DSSERR("Failed to set DSI PLL power mode to %d\n",
1344 unsigned long dsi_get_pll_clkin(struct platform_device
*dsidev
)
1346 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1347 return clk_get_rate(dsi
->sys_clk
);
1350 bool dsi_hsdiv_calc(struct platform_device
*dsidev
, unsigned long pll
,
1351 unsigned long out_min
, dsi_hsdiv_calc_func func
, void *data
)
1353 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1354 int regm
, regm_start
, regm_stop
;
1355 unsigned long out_max
;
1358 out_min
= out_min
? out_min
: 1;
1359 out_max
= dss_feat_get_param_max(FEAT_PARAM_DSS_FCK
);
1361 regm_start
= max(DIV_ROUND_UP(pll
, out_max
), 1ul);
1362 regm_stop
= min(pll
/ out_min
, dsi
->regm_dispc_max
);
1364 for (regm
= regm_start
; regm
<= regm_stop
; ++regm
) {
1367 if (func(regm
, out
, data
))
1374 bool dsi_pll_calc(struct platform_device
*dsidev
, unsigned long clkin
,
1375 unsigned long pll_min
, unsigned long pll_max
,
1376 dsi_pll_calc_func func
, void *data
)
1378 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1379 int regn
, regn_start
, regn_stop
;
1380 int regm
, regm_start
, regm_stop
;
1381 unsigned long fint
, pll
;
1382 const unsigned long pll_hw_max
= 1800000000;
1383 unsigned long fint_hw_min
, fint_hw_max
;
1385 fint_hw_min
= dsi
->fint_min
;
1386 fint_hw_max
= dsi
->fint_max
;
1388 regn_start
= max(DIV_ROUND_UP(clkin
, fint_hw_max
), 1ul);
1389 regn_stop
= min(clkin
/ fint_hw_min
, dsi
->regn_max
);
1391 pll_max
= pll_max
? pll_max
: ULONG_MAX
;
1393 for (regn
= regn_start
; regn
<= regn_stop
; ++regn
) {
1394 fint
= clkin
/ regn
;
1396 regm_start
= max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min
, fint
), 2),
1398 regm_stop
= min3(pll_max
/ fint
/ 2,
1399 pll_hw_max
/ fint
/ 2,
1402 for (regm
= regm_start
; regm
<= regm_stop
; ++regm
) {
1403 pll
= 2 * regm
* fint
;
1405 if (func(regn
, regm
, fint
, pll
, data
))
1413 /* calculate clock rates using dividers in cinfo */
1414 static int dsi_calc_clock_rates(struct platform_device
*dsidev
,
1415 struct dsi_clock_info
*cinfo
)
1417 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1419 if (cinfo
->regn
== 0 || cinfo
->regn
> dsi
->regn_max
)
1422 if (cinfo
->regm
== 0 || cinfo
->regm
> dsi
->regm_max
)
1425 if (cinfo
->regm_dispc
> dsi
->regm_dispc_max
)
1428 if (cinfo
->regm_dsi
> dsi
->regm_dsi_max
)
1431 cinfo
->clkin
= clk_get_rate(dsi
->sys_clk
);
1432 cinfo
->fint
= cinfo
->clkin
/ cinfo
->regn
;
1434 if (cinfo
->fint
> dsi
->fint_max
|| cinfo
->fint
< dsi
->fint_min
)
1437 cinfo
->clkin4ddr
= 2 * cinfo
->regm
* cinfo
->fint
;
1439 if (cinfo
->clkin4ddr
> 1800 * 1000 * 1000)
1442 if (cinfo
->regm_dispc
> 0)
1443 cinfo
->dsi_pll_hsdiv_dispc_clk
=
1444 cinfo
->clkin4ddr
/ cinfo
->regm_dispc
;
1446 cinfo
->dsi_pll_hsdiv_dispc_clk
= 0;
1448 if (cinfo
->regm_dsi
> 0)
1449 cinfo
->dsi_pll_hsdiv_dsi_clk
=
1450 cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1452 cinfo
->dsi_pll_hsdiv_dsi_clk
= 0;
1457 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info
*cinfo
)
1459 unsigned long max_dsi_fck
;
1461 max_dsi_fck
= dss_feat_get_param_max(FEAT_PARAM_DSI_FCK
);
1463 cinfo
->regm_dsi
= DIV_ROUND_UP(cinfo
->clkin4ddr
, max_dsi_fck
);
1464 cinfo
->dsi_pll_hsdiv_dsi_clk
= cinfo
->clkin4ddr
/ cinfo
->regm_dsi
;
1467 int dsi_pll_set_clock_div(struct platform_device
*dsidev
,
1468 struct dsi_clock_info
*cinfo
)
1470 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1474 u8 regn_start
, regn_end
, regm_start
, regm_end
;
1475 u8 regm_dispc_start
, regm_dispc_end
, regm_dsi_start
, regm_dsi_end
;
1477 DSSDBG("DSI PLL clock config starts");
1479 dsi
->current_cinfo
.clkin
= cinfo
->clkin
;
1480 dsi
->current_cinfo
.fint
= cinfo
->fint
;
1481 dsi
->current_cinfo
.clkin4ddr
= cinfo
->clkin4ddr
;
1482 dsi
->current_cinfo
.dsi_pll_hsdiv_dispc_clk
=
1483 cinfo
->dsi_pll_hsdiv_dispc_clk
;
1484 dsi
->current_cinfo
.dsi_pll_hsdiv_dsi_clk
=
1485 cinfo
->dsi_pll_hsdiv_dsi_clk
;
1487 dsi
->current_cinfo
.regn
= cinfo
->regn
;
1488 dsi
->current_cinfo
.regm
= cinfo
->regm
;
1489 dsi
->current_cinfo
.regm_dispc
= cinfo
->regm_dispc
;
1490 dsi
->current_cinfo
.regm_dsi
= cinfo
->regm_dsi
;
1492 DSSDBG("DSI Fint %ld\n", cinfo
->fint
);
1494 DSSDBG("clkin rate %ld\n", cinfo
->clkin
);
1496 /* DSIPHY == CLKIN4DDR */
1497 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1503 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1504 cinfo
->clkin4ddr
/ 1000 / 1000 / 2);
1506 DSSDBG("Clock lane freq %ld Hz\n", cinfo
->clkin4ddr
/ 4);
1508 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo
->regm_dispc
,
1509 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1510 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
1511 cinfo
->dsi_pll_hsdiv_dispc_clk
);
1512 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo
->regm_dsi
,
1513 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1514 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
1515 cinfo
->dsi_pll_hsdiv_dsi_clk
);
1517 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN
, ®n_start
, ®n_end
);
1518 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM
, ®m_start
, ®m_end
);
1519 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC
, ®m_dispc_start
,
1521 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI
, ®m_dsi_start
,
1524 /* DSI_PLL_AUTOMODE = manual */
1525 REG_FLD_MOD(dsidev
, DSI_PLL_CONTROL
, 0, 0, 0);
1527 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION1
);
1528 l
= FLD_MOD(l
, 1, 0, 0); /* DSI_PLL_STOPMODE */
1530 l
= FLD_MOD(l
, cinfo
->regn
- 1, regn_start
, regn_end
);
1532 l
= FLD_MOD(l
, cinfo
->regm
, regm_start
, regm_end
);
1534 l
= FLD_MOD(l
, cinfo
->regm_dispc
> 0 ? cinfo
->regm_dispc
- 1 : 0,
1535 regm_dispc_start
, regm_dispc_end
);
1536 /* DSIPROTO_CLOCK_DIV */
1537 l
= FLD_MOD(l
, cinfo
->regm_dsi
> 0 ? cinfo
->regm_dsi
- 1 : 0,
1538 regm_dsi_start
, regm_dsi_end
);
1539 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION1
, l
);
1541 BUG_ON(cinfo
->fint
< dsi
->fint_min
|| cinfo
->fint
> dsi
->fint_max
);
1543 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1545 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL
)) {
1546 f
= cinfo
->fint
< 1000000 ? 0x3 :
1547 cinfo
->fint
< 1250000 ? 0x4 :
1548 cinfo
->fint
< 1500000 ? 0x5 :
1549 cinfo
->fint
< 1750000 ? 0x6 :
1552 l
= FLD_MOD(l
, f
, 4, 1); /* DSI_PLL_FREQSEL */
1553 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO
)) {
1554 f
= cinfo
->clkin4ddr
< 1000000000 ? 0x2 : 0x4;
1556 l
= FLD_MOD(l
, f
, 4, 1); /* PLL_SELFREQDCO */
1559 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1560 l
= FLD_MOD(l
, 0, 14, 14); /* DSIPHY_CLKINEN */
1561 l
= FLD_MOD(l
, 1, 20, 20); /* DSI_HSDIVBYPASS */
1562 if (dss_has_feature(FEAT_DSI_PLL_REFSEL
))
1563 l
= FLD_MOD(l
, 3, 22, 21); /* REF_SYSCLK = sysclk */
1564 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1566 REG_FLD_MOD(dsidev
, DSI_PLL_GO
, 1, 0, 0); /* DSI_PLL_GO */
1568 if (wait_for_bit_change(dsidev
, DSI_PLL_GO
, 0, 0) != 0) {
1569 DSSERR("dsi pll go bit not going down.\n");
1574 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 1, 1) != 1) {
1575 DSSERR("cannot lock PLL\n");
1580 dsi
->pll_locked
= 1;
1582 l
= dsi_read_reg(dsidev
, DSI_PLL_CONFIGURATION2
);
1583 l
= FLD_MOD(l
, 0, 0, 0); /* DSI_PLL_IDLE */
1584 l
= FLD_MOD(l
, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1585 l
= FLD_MOD(l
, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1586 l
= FLD_MOD(l
, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1587 l
= FLD_MOD(l
, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1588 l
= FLD_MOD(l
, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1589 l
= FLD_MOD(l
, 1, 13, 13); /* DSI_PLL_REFEN */
1590 l
= FLD_MOD(l
, 1, 14, 14); /* DSIPHY_CLKINEN */
1591 l
= FLD_MOD(l
, 0, 15, 15); /* DSI_BYPASSEN */
1592 l
= FLD_MOD(l
, 1, 16, 16); /* DSS_CLOCK_EN */
1593 l
= FLD_MOD(l
, 0, 17, 17); /* DSS_CLOCK_PWDN */
1594 l
= FLD_MOD(l
, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1595 l
= FLD_MOD(l
, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1596 l
= FLD_MOD(l
, 0, 20, 20); /* DSI_HSDIVBYPASS */
1597 dsi_write_reg(dsidev
, DSI_PLL_CONFIGURATION2
, l
);
1599 DSSDBG("PLL config done\n");
1604 int dsi_pll_init(struct platform_device
*dsidev
, bool enable_hsclk
,
1607 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1609 enum dsi_pll_power_state pwstate
;
1611 DSSDBG("PLL init\n");
1614 * It seems that on many OMAPs we need to enable both to have a
1615 * functional HSDivider.
1617 enable_hsclk
= enable_hsdiv
= true;
1619 r
= dsi_regulator_init(dsidev
);
1623 dsi_enable_pll_clock(dsidev
, 1);
1625 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1627 dsi_enable_scp_clk(dsidev
);
1629 if (!dsi
->vdds_dsi_enabled
) {
1630 r
= regulator_enable(dsi
->vdds_dsi_reg
);
1633 dsi
->vdds_dsi_enabled
= true;
1636 /* XXX PLL does not come out of reset without this... */
1637 dispc_pck_free_enable(1);
1639 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 0, 1) != 1) {
1640 DSSERR("PLL not coming out of reset.\n");
1642 dispc_pck_free_enable(0);
1646 /* XXX ... but if left on, we get problems when planes do not
1647 * fill the whole display. No idea about this */
1648 dispc_pck_free_enable(0);
1650 if (enable_hsclk
&& enable_hsdiv
)
1651 pwstate
= DSI_PLL_POWER_ON_ALL
;
1652 else if (enable_hsclk
)
1653 pwstate
= DSI_PLL_POWER_ON_HSCLK
;
1654 else if (enable_hsdiv
)
1655 pwstate
= DSI_PLL_POWER_ON_DIV
;
1657 pwstate
= DSI_PLL_POWER_OFF
;
1659 r
= dsi_pll_power(dsidev
, pwstate
);
1664 DSSDBG("PLL init done\n");
1668 if (dsi
->vdds_dsi_enabled
) {
1669 regulator_disable(dsi
->vdds_dsi_reg
);
1670 dsi
->vdds_dsi_enabled
= false;
1673 dsi_disable_scp_clk(dsidev
);
1674 dsi_enable_pll_clock(dsidev
, 0);
1678 void dsi_pll_uninit(struct platform_device
*dsidev
, bool disconnect_lanes
)
1680 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1682 dsi
->pll_locked
= 0;
1683 dsi_pll_power(dsidev
, DSI_PLL_POWER_OFF
);
1684 if (disconnect_lanes
) {
1685 WARN_ON(!dsi
->vdds_dsi_enabled
);
1686 regulator_disable(dsi
->vdds_dsi_reg
);
1687 dsi
->vdds_dsi_enabled
= false;
1690 dsi_disable_scp_clk(dsidev
);
1691 dsi_enable_pll_clock(dsidev
, 0);
1693 DSSDBG("PLL uninit done\n");
1696 static void dsi_dump_dsidev_clocks(struct platform_device
*dsidev
,
1699 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1700 struct dsi_clock_info
*cinfo
= &dsi
->current_cinfo
;
1701 enum omap_dss_clk_source dispc_clk_src
, dsi_clk_src
;
1702 int dsi_module
= dsi
->module_id
;
1704 dispc_clk_src
= dss_get_dispc_clk_source();
1705 dsi_clk_src
= dss_get_dsi_clk_source(dsi_module
);
1707 if (dsi_runtime_get(dsidev
))
1710 seq_printf(s
, "- DSI%d PLL -\n", dsi_module
+ 1);
1712 seq_printf(s
, "dsi pll clkin\t%lu\n", cinfo
->clkin
);
1714 seq_printf(s
, "Fint\t\t%-16luregn %u\n", cinfo
->fint
, cinfo
->regn
);
1716 seq_printf(s
, "CLKIN4DDR\t%-16luregm %u\n",
1717 cinfo
->clkin4ddr
, cinfo
->regm
);
1719 seq_printf(s
, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1720 dss_feat_get_clk_source_name(dsi_module
== 0 ?
1721 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
1722 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
),
1723 cinfo
->dsi_pll_hsdiv_dispc_clk
,
1725 dispc_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1728 seq_printf(s
, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1729 dss_feat_get_clk_source_name(dsi_module
== 0 ?
1730 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
:
1731 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
),
1732 cinfo
->dsi_pll_hsdiv_dsi_clk
,
1734 dsi_clk_src
== OMAP_DSS_CLK_SRC_FCK
?
1737 seq_printf(s
, "- DSI%d -\n", dsi_module
+ 1);
1739 seq_printf(s
, "dsi fclk source = %s (%s)\n",
1740 dss_get_generic_clk_source_name(dsi_clk_src
),
1741 dss_feat_get_clk_source_name(dsi_clk_src
));
1743 seq_printf(s
, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev
));
1745 seq_printf(s
, "DDR_CLK\t\t%lu\n",
1746 cinfo
->clkin4ddr
/ 4);
1748 seq_printf(s
, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev
));
1750 seq_printf(s
, "LP_CLK\t\t%lu\n", cinfo
->lp_clk
);
1752 dsi_runtime_put(dsidev
);
1755 void dsi_dump_clocks(struct seq_file
*s
)
1757 struct platform_device
*dsidev
;
1760 for (i
= 0; i
< MAX_NUM_DSI
; i
++) {
1761 dsidev
= dsi_get_dsidev_from_id(i
);
1763 dsi_dump_dsidev_clocks(dsidev
, s
);
1767 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1768 static void dsi_dump_dsidev_irqs(struct platform_device
*dsidev
,
1771 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
1772 unsigned long flags
;
1773 struct dsi_irq_stats stats
;
1775 spin_lock_irqsave(&dsi
->irq_stats_lock
, flags
);
1777 stats
= dsi
->irq_stats
;
1778 memset(&dsi
->irq_stats
, 0, sizeof(dsi
->irq_stats
));
1779 dsi
->irq_stats
.last_reset
= jiffies
;
1781 spin_unlock_irqrestore(&dsi
->irq_stats_lock
, flags
);
1783 seq_printf(s
, "period %u ms\n",
1784 jiffies_to_msecs(jiffies
- stats
.last_reset
));
1786 seq_printf(s
, "irqs %d\n", stats
.irq_count
);
1788 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1790 seq_printf(s
, "-- DSI%d interrupts --\n", dsi
->module_id
+ 1);
1806 PIS(LDO_POWER_GOOD
);
1811 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1812 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1813 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1814 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1815 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1817 seq_printf(s
, "-- VC interrupts --\n");
1826 PIS(PP_BUSY_CHANGE
);
1830 seq_printf(s, "%-20s %10d\n", #x, \
1831 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1833 seq_printf(s
, "-- CIO interrupts --\n");
1846 PIS(ERRCONTENTIONLP0_1
);
1847 PIS(ERRCONTENTIONLP1_1
);
1848 PIS(ERRCONTENTIONLP0_2
);
1849 PIS(ERRCONTENTIONLP1_2
);
1850 PIS(ERRCONTENTIONLP0_3
);
1851 PIS(ERRCONTENTIONLP1_3
);
1852 PIS(ULPSACTIVENOT_ALL0
);
1853 PIS(ULPSACTIVENOT_ALL1
);
1857 static void dsi1_dump_irqs(struct seq_file
*s
)
1859 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1861 dsi_dump_dsidev_irqs(dsidev
, s
);
1864 static void dsi2_dump_irqs(struct seq_file
*s
)
1866 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1868 dsi_dump_dsidev_irqs(dsidev
, s
);
1872 static void dsi_dump_dsidev_regs(struct platform_device
*dsidev
,
1875 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1877 if (dsi_runtime_get(dsidev
))
1879 dsi_enable_scp_clk(dsidev
);
1881 DUMPREG(DSI_REVISION
);
1882 DUMPREG(DSI_SYSCONFIG
);
1883 DUMPREG(DSI_SYSSTATUS
);
1884 DUMPREG(DSI_IRQSTATUS
);
1885 DUMPREG(DSI_IRQENABLE
);
1887 DUMPREG(DSI_COMPLEXIO_CFG1
);
1888 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS
);
1889 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE
);
1890 DUMPREG(DSI_CLK_CTRL
);
1891 DUMPREG(DSI_TIMING1
);
1892 DUMPREG(DSI_TIMING2
);
1893 DUMPREG(DSI_VM_TIMING1
);
1894 DUMPREG(DSI_VM_TIMING2
);
1895 DUMPREG(DSI_VM_TIMING3
);
1896 DUMPREG(DSI_CLK_TIMING
);
1897 DUMPREG(DSI_TX_FIFO_VC_SIZE
);
1898 DUMPREG(DSI_RX_FIFO_VC_SIZE
);
1899 DUMPREG(DSI_COMPLEXIO_CFG2
);
1900 DUMPREG(DSI_RX_FIFO_VC_FULLNESS
);
1901 DUMPREG(DSI_VM_TIMING4
);
1902 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS
);
1903 DUMPREG(DSI_VM_TIMING5
);
1904 DUMPREG(DSI_VM_TIMING6
);
1905 DUMPREG(DSI_VM_TIMING7
);
1906 DUMPREG(DSI_STOPCLK_TIMING
);
1908 DUMPREG(DSI_VC_CTRL(0));
1909 DUMPREG(DSI_VC_TE(0));
1910 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1911 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1912 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1913 DUMPREG(DSI_VC_IRQSTATUS(0));
1914 DUMPREG(DSI_VC_IRQENABLE(0));
1916 DUMPREG(DSI_VC_CTRL(1));
1917 DUMPREG(DSI_VC_TE(1));
1918 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1919 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1920 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1921 DUMPREG(DSI_VC_IRQSTATUS(1));
1922 DUMPREG(DSI_VC_IRQENABLE(1));
1924 DUMPREG(DSI_VC_CTRL(2));
1925 DUMPREG(DSI_VC_TE(2));
1926 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1927 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1928 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1929 DUMPREG(DSI_VC_IRQSTATUS(2));
1930 DUMPREG(DSI_VC_IRQENABLE(2));
1932 DUMPREG(DSI_VC_CTRL(3));
1933 DUMPREG(DSI_VC_TE(3));
1934 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1935 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1936 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1937 DUMPREG(DSI_VC_IRQSTATUS(3));
1938 DUMPREG(DSI_VC_IRQENABLE(3));
1940 DUMPREG(DSI_DSIPHY_CFG0
);
1941 DUMPREG(DSI_DSIPHY_CFG1
);
1942 DUMPREG(DSI_DSIPHY_CFG2
);
1943 DUMPREG(DSI_DSIPHY_CFG5
);
1945 DUMPREG(DSI_PLL_CONTROL
);
1946 DUMPREG(DSI_PLL_STATUS
);
1947 DUMPREG(DSI_PLL_GO
);
1948 DUMPREG(DSI_PLL_CONFIGURATION1
);
1949 DUMPREG(DSI_PLL_CONFIGURATION2
);
1951 dsi_disable_scp_clk(dsidev
);
1952 dsi_runtime_put(dsidev
);
1956 static void dsi1_dump_regs(struct seq_file
*s
)
1958 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(0);
1960 dsi_dump_dsidev_regs(dsidev
, s
);
1963 static void dsi2_dump_regs(struct seq_file
*s
)
1965 struct platform_device
*dsidev
= dsi_get_dsidev_from_id(1);
1967 dsi_dump_dsidev_regs(dsidev
, s
);
1970 enum dsi_cio_power_state
{
1971 DSI_COMPLEXIO_POWER_OFF
= 0x0,
1972 DSI_COMPLEXIO_POWER_ON
= 0x1,
1973 DSI_COMPLEXIO_POWER_ULPS
= 0x2,
1976 static int dsi_cio_power(struct platform_device
*dsidev
,
1977 enum dsi_cio_power_state state
)
1982 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG1
, state
, 28, 27);
1985 while (FLD_GET(dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
),
1988 DSSERR("failed to set complexio power state to "
1998 static unsigned dsi_get_line_buf_size(struct platform_device
*dsidev
)
2002 /* line buffer on OMAP3 is 1024 x 24bits */
2003 /* XXX: for some reason using full buffer size causes
2004 * considerable TX slowdown with update sizes that fill the
2006 if (!dss_has_feature(FEAT_DSI_GNQ
))
2009 val
= REG_GET(dsidev
, DSI_GNQ
, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2013 return 512 * 3; /* 512x24 bits */
2015 return 682 * 3; /* 682x24 bits */
2017 return 853 * 3; /* 853x24 bits */
2019 return 1024 * 3; /* 1024x24 bits */
2021 return 1194 * 3; /* 1194x24 bits */
2023 return 1365 * 3; /* 1365x24 bits */
2025 return 1920 * 3; /* 1920x24 bits */
2032 static int dsi_set_lane_config(struct platform_device
*dsidev
)
2034 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2035 static const u8 offsets
[] = { 0, 4, 8, 12, 16 };
2036 static const enum dsi_lane_function functions
[] = {
2046 r
= dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG1
);
2048 for (i
= 0; i
< dsi
->num_lanes_used
; ++i
) {
2049 unsigned offset
= offsets
[i
];
2050 unsigned polarity
, lane_number
;
2053 for (t
= 0; t
< dsi
->num_lanes_supported
; ++t
)
2054 if (dsi
->lanes
[t
].function
== functions
[i
])
2057 if (t
== dsi
->num_lanes_supported
)
2061 polarity
= dsi
->lanes
[t
].polarity
;
2063 r
= FLD_MOD(r
, lane_number
+ 1, offset
+ 2, offset
);
2064 r
= FLD_MOD(r
, polarity
, offset
+ 3, offset
+ 3);
2067 /* clear the unused lanes */
2068 for (; i
< dsi
->num_lanes_supported
; ++i
) {
2069 unsigned offset
= offsets
[i
];
2071 r
= FLD_MOD(r
, 0, offset
+ 2, offset
);
2072 r
= FLD_MOD(r
, 0, offset
+ 3, offset
+ 3);
2075 dsi_write_reg(dsidev
, DSI_COMPLEXIO_CFG1
, r
);
2080 static inline unsigned ns2ddr(struct platform_device
*dsidev
, unsigned ns
)
2082 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2084 /* convert time in ns to ddr ticks, rounding up */
2085 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2086 return (ns
* (ddr_clk
/ 1000 / 1000) + 999) / 1000;
2089 static inline unsigned ddr2ns(struct platform_device
*dsidev
, unsigned ddr
)
2091 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2093 unsigned long ddr_clk
= dsi
->current_cinfo
.clkin4ddr
/ 4;
2094 return ddr
* 1000 * 1000 / (ddr_clk
/ 1000);
2097 static void dsi_cio_timings(struct platform_device
*dsidev
)
2100 u32 ths_prepare
, ths_prepare_ths_zero
, ths_trail
, ths_exit
;
2101 u32 tlpx_half
, tclk_trail
, tclk_zero
;
2104 /* calculate timings */
2106 /* 1 * DDR_CLK = 2 * UI */
2108 /* min 40ns + 4*UI max 85ns + 6*UI */
2109 ths_prepare
= ns2ddr(dsidev
, 70) + 2;
2111 /* min 145ns + 10*UI */
2112 ths_prepare_ths_zero
= ns2ddr(dsidev
, 175) + 2;
2114 /* min max(8*UI, 60ns+4*UI) */
2115 ths_trail
= ns2ddr(dsidev
, 60) + 5;
2118 ths_exit
= ns2ddr(dsidev
, 145);
2121 tlpx_half
= ns2ddr(dsidev
, 25);
2124 tclk_trail
= ns2ddr(dsidev
, 60) + 2;
2126 /* min 38ns, max 95ns */
2127 tclk_prepare
= ns2ddr(dsidev
, 65);
2129 /* min tclk-prepare + tclk-zero = 300ns */
2130 tclk_zero
= ns2ddr(dsidev
, 260);
2132 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2133 ths_prepare
, ddr2ns(dsidev
, ths_prepare
),
2134 ths_prepare_ths_zero
, ddr2ns(dsidev
, ths_prepare_ths_zero
));
2135 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2136 ths_trail
, ddr2ns(dsidev
, ths_trail
),
2137 ths_exit
, ddr2ns(dsidev
, ths_exit
));
2139 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2140 "tclk_zero %u (%uns)\n",
2141 tlpx_half
, ddr2ns(dsidev
, tlpx_half
),
2142 tclk_trail
, ddr2ns(dsidev
, tclk_trail
),
2143 tclk_zero
, ddr2ns(dsidev
, tclk_zero
));
2144 DSSDBG("tclk_prepare %u (%uns)\n",
2145 tclk_prepare
, ddr2ns(dsidev
, tclk_prepare
));
2147 /* program timings */
2149 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
2150 r
= FLD_MOD(r
, ths_prepare
, 31, 24);
2151 r
= FLD_MOD(r
, ths_prepare_ths_zero
, 23, 16);
2152 r
= FLD_MOD(r
, ths_trail
, 15, 8);
2153 r
= FLD_MOD(r
, ths_exit
, 7, 0);
2154 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG0
, r
);
2156 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
2157 r
= FLD_MOD(r
, tlpx_half
, 20, 16);
2158 r
= FLD_MOD(r
, tclk_trail
, 15, 8);
2159 r
= FLD_MOD(r
, tclk_zero
, 7, 0);
2161 if (dss_has_feature(FEAT_DSI_PHY_DCC
)) {
2162 r
= FLD_MOD(r
, 0, 21, 21); /* DCCEN = disable */
2163 r
= FLD_MOD(r
, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2164 r
= FLD_MOD(r
, 1, 23, 23); /* CLKINP_SEL = enable */
2167 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG1
, r
);
2169 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
2170 r
= FLD_MOD(r
, tclk_prepare
, 7, 0);
2171 dsi_write_reg(dsidev
, DSI_DSIPHY_CFG2
, r
);
2174 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2175 static void dsi_cio_enable_lane_override(struct platform_device
*dsidev
,
2176 unsigned mask_p
, unsigned mask_n
)
2178 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2181 u8 lptxscp_start
= dsi
->num_lanes_supported
== 3 ? 22 : 26;
2185 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2186 unsigned p
= dsi
->lanes
[i
].polarity
;
2188 if (mask_p
& (1 << i
))
2189 l
|= 1 << (i
* 2 + (p
? 0 : 1));
2191 if (mask_n
& (1 << i
))
2192 l
|= 1 << (i
* 2 + (p
? 1 : 0));
2196 * Bits in REGLPTXSCPDAT4TO0DXDY:
2204 /* Set the lane override configuration */
2206 /* REGLPTXSCPDAT4TO0DXDY */
2207 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, l
, lptxscp_start
, 17);
2209 /* Enable lane override */
2212 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 1, 27, 27);
2215 static void dsi_cio_disable_lane_override(struct platform_device
*dsidev
)
2217 /* Disable lane override */
2218 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 27, 27); /* ENLPTXSCPDAT */
2219 /* Reset the lane override configuration */
2220 /* REGLPTXSCPDAT4TO0DXDY */
2221 REG_FLD_MOD(dsidev
, DSI_DSIPHY_CFG10
, 0, 22, 17);
2224 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device
*dsidev
)
2226 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2228 bool in_use
[DSI_MAX_NR_LANES
];
2229 static const u8 offsets_old
[] = { 28, 27, 26 };
2230 static const u8 offsets_new
[] = { 24, 25, 26, 27, 28 };
2233 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC
))
2234 offsets
= offsets_old
;
2236 offsets
= offsets_new
;
2238 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
)
2239 in_use
[i
] = dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
;
2246 l
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2249 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2250 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2254 if (ok
== dsi
->num_lanes_supported
)
2258 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2259 if (!in_use
[i
] || (l
& (1 << offsets
[i
])))
2262 DSSERR("CIO TXCLKESC%d domain not coming " \
2263 "out of reset\n", i
);
2272 /* return bitmask of enabled lanes, lane0 being the lsb */
2273 static unsigned dsi_get_lane_mask(struct platform_device
*dsidev
)
2275 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2279 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2280 if (dsi
->lanes
[i
].function
!= DSI_LANE_UNUSED
)
2287 static int dsi_cio_init(struct platform_device
*dsidev
)
2289 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2293 DSSDBG("DSI CIO init starts");
2295 r
= dss_dsi_enable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2299 dsi_enable_scp_clk(dsidev
);
2301 /* A dummy read using the SCP interface to any DSIPHY register is
2302 * required after DSIPHY reset to complete the reset of the DSI complex
2304 dsi_read_reg(dsidev
, DSI_DSIPHY_CFG5
);
2306 if (wait_for_bit_change(dsidev
, DSI_DSIPHY_CFG5
, 30, 1) != 1) {
2307 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2309 goto err_scp_clk_dom
;
2312 r
= dsi_set_lane_config(dsidev
);
2314 goto err_scp_clk_dom
;
2316 /* set TX STOP MODE timer to maximum for this operation */
2317 l
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2318 l
= FLD_MOD(l
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2319 l
= FLD_MOD(l
, 1, 14, 14); /* STOP_STATE_X16_IO */
2320 l
= FLD_MOD(l
, 1, 13, 13); /* STOP_STATE_X4_IO */
2321 l
= FLD_MOD(l
, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2322 dsi_write_reg(dsidev
, DSI_TIMING1
, l
);
2324 if (dsi
->ulps_enabled
) {
2328 DSSDBG("manual ulps exit\n");
2330 /* ULPS is exited by Mark-1 state for 1ms, followed by
2331 * stop state. DSS HW cannot do this via the normal
2332 * ULPS exit sequence, as after reset the DSS HW thinks
2333 * that we are not in ULPS mode, and refuses to send the
2334 * sequence. So we need to send the ULPS exit sequence
2335 * manually by setting positive lines high and negative lines
2341 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
2342 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
2347 dsi_cio_enable_lane_override(dsidev
, mask_p
, 0);
2350 r
= dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ON
);
2354 if (wait_for_bit_change(dsidev
, DSI_COMPLEXIO_CFG1
, 29, 1) != 1) {
2355 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2357 goto err_cio_pwr_dom
;
2360 dsi_if_enable(dsidev
, true);
2361 dsi_if_enable(dsidev
, false);
2362 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 1, 20, 20); /* LP_CLK_ENABLE */
2364 r
= dsi_cio_wait_tx_clk_esc_reset(dsidev
);
2366 goto err_tx_clk_esc_rst
;
2368 if (dsi
->ulps_enabled
) {
2369 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2370 ktime_t wait
= ns_to_ktime(1000 * 1000);
2371 set_current_state(TASK_UNINTERRUPTIBLE
);
2372 schedule_hrtimeout(&wait
, HRTIMER_MODE_REL
);
2374 /* Disable the override. The lanes should be set to Mark-11
2375 * state by the HW */
2376 dsi_cio_disable_lane_override(dsidev
);
2379 /* FORCE_TX_STOP_MODE_IO */
2380 REG_FLD_MOD(dsidev
, DSI_TIMING1
, 0, 15, 15);
2382 dsi_cio_timings(dsidev
);
2384 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
2385 /* DDR_CLK_ALWAYS_ON */
2386 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
,
2387 dsi
->vm_timings
.ddr_clk_always_on
, 13, 13);
2390 dsi
->ulps_enabled
= false;
2392 DSSDBG("CIO init done\n");
2397 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 20, 20); /* LP_CLK_ENABLE */
2399 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2401 if (dsi
->ulps_enabled
)
2402 dsi_cio_disable_lane_override(dsidev
);
2404 dsi_disable_scp_clk(dsidev
);
2405 dss_dsi_disable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2409 static void dsi_cio_uninit(struct platform_device
*dsidev
)
2411 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2413 /* DDR_CLK_ALWAYS_ON */
2414 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
2416 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_OFF
);
2417 dsi_disable_scp_clk(dsidev
);
2418 dss_dsi_disable_pads(dsi
->module_id
, dsi_get_lane_mask(dsidev
));
2421 static void dsi_config_tx_fifo(struct platform_device
*dsidev
,
2422 enum fifo_size size1
, enum fifo_size size2
,
2423 enum fifo_size size3
, enum fifo_size size4
)
2425 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2430 dsi
->vc
[0].fifo_size
= size1
;
2431 dsi
->vc
[1].fifo_size
= size2
;
2432 dsi
->vc
[2].fifo_size
= size3
;
2433 dsi
->vc
[3].fifo_size
= size4
;
2435 for (i
= 0; i
< 4; i
++) {
2437 int size
= dsi
->vc
[i
].fifo_size
;
2439 if (add
+ size
> 4) {
2440 DSSERR("Illegal FIFO configuration\n");
2445 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2447 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2451 dsi_write_reg(dsidev
, DSI_TX_FIFO_VC_SIZE
, r
);
2454 static void dsi_config_rx_fifo(struct platform_device
*dsidev
,
2455 enum fifo_size size1
, enum fifo_size size2
,
2456 enum fifo_size size3
, enum fifo_size size4
)
2458 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2463 dsi
->vc
[0].fifo_size
= size1
;
2464 dsi
->vc
[1].fifo_size
= size2
;
2465 dsi
->vc
[2].fifo_size
= size3
;
2466 dsi
->vc
[3].fifo_size
= size4
;
2468 for (i
= 0; i
< 4; i
++) {
2470 int size
= dsi
->vc
[i
].fifo_size
;
2472 if (add
+ size
> 4) {
2473 DSSERR("Illegal FIFO configuration\n");
2478 v
= FLD_VAL(add
, 2, 0) | FLD_VAL(size
, 7, 4);
2480 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2484 dsi_write_reg(dsidev
, DSI_RX_FIFO_VC_SIZE
, r
);
2487 static int dsi_force_tx_stop_mode_io(struct platform_device
*dsidev
)
2491 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
2492 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2493 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
2495 if (wait_for_bit_change(dsidev
, DSI_TIMING1
, 15, 0) != 0) {
2496 DSSERR("TX_STOP bit not going down\n");
2503 static bool dsi_vc_is_enabled(struct platform_device
*dsidev
, int channel
)
2505 return REG_GET(dsidev
, DSI_VC_CTRL(channel
), 0, 0);
2508 static void dsi_packet_sent_handler_vp(void *data
, u32 mask
)
2510 struct dsi_packet_sent_handler_data
*vp_data
=
2511 (struct dsi_packet_sent_handler_data
*) data
;
2512 struct dsi_data
*dsi
= dsi_get_dsidrv_data(vp_data
->dsidev
);
2513 const int channel
= dsi
->update_channel
;
2514 u8 bit
= dsi
->te_enabled
? 30 : 31;
2516 if (REG_GET(vp_data
->dsidev
, DSI_VC_TE(channel
), bit
, bit
) == 0)
2517 complete(vp_data
->completion
);
2520 static int dsi_sync_vc_vp(struct platform_device
*dsidev
, int channel
)
2522 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2523 DECLARE_COMPLETION_ONSTACK(completion
);
2524 struct dsi_packet_sent_handler_data vp_data
= { dsidev
, &completion
};
2528 bit
= dsi
->te_enabled
? 30 : 31;
2530 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2531 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2535 /* Wait for completion only if TE_EN/TE_START is still set */
2536 if (REG_GET(dsidev
, DSI_VC_TE(channel
), bit
, bit
)) {
2537 if (wait_for_completion_timeout(&completion
,
2538 msecs_to_jiffies(10)) == 0) {
2539 DSSERR("Failed to complete previous frame transfer\n");
2545 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2546 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2550 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_vp
,
2551 &vp_data
, DSI_VC_IRQ_PACKET_SENT
);
2556 static void dsi_packet_sent_handler_l4(void *data
, u32 mask
)
2558 struct dsi_packet_sent_handler_data
*l4_data
=
2559 (struct dsi_packet_sent_handler_data
*) data
;
2560 struct dsi_data
*dsi
= dsi_get_dsidrv_data(l4_data
->dsidev
);
2561 const int channel
= dsi
->update_channel
;
2563 if (REG_GET(l4_data
->dsidev
, DSI_VC_CTRL(channel
), 5, 5) == 0)
2564 complete(l4_data
->completion
);
2567 static int dsi_sync_vc_l4(struct platform_device
*dsidev
, int channel
)
2569 DECLARE_COMPLETION_ONSTACK(completion
);
2570 struct dsi_packet_sent_handler_data l4_data
= { dsidev
, &completion
};
2573 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2574 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2578 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2579 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 5, 5)) {
2580 if (wait_for_completion_timeout(&completion
,
2581 msecs_to_jiffies(10)) == 0) {
2582 DSSERR("Failed to complete previous l4 transfer\n");
2588 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2589 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2593 dsi_unregister_isr_vc(dsidev
, channel
, dsi_packet_sent_handler_l4
,
2594 &l4_data
, DSI_VC_IRQ_PACKET_SENT
);
2599 static int dsi_sync_vc(struct platform_device
*dsidev
, int channel
)
2601 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2603 WARN_ON(!dsi_bus_is_locked(dsidev
));
2605 WARN_ON(in_interrupt());
2607 if (!dsi_vc_is_enabled(dsidev
, channel
))
2610 switch (dsi
->vc
[channel
].source
) {
2611 case DSI_VC_SOURCE_VP
:
2612 return dsi_sync_vc_vp(dsidev
, channel
);
2613 case DSI_VC_SOURCE_L4
:
2614 return dsi_sync_vc_l4(dsidev
, channel
);
2621 static int dsi_vc_enable(struct platform_device
*dsidev
, int channel
,
2624 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2627 enable
= enable
? 1 : 0;
2629 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 0, 0);
2631 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
),
2632 0, enable
) != enable
) {
2633 DSSERR("Failed to set dsi_vc_enable to %d\n", enable
);
2640 static void dsi_vc_initial_config(struct platform_device
*dsidev
, int channel
)
2642 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2645 DSSDBG("Initial config of virtual channel %d", channel
);
2647 r
= dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2649 if (FLD_GET(r
, 15, 15)) /* VC_BUSY */
2650 DSSERR("VC(%d) busy when trying to configure it!\n",
2653 r
= FLD_MOD(r
, 0, 1, 1); /* SOURCE, 0 = L4 */
2654 r
= FLD_MOD(r
, 0, 2, 2); /* BTA_SHORT_EN */
2655 r
= FLD_MOD(r
, 0, 3, 3); /* BTA_LONG_EN */
2656 r
= FLD_MOD(r
, 0, 4, 4); /* MODE, 0 = command */
2657 r
= FLD_MOD(r
, 1, 7, 7); /* CS_TX_EN */
2658 r
= FLD_MOD(r
, 1, 8, 8); /* ECC_TX_EN */
2659 r
= FLD_MOD(r
, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2660 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH
))
2661 r
= FLD_MOD(r
, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2663 r
= FLD_MOD(r
, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2664 r
= FLD_MOD(r
, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2666 dsi_write_reg(dsidev
, DSI_VC_CTRL(channel
), r
);
2668 dsi
->vc
[channel
].source
= DSI_VC_SOURCE_L4
;
2671 static int dsi_vc_config_source(struct platform_device
*dsidev
, int channel
,
2672 enum dsi_vc_source source
)
2674 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2676 if (dsi
->vc
[channel
].source
== source
)
2679 DSSDBG("Source config of virtual channel %d", channel
);
2681 dsi_sync_vc(dsidev
, channel
);
2683 dsi_vc_enable(dsidev
, channel
, 0);
2686 if (wait_for_bit_change(dsidev
, DSI_VC_CTRL(channel
), 15, 0) != 0) {
2687 DSSERR("vc(%d) busy when trying to config for VP\n", channel
);
2691 /* SOURCE, 0 = L4, 1 = video port */
2692 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), source
, 1, 1);
2694 /* DCS_CMD_ENABLE */
2695 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
2696 bool enable
= source
== DSI_VC_SOURCE_VP
;
2697 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 30, 30);
2700 dsi_vc_enable(dsidev
, channel
, 1);
2702 dsi
->vc
[channel
].source
= source
;
2707 void omapdss_dsi_vc_enable_hs(struct omap_dss_device
*dssdev
, int channel
,
2710 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2711 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2713 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel
, enable
);
2715 WARN_ON(!dsi_bus_is_locked(dsidev
));
2717 dsi_vc_enable(dsidev
, channel
, 0);
2718 dsi_if_enable(dsidev
, 0);
2720 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), enable
, 9, 9);
2722 dsi_vc_enable(dsidev
, channel
, 1);
2723 dsi_if_enable(dsidev
, 1);
2725 dsi_force_tx_stop_mode_io(dsidev
);
2727 /* start the DDR clock by sending a NULL packet */
2728 if (dsi
->vm_timings
.ddr_clk_always_on
&& enable
)
2729 dsi_vc_send_null(dssdev
, channel
);
2731 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs
);
2733 static void dsi_vc_flush_long_data(struct platform_device
*dsidev
, int channel
)
2735 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2737 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2738 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2742 (val
>> 24) & 0xff);
2746 static void dsi_show_rx_ack_with_err(u16 err
)
2748 DSSERR("\tACK with ERROR (%#x):\n", err
);
2750 DSSERR("\t\tSoT Error\n");
2752 DSSERR("\t\tSoT Sync Error\n");
2754 DSSERR("\t\tEoT Sync Error\n");
2756 DSSERR("\t\tEscape Mode Entry Command Error\n");
2758 DSSERR("\t\tLP Transmit Sync Error\n");
2760 DSSERR("\t\tHS Receive Timeout Error\n");
2762 DSSERR("\t\tFalse Control Error\n");
2764 DSSERR("\t\t(reserved7)\n");
2766 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2768 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2769 if (err
& (1 << 10))
2770 DSSERR("\t\tChecksum Error\n");
2771 if (err
& (1 << 11))
2772 DSSERR("\t\tData type not recognized\n");
2773 if (err
& (1 << 12))
2774 DSSERR("\t\tInvalid VC ID\n");
2775 if (err
& (1 << 13))
2776 DSSERR("\t\tInvalid Transmission Length\n");
2777 if (err
& (1 << 14))
2778 DSSERR("\t\t(reserved14)\n");
2779 if (err
& (1 << 15))
2780 DSSERR("\t\tDSI Protocol Violation\n");
2783 static u16
dsi_vc_flush_receive_data(struct platform_device
*dsidev
,
2786 /* RX_FIFO_NOT_EMPTY */
2787 while (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2790 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
2791 DSSERR("\trawval %#08x\n", val
);
2792 dt
= FLD_GET(val
, 5, 0);
2793 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
2794 u16 err
= FLD_GET(val
, 23, 8);
2795 dsi_show_rx_ack_with_err(err
);
2796 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
) {
2797 DSSERR("\tDCS short response, 1 byte: %#x\n",
2798 FLD_GET(val
, 23, 8));
2799 } else if (dt
== MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
) {
2800 DSSERR("\tDCS short response, 2 byte: %#x\n",
2801 FLD_GET(val
, 23, 8));
2802 } else if (dt
== MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
) {
2803 DSSERR("\tDCS long response, len %d\n",
2804 FLD_GET(val
, 23, 8));
2805 dsi_vc_flush_long_data(dsidev
, channel
);
2807 DSSERR("\tunknown datatype 0x%02x\n", dt
);
2813 static int dsi_vc_send_bta(struct platform_device
*dsidev
, int channel
)
2815 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2817 if (dsi
->debug_write
|| dsi
->debug_read
)
2818 DSSDBG("dsi_vc_send_bta %d\n", channel
);
2820 WARN_ON(!dsi_bus_is_locked(dsidev
));
2822 /* RX_FIFO_NOT_EMPTY */
2823 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
2824 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2825 dsi_vc_flush_receive_data(dsidev
, channel
);
2828 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 6, 6); /* BTA_EN */
2830 /* flush posted write */
2831 dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
));
2836 int dsi_vc_send_bta_sync(struct omap_dss_device
*dssdev
, int channel
)
2838 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
2839 DECLARE_COMPLETION_ONSTACK(completion
);
2843 r
= dsi_register_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2844 &completion
, DSI_VC_IRQ_BTA
);
2848 r
= dsi_register_isr(dsidev
, dsi_completion_handler
, &completion
,
2849 DSI_IRQ_ERROR_MASK
);
2853 r
= dsi_vc_send_bta(dsidev
, channel
);
2857 if (wait_for_completion_timeout(&completion
,
2858 msecs_to_jiffies(500)) == 0) {
2859 DSSERR("Failed to receive BTA\n");
2864 err
= dsi_get_errors(dsidev
);
2866 DSSERR("Error while sending BTA: %x\n", err
);
2871 dsi_unregister_isr(dsidev
, dsi_completion_handler
, &completion
,
2872 DSI_IRQ_ERROR_MASK
);
2874 dsi_unregister_isr_vc(dsidev
, channel
, dsi_completion_handler
,
2875 &completion
, DSI_VC_IRQ_BTA
);
2879 EXPORT_SYMBOL(dsi_vc_send_bta_sync
);
2881 static inline void dsi_vc_write_long_header(struct platform_device
*dsidev
,
2882 int channel
, u8 data_type
, u16 len
, u8 ecc
)
2884 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2888 WARN_ON(!dsi_bus_is_locked(dsidev
));
2890 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
2892 val
= FLD_VAL(data_id
, 7, 0) | FLD_VAL(len
, 23, 8) |
2893 FLD_VAL(ecc
, 31, 24);
2895 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_HEADER(channel
), val
);
2898 static inline void dsi_vc_write_long_payload(struct platform_device
*dsidev
,
2899 int channel
, u8 b1
, u8 b2
, u8 b3
, u8 b4
)
2903 val
= b4
<< 24 | b3
<< 16 | b2
<< 8 | b1
<< 0;
2905 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2906 b1, b2, b3, b4, val); */
2908 dsi_write_reg(dsidev
, DSI_VC_LONG_PACKET_PAYLOAD(channel
), val
);
2911 static int dsi_vc_send_long(struct platform_device
*dsidev
, int channel
,
2912 u8 data_type
, u8
*data
, u16 len
, u8 ecc
)
2915 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2921 if (dsi
->debug_write
)
2922 DSSDBG("dsi_vc_send_long, %d bytes\n", len
);
2925 if (dsi
->vc
[channel
].fifo_size
* 32 * 4 < len
+ 4) {
2926 DSSERR("unable to send long packet: packet too long.\n");
2930 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
2932 dsi_vc_write_long_header(dsidev
, channel
, data_type
, len
, ecc
);
2935 for (i
= 0; i
< len
>> 2; i
++) {
2936 if (dsi
->debug_write
)
2937 DSSDBG("\tsending full packet %d\n", i
);
2944 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, b4
);
2949 b1
= 0; b2
= 0; b3
= 0;
2951 if (dsi
->debug_write
)
2952 DSSDBG("\tsending remainder bytes %d\n", i
);
2969 dsi_vc_write_long_payload(dsidev
, channel
, b1
, b2
, b3
, 0);
2975 static int dsi_vc_send_short(struct platform_device
*dsidev
, int channel
,
2976 u8 data_type
, u16 data
, u8 ecc
)
2978 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
2982 WARN_ON(!dsi_bus_is_locked(dsidev
));
2984 if (dsi
->debug_write
)
2985 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2987 data_type
, data
& 0xff, (data
>> 8) & 0xff);
2989 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_L4
);
2991 if (FLD_GET(dsi_read_reg(dsidev
, DSI_VC_CTRL(channel
)), 16, 16)) {
2992 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2996 data_id
= data_type
| dsi
->vc
[channel
].vc_id
<< 6;
2998 r
= (data_id
<< 0) | (data
<< 8) | (ecc
<< 24);
3000 dsi_write_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
), r
);
3005 int dsi_vc_send_null(struct omap_dss_device
*dssdev
, int channel
)
3007 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3009 return dsi_vc_send_long(dsidev
, channel
, MIPI_DSI_NULL_PACKET
, NULL
,
3012 EXPORT_SYMBOL(dsi_vc_send_null
);
3014 static int dsi_vc_write_nosync_common(struct platform_device
*dsidev
,
3015 int channel
, u8
*data
, int len
, enum dss_dsi_content_type type
)
3020 BUG_ON(type
== DSS_DSI_CONTENT_DCS
);
3021 r
= dsi_vc_send_short(dsidev
, channel
,
3022 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM
, 0, 0);
3023 } else if (len
== 1) {
3024 r
= dsi_vc_send_short(dsidev
, channel
,
3025 type
== DSS_DSI_CONTENT_GENERIC
?
3026 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM
:
3027 MIPI_DSI_DCS_SHORT_WRITE
, data
[0], 0);
3028 } else if (len
== 2) {
3029 r
= dsi_vc_send_short(dsidev
, channel
,
3030 type
== DSS_DSI_CONTENT_GENERIC
?
3031 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM
:
3032 MIPI_DSI_DCS_SHORT_WRITE_PARAM
,
3033 data
[0] | (data
[1] << 8), 0);
3035 r
= dsi_vc_send_long(dsidev
, channel
,
3036 type
== DSS_DSI_CONTENT_GENERIC
?
3037 MIPI_DSI_GENERIC_LONG_WRITE
:
3038 MIPI_DSI_DCS_LONG_WRITE
, data
, len
, 0);
3044 int dsi_vc_dcs_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3047 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3049 return dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
,
3050 DSS_DSI_CONTENT_DCS
);
3052 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync
);
3054 int dsi_vc_generic_write_nosync(struct omap_dss_device
*dssdev
, int channel
,
3057 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3059 return dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
,
3060 DSS_DSI_CONTENT_GENERIC
);
3062 EXPORT_SYMBOL(dsi_vc_generic_write_nosync
);
3064 static int dsi_vc_write_common(struct omap_dss_device
*dssdev
, int channel
,
3065 u8
*data
, int len
, enum dss_dsi_content_type type
)
3067 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3070 r
= dsi_vc_write_nosync_common(dsidev
, channel
, data
, len
, type
);
3074 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3078 /* RX_FIFO_NOT_EMPTY */
3079 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20)) {
3080 DSSERR("rx fifo not empty after write, dumping data:\n");
3081 dsi_vc_flush_receive_data(dsidev
, channel
);
3088 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3089 channel
, data
[0], len
);
3093 int dsi_vc_dcs_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3096 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3097 DSS_DSI_CONTENT_DCS
);
3099 EXPORT_SYMBOL(dsi_vc_dcs_write
);
3101 int dsi_vc_generic_write(struct omap_dss_device
*dssdev
, int channel
, u8
*data
,
3104 return dsi_vc_write_common(dssdev
, channel
, data
, len
,
3105 DSS_DSI_CONTENT_GENERIC
);
3107 EXPORT_SYMBOL(dsi_vc_generic_write
);
3109 int dsi_vc_dcs_write_0(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
)
3111 return dsi_vc_dcs_write(dssdev
, channel
, &dcs_cmd
, 1);
3113 EXPORT_SYMBOL(dsi_vc_dcs_write_0
);
3115 int dsi_vc_generic_write_0(struct omap_dss_device
*dssdev
, int channel
)
3117 return dsi_vc_generic_write(dssdev
, channel
, NULL
, 0);
3119 EXPORT_SYMBOL(dsi_vc_generic_write_0
);
3121 int dsi_vc_dcs_write_1(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3127 return dsi_vc_dcs_write(dssdev
, channel
, buf
, 2);
3129 EXPORT_SYMBOL(dsi_vc_dcs_write_1
);
3131 int dsi_vc_generic_write_1(struct omap_dss_device
*dssdev
, int channel
,
3134 return dsi_vc_generic_write(dssdev
, channel
, ¶m
, 1);
3136 EXPORT_SYMBOL(dsi_vc_generic_write_1
);
3138 int dsi_vc_generic_write_2(struct omap_dss_device
*dssdev
, int channel
,
3139 u8 param1
, u8 param2
)
3144 return dsi_vc_generic_write(dssdev
, channel
, buf
, 2);
3146 EXPORT_SYMBOL(dsi_vc_generic_write_2
);
3148 static int dsi_vc_dcs_send_read_request(struct platform_device
*dsidev
,
3149 int channel
, u8 dcs_cmd
)
3151 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3154 if (dsi
->debug_read
)
3155 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3158 r
= dsi_vc_send_short(dsidev
, channel
, MIPI_DSI_DCS_READ
, dcs_cmd
, 0);
3160 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3161 " failed\n", channel
, dcs_cmd
);
3168 static int dsi_vc_generic_send_read_request(struct platform_device
*dsidev
,
3169 int channel
, u8
*reqdata
, int reqlen
)
3171 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3176 if (dsi
->debug_read
)
3177 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3181 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM
;
3183 } else if (reqlen
== 1) {
3184 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM
;
3186 } else if (reqlen
== 2) {
3187 data_type
= MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM
;
3188 data
= reqdata
[0] | (reqdata
[1] << 8);
3194 r
= dsi_vc_send_short(dsidev
, channel
, data_type
, data
, 0);
3196 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3197 " failed\n", channel
, reqlen
);
3204 static int dsi_vc_read_rx_fifo(struct platform_device
*dsidev
, int channel
,
3205 u8
*buf
, int buflen
, enum dss_dsi_content_type type
)
3207 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3212 /* RX_FIFO_NOT_EMPTY */
3213 if (REG_GET(dsidev
, DSI_VC_CTRL(channel
), 20, 20) == 0) {
3214 DSSERR("RX fifo empty when trying to read.\n");
3219 val
= dsi_read_reg(dsidev
, DSI_VC_SHORT_PACKET_HEADER(channel
));
3220 if (dsi
->debug_read
)
3221 DSSDBG("\theader: %08x\n", val
);
3222 dt
= FLD_GET(val
, 5, 0);
3223 if (dt
== MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
) {
3224 u16 err
= FLD_GET(val
, 23, 8);
3225 dsi_show_rx_ack_with_err(err
);
3229 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3230 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
3231 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
)) {
3232 u8 data
= FLD_GET(val
, 15, 8);
3233 if (dsi
->debug_read
)
3234 DSSDBG("\t%s short response, 1 byte: %02x\n",
3235 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3246 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3247 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
3248 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
)) {
3249 u16 data
= FLD_GET(val
, 23, 8);
3250 if (dsi
->debug_read
)
3251 DSSDBG("\t%s short response, 2 byte: %04x\n",
3252 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3260 buf
[0] = data
& 0xff;
3261 buf
[1] = (data
>> 8) & 0xff;
3264 } else if (dt
== (type
== DSS_DSI_CONTENT_GENERIC
?
3265 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
3266 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
)) {
3268 int len
= FLD_GET(val
, 23, 8);
3269 if (dsi
->debug_read
)
3270 DSSDBG("\t%s long response, len %d\n",
3271 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" :
3279 /* two byte checksum ends the packet, not included in len */
3280 for (w
= 0; w
< len
+ 2;) {
3282 val
= dsi_read_reg(dsidev
,
3283 DSI_VC_SHORT_PACKET_HEADER(channel
));
3284 if (dsi
->debug_read
)
3285 DSSDBG("\t\t%02x %02x %02x %02x\n",
3289 (val
>> 24) & 0xff);
3291 for (b
= 0; b
< 4; ++b
) {
3293 buf
[w
] = (val
>> (b
* 8)) & 0xff;
3294 /* we discard the 2 byte checksum */
3301 DSSERR("\tunknown datatype 0x%02x\n", dt
);
3307 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel
,
3308 type
== DSS_DSI_CONTENT_GENERIC
? "GENERIC" : "DCS");
3313 int dsi_vc_dcs_read(struct omap_dss_device
*dssdev
, int channel
, u8 dcs_cmd
,
3314 u8
*buf
, int buflen
)
3316 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3319 r
= dsi_vc_dcs_send_read_request(dsidev
, channel
, dcs_cmd
);
3323 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3327 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3328 DSS_DSI_CONTENT_DCS
);
3339 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel
, dcs_cmd
);
3342 EXPORT_SYMBOL(dsi_vc_dcs_read
);
3344 static int dsi_vc_generic_read(struct omap_dss_device
*dssdev
, int channel
,
3345 u8
*reqdata
, int reqlen
, u8
*buf
, int buflen
)
3347 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3350 r
= dsi_vc_generic_send_read_request(dsidev
, channel
, reqdata
, reqlen
);
3354 r
= dsi_vc_send_bta_sync(dssdev
, channel
);
3358 r
= dsi_vc_read_rx_fifo(dsidev
, channel
, buf
, buflen
,
3359 DSS_DSI_CONTENT_GENERIC
);
3371 int dsi_vc_generic_read_0(struct omap_dss_device
*dssdev
, int channel
, u8
*buf
,
3376 r
= dsi_vc_generic_read(dssdev
, channel
, NULL
, 0, buf
, buflen
);
3378 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel
);
3384 EXPORT_SYMBOL(dsi_vc_generic_read_0
);
3386 int dsi_vc_generic_read_1(struct omap_dss_device
*dssdev
, int channel
, u8 param
,
3387 u8
*buf
, int buflen
)
3391 r
= dsi_vc_generic_read(dssdev
, channel
, ¶m
, 1, buf
, buflen
);
3393 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel
);
3399 EXPORT_SYMBOL(dsi_vc_generic_read_1
);
3401 int dsi_vc_generic_read_2(struct omap_dss_device
*dssdev
, int channel
,
3402 u8 param1
, u8 param2
, u8
*buf
, int buflen
)
3407 reqdata
[0] = param1
;
3408 reqdata
[1] = param2
;
3410 r
= dsi_vc_generic_read(dssdev
, channel
, reqdata
, 2, buf
, buflen
);
3412 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel
);
3418 EXPORT_SYMBOL(dsi_vc_generic_read_2
);
3420 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device
*dssdev
, int channel
,
3423 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
3425 return dsi_vc_send_short(dsidev
, channel
,
3426 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
, len
, 0);
3428 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size
);
3430 static int dsi_enter_ulps(struct platform_device
*dsidev
)
3432 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3433 DECLARE_COMPLETION_ONSTACK(completion
);
3437 DSSDBG("Entering ULPS");
3439 WARN_ON(!dsi_bus_is_locked(dsidev
));
3441 WARN_ON(dsi
->ulps_enabled
);
3443 if (dsi
->ulps_enabled
)
3446 /* DDR_CLK_ALWAYS_ON */
3447 if (REG_GET(dsidev
, DSI_CLK_CTRL
, 13, 13)) {
3448 dsi_if_enable(dsidev
, 0);
3449 REG_FLD_MOD(dsidev
, DSI_CLK_CTRL
, 0, 13, 13);
3450 dsi_if_enable(dsidev
, 1);
3453 dsi_sync_vc(dsidev
, 0);
3454 dsi_sync_vc(dsidev
, 1);
3455 dsi_sync_vc(dsidev
, 2);
3456 dsi_sync_vc(dsidev
, 3);
3458 dsi_force_tx_stop_mode_io(dsidev
);
3460 dsi_vc_enable(dsidev
, 0, false);
3461 dsi_vc_enable(dsidev
, 1, false);
3462 dsi_vc_enable(dsidev
, 2, false);
3463 dsi_vc_enable(dsidev
, 3, false);
3465 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 16, 16)) { /* HS_BUSY */
3466 DSSERR("HS busy when enabling ULPS\n");
3470 if (REG_GET(dsidev
, DSI_COMPLEXIO_CFG2
, 17, 17)) { /* LP_BUSY */
3471 DSSERR("LP busy when enabling ULPS\n");
3475 r
= dsi_register_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3476 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3482 for (i
= 0; i
< dsi
->num_lanes_supported
; ++i
) {
3483 if (dsi
->lanes
[i
].function
== DSI_LANE_UNUSED
)
3487 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3488 /* LANEx_ULPS_SIG2 */
3489 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, mask
, 9, 5);
3491 /* flush posted write and wait for SCP interface to finish the write */
3492 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3494 if (wait_for_completion_timeout(&completion
,
3495 msecs_to_jiffies(1000)) == 0) {
3496 DSSERR("ULPS enable timeout\n");
3501 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3502 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3504 /* Reset LANEx_ULPS_SIG2 */
3505 REG_FLD_MOD(dsidev
, DSI_COMPLEXIO_CFG2
, 0, 9, 5);
3507 /* flush posted write and wait for SCP interface to finish the write */
3508 dsi_read_reg(dsidev
, DSI_COMPLEXIO_CFG2
);
3510 dsi_cio_power(dsidev
, DSI_COMPLEXIO_POWER_ULPS
);
3512 dsi_if_enable(dsidev
, false);
3514 dsi
->ulps_enabled
= true;
3519 dsi_unregister_isr_cio(dsidev
, dsi_completion_handler
, &completion
,
3520 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0
);
3524 static void dsi_set_lp_rx_timeout(struct platform_device
*dsidev
,
3525 unsigned ticks
, bool x4
, bool x16
)
3528 unsigned long total_ticks
;
3531 BUG_ON(ticks
> 0x1fff);
3533 /* ticks in DSI_FCK */
3534 fck
= dsi_fclk_rate(dsidev
);
3536 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3537 r
= FLD_MOD(r
, 1, 15, 15); /* LP_RX_TO */
3538 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3539 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3540 r
= FLD_MOD(r
, ticks
, 12, 0); /* LP_RX_COUNTER */
3541 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3543 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3545 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3547 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3548 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3551 static void dsi_set_ta_timeout(struct platform_device
*dsidev
, unsigned ticks
,
3555 unsigned long total_ticks
;
3558 BUG_ON(ticks
> 0x1fff);
3560 /* ticks in DSI_FCK */
3561 fck
= dsi_fclk_rate(dsidev
);
3563 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3564 r
= FLD_MOD(r
, 1, 31, 31); /* TA_TO */
3565 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* TA_TO_X16 */
3566 r
= FLD_MOD(r
, x8
? 1 : 0, 29, 29); /* TA_TO_X8 */
3567 r
= FLD_MOD(r
, ticks
, 28, 16); /* TA_TO_COUNTER */
3568 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3570 total_ticks
= ticks
* (x16
? 16 : 1) * (x8
? 8 : 1);
3572 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3574 ticks
, x8
? " x8" : "", x16
? " x16" : "",
3575 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3578 static void dsi_set_stop_state_counter(struct platform_device
*dsidev
,
3579 unsigned ticks
, bool x4
, bool x16
)
3582 unsigned long total_ticks
;
3585 BUG_ON(ticks
> 0x1fff);
3587 /* ticks in DSI_FCK */
3588 fck
= dsi_fclk_rate(dsidev
);
3590 r
= dsi_read_reg(dsidev
, DSI_TIMING1
);
3591 r
= FLD_MOD(r
, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3592 r
= FLD_MOD(r
, x16
? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3593 r
= FLD_MOD(r
, x4
? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3594 r
= FLD_MOD(r
, ticks
, 12, 0); /* STOP_STATE_COUNTER_IO */
3595 dsi_write_reg(dsidev
, DSI_TIMING1
, r
);
3597 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3599 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3601 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3602 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3605 static void dsi_set_hs_tx_timeout(struct platform_device
*dsidev
,
3606 unsigned ticks
, bool x4
, bool x16
)
3609 unsigned long total_ticks
;
3612 BUG_ON(ticks
> 0x1fff);
3614 /* ticks in TxByteClkHS */
3615 fck
= dsi_get_txbyteclkhs(dsidev
);
3617 r
= dsi_read_reg(dsidev
, DSI_TIMING2
);
3618 r
= FLD_MOD(r
, 1, 31, 31); /* HS_TX_TO */
3619 r
= FLD_MOD(r
, x16
? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3620 r
= FLD_MOD(r
, x4
? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3621 r
= FLD_MOD(r
, ticks
, 28, 16); /* HS_TX_TO_COUNTER */
3622 dsi_write_reg(dsidev
, DSI_TIMING2
, r
);
3624 total_ticks
= ticks
* (x16
? 16 : 1) * (x4
? 4 : 1);
3626 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3628 ticks
, x4
? " x4" : "", x16
? " x16" : "",
3629 (total_ticks
* 1000) / (fck
/ 1000 / 1000));
3632 static void dsi_config_vp_num_line_buffers(struct platform_device
*dsidev
)
3634 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3635 int num_line_buffers
;
3637 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3638 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
3639 struct omap_video_timings
*timings
= &dsi
->timings
;
3641 * Don't use line buffers if width is greater than the video
3642 * port's line buffer size
3644 if (dsi
->line_buffer_size
<= timings
->x_res
* bpp
/ 8)
3645 num_line_buffers
= 0;
3647 num_line_buffers
= 2;
3649 /* Use maximum number of line buffers in command mode */
3650 num_line_buffers
= 2;
3654 REG_FLD_MOD(dsidev
, DSI_CTRL
, num_line_buffers
, 13, 12);
3657 static void dsi_config_vp_sync_events(struct platform_device
*dsidev
)
3659 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3663 if (dsi
->vm_timings
.trans_mode
== OMAP_DSS_DSI_PULSE_MODE
)
3668 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3669 r
= FLD_MOD(r
, 1, 9, 9); /* VP_DE_POL */
3670 r
= FLD_MOD(r
, 1, 10, 10); /* VP_HSYNC_POL */
3671 r
= FLD_MOD(r
, 1, 11, 11); /* VP_VSYNC_POL */
3672 r
= FLD_MOD(r
, 1, 15, 15); /* VP_VSYNC_START */
3673 r
= FLD_MOD(r
, sync_end
, 16, 16); /* VP_VSYNC_END */
3674 r
= FLD_MOD(r
, 1, 17, 17); /* VP_HSYNC_START */
3675 r
= FLD_MOD(r
, sync_end
, 18, 18); /* VP_HSYNC_END */
3676 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3679 static void dsi_config_blanking_modes(struct platform_device
*dsidev
)
3681 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3682 int blanking_mode
= dsi
->vm_timings
.blanking_mode
;
3683 int hfp_blanking_mode
= dsi
->vm_timings
.hfp_blanking_mode
;
3684 int hbp_blanking_mode
= dsi
->vm_timings
.hbp_blanking_mode
;
3685 int hsa_blanking_mode
= dsi
->vm_timings
.hsa_blanking_mode
;
3689 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3690 * 1 = Long blanking packets are sent in corresponding blanking periods
3692 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3693 r
= FLD_MOD(r
, blanking_mode
, 20, 20); /* BLANKING_MODE */
3694 r
= FLD_MOD(r
, hfp_blanking_mode
, 21, 21); /* HFP_BLANKING */
3695 r
= FLD_MOD(r
, hbp_blanking_mode
, 22, 22); /* HBP_BLANKING */
3696 r
= FLD_MOD(r
, hsa_blanking_mode
, 23, 23); /* HSA_BLANKING */
3697 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3701 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3702 * results in maximum transition time for data and clock lanes to enter and
3703 * exit HS mode. Hence, this is the scenario where the least amount of command
3704 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3705 * clock cycles that can be used to interleave command mode data in HS so that
3706 * all scenarios are satisfied.
3708 static int dsi_compute_interleave_hs(int blank
, bool ddr_alwon
, int enter_hs
,
3709 int exit_hs
, int exiths_clk
, int ddr_pre
, int ddr_post
)
3714 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3715 * time of data lanes only, if it isn't set, we need to consider HS
3716 * transition time of both data and clock lanes. HS transition time
3717 * of Scenario 3 is considered.
3720 transition
= enter_hs
+ exit_hs
+ max(enter_hs
, 2) + 1;
3723 trans1
= ddr_pre
+ enter_hs
+ exit_hs
+ max(enter_hs
, 2) + 1;
3724 trans2
= ddr_pre
+ enter_hs
+ exiths_clk
+ ddr_post
+ ddr_pre
+
3726 transition
= max(trans1
, trans2
);
3729 return blank
> transition
? blank
- transition
: 0;
3733 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3734 * results in maximum transition time for data lanes to enter and exit LP mode.
3735 * Hence, this is the scenario where the least amount of command mode data can
3736 * be interleaved. We program the minimum amount of bytes that can be
3737 * interleaved in LP so that all scenarios are satisfied.
3739 static int dsi_compute_interleave_lp(int blank
, int enter_hs
, int exit_hs
,
3740 int lp_clk_div
, int tdsi_fclk
)
3742 int trans_lp
; /* time required for a LP transition, in TXBYTECLKHS */
3743 int tlp_avail
; /* time left for interleaving commands, in CLKIN4DDR */
3744 int ttxclkesc
; /* period of LP transmit escape clock, in CLKIN4DDR */
3745 int thsbyte_clk
= 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3746 int lp_inter
; /* cmd mode data that can be interleaved, in bytes */
3748 /* maximum LP transition time according to Scenario 1 */
3749 trans_lp
= exit_hs
+ max(enter_hs
, 2) + 1;
3751 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3752 tlp_avail
= thsbyte_clk
* (blank
- trans_lp
);
3754 ttxclkesc
= tdsi_fclk
* lp_clk_div
;
3756 lp_inter
= ((tlp_avail
- 8 * thsbyte_clk
- 5 * tdsi_fclk
) / ttxclkesc
-
3759 return max(lp_inter
, 0);
3762 static void dsi_config_cmd_mode_interleaving(struct platform_device
*dsidev
)
3764 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3766 int hfp_blanking_mode
, hbp_blanking_mode
, hsa_blanking_mode
;
3767 int hsa
, hfp
, hbp
, width_bytes
, bllp
, lp_clk_div
;
3768 int ddr_clk_pre
, ddr_clk_post
, enter_hs_mode_lat
, exit_hs_mode_lat
;
3769 int tclk_trail
, ths_exit
, exiths_clk
;
3771 struct omap_video_timings
*timings
= &dsi
->timings
;
3772 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
3773 int ndl
= dsi
->num_lanes_used
- 1;
3774 int dsi_fclk_hsdiv
= dsi
->user_dsi_cinfo
.regm_dsi
+ 1;
3775 int hsa_interleave_hs
= 0, hsa_interleave_lp
= 0;
3776 int hfp_interleave_hs
= 0, hfp_interleave_lp
= 0;
3777 int hbp_interleave_hs
= 0, hbp_interleave_lp
= 0;
3778 int bl_interleave_hs
= 0, bl_interleave_lp
= 0;
3781 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3782 blanking_mode
= FLD_GET(r
, 20, 20);
3783 hfp_blanking_mode
= FLD_GET(r
, 21, 21);
3784 hbp_blanking_mode
= FLD_GET(r
, 22, 22);
3785 hsa_blanking_mode
= FLD_GET(r
, 23, 23);
3787 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
3788 hbp
= FLD_GET(r
, 11, 0);
3789 hfp
= FLD_GET(r
, 23, 12);
3790 hsa
= FLD_GET(r
, 31, 24);
3792 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3793 ddr_clk_post
= FLD_GET(r
, 7, 0);
3794 ddr_clk_pre
= FLD_GET(r
, 15, 8);
3796 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING7
);
3797 exit_hs_mode_lat
= FLD_GET(r
, 15, 0);
3798 enter_hs_mode_lat
= FLD_GET(r
, 31, 16);
3800 r
= dsi_read_reg(dsidev
, DSI_CLK_CTRL
);
3801 lp_clk_div
= FLD_GET(r
, 12, 0);
3802 ddr_alwon
= FLD_GET(r
, 13, 13);
3804 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3805 ths_exit
= FLD_GET(r
, 7, 0);
3807 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3808 tclk_trail
= FLD_GET(r
, 15, 8);
3810 exiths_clk
= ths_exit
+ tclk_trail
;
3812 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
3813 bllp
= hbp
+ hfp
+ hsa
+ DIV_ROUND_UP(width_bytes
+ 6, ndl
);
3815 if (!hsa_blanking_mode
) {
3816 hsa_interleave_hs
= dsi_compute_interleave_hs(hsa
, ddr_alwon
,
3817 enter_hs_mode_lat
, exit_hs_mode_lat
,
3818 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3819 hsa_interleave_lp
= dsi_compute_interleave_lp(hsa
,
3820 enter_hs_mode_lat
, exit_hs_mode_lat
,
3821 lp_clk_div
, dsi_fclk_hsdiv
);
3824 if (!hfp_blanking_mode
) {
3825 hfp_interleave_hs
= dsi_compute_interleave_hs(hfp
, ddr_alwon
,
3826 enter_hs_mode_lat
, exit_hs_mode_lat
,
3827 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3828 hfp_interleave_lp
= dsi_compute_interleave_lp(hfp
,
3829 enter_hs_mode_lat
, exit_hs_mode_lat
,
3830 lp_clk_div
, dsi_fclk_hsdiv
);
3833 if (!hbp_blanking_mode
) {
3834 hbp_interleave_hs
= dsi_compute_interleave_hs(hbp
, ddr_alwon
,
3835 enter_hs_mode_lat
, exit_hs_mode_lat
,
3836 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3838 hbp_interleave_lp
= dsi_compute_interleave_lp(hbp
,
3839 enter_hs_mode_lat
, exit_hs_mode_lat
,
3840 lp_clk_div
, dsi_fclk_hsdiv
);
3843 if (!blanking_mode
) {
3844 bl_interleave_hs
= dsi_compute_interleave_hs(bllp
, ddr_alwon
,
3845 enter_hs_mode_lat
, exit_hs_mode_lat
,
3846 exiths_clk
, ddr_clk_pre
, ddr_clk_post
);
3848 bl_interleave_lp
= dsi_compute_interleave_lp(bllp
,
3849 enter_hs_mode_lat
, exit_hs_mode_lat
,
3850 lp_clk_div
, dsi_fclk_hsdiv
);
3853 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3854 hsa_interleave_hs
, hfp_interleave_hs
, hbp_interleave_hs
,
3857 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3858 hsa_interleave_lp
, hfp_interleave_lp
, hbp_interleave_lp
,
3861 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING4
);
3862 r
= FLD_MOD(r
, hsa_interleave_hs
, 23, 16);
3863 r
= FLD_MOD(r
, hfp_interleave_hs
, 15, 8);
3864 r
= FLD_MOD(r
, hbp_interleave_hs
, 7, 0);
3865 dsi_write_reg(dsidev
, DSI_VM_TIMING4
, r
);
3867 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING5
);
3868 r
= FLD_MOD(r
, hsa_interleave_lp
, 23, 16);
3869 r
= FLD_MOD(r
, hfp_interleave_lp
, 15, 8);
3870 r
= FLD_MOD(r
, hbp_interleave_lp
, 7, 0);
3871 dsi_write_reg(dsidev
, DSI_VM_TIMING5
, r
);
3873 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING6
);
3874 r
= FLD_MOD(r
, bl_interleave_hs
, 31, 15);
3875 r
= FLD_MOD(r
, bl_interleave_lp
, 16, 0);
3876 dsi_write_reg(dsidev
, DSI_VM_TIMING6
, r
);
3879 static int dsi_proto_config(struct platform_device
*dsidev
)
3881 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3885 dsi_config_tx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3890 dsi_config_rx_fifo(dsidev
, DSI_FIFO_SIZE_32
,
3895 /* XXX what values for the timeouts? */
3896 dsi_set_stop_state_counter(dsidev
, 0x1000, false, false);
3897 dsi_set_ta_timeout(dsidev
, 0x1fff, true, true);
3898 dsi_set_lp_rx_timeout(dsidev
, 0x1fff, true, true);
3899 dsi_set_hs_tx_timeout(dsidev
, 0x1fff, true, true);
3901 switch (dsi_get_pixel_size(dsi
->pix_fmt
)) {
3916 r
= dsi_read_reg(dsidev
, DSI_CTRL
);
3917 r
= FLD_MOD(r
, 1, 1, 1); /* CS_RX_EN */
3918 r
= FLD_MOD(r
, 1, 2, 2); /* ECC_RX_EN */
3919 r
= FLD_MOD(r
, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3920 r
= FLD_MOD(r
, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3921 r
= FLD_MOD(r
, buswidth
, 7, 6); /* VP_DATA_BUS_WIDTH */
3922 r
= FLD_MOD(r
, 0, 8, 8); /* VP_CLK_POL */
3923 r
= FLD_MOD(r
, 1, 14, 14); /* TRIGGER_RESET_MODE */
3924 r
= FLD_MOD(r
, 1, 19, 19); /* EOT_ENABLE */
3925 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC
)) {
3926 r
= FLD_MOD(r
, 1, 24, 24); /* DCS_CMD_ENABLE */
3927 /* DCS_CMD_CODE, 1=start, 0=continue */
3928 r
= FLD_MOD(r
, 0, 25, 25);
3931 dsi_write_reg(dsidev
, DSI_CTRL
, r
);
3933 dsi_config_vp_num_line_buffers(dsidev
);
3935 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
3936 dsi_config_vp_sync_events(dsidev
);
3937 dsi_config_blanking_modes(dsidev
);
3938 dsi_config_cmd_mode_interleaving(dsidev
);
3941 dsi_vc_initial_config(dsidev
, 0);
3942 dsi_vc_initial_config(dsidev
, 1);
3943 dsi_vc_initial_config(dsidev
, 2);
3944 dsi_vc_initial_config(dsidev
, 3);
3949 static void dsi_proto_timings(struct platform_device
*dsidev
)
3951 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
3952 unsigned tlpx
, tclk_zero
, tclk_prepare
, tclk_trail
;
3953 unsigned tclk_pre
, tclk_post
;
3954 unsigned ths_prepare
, ths_prepare_ths_zero
, ths_zero
;
3955 unsigned ths_trail
, ths_exit
;
3956 unsigned ddr_clk_pre
, ddr_clk_post
;
3957 unsigned enter_hs_mode_lat
, exit_hs_mode_lat
;
3959 int ndl
= dsi
->num_lanes_used
- 1;
3962 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG0
);
3963 ths_prepare
= FLD_GET(r
, 31, 24);
3964 ths_prepare_ths_zero
= FLD_GET(r
, 23, 16);
3965 ths_zero
= ths_prepare_ths_zero
- ths_prepare
;
3966 ths_trail
= FLD_GET(r
, 15, 8);
3967 ths_exit
= FLD_GET(r
, 7, 0);
3969 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG1
);
3970 tlpx
= FLD_GET(r
, 20, 16) * 2;
3971 tclk_trail
= FLD_GET(r
, 15, 8);
3972 tclk_zero
= FLD_GET(r
, 7, 0);
3974 r
= dsi_read_reg(dsidev
, DSI_DSIPHY_CFG2
);
3975 tclk_prepare
= FLD_GET(r
, 7, 0);
3979 /* min 60ns + 52*UI */
3980 tclk_post
= ns2ddr(dsidev
, 60) + 26;
3982 ths_eot
= DIV_ROUND_UP(4, ndl
);
3984 ddr_clk_pre
= DIV_ROUND_UP(tclk_pre
+ tlpx
+ tclk_zero
+ tclk_prepare
,
3986 ddr_clk_post
= DIV_ROUND_UP(tclk_post
+ ths_trail
, 4) + ths_eot
;
3988 BUG_ON(ddr_clk_pre
== 0 || ddr_clk_pre
> 255);
3989 BUG_ON(ddr_clk_post
== 0 || ddr_clk_post
> 255);
3991 r
= dsi_read_reg(dsidev
, DSI_CLK_TIMING
);
3992 r
= FLD_MOD(r
, ddr_clk_pre
, 15, 8);
3993 r
= FLD_MOD(r
, ddr_clk_post
, 7, 0);
3994 dsi_write_reg(dsidev
, DSI_CLK_TIMING
, r
);
3996 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
4000 enter_hs_mode_lat
= 1 + DIV_ROUND_UP(tlpx
, 4) +
4001 DIV_ROUND_UP(ths_prepare
, 4) +
4002 DIV_ROUND_UP(ths_zero
+ 3, 4);
4004 exit_hs_mode_lat
= DIV_ROUND_UP(ths_trail
+ ths_exit
, 4) + 1 + ths_eot
;
4006 r
= FLD_VAL(enter_hs_mode_lat
, 31, 16) |
4007 FLD_VAL(exit_hs_mode_lat
, 15, 0);
4008 dsi_write_reg(dsidev
, DSI_VM_TIMING7
, r
);
4010 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4011 enter_hs_mode_lat
, exit_hs_mode_lat
);
4013 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4014 /* TODO: Implement a video mode check_timings function */
4015 int hsa
= dsi
->vm_timings
.hsa
;
4016 int hfp
= dsi
->vm_timings
.hfp
;
4017 int hbp
= dsi
->vm_timings
.hbp
;
4018 int vsa
= dsi
->vm_timings
.vsa
;
4019 int vfp
= dsi
->vm_timings
.vfp
;
4020 int vbp
= dsi
->vm_timings
.vbp
;
4021 int window_sync
= dsi
->vm_timings
.window_sync
;
4023 struct omap_video_timings
*timings
= &dsi
->timings
;
4024 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
4025 int tl
, t_he
, width_bytes
;
4027 hsync_end
= dsi
->vm_timings
.trans_mode
== OMAP_DSS_DSI_PULSE_MODE
;
4029 ((hsa
== 0 && ndl
== 3) ? 1 : DIV_ROUND_UP(4, ndl
)) : 0;
4031 width_bytes
= DIV_ROUND_UP(timings
->x_res
* bpp
, 8);
4033 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4034 tl
= DIV_ROUND_UP(4, ndl
) + (hsync_end
? hsa
: 0) + t_he
+ hfp
+
4035 DIV_ROUND_UP(width_bytes
+ 6, ndl
) + hbp
;
4037 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp
,
4038 hfp
, hsync_end
? hsa
: 0, tl
);
4039 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp
, vfp
,
4040 vsa
, timings
->y_res
);
4042 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING1
);
4043 r
= FLD_MOD(r
, hbp
, 11, 0); /* HBP */
4044 r
= FLD_MOD(r
, hfp
, 23, 12); /* HFP */
4045 r
= FLD_MOD(r
, hsync_end
? hsa
: 0, 31, 24); /* HSA */
4046 dsi_write_reg(dsidev
, DSI_VM_TIMING1
, r
);
4048 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING2
);
4049 r
= FLD_MOD(r
, vbp
, 7, 0); /* VBP */
4050 r
= FLD_MOD(r
, vfp
, 15, 8); /* VFP */
4051 r
= FLD_MOD(r
, vsa
, 23, 16); /* VSA */
4052 r
= FLD_MOD(r
, window_sync
, 27, 24); /* WINDOW_SYNC */
4053 dsi_write_reg(dsidev
, DSI_VM_TIMING2
, r
);
4055 r
= dsi_read_reg(dsidev
, DSI_VM_TIMING3
);
4056 r
= FLD_MOD(r
, timings
->y_res
, 14, 0); /* VACT */
4057 r
= FLD_MOD(r
, tl
, 31, 16); /* TL */
4058 dsi_write_reg(dsidev
, DSI_VM_TIMING3
, r
);
4062 int omapdss_dsi_configure_pins(struct omap_dss_device
*dssdev
,
4063 const struct omap_dsi_pin_config
*pin_cfg
)
4065 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4066 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4069 struct dsi_lane_config lanes
[DSI_MAX_NR_LANES
];
4073 static const enum dsi_lane_function functions
[] = {
4081 num_pins
= pin_cfg
->num_pins
;
4082 pins
= pin_cfg
->pins
;
4084 if (num_pins
< 4 || num_pins
> dsi
->num_lanes_supported
* 2
4085 || num_pins
% 2 != 0)
4088 for (i
= 0; i
< DSI_MAX_NR_LANES
; ++i
)
4089 lanes
[i
].function
= DSI_LANE_UNUSED
;
4093 for (i
= 0; i
< num_pins
; i
+= 2) {
4100 if (dx
< 0 || dx
>= dsi
->num_lanes_supported
* 2)
4103 if (dy
< 0 || dy
>= dsi
->num_lanes_supported
* 2)
4118 lanes
[lane
].function
= functions
[i
/ 2];
4119 lanes
[lane
].polarity
= pol
;
4123 memcpy(dsi
->lanes
, lanes
, sizeof(dsi
->lanes
));
4124 dsi
->num_lanes_used
= num_lanes
;
4128 EXPORT_SYMBOL(omapdss_dsi_configure_pins
);
4130 int dsi_enable_video_output(struct omap_dss_device
*dssdev
, int channel
)
4132 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4133 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4134 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4135 int bpp
= dsi_get_pixel_size(dsi
->pix_fmt
);
4136 struct omap_dss_output
*out
= &dsi
->output
;
4141 if (out
== NULL
|| out
->manager
== NULL
) {
4142 DSSERR("failed to enable display: no output/manager\n");
4146 r
= dsi_display_init_dispc(dsidev
, mgr
);
4148 goto err_init_dispc
;
4150 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4151 switch (dsi
->pix_fmt
) {
4152 case OMAP_DSS_DSI_FMT_RGB888
:
4153 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
4155 case OMAP_DSS_DSI_FMT_RGB666
:
4156 data_type
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
4158 case OMAP_DSS_DSI_FMT_RGB666_PACKED
:
4159 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
4161 case OMAP_DSS_DSI_FMT_RGB565
:
4162 data_type
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
4169 dsi_if_enable(dsidev
, false);
4170 dsi_vc_enable(dsidev
, channel
, false);
4172 /* MODE, 1 = video mode */
4173 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 1, 4, 4);
4175 word_count
= DIV_ROUND_UP(dsi
->timings
.x_res
* bpp
, 8);
4177 dsi_vc_write_long_header(dsidev
, channel
, data_type
,
4180 dsi_vc_enable(dsidev
, channel
, true);
4181 dsi_if_enable(dsidev
, true);
4184 r
= dss_mgr_enable(mgr
);
4186 goto err_mgr_enable
;
4191 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4192 dsi_if_enable(dsidev
, false);
4193 dsi_vc_enable(dsidev
, channel
, false);
4196 dsi_display_uninit_dispc(dsidev
, mgr
);
4200 EXPORT_SYMBOL(dsi_enable_video_output
);
4202 void dsi_disable_video_output(struct omap_dss_device
*dssdev
, int channel
)
4204 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4205 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4206 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4208 if (dsi
->mode
== OMAP_DSS_DSI_VIDEO_MODE
) {
4209 dsi_if_enable(dsidev
, false);
4210 dsi_vc_enable(dsidev
, channel
, false);
4212 /* MODE, 0 = command mode */
4213 REG_FLD_MOD(dsidev
, DSI_VC_CTRL(channel
), 0, 4, 4);
4215 dsi_vc_enable(dsidev
, channel
, true);
4216 dsi_if_enable(dsidev
, true);
4219 dss_mgr_disable(mgr
);
4221 dsi_display_uninit_dispc(dsidev
, mgr
);
4223 EXPORT_SYMBOL(dsi_disable_video_output
);
4225 static void dsi_update_screen_dispc(struct platform_device
*dsidev
)
4227 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4228 struct omap_overlay_manager
*mgr
= dsi
->output
.manager
;
4233 unsigned packet_payload
;
4234 unsigned packet_len
;
4237 const unsigned channel
= dsi
->update_channel
;
4238 const unsigned line_buf_size
= dsi
->line_buffer_size
;
4239 u16 w
= dsi
->timings
.x_res
;
4240 u16 h
= dsi
->timings
.y_res
;
4242 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w
, h
);
4244 dsi_vc_config_source(dsidev
, channel
, DSI_VC_SOURCE_VP
);
4246 bytespp
= dsi_get_pixel_size(dsi
->pix_fmt
) / 8;
4247 bytespl
= w
* bytespp
;
4248 bytespf
= bytespl
* h
;
4250 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4251 * number of lines in a packet. See errata about VP_CLK_RATIO */
4253 if (bytespf
< line_buf_size
)
4254 packet_payload
= bytespf
;
4256 packet_payload
= (line_buf_size
) / bytespl
* bytespl
;
4258 packet_len
= packet_payload
+ 1; /* 1 byte for DCS cmd */
4259 total_len
= (bytespf
/ packet_payload
) * packet_len
;
4261 if (bytespf
% packet_payload
)
4262 total_len
+= (bytespf
% packet_payload
) + 1;
4264 l
= FLD_VAL(total_len
, 23, 0); /* TE_SIZE */
4265 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4267 dsi_vc_write_long_header(dsidev
, channel
, MIPI_DSI_DCS_LONG_WRITE
,
4270 if (dsi
->te_enabled
)
4271 l
= FLD_MOD(l
, 1, 30, 30); /* TE_EN */
4273 l
= FLD_MOD(l
, 1, 31, 31); /* TE_START */
4274 dsi_write_reg(dsidev
, DSI_VC_TE(channel
), l
);
4276 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4277 * because DSS interrupts are not capable of waking up the CPU and the
4278 * framedone interrupt could be delayed for quite a long time. I think
4279 * the same goes for any DSS interrupts, but for some reason I have not
4280 * seen the problem anywhere else than here.
4282 dispc_disable_sidle();
4284 dsi_perf_mark_start(dsidev
);
4286 r
= schedule_delayed_work(&dsi
->framedone_timeout_work
,
4287 msecs_to_jiffies(250));
4290 dss_mgr_set_timings(mgr
, &dsi
->timings
);
4292 dss_mgr_start_update(mgr
);
4294 if (dsi
->te_enabled
) {
4295 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4296 * for TE is longer than the timer allows */
4297 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 0, 15, 15); /* LP_RX_TO */
4299 dsi_vc_send_bta(dsidev
, channel
);
4301 #ifdef DSI_CATCH_MISSING_TE
4302 mod_timer(&dsi
->te_timer
, jiffies
+ msecs_to_jiffies(250));
4307 #ifdef DSI_CATCH_MISSING_TE
4308 static void dsi_te_timeout(unsigned long arg
)
4310 DSSERR("TE not received for 250ms!\n");
4314 static void dsi_handle_framedone(struct platform_device
*dsidev
, int error
)
4316 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4318 /* SIDLEMODE back to smart-idle */
4319 dispc_enable_sidle();
4321 if (dsi
->te_enabled
) {
4322 /* enable LP_RX_TO again after the TE */
4323 REG_FLD_MOD(dsidev
, DSI_TIMING2
, 1, 15, 15); /* LP_RX_TO */
4326 dsi
->framedone_callback(error
, dsi
->framedone_data
);
4329 dsi_perf_show(dsidev
, "DISPC");
4332 static void dsi_framedone_timeout_work_callback(struct work_struct
*work
)
4334 struct dsi_data
*dsi
= container_of(work
, struct dsi_data
,
4335 framedone_timeout_work
.work
);
4336 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4337 * 250ms which would conflict with this timeout work. What should be
4338 * done is first cancel the transfer on the HW, and then cancel the
4339 * possibly scheduled framedone work. However, cancelling the transfer
4340 * on the HW is buggy, and would probably require resetting the whole
4343 DSSERR("Framedone not received for 250ms!\n");
4345 dsi_handle_framedone(dsi
->pdev
, -ETIMEDOUT
);
4348 static void dsi_framedone_irq_callback(void *data
)
4350 struct platform_device
*dsidev
= (struct platform_device
*) data
;
4351 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4353 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4354 * turns itself off. However, DSI still has the pixels in its buffers,
4355 * and is sending the data.
4358 cancel_delayed_work(&dsi
->framedone_timeout_work
);
4360 dsi_handle_framedone(dsidev
, 0);
4363 int omap_dsi_update(struct omap_dss_device
*dssdev
, int channel
,
4364 void (*callback
)(int, void *), void *data
)
4366 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4367 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4370 dsi_perf_mark_setup(dsidev
);
4372 dsi
->update_channel
= channel
;
4374 dsi
->framedone_callback
= callback
;
4375 dsi
->framedone_data
= data
;
4377 dw
= dsi
->timings
.x_res
;
4378 dh
= dsi
->timings
.y_res
;
4381 dsi
->update_bytes
= dw
* dh
*
4382 dsi_get_pixel_size(dsi
->pix_fmt
) / 8;
4384 dsi_update_screen_dispc(dsidev
);
4388 EXPORT_SYMBOL(omap_dsi_update
);
4392 static int dsi_configure_dispc_clocks(struct platform_device
*dsidev
)
4394 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4395 struct dispc_clock_info dispc_cinfo
;
4399 fck
= dsi_get_pll_hsdiv_dispc_rate(dsidev
);
4401 dispc_cinfo
.lck_div
= dsi
->user_dispc_cinfo
.lck_div
;
4402 dispc_cinfo
.pck_div
= dsi
->user_dispc_cinfo
.pck_div
;
4404 r
= dispc_calc_clock_rates(fck
, &dispc_cinfo
);
4406 DSSERR("Failed to calc dispc clocks\n");
4410 dsi
->mgr_config
.clock_info
= dispc_cinfo
;
4415 static int dsi_display_init_dispc(struct platform_device
*dsidev
,
4416 struct omap_overlay_manager
*mgr
)
4418 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4421 dss_select_lcd_clk_source(mgr
->id
, dsi
->module_id
== 0 ?
4422 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
:
4423 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC
);
4425 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
) {
4426 r
= dss_mgr_register_framedone_handler(mgr
,
4427 dsi_framedone_irq_callback
, dsidev
);
4429 DSSERR("can't register FRAMEDONE handler\n");
4433 dsi
->mgr_config
.stallmode
= true;
4434 dsi
->mgr_config
.fifohandcheck
= true;
4436 dsi
->mgr_config
.stallmode
= false;
4437 dsi
->mgr_config
.fifohandcheck
= false;
4441 * override interlace, logic level and edge related parameters in
4442 * omap_video_timings with default values
4444 dsi
->timings
.interlace
= false;
4445 dsi
->timings
.hsync_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4446 dsi
->timings
.vsync_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4447 dsi
->timings
.data_pclk_edge
= OMAPDSS_DRIVE_SIG_RISING_EDGE
;
4448 dsi
->timings
.de_level
= OMAPDSS_SIG_ACTIVE_HIGH
;
4449 dsi
->timings
.sync_pclk_edge
= OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES
;
4451 dss_mgr_set_timings(mgr
, &dsi
->timings
);
4453 r
= dsi_configure_dispc_clocks(dsidev
);
4457 dsi
->mgr_config
.io_pad_mode
= DSS_IO_PAD_MODE_BYPASS
;
4458 dsi
->mgr_config
.video_port_width
=
4459 dsi_get_pixel_size(dsi
->pix_fmt
);
4460 dsi
->mgr_config
.lcden_sig_polarity
= 0;
4462 dss_mgr_set_lcd_config(mgr
, &dsi
->mgr_config
);
4466 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
)
4467 dss_mgr_unregister_framedone_handler(mgr
,
4468 dsi_framedone_irq_callback
, dsidev
);
4470 dss_select_lcd_clk_source(mgr
->id
, OMAP_DSS_CLK_SRC_FCK
);
4474 static void dsi_display_uninit_dispc(struct platform_device
*dsidev
,
4475 struct omap_overlay_manager
*mgr
)
4477 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4479 if (dsi
->mode
== OMAP_DSS_DSI_CMD_MODE
)
4480 dss_mgr_unregister_framedone_handler(mgr
,
4481 dsi_framedone_irq_callback
, dsidev
);
4483 dss_select_lcd_clk_source(mgr
->id
, OMAP_DSS_CLK_SRC_FCK
);
4486 static int dsi_configure_dsi_clocks(struct platform_device
*dsidev
)
4488 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4489 struct dsi_clock_info cinfo
;
4492 cinfo
= dsi
->user_dsi_cinfo
;
4494 r
= dsi_calc_clock_rates(dsidev
, &cinfo
);
4496 DSSERR("Failed to calc dsi clocks\n");
4500 r
= dsi_pll_set_clock_div(dsidev
, &cinfo
);
4502 DSSERR("Failed to set dsi clocks\n");
4509 static int dsi_display_init_dsi(struct platform_device
*dsidev
)
4511 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4514 r
= dsi_pll_init(dsidev
, true, true);
4518 r
= dsi_configure_dsi_clocks(dsidev
);
4522 dss_select_dsi_clk_source(dsi
->module_id
, dsi
->module_id
== 0 ?
4523 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
:
4524 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI
);
4528 r
= dsi_cio_init(dsidev
);
4532 _dsi_print_reset_status(dsidev
);
4534 dsi_proto_timings(dsidev
);
4535 dsi_set_lp_clk_divisor(dsidev
);
4538 _dsi_print_reset_status(dsidev
);
4540 r
= dsi_proto_config(dsidev
);
4544 /* enable interface */
4545 dsi_vc_enable(dsidev
, 0, 1);
4546 dsi_vc_enable(dsidev
, 1, 1);
4547 dsi_vc_enable(dsidev
, 2, 1);
4548 dsi_vc_enable(dsidev
, 3, 1);
4549 dsi_if_enable(dsidev
, 1);
4550 dsi_force_tx_stop_mode_io(dsidev
);
4554 dsi_cio_uninit(dsidev
);
4556 dss_select_dsi_clk_source(dsi
->module_id
, OMAP_DSS_CLK_SRC_FCK
);
4558 dsi_pll_uninit(dsidev
, true);
4563 static void dsi_display_uninit_dsi(struct platform_device
*dsidev
,
4564 bool disconnect_lanes
, bool enter_ulps
)
4566 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4568 if (enter_ulps
&& !dsi
->ulps_enabled
)
4569 dsi_enter_ulps(dsidev
);
4571 /* disable interface */
4572 dsi_if_enable(dsidev
, 0);
4573 dsi_vc_enable(dsidev
, 0, 0);
4574 dsi_vc_enable(dsidev
, 1, 0);
4575 dsi_vc_enable(dsidev
, 2, 0);
4576 dsi_vc_enable(dsidev
, 3, 0);
4578 dss_select_dsi_clk_source(dsi
->module_id
, OMAP_DSS_CLK_SRC_FCK
);
4579 dsi_cio_uninit(dsidev
);
4580 dsi_pll_uninit(dsidev
, disconnect_lanes
);
4583 int omapdss_dsi_display_enable(struct omap_dss_device
*dssdev
)
4585 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4586 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4589 DSSDBG("dsi_display_enable\n");
4591 WARN_ON(!dsi_bus_is_locked(dsidev
));
4593 mutex_lock(&dsi
->lock
);
4595 r
= dsi_runtime_get(dsidev
);
4599 dsi_enable_pll_clock(dsidev
, 1);
4601 _dsi_initialize_irq(dsidev
);
4603 r
= dsi_display_init_dsi(dsidev
);
4607 mutex_unlock(&dsi
->lock
);
4612 dsi_enable_pll_clock(dsidev
, 0);
4613 dsi_runtime_put(dsidev
);
4615 mutex_unlock(&dsi
->lock
);
4616 DSSDBG("dsi_display_enable FAILED\n");
4619 EXPORT_SYMBOL(omapdss_dsi_display_enable
);
4621 void omapdss_dsi_display_disable(struct omap_dss_device
*dssdev
,
4622 bool disconnect_lanes
, bool enter_ulps
)
4624 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4625 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4627 DSSDBG("dsi_display_disable\n");
4629 WARN_ON(!dsi_bus_is_locked(dsidev
));
4631 mutex_lock(&dsi
->lock
);
4633 dsi_sync_vc(dsidev
, 0);
4634 dsi_sync_vc(dsidev
, 1);
4635 dsi_sync_vc(dsidev
, 2);
4636 dsi_sync_vc(dsidev
, 3);
4638 dsi_display_uninit_dsi(dsidev
, disconnect_lanes
, enter_ulps
);
4640 dsi_runtime_put(dsidev
);
4641 dsi_enable_pll_clock(dsidev
, 0);
4643 mutex_unlock(&dsi
->lock
);
4645 EXPORT_SYMBOL(omapdss_dsi_display_disable
);
4647 int omapdss_dsi_enable_te(struct omap_dss_device
*dssdev
, bool enable
)
4649 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
4650 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
4652 dsi
->te_enabled
= enable
;
4655 EXPORT_SYMBOL(omapdss_dsi_enable_te
);
4657 #ifdef PRINT_VERBOSE_VM_TIMINGS
4658 static void print_dsi_vm(const char *str
,
4659 const struct omap_dss_dsi_videomode_timings
*t
)
4661 unsigned long byteclk
= t
->hsclk
/ 4;
4662 int bl
, wc
, pps
, tot
;
4664 wc
= DIV_ROUND_UP(t
->hact
* t
->bitspp
, 8);
4665 pps
= DIV_ROUND_UP(wc
+ 6, t
->ndl
); /* pixel packet size */
4666 bl
= t
->hss
+ t
->hsa
+ t
->hse
+ t
->hbp
+ t
->hfp
;
4669 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4671 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4672 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4675 t
->hss
, t
->hsa
, t
->hse
, t
->hbp
, pps
, t
->hfp
,
4691 static void print_dispc_vm(const char *str
, const struct omap_video_timings
*t
)
4693 unsigned long pck
= t
->pixel_clock
* 1000;
4697 bl
= t
->hsw
+ t
->hbp
+ t
->hfp
;
4700 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4702 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4703 "%u/%u/%u/%u = %u + %u = %u\n",
4706 t
->hsw
, t
->hbp
, hact
, t
->hfp
,
4718 /* note: this is not quite accurate */
4719 static void print_dsi_dispc_vm(const char *str
,
4720 const struct omap_dss_dsi_videomode_timings
*t
)
4722 struct omap_video_timings vm
= { 0 };
4723 unsigned long byteclk
= t
->hsclk
/ 4;
4726 int dsi_hact
, dsi_htot
;
4728 dsi_tput
= (u64
)byteclk
* t
->ndl
* 8;
4729 pck
= (u32
)div64_u64(dsi_tput
, t
->bitspp
);
4730 dsi_hact
= DIV_ROUND_UP(DIV_ROUND_UP(t
->hact
* t
->bitspp
, 8) + 6, t
->ndl
);
4731 dsi_htot
= t
->hss
+ t
->hsa
+ t
->hse
+ t
->hbp
+ dsi_hact
+ t
->hfp
;
4733 vm
.pixel_clock
= pck
/ 1000;
4734 vm
.hsw
= div64_u64((u64
)(t
->hsa
+ t
->hse
) * pck
, byteclk
);
4735 vm
.hbp
= div64_u64((u64
)t
->hbp
* pck
, byteclk
);
4736 vm
.hfp
= div64_u64((u64
)t
->hfp
* pck
, byteclk
);
4739 print_dispc_vm(str
, &vm
);
4741 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4743 static bool dsi_cm_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
4744 unsigned long pck
, void *data
)
4746 struct dsi_clk_calc_ctx
*ctx
= data
;
4747 struct omap_video_timings
*t
= &ctx
->dispc_vm
;
4749 ctx
->dispc_cinfo
.lck_div
= lckd
;
4750 ctx
->dispc_cinfo
.pck_div
= pckd
;
4751 ctx
->dispc_cinfo
.lck
= lck
;
4752 ctx
->dispc_cinfo
.pck
= pck
;
4754 *t
= *ctx
->config
->timings
;
4755 t
->pixel_clock
= pck
/ 1000;
4756 t
->x_res
= ctx
->config
->timings
->x_res
;
4757 t
->y_res
= ctx
->config
->timings
->y_res
;
4758 t
->hsw
= t
->hfp
= t
->hbp
= t
->vsw
= 1;
4759 t
->vfp
= t
->vbp
= 0;
4764 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc
, unsigned long dispc
,
4767 struct dsi_clk_calc_ctx
*ctx
= data
;
4769 ctx
->dsi_cinfo
.regm_dispc
= regm_dispc
;
4770 ctx
->dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
= dispc
;
4772 return dispc_div_calc(dispc
, ctx
->req_pck_min
, ctx
->req_pck_max
,
4773 dsi_cm_calc_dispc_cb
, ctx
);
4776 static bool dsi_cm_calc_pll_cb(int regn
, int regm
, unsigned long fint
,
4777 unsigned long pll
, void *data
)
4779 struct dsi_clk_calc_ctx
*ctx
= data
;
4781 ctx
->dsi_cinfo
.regn
= regn
;
4782 ctx
->dsi_cinfo
.regm
= regm
;
4783 ctx
->dsi_cinfo
.fint
= fint
;
4784 ctx
->dsi_cinfo
.clkin4ddr
= pll
;
4786 return dsi_hsdiv_calc(ctx
->dsidev
, pll
, ctx
->req_pck_min
,
4787 dsi_cm_calc_hsdiv_cb
, ctx
);
4790 static bool dsi_cm_calc(struct dsi_data
*dsi
,
4791 const struct omap_dss_dsi_config
*cfg
,
4792 struct dsi_clk_calc_ctx
*ctx
)
4794 unsigned long clkin
;
4796 unsigned long pll_min
, pll_max
;
4797 unsigned long pck
, txbyteclk
;
4799 clkin
= clk_get_rate(dsi
->sys_clk
);
4800 bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
4801 ndl
= dsi
->num_lanes_used
- 1;
4804 * Here we should calculate minimum txbyteclk to be able to send the
4805 * frame in time, and also to handle TE. That's not very simple, though,
4806 * especially as we go to LP between each pixel packet due to HW
4807 * "feature". So let's just estimate very roughly and multiply by 1.5.
4809 pck
= cfg
->timings
->pixel_clock
* 1000;
4811 txbyteclk
= pck
* bitspp
/ 8 / ndl
;
4813 memset(ctx
, 0, sizeof(*ctx
));
4814 ctx
->dsidev
= dsi
->pdev
;
4816 ctx
->req_pck_min
= pck
;
4817 ctx
->req_pck_nom
= pck
;
4818 ctx
->req_pck_max
= pck
* 3 / 2;
4819 ctx
->dsi_cinfo
.clkin
= clkin
;
4821 pll_min
= max(cfg
->hs_clk_min
* 4, txbyteclk
* 4 * 4);
4822 pll_max
= cfg
->hs_clk_max
* 4;
4824 return dsi_pll_calc(dsi
->pdev
, clkin
,
4826 dsi_cm_calc_pll_cb
, ctx
);
4829 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx
*ctx
)
4831 struct dsi_data
*dsi
= dsi_get_dsidrv_data(ctx
->dsidev
);
4832 const struct omap_dss_dsi_config
*cfg
= ctx
->config
;
4833 int bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
4834 int ndl
= dsi
->num_lanes_used
- 1;
4835 unsigned long hsclk
= ctx
->dsi_cinfo
.clkin4ddr
/ 4;
4836 unsigned long byteclk
= hsclk
/ 4;
4838 unsigned long dispc_pck
, req_pck_min
, req_pck_nom
, req_pck_max
;
4840 int panel_htot
, panel_hbl
; /* pixels */
4841 int dispc_htot
, dispc_hbl
; /* pixels */
4842 int dsi_htot
, dsi_hact
, dsi_hbl
, hss
, hse
; /* byteclks */
4844 const struct omap_video_timings
*req_vm
;
4845 struct omap_video_timings
*dispc_vm
;
4846 struct omap_dss_dsi_videomode_timings
*dsi_vm
;
4847 u64 dsi_tput
, dispc_tput
;
4849 dsi_tput
= (u64
)byteclk
* ndl
* 8;
4851 req_vm
= cfg
->timings
;
4852 req_pck_min
= ctx
->req_pck_min
;
4853 req_pck_max
= ctx
->req_pck_max
;
4854 req_pck_nom
= ctx
->req_pck_nom
;
4856 dispc_pck
= ctx
->dispc_cinfo
.pck
;
4857 dispc_tput
= (u64
)dispc_pck
* bitspp
;
4859 xres
= req_vm
->x_res
;
4861 panel_hbl
= req_vm
->hfp
+ req_vm
->hbp
+ req_vm
->hsw
;
4862 panel_htot
= xres
+ panel_hbl
;
4864 dsi_hact
= DIV_ROUND_UP(DIV_ROUND_UP(xres
* bitspp
, 8) + 6, ndl
);
4867 * When there are no line buffers, DISPC and DSI must have the
4868 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4870 if (dsi
->line_buffer_size
< xres
* bitspp
/ 8) {
4871 if (dispc_tput
!= dsi_tput
)
4874 if (dispc_tput
< dsi_tput
)
4878 /* DSI tput must be over the min requirement */
4879 if (dsi_tput
< (u64
)bitspp
* req_pck_min
)
4882 /* When non-burst mode, DSI tput must be below max requirement. */
4883 if (cfg
->trans_mode
!= OMAP_DSS_DSI_BURST_MODE
) {
4884 if (dsi_tput
> (u64
)bitspp
* req_pck_max
)
4888 hss
= DIV_ROUND_UP(4, ndl
);
4890 if (cfg
->trans_mode
== OMAP_DSS_DSI_PULSE_MODE
) {
4891 if (ndl
== 3 && req_vm
->hsw
== 0)
4894 hse
= DIV_ROUND_UP(4, ndl
);
4899 /* DSI htot to match the panel's nominal pck */
4900 dsi_htot
= div64_u64((u64
)panel_htot
* byteclk
, req_pck_nom
);
4902 /* fail if there would be no time for blanking */
4903 if (dsi_htot
< hss
+ hse
+ dsi_hact
)
4906 /* total DSI blanking needed to achieve panel's TL */
4907 dsi_hbl
= dsi_htot
- dsi_hact
;
4909 /* DISPC htot to match the DSI TL */
4910 dispc_htot
= div64_u64((u64
)dsi_htot
* dispc_pck
, byteclk
);
4912 /* verify that the DSI and DISPC TLs are the same */
4913 if ((u64
)dsi_htot
* dispc_pck
!= (u64
)dispc_htot
* byteclk
)
4916 dispc_hbl
= dispc_htot
- xres
;
4918 /* setup DSI videomode */
4920 dsi_vm
= &ctx
->dsi_vm
;
4921 memset(dsi_vm
, 0, sizeof(*dsi_vm
));
4923 dsi_vm
->hsclk
= hsclk
;
4926 dsi_vm
->bitspp
= bitspp
;
4928 if (cfg
->trans_mode
!= OMAP_DSS_DSI_PULSE_MODE
) {
4930 } else if (ndl
== 3 && req_vm
->hsw
== 0) {
4933 hsa
= div64_u64((u64
)req_vm
->hsw
* byteclk
, req_pck_nom
);
4934 hsa
= max(hsa
- hse
, 1);
4937 hbp
= div64_u64((u64
)req_vm
->hbp
* byteclk
, req_pck_nom
);
4940 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4943 /* we need to take cycles from hbp */
4946 hbp
= max(hbp
- t
, 1);
4947 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4949 if (hfp
< 1 && hsa
> 0) {
4950 /* we need to take cycles from hsa */
4952 hsa
= max(hsa
- t
, 1);
4953 hfp
= dsi_hbl
- (hss
+ hsa
+ hse
+ hbp
);
4964 dsi_vm
->hact
= xres
;
4967 dsi_vm
->vsa
= req_vm
->vsw
;
4968 dsi_vm
->vbp
= req_vm
->vbp
;
4969 dsi_vm
->vact
= req_vm
->y_res
;
4970 dsi_vm
->vfp
= req_vm
->vfp
;
4972 dsi_vm
->trans_mode
= cfg
->trans_mode
;
4974 dsi_vm
->blanking_mode
= 0;
4975 dsi_vm
->hsa_blanking_mode
= 1;
4976 dsi_vm
->hfp_blanking_mode
= 1;
4977 dsi_vm
->hbp_blanking_mode
= 1;
4979 dsi_vm
->ddr_clk_always_on
= cfg
->ddr_clk_always_on
;
4980 dsi_vm
->window_sync
= 4;
4982 /* setup DISPC videomode */
4984 dispc_vm
= &ctx
->dispc_vm
;
4985 *dispc_vm
= *req_vm
;
4986 dispc_vm
->pixel_clock
= dispc_pck
/ 1000;
4988 if (cfg
->trans_mode
== OMAP_DSS_DSI_PULSE_MODE
) {
4989 hsa
= div64_u64((u64
)req_vm
->hsw
* dispc_pck
,
4996 hbp
= div64_u64((u64
)req_vm
->hbp
* dispc_pck
, req_pck_nom
);
4999 hfp
= dispc_hbl
- hsa
- hbp
;
5002 /* we need to take cycles from hbp */
5005 hbp
= max(hbp
- t
, 1);
5006 hfp
= dispc_hbl
- hsa
- hbp
;
5009 /* we need to take cycles from hsa */
5011 hsa
= max(hsa
- t
, 1);
5012 hfp
= dispc_hbl
- hsa
- hbp
;
5019 dispc_vm
->hfp
= hfp
;
5020 dispc_vm
->hsw
= hsa
;
5021 dispc_vm
->hbp
= hbp
;
5027 static bool dsi_vm_calc_dispc_cb(int lckd
, int pckd
, unsigned long lck
,
5028 unsigned long pck
, void *data
)
5030 struct dsi_clk_calc_ctx
*ctx
= data
;
5032 ctx
->dispc_cinfo
.lck_div
= lckd
;
5033 ctx
->dispc_cinfo
.pck_div
= pckd
;
5034 ctx
->dispc_cinfo
.lck
= lck
;
5035 ctx
->dispc_cinfo
.pck
= pck
;
5037 if (dsi_vm_calc_blanking(ctx
) == false)
5040 #ifdef PRINT_VERBOSE_VM_TIMINGS
5041 print_dispc_vm("dispc", &ctx
->dispc_vm
);
5042 print_dsi_vm("dsi ", &ctx
->dsi_vm
);
5043 print_dispc_vm("req ", ctx
->config
->timings
);
5044 print_dsi_dispc_vm("act ", &ctx
->dsi_vm
);
5050 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc
, unsigned long dispc
,
5053 struct dsi_clk_calc_ctx
*ctx
= data
;
5054 unsigned long pck_max
;
5056 ctx
->dsi_cinfo
.regm_dispc
= regm_dispc
;
5057 ctx
->dsi_cinfo
.dsi_pll_hsdiv_dispc_clk
= dispc
;
5060 * In burst mode we can let the dispc pck be arbitrarily high, but it
5061 * limits our scaling abilities. So for now, don't aim too high.
5064 if (ctx
->config
->trans_mode
== OMAP_DSS_DSI_BURST_MODE
)
5065 pck_max
= ctx
->req_pck_max
+ 10000000;
5067 pck_max
= ctx
->req_pck_max
;
5069 return dispc_div_calc(dispc
, ctx
->req_pck_min
, pck_max
,
5070 dsi_vm_calc_dispc_cb
, ctx
);
5073 static bool dsi_vm_calc_pll_cb(int regn
, int regm
, unsigned long fint
,
5074 unsigned long pll
, void *data
)
5076 struct dsi_clk_calc_ctx
*ctx
= data
;
5078 ctx
->dsi_cinfo
.regn
= regn
;
5079 ctx
->dsi_cinfo
.regm
= regm
;
5080 ctx
->dsi_cinfo
.fint
= fint
;
5081 ctx
->dsi_cinfo
.clkin4ddr
= pll
;
5083 return dsi_hsdiv_calc(ctx
->dsidev
, pll
, ctx
->req_pck_min
,
5084 dsi_vm_calc_hsdiv_cb
, ctx
);
5087 static bool dsi_vm_calc(struct dsi_data
*dsi
,
5088 const struct omap_dss_dsi_config
*cfg
,
5089 struct dsi_clk_calc_ctx
*ctx
)
5091 const struct omap_video_timings
*t
= cfg
->timings
;
5092 unsigned long clkin
;
5093 unsigned long pll_min
;
5094 unsigned long pll_max
;
5095 int ndl
= dsi
->num_lanes_used
- 1;
5096 int bitspp
= dsi_get_pixel_size(cfg
->pixel_format
);
5097 unsigned long byteclk_min
;
5099 clkin
= clk_get_rate(dsi
->sys_clk
);
5101 memset(ctx
, 0, sizeof(*ctx
));
5102 ctx
->dsidev
= dsi
->pdev
;
5105 ctx
->dsi_cinfo
.clkin
= clkin
;
5107 /* these limits should come from the panel driver */
5108 ctx
->req_pck_min
= t
->pixel_clock
* 1000 - 1000;
5109 ctx
->req_pck_nom
= t
->pixel_clock
* 1000;
5110 ctx
->req_pck_max
= t
->pixel_clock
* 1000 + 1000;
5112 byteclk_min
= div64_u64((u64
)ctx
->req_pck_min
* bitspp
, ndl
* 8);
5113 pll_min
= max(cfg
->hs_clk_min
* 4, byteclk_min
* 4 * 4);
5115 if (cfg
->trans_mode
== OMAP_DSS_DSI_BURST_MODE
) {
5116 pll_max
= cfg
->hs_clk_max
* 4;
5118 unsigned long byteclk_max
;
5119 byteclk_max
= div64_u64((u64
)ctx
->req_pck_max
* bitspp
,
5122 pll_max
= byteclk_max
* 4 * 4;
5125 return dsi_pll_calc(dsi
->pdev
, clkin
,
5127 dsi_vm_calc_pll_cb
, ctx
);
5130 int omapdss_dsi_set_config(struct omap_dss_device
*dssdev
,
5131 const struct omap_dss_dsi_config
*config
)
5133 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5134 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5135 struct dsi_clk_calc_ctx ctx
;
5139 mutex_lock(&dsi
->lock
);
5141 dsi
->pix_fmt
= config
->pixel_format
;
5142 dsi
->mode
= config
->mode
;
5144 if (config
->mode
== OMAP_DSS_DSI_VIDEO_MODE
)
5145 ok
= dsi_vm_calc(dsi
, config
, &ctx
);
5147 ok
= dsi_cm_calc(dsi
, config
, &ctx
);
5150 DSSERR("failed to find suitable DSI clock settings\n");
5155 dsi_pll_calc_dsi_fck(&ctx
.dsi_cinfo
);
5157 r
= dsi_lp_clock_calc(&ctx
.dsi_cinfo
, config
->lp_clk_min
,
5158 config
->lp_clk_max
);
5160 DSSERR("failed to find suitable DSI LP clock settings\n");
5164 dsi
->user_dsi_cinfo
= ctx
.dsi_cinfo
;
5165 dsi
->user_dispc_cinfo
= ctx
.dispc_cinfo
;
5167 dsi
->timings
= ctx
.dispc_vm
;
5168 dsi
->vm_timings
= ctx
.dsi_vm
;
5170 mutex_unlock(&dsi
->lock
);
5174 mutex_unlock(&dsi
->lock
);
5178 EXPORT_SYMBOL(omapdss_dsi_set_config
);
5181 * Return a hardcoded channel for the DSI output. This should work for
5182 * current use cases, but this can be later expanded to either resolve
5183 * the channel in some more dynamic manner, or get the channel as a user
5186 static enum omap_channel
dsi_get_channel(int module_id
)
5188 switch (omapdss_get_version()) {
5189 case OMAPDSS_VER_OMAP24xx
:
5190 DSSWARN("DSI not supported\n");
5191 return OMAP_DSS_CHANNEL_LCD
;
5193 case OMAPDSS_VER_OMAP34xx_ES1
:
5194 case OMAPDSS_VER_OMAP34xx_ES3
:
5195 case OMAPDSS_VER_OMAP3630
:
5196 case OMAPDSS_VER_AM35xx
:
5197 return OMAP_DSS_CHANNEL_LCD
;
5199 case OMAPDSS_VER_OMAP4430_ES1
:
5200 case OMAPDSS_VER_OMAP4430_ES2
:
5201 case OMAPDSS_VER_OMAP4
:
5202 switch (module_id
) {
5204 return OMAP_DSS_CHANNEL_LCD
;
5206 return OMAP_DSS_CHANNEL_LCD2
;
5208 DSSWARN("unsupported module id\n");
5209 return OMAP_DSS_CHANNEL_LCD
;
5212 case OMAPDSS_VER_OMAP5
:
5213 switch (module_id
) {
5215 return OMAP_DSS_CHANNEL_LCD
;
5217 return OMAP_DSS_CHANNEL_LCD3
;
5219 DSSWARN("unsupported module id\n");
5220 return OMAP_DSS_CHANNEL_LCD
;
5224 DSSWARN("unsupported DSS version\n");
5225 return OMAP_DSS_CHANNEL_LCD
;
5229 int omap_dsi_request_vc(struct omap_dss_device
*dssdev
, int *channel
)
5231 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5232 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5235 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
5236 if (!dsi
->vc
[i
].dssdev
) {
5237 dsi
->vc
[i
].dssdev
= dssdev
;
5243 DSSERR("cannot get VC for display %s", dssdev
->name
);
5246 EXPORT_SYMBOL(omap_dsi_request_vc
);
5248 int omap_dsi_set_vc_id(struct omap_dss_device
*dssdev
, int channel
, int vc_id
)
5250 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5251 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5253 if (vc_id
< 0 || vc_id
> 3) {
5254 DSSERR("VC ID out of range\n");
5258 if (channel
< 0 || channel
> 3) {
5259 DSSERR("Virtual Channel out of range\n");
5263 if (dsi
->vc
[channel
].dssdev
!= dssdev
) {
5264 DSSERR("Virtual Channel not allocated to display %s\n",
5269 dsi
->vc
[channel
].vc_id
= vc_id
;
5273 EXPORT_SYMBOL(omap_dsi_set_vc_id
);
5275 void omap_dsi_release_vc(struct omap_dss_device
*dssdev
, int channel
)
5277 struct platform_device
*dsidev
= dsi_get_dsidev_from_dssdev(dssdev
);
5278 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5280 if ((channel
>= 0 && channel
<= 3) &&
5281 dsi
->vc
[channel
].dssdev
== dssdev
) {
5282 dsi
->vc
[channel
].dssdev
= NULL
;
5283 dsi
->vc
[channel
].vc_id
= 0;
5286 EXPORT_SYMBOL(omap_dsi_release_vc
);
5288 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device
*dsidev
)
5290 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 7, 1) != 1)
5291 DSSERR("%s (%s) not active\n",
5292 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
),
5293 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
));
5296 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device
*dsidev
)
5298 if (wait_for_bit_change(dsidev
, DSI_PLL_STATUS
, 8, 1) != 1)
5299 DSSERR("%s (%s) not active\n",
5300 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
),
5301 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
));
5304 static void dsi_calc_clock_param_ranges(struct platform_device
*dsidev
)
5306 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5308 dsi
->regn_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN
);
5309 dsi
->regm_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM
);
5310 dsi
->regm_dispc_max
=
5311 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC
);
5312 dsi
->regm_dsi_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI
);
5313 dsi
->fint_min
= dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT
);
5314 dsi
->fint_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT
);
5315 dsi
->lpdiv_max
= dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV
);
5318 static int dsi_get_clocks(struct platform_device
*dsidev
)
5320 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5323 clk
= devm_clk_get(&dsidev
->dev
, "fck");
5325 DSSERR("can't get fck\n");
5326 return PTR_ERR(clk
);
5331 clk
= devm_clk_get(&dsidev
->dev
, "sys_clk");
5333 DSSERR("can't get sys_clk\n");
5334 return PTR_ERR(clk
);
5342 static struct omap_dss_device
*dsi_find_dssdev(struct platform_device
*pdev
)
5344 struct omap_dss_board_info
*pdata
= pdev
->dev
.platform_data
;
5345 struct dsi_data
*dsi
= dsi_get_dsidrv_data(pdev
);
5346 const char *def_disp_name
= omapdss_get_default_display_name();
5347 struct omap_dss_device
*def_dssdev
;
5352 for (i
= 0; i
< pdata
->num_devices
; ++i
) {
5353 struct omap_dss_device
*dssdev
= pdata
->devices
[i
];
5355 if (dssdev
->type
!= OMAP_DISPLAY_TYPE_DSI
)
5358 if (dssdev
->phy
.dsi
.module
!= dsi
->module_id
)
5361 if (def_dssdev
== NULL
)
5362 def_dssdev
= dssdev
;
5364 if (def_disp_name
!= NULL
&&
5365 strcmp(dssdev
->name
, def_disp_name
) == 0) {
5366 def_dssdev
= dssdev
;
5374 static int dsi_probe_pdata(struct platform_device
*dsidev
)
5376 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5377 struct omap_dss_device
*plat_dssdev
;
5378 struct omap_dss_device
*dssdev
;
5381 plat_dssdev
= dsi_find_dssdev(dsidev
);
5386 r
= dsi_regulator_init(dsidev
);
5390 dssdev
= dss_alloc_and_init_device(&dsidev
->dev
);
5394 dss_copy_device_pdata(dssdev
, plat_dssdev
);
5396 r
= omapdss_output_set_device(&dsi
->output
, dssdev
);
5398 DSSERR("failed to connect output to new device: %s\n",
5400 dss_put_device(dssdev
);
5404 r
= dss_add_device(dssdev
);
5406 DSSERR("device %s register failed: %d\n", dssdev
->name
, r
);
5407 omapdss_output_unset_device(&dsi
->output
);
5408 dss_put_device(dssdev
);
5415 static void dsi_init_output(struct platform_device
*dsidev
)
5417 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5418 struct omap_dss_output
*out
= &dsi
->output
;
5421 out
->id
= dsi
->module_id
== 0 ?
5422 OMAP_DSS_OUTPUT_DSI1
: OMAP_DSS_OUTPUT_DSI2
;
5424 out
->type
= OMAP_DISPLAY_TYPE_DSI
;
5425 out
->name
= dsi
->module_id
== 0 ? "dsi.0" : "dsi.1";
5426 out
->dispc_channel
= dsi_get_channel(dsi
->module_id
);
5428 dss_register_output(out
);
5431 static void dsi_uninit_output(struct platform_device
*dsidev
)
5433 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5434 struct omap_dss_output
*out
= &dsi
->output
;
5436 dss_unregister_output(out
);
5439 /* DSI1 HW IP initialisation */
5440 static int omap_dsihw_probe(struct platform_device
*dsidev
)
5444 struct resource
*dsi_mem
;
5445 struct dsi_data
*dsi
;
5447 dsi
= devm_kzalloc(&dsidev
->dev
, sizeof(*dsi
), GFP_KERNEL
);
5451 dsi
->module_id
= dsidev
->id
;
5453 dev_set_drvdata(&dsidev
->dev
, dsi
);
5455 spin_lock_init(&dsi
->irq_lock
);
5456 spin_lock_init(&dsi
->errors_lock
);
5459 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5460 spin_lock_init(&dsi
->irq_stats_lock
);
5461 dsi
->irq_stats
.last_reset
= jiffies
;
5464 mutex_init(&dsi
->lock
);
5465 sema_init(&dsi
->bus_lock
, 1);
5467 INIT_DEFERRABLE_WORK(&dsi
->framedone_timeout_work
,
5468 dsi_framedone_timeout_work_callback
);
5470 #ifdef DSI_CATCH_MISSING_TE
5471 init_timer(&dsi
->te_timer
);
5472 dsi
->te_timer
.function
= dsi_te_timeout
;
5473 dsi
->te_timer
.data
= 0;
5475 dsi_mem
= platform_get_resource(dsi
->pdev
, IORESOURCE_MEM
, 0);
5477 DSSERR("can't get IORESOURCE_MEM DSI\n");
5481 dsi
->base
= devm_ioremap(&dsidev
->dev
, dsi_mem
->start
,
5482 resource_size(dsi_mem
));
5484 DSSERR("can't ioremap DSI\n");
5488 dsi
->irq
= platform_get_irq(dsi
->pdev
, 0);
5490 DSSERR("platform_get_irq failed\n");
5494 r
= devm_request_irq(&dsidev
->dev
, dsi
->irq
, omap_dsi_irq_handler
,
5495 IRQF_SHARED
, dev_name(&dsidev
->dev
), dsi
->pdev
);
5497 DSSERR("request_irq failed\n");
5501 /* DSI VCs initialization */
5502 for (i
= 0; i
< ARRAY_SIZE(dsi
->vc
); i
++) {
5503 dsi
->vc
[i
].source
= DSI_VC_SOURCE_L4
;
5504 dsi
->vc
[i
].dssdev
= NULL
;
5505 dsi
->vc
[i
].vc_id
= 0;
5508 dsi_calc_clock_param_ranges(dsidev
);
5510 r
= dsi_get_clocks(dsidev
);
5514 pm_runtime_enable(&dsidev
->dev
);
5516 r
= dsi_runtime_get(dsidev
);
5518 goto err_runtime_get
;
5520 rev
= dsi_read_reg(dsidev
, DSI_REVISION
);
5521 dev_dbg(&dsidev
->dev
, "OMAP DSI rev %d.%d\n",
5522 FLD_GET(rev
, 7, 4), FLD_GET(rev
, 3, 0));
5524 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5525 * of data to 3 by default */
5526 if (dss_has_feature(FEAT_DSI_GNQ
))
5528 dsi
->num_lanes_supported
= 1 + REG_GET(dsidev
, DSI_GNQ
, 11, 9);
5530 dsi
->num_lanes_supported
= 3;
5532 dsi
->line_buffer_size
= dsi_get_line_buf_size(dsidev
);
5534 dsi_init_output(dsidev
);
5536 if (dsidev
->dev
.platform_data
) {
5537 r
= dsi_probe_pdata(dsidev
);
5542 dsi_runtime_put(dsidev
);
5544 if (dsi
->module_id
== 0)
5545 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs
);
5546 else if (dsi
->module_id
== 1)
5547 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs
);
5549 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5550 if (dsi
->module_id
== 0)
5551 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs
);
5552 else if (dsi
->module_id
== 1)
5553 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs
);
5558 dsi_runtime_put(dsidev
);
5559 dsi_uninit_output(dsidev
);
5561 pm_runtime_disable(&dsidev
->dev
);
5565 static int __exit
omap_dsihw_remove(struct platform_device
*dsidev
)
5567 struct dsi_data
*dsi
= dsi_get_dsidrv_data(dsidev
);
5569 WARN_ON(dsi
->scp_clk_refcount
> 0);
5571 dss_unregister_child_devices(&dsidev
->dev
);
5573 dsi_uninit_output(dsidev
);
5575 pm_runtime_disable(&dsidev
->dev
);
5577 if (dsi
->vdds_dsi_reg
!= NULL
&& dsi
->vdds_dsi_enabled
) {
5578 regulator_disable(dsi
->vdds_dsi_reg
);
5579 dsi
->vdds_dsi_enabled
= false;
5585 static int dsi_runtime_suspend(struct device
*dev
)
5587 dispc_runtime_put();
5592 static int dsi_runtime_resume(struct device
*dev
)
5596 r
= dispc_runtime_get();
5603 static const struct dev_pm_ops dsi_pm_ops
= {
5604 .runtime_suspend
= dsi_runtime_suspend
,
5605 .runtime_resume
= dsi_runtime_resume
,
5608 static struct platform_driver omap_dsihw_driver
= {
5609 .probe
= omap_dsihw_probe
,
5610 .remove
= __exit_p(omap_dsihw_remove
),
5612 .name
= "omapdss_dsi",
5613 .owner
= THIS_MODULE
,
5618 int __init
dsi_init_platform_driver(void)
5620 return platform_driver_register(&omap_dsihw_driver
);
5623 void __exit
dsi_uninit_platform_driver(void)
5625 platform_driver_unregister(&omap_dsihw_driver
);