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OMAPDSS: don't print errors on -EPROBE_DEFER
[deliverable/linux.git] / drivers / video / omap2 / dss / dsi.c
1 /*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #define DSS_SUBSYS_NAME "DSI"
21
22 #include <linux/kernel.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
41
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44
45 #include "dss.h"
46 #include "dss_features.h"
47
48 #define DSI_CATCH_MISSING_TE
49
50 struct dsi_reg { u16 module; u16 idx; };
51
52 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
53
54 /* DSI Protocol Engine */
55
56 #define DSI_PROTO 0
57 #define DSI_PROTO_SZ 0x200
58
59 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
60 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
61 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
62 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
63 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
64 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
65 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
69 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
70 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
71 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
75 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
93
94 /* DSIPHY_SCP */
95
96 #define DSI_PHY 1
97 #define DSI_PHY_OFFSET 0x200
98 #define DSI_PHY_SZ 0x40
99
100 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
101 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
102 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
103 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
104 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
105
106 /* DSI_PLL_CTRL_SCP */
107
108 #define DSI_PLL 2
109 #define DSI_PLL_OFFSET 0x300
110 #define DSI_PLL_SZ 0x20
111
112 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
113 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
114 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
115 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
116 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
117
118 #define REG_GET(dsidev, idx, start, end) \
119 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
120
121 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
122 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
123
124 /* Global interrupts */
125 #define DSI_IRQ_VC0 (1 << 0)
126 #define DSI_IRQ_VC1 (1 << 1)
127 #define DSI_IRQ_VC2 (1 << 2)
128 #define DSI_IRQ_VC3 (1 << 3)
129 #define DSI_IRQ_WAKEUP (1 << 4)
130 #define DSI_IRQ_RESYNC (1 << 5)
131 #define DSI_IRQ_PLL_LOCK (1 << 7)
132 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
133 #define DSI_IRQ_PLL_RECALL (1 << 9)
134 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
135 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
136 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
137 #define DSI_IRQ_TE_TRIGGER (1 << 16)
138 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
139 #define DSI_IRQ_SYNC_LOST (1 << 18)
140 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
141 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
142 #define DSI_IRQ_ERROR_MASK \
143 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
144 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
145 #define DSI_IRQ_CHANNEL_MASK 0xf
146
147 /* Virtual channel interrupts */
148 #define DSI_VC_IRQ_CS (1 << 0)
149 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
150 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
151 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
152 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
153 #define DSI_VC_IRQ_BTA (1 << 5)
154 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
155 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
156 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
157 #define DSI_VC_IRQ_ERROR_MASK \
158 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
159 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
160 DSI_VC_IRQ_FIFO_TX_UDF)
161
162 /* ComplexIO interrupts */
163 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
164 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
165 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
166 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
167 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
168 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
169 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
170 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
171 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
172 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
173 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
174 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
175 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
176 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
177 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
178 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
179 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
180 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
181 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
182 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
193 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
194 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
195 #define DSI_CIO_IRQ_ERROR_MASK \
196 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
197 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
198 DSI_CIO_IRQ_ERRSYNCESC5 | \
199 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
200 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
201 DSI_CIO_IRQ_ERRESC5 | \
202 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
203 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
204 DSI_CIO_IRQ_ERRCONTROL5 | \
205 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
206 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
207 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
208 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
210
211 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
212
213 static int dsi_display_init_dispc(struct platform_device *dsidev,
214 struct omap_overlay_manager *mgr);
215 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
216 struct omap_overlay_manager *mgr);
217
218 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
219
220 #define DSI_MAX_NR_ISRS 2
221 #define DSI_MAX_NR_LANES 5
222
223 enum dsi_lane_function {
224 DSI_LANE_UNUSED = 0,
225 DSI_LANE_CLK,
226 DSI_LANE_DATA1,
227 DSI_LANE_DATA2,
228 DSI_LANE_DATA3,
229 DSI_LANE_DATA4,
230 };
231
232 struct dsi_lane_config {
233 enum dsi_lane_function function;
234 u8 polarity;
235 };
236
237 struct dsi_isr_data {
238 omap_dsi_isr_t isr;
239 void *arg;
240 u32 mask;
241 };
242
243 enum fifo_size {
244 DSI_FIFO_SIZE_0 = 0,
245 DSI_FIFO_SIZE_32 = 1,
246 DSI_FIFO_SIZE_64 = 2,
247 DSI_FIFO_SIZE_96 = 3,
248 DSI_FIFO_SIZE_128 = 4,
249 };
250
251 enum dsi_vc_source {
252 DSI_VC_SOURCE_L4 = 0,
253 DSI_VC_SOURCE_VP,
254 };
255
256 struct dsi_irq_stats {
257 unsigned long last_reset;
258 unsigned irq_count;
259 unsigned dsi_irqs[32];
260 unsigned vc_irqs[4][32];
261 unsigned cio_irqs[32];
262 };
263
264 struct dsi_isr_tables {
265 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
266 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
267 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
268 };
269
270 struct dsi_clk_calc_ctx {
271 struct platform_device *dsidev;
272
273 /* inputs */
274
275 const struct omap_dss_dsi_config *config;
276
277 unsigned long req_pck_min, req_pck_nom, req_pck_max;
278
279 /* outputs */
280
281 struct dsi_clock_info dsi_cinfo;
282 struct dispc_clock_info dispc_cinfo;
283
284 struct omap_video_timings dispc_vm;
285 struct omap_dss_dsi_videomode_timings dsi_vm;
286 };
287
288 struct dsi_data {
289 struct platform_device *pdev;
290 void __iomem *proto_base;
291 void __iomem *phy_base;
292 void __iomem *pll_base;
293
294 int module_id;
295
296 int irq;
297
298 struct clk *dss_clk;
299 struct clk *sys_clk;
300
301 struct dispc_clock_info user_dispc_cinfo;
302 struct dsi_clock_info user_dsi_cinfo;
303
304 struct dsi_clock_info current_cinfo;
305
306 bool vdds_dsi_enabled;
307 struct regulator *vdds_dsi_reg;
308
309 struct {
310 enum dsi_vc_source source;
311 struct omap_dss_device *dssdev;
312 enum fifo_size tx_fifo_size;
313 enum fifo_size rx_fifo_size;
314 int vc_id;
315 } vc[4];
316
317 struct mutex lock;
318 struct semaphore bus_lock;
319
320 unsigned pll_locked;
321
322 spinlock_t irq_lock;
323 struct dsi_isr_tables isr_tables;
324 /* space for a copy used by the interrupt handler */
325 struct dsi_isr_tables isr_tables_copy;
326
327 int update_channel;
328 #ifdef DSI_PERF_MEASURE
329 unsigned update_bytes;
330 #endif
331
332 bool te_enabled;
333 bool ulps_enabled;
334
335 void (*framedone_callback)(int, void *);
336 void *framedone_data;
337
338 struct delayed_work framedone_timeout_work;
339
340 #ifdef DSI_CATCH_MISSING_TE
341 struct timer_list te_timer;
342 #endif
343
344 unsigned long cache_req_pck;
345 unsigned long cache_clk_freq;
346 struct dsi_clock_info cache_cinfo;
347
348 u32 errors;
349 spinlock_t errors_lock;
350 #ifdef DSI_PERF_MEASURE
351 ktime_t perf_setup_time;
352 ktime_t perf_start_time;
353 #endif
354 int debug_read;
355 int debug_write;
356
357 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
358 spinlock_t irq_stats_lock;
359 struct dsi_irq_stats irq_stats;
360 #endif
361 /* DSI PLL Parameter Ranges */
362 unsigned long regm_max, regn_max;
363 unsigned long regm_dispc_max, regm_dsi_max;
364 unsigned long fint_min, fint_max;
365 unsigned long lpdiv_max;
366
367 unsigned num_lanes_supported;
368 unsigned line_buffer_size;
369
370 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
371 unsigned num_lanes_used;
372
373 unsigned scp_clk_refcount;
374
375 struct dss_lcd_mgr_config mgr_config;
376 struct omap_video_timings timings;
377 enum omap_dss_dsi_pixel_format pix_fmt;
378 enum omap_dss_dsi_mode mode;
379 struct omap_dss_dsi_videomode_timings vm_timings;
380
381 struct omap_dss_device output;
382 };
383
384 struct dsi_packet_sent_handler_data {
385 struct platform_device *dsidev;
386 struct completion *completion;
387 };
388
389 #ifdef DSI_PERF_MEASURE
390 static bool dsi_perf;
391 module_param(dsi_perf, bool, 0644);
392 #endif
393
394 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
395 {
396 return dev_get_drvdata(&dsidev->dev);
397 }
398
399 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
400 {
401 return to_platform_device(dssdev->dev);
402 }
403
404 struct platform_device *dsi_get_dsidev_from_id(int module)
405 {
406 struct omap_dss_device *out;
407 enum omap_dss_output_id id;
408
409 switch (module) {
410 case 0:
411 id = OMAP_DSS_OUTPUT_DSI1;
412 break;
413 case 1:
414 id = OMAP_DSS_OUTPUT_DSI2;
415 break;
416 default:
417 return NULL;
418 }
419
420 out = omap_dss_get_output(id);
421
422 return out ? to_platform_device(out->dev) : NULL;
423 }
424
425 static inline void dsi_write_reg(struct platform_device *dsidev,
426 const struct dsi_reg idx, u32 val)
427 {
428 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
429 void __iomem *base;
430
431 switch(idx.module) {
432 case DSI_PROTO: base = dsi->proto_base; break;
433 case DSI_PHY: base = dsi->phy_base; break;
434 case DSI_PLL: base = dsi->pll_base; break;
435 default: return;
436 }
437
438 __raw_writel(val, base + idx.idx);
439 }
440
441 static inline u32 dsi_read_reg(struct platform_device *dsidev,
442 const struct dsi_reg idx)
443 {
444 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
445 void __iomem *base;
446
447 switch(idx.module) {
448 case DSI_PROTO: base = dsi->proto_base; break;
449 case DSI_PHY: base = dsi->phy_base; break;
450 case DSI_PLL: base = dsi->pll_base; break;
451 default: return 0;
452 }
453
454 return __raw_readl(base + idx.idx);
455 }
456
457 static void dsi_bus_lock(struct omap_dss_device *dssdev)
458 {
459 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
460 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
461
462 down(&dsi->bus_lock);
463 }
464
465 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
466 {
467 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
468 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
469
470 up(&dsi->bus_lock);
471 }
472
473 static bool dsi_bus_is_locked(struct platform_device *dsidev)
474 {
475 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
476
477 return dsi->bus_lock.count == 0;
478 }
479
480 static void dsi_completion_handler(void *data, u32 mask)
481 {
482 complete((struct completion *)data);
483 }
484
485 static inline int wait_for_bit_change(struct platform_device *dsidev,
486 const struct dsi_reg idx, int bitnum, int value)
487 {
488 unsigned long timeout;
489 ktime_t wait;
490 int t;
491
492 /* first busyloop to see if the bit changes right away */
493 t = 100;
494 while (t-- > 0) {
495 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
496 return value;
497 }
498
499 /* then loop for 500ms, sleeping for 1ms in between */
500 timeout = jiffies + msecs_to_jiffies(500);
501 while (time_before(jiffies, timeout)) {
502 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
503 return value;
504
505 wait = ns_to_ktime(1000 * 1000);
506 set_current_state(TASK_UNINTERRUPTIBLE);
507 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
508 }
509
510 return !value;
511 }
512
513 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
514 {
515 switch (fmt) {
516 case OMAP_DSS_DSI_FMT_RGB888:
517 case OMAP_DSS_DSI_FMT_RGB666:
518 return 24;
519 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
520 return 18;
521 case OMAP_DSS_DSI_FMT_RGB565:
522 return 16;
523 default:
524 BUG();
525 return 0;
526 }
527 }
528
529 #ifdef DSI_PERF_MEASURE
530 static void dsi_perf_mark_setup(struct platform_device *dsidev)
531 {
532 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
533 dsi->perf_setup_time = ktime_get();
534 }
535
536 static void dsi_perf_mark_start(struct platform_device *dsidev)
537 {
538 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
539 dsi->perf_start_time = ktime_get();
540 }
541
542 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
543 {
544 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
545 ktime_t t, setup_time, trans_time;
546 u32 total_bytes;
547 u32 setup_us, trans_us, total_us;
548
549 if (!dsi_perf)
550 return;
551
552 t = ktime_get();
553
554 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
555 setup_us = (u32)ktime_to_us(setup_time);
556 if (setup_us == 0)
557 setup_us = 1;
558
559 trans_time = ktime_sub(t, dsi->perf_start_time);
560 trans_us = (u32)ktime_to_us(trans_time);
561 if (trans_us == 0)
562 trans_us = 1;
563
564 total_us = setup_us + trans_us;
565
566 total_bytes = dsi->update_bytes;
567
568 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
569 "%u bytes, %u kbytes/sec\n",
570 name,
571 setup_us,
572 trans_us,
573 total_us,
574 1000*1000 / total_us,
575 total_bytes,
576 total_bytes * 1000 / total_us);
577 }
578 #else
579 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
580 {
581 }
582
583 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
584 {
585 }
586
587 static inline void dsi_perf_show(struct platform_device *dsidev,
588 const char *name)
589 {
590 }
591 #endif
592
593 static int verbose_irq;
594
595 static void print_irq_status(u32 status)
596 {
597 if (status == 0)
598 return;
599
600 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
601 return;
602
603 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
604
605 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
606 status,
607 verbose_irq ? PIS(VC0) : "",
608 verbose_irq ? PIS(VC1) : "",
609 verbose_irq ? PIS(VC2) : "",
610 verbose_irq ? PIS(VC3) : "",
611 PIS(WAKEUP),
612 PIS(RESYNC),
613 PIS(PLL_LOCK),
614 PIS(PLL_UNLOCK),
615 PIS(PLL_RECALL),
616 PIS(COMPLEXIO_ERR),
617 PIS(HS_TX_TIMEOUT),
618 PIS(LP_RX_TIMEOUT),
619 PIS(TE_TRIGGER),
620 PIS(ACK_TRIGGER),
621 PIS(SYNC_LOST),
622 PIS(LDO_POWER_GOOD),
623 PIS(TA_TIMEOUT));
624 #undef PIS
625 }
626
627 static void print_irq_status_vc(int channel, u32 status)
628 {
629 if (status == 0)
630 return;
631
632 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
633 return;
634
635 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
636
637 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
638 channel,
639 status,
640 PIS(CS),
641 PIS(ECC_CORR),
642 PIS(ECC_NO_CORR),
643 verbose_irq ? PIS(PACKET_SENT) : "",
644 PIS(BTA),
645 PIS(FIFO_TX_OVF),
646 PIS(FIFO_RX_OVF),
647 PIS(FIFO_TX_UDF),
648 PIS(PP_BUSY_CHANGE));
649 #undef PIS
650 }
651
652 static void print_irq_status_cio(u32 status)
653 {
654 if (status == 0)
655 return;
656
657 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
658
659 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
660 status,
661 PIS(ERRSYNCESC1),
662 PIS(ERRSYNCESC2),
663 PIS(ERRSYNCESC3),
664 PIS(ERRESC1),
665 PIS(ERRESC2),
666 PIS(ERRESC3),
667 PIS(ERRCONTROL1),
668 PIS(ERRCONTROL2),
669 PIS(ERRCONTROL3),
670 PIS(STATEULPS1),
671 PIS(STATEULPS2),
672 PIS(STATEULPS3),
673 PIS(ERRCONTENTIONLP0_1),
674 PIS(ERRCONTENTIONLP1_1),
675 PIS(ERRCONTENTIONLP0_2),
676 PIS(ERRCONTENTIONLP1_2),
677 PIS(ERRCONTENTIONLP0_3),
678 PIS(ERRCONTENTIONLP1_3),
679 PIS(ULPSACTIVENOT_ALL0),
680 PIS(ULPSACTIVENOT_ALL1));
681 #undef PIS
682 }
683
684 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
685 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
686 u32 *vcstatus, u32 ciostatus)
687 {
688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
689 int i;
690
691 spin_lock(&dsi->irq_stats_lock);
692
693 dsi->irq_stats.irq_count++;
694 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
695
696 for (i = 0; i < 4; ++i)
697 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
698
699 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
700
701 spin_unlock(&dsi->irq_stats_lock);
702 }
703 #else
704 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
705 #endif
706
707 static int debug_irq;
708
709 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
710 u32 *vcstatus, u32 ciostatus)
711 {
712 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
713 int i;
714
715 if (irqstatus & DSI_IRQ_ERROR_MASK) {
716 DSSERR("DSI error, irqstatus %x\n", irqstatus);
717 print_irq_status(irqstatus);
718 spin_lock(&dsi->errors_lock);
719 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
720 spin_unlock(&dsi->errors_lock);
721 } else if (debug_irq) {
722 print_irq_status(irqstatus);
723 }
724
725 for (i = 0; i < 4; ++i) {
726 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
727 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
728 i, vcstatus[i]);
729 print_irq_status_vc(i, vcstatus[i]);
730 } else if (debug_irq) {
731 print_irq_status_vc(i, vcstatus[i]);
732 }
733 }
734
735 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
736 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
737 print_irq_status_cio(ciostatus);
738 } else if (debug_irq) {
739 print_irq_status_cio(ciostatus);
740 }
741 }
742
743 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
744 unsigned isr_array_size, u32 irqstatus)
745 {
746 struct dsi_isr_data *isr_data;
747 int i;
748
749 for (i = 0; i < isr_array_size; i++) {
750 isr_data = &isr_array[i];
751 if (isr_data->isr && isr_data->mask & irqstatus)
752 isr_data->isr(isr_data->arg, irqstatus);
753 }
754 }
755
756 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
757 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
758 {
759 int i;
760
761 dsi_call_isrs(isr_tables->isr_table,
762 ARRAY_SIZE(isr_tables->isr_table),
763 irqstatus);
764
765 for (i = 0; i < 4; ++i) {
766 if (vcstatus[i] == 0)
767 continue;
768 dsi_call_isrs(isr_tables->isr_table_vc[i],
769 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
770 vcstatus[i]);
771 }
772
773 if (ciostatus != 0)
774 dsi_call_isrs(isr_tables->isr_table_cio,
775 ARRAY_SIZE(isr_tables->isr_table_cio),
776 ciostatus);
777 }
778
779 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
780 {
781 struct platform_device *dsidev;
782 struct dsi_data *dsi;
783 u32 irqstatus, vcstatus[4], ciostatus;
784 int i;
785
786 dsidev = (struct platform_device *) arg;
787 dsi = dsi_get_dsidrv_data(dsidev);
788
789 spin_lock(&dsi->irq_lock);
790
791 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
792
793 /* IRQ is not for us */
794 if (!irqstatus) {
795 spin_unlock(&dsi->irq_lock);
796 return IRQ_NONE;
797 }
798
799 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
800 /* flush posted write */
801 dsi_read_reg(dsidev, DSI_IRQSTATUS);
802
803 for (i = 0; i < 4; ++i) {
804 if ((irqstatus & (1 << i)) == 0) {
805 vcstatus[i] = 0;
806 continue;
807 }
808
809 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
810
811 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
812 /* flush posted write */
813 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
814 }
815
816 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
817 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
818
819 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
820 /* flush posted write */
821 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
822 } else {
823 ciostatus = 0;
824 }
825
826 #ifdef DSI_CATCH_MISSING_TE
827 if (irqstatus & DSI_IRQ_TE_TRIGGER)
828 del_timer(&dsi->te_timer);
829 #endif
830
831 /* make a copy and unlock, so that isrs can unregister
832 * themselves */
833 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
834 sizeof(dsi->isr_tables));
835
836 spin_unlock(&dsi->irq_lock);
837
838 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
839
840 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
841
842 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
843
844 return IRQ_HANDLED;
845 }
846
847 /* dsi->irq_lock has to be locked by the caller */
848 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
849 struct dsi_isr_data *isr_array,
850 unsigned isr_array_size, u32 default_mask,
851 const struct dsi_reg enable_reg,
852 const struct dsi_reg status_reg)
853 {
854 struct dsi_isr_data *isr_data;
855 u32 mask;
856 u32 old_mask;
857 int i;
858
859 mask = default_mask;
860
861 for (i = 0; i < isr_array_size; i++) {
862 isr_data = &isr_array[i];
863
864 if (isr_data->isr == NULL)
865 continue;
866
867 mask |= isr_data->mask;
868 }
869
870 old_mask = dsi_read_reg(dsidev, enable_reg);
871 /* clear the irqstatus for newly enabled irqs */
872 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
873 dsi_write_reg(dsidev, enable_reg, mask);
874
875 /* flush posted writes */
876 dsi_read_reg(dsidev, enable_reg);
877 dsi_read_reg(dsidev, status_reg);
878 }
879
880 /* dsi->irq_lock has to be locked by the caller */
881 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
882 {
883 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
884 u32 mask = DSI_IRQ_ERROR_MASK;
885 #ifdef DSI_CATCH_MISSING_TE
886 mask |= DSI_IRQ_TE_TRIGGER;
887 #endif
888 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
889 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
890 DSI_IRQENABLE, DSI_IRQSTATUS);
891 }
892
893 /* dsi->irq_lock has to be locked by the caller */
894 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
895 {
896 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
897
898 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
899 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
900 DSI_VC_IRQ_ERROR_MASK,
901 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
902 }
903
904 /* dsi->irq_lock has to be locked by the caller */
905 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
906 {
907 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
908
909 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
910 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
911 DSI_CIO_IRQ_ERROR_MASK,
912 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
913 }
914
915 static void _dsi_initialize_irq(struct platform_device *dsidev)
916 {
917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
918 unsigned long flags;
919 int vc;
920
921 spin_lock_irqsave(&dsi->irq_lock, flags);
922
923 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
924
925 _omap_dsi_set_irqs(dsidev);
926 for (vc = 0; vc < 4; ++vc)
927 _omap_dsi_set_irqs_vc(dsidev, vc);
928 _omap_dsi_set_irqs_cio(dsidev);
929
930 spin_unlock_irqrestore(&dsi->irq_lock, flags);
931 }
932
933 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
934 struct dsi_isr_data *isr_array, unsigned isr_array_size)
935 {
936 struct dsi_isr_data *isr_data;
937 int free_idx;
938 int i;
939
940 BUG_ON(isr == NULL);
941
942 /* check for duplicate entry and find a free slot */
943 free_idx = -1;
944 for (i = 0; i < isr_array_size; i++) {
945 isr_data = &isr_array[i];
946
947 if (isr_data->isr == isr && isr_data->arg == arg &&
948 isr_data->mask == mask) {
949 return -EINVAL;
950 }
951
952 if (isr_data->isr == NULL && free_idx == -1)
953 free_idx = i;
954 }
955
956 if (free_idx == -1)
957 return -EBUSY;
958
959 isr_data = &isr_array[free_idx];
960 isr_data->isr = isr;
961 isr_data->arg = arg;
962 isr_data->mask = mask;
963
964 return 0;
965 }
966
967 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
968 struct dsi_isr_data *isr_array, unsigned isr_array_size)
969 {
970 struct dsi_isr_data *isr_data;
971 int i;
972
973 for (i = 0; i < isr_array_size; i++) {
974 isr_data = &isr_array[i];
975 if (isr_data->isr != isr || isr_data->arg != arg ||
976 isr_data->mask != mask)
977 continue;
978
979 isr_data->isr = NULL;
980 isr_data->arg = NULL;
981 isr_data->mask = 0;
982
983 return 0;
984 }
985
986 return -EINVAL;
987 }
988
989 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
990 void *arg, u32 mask)
991 {
992 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
993 unsigned long flags;
994 int r;
995
996 spin_lock_irqsave(&dsi->irq_lock, flags);
997
998 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
999 ARRAY_SIZE(dsi->isr_tables.isr_table));
1000
1001 if (r == 0)
1002 _omap_dsi_set_irqs(dsidev);
1003
1004 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1005
1006 return r;
1007 }
1008
1009 static int dsi_unregister_isr(struct platform_device *dsidev,
1010 omap_dsi_isr_t isr, void *arg, u32 mask)
1011 {
1012 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1013 unsigned long flags;
1014 int r;
1015
1016 spin_lock_irqsave(&dsi->irq_lock, flags);
1017
1018 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1019 ARRAY_SIZE(dsi->isr_tables.isr_table));
1020
1021 if (r == 0)
1022 _omap_dsi_set_irqs(dsidev);
1023
1024 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1025
1026 return r;
1027 }
1028
1029 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1030 omap_dsi_isr_t isr, void *arg, u32 mask)
1031 {
1032 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1033 unsigned long flags;
1034 int r;
1035
1036 spin_lock_irqsave(&dsi->irq_lock, flags);
1037
1038 r = _dsi_register_isr(isr, arg, mask,
1039 dsi->isr_tables.isr_table_vc[channel],
1040 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1041
1042 if (r == 0)
1043 _omap_dsi_set_irqs_vc(dsidev, channel);
1044
1045 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1046
1047 return r;
1048 }
1049
1050 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1051 omap_dsi_isr_t isr, void *arg, u32 mask)
1052 {
1053 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1054 unsigned long flags;
1055 int r;
1056
1057 spin_lock_irqsave(&dsi->irq_lock, flags);
1058
1059 r = _dsi_unregister_isr(isr, arg, mask,
1060 dsi->isr_tables.isr_table_vc[channel],
1061 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1062
1063 if (r == 0)
1064 _omap_dsi_set_irqs_vc(dsidev, channel);
1065
1066 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1067
1068 return r;
1069 }
1070
1071 static int dsi_register_isr_cio(struct platform_device *dsidev,
1072 omap_dsi_isr_t isr, void *arg, u32 mask)
1073 {
1074 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1075 unsigned long flags;
1076 int r;
1077
1078 spin_lock_irqsave(&dsi->irq_lock, flags);
1079
1080 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1081 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1082
1083 if (r == 0)
1084 _omap_dsi_set_irqs_cio(dsidev);
1085
1086 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1087
1088 return r;
1089 }
1090
1091 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1092 omap_dsi_isr_t isr, void *arg, u32 mask)
1093 {
1094 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1095 unsigned long flags;
1096 int r;
1097
1098 spin_lock_irqsave(&dsi->irq_lock, flags);
1099
1100 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1101 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1102
1103 if (r == 0)
1104 _omap_dsi_set_irqs_cio(dsidev);
1105
1106 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1107
1108 return r;
1109 }
1110
1111 static u32 dsi_get_errors(struct platform_device *dsidev)
1112 {
1113 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1114 unsigned long flags;
1115 u32 e;
1116 spin_lock_irqsave(&dsi->errors_lock, flags);
1117 e = dsi->errors;
1118 dsi->errors = 0;
1119 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1120 return e;
1121 }
1122
1123 int dsi_runtime_get(struct platform_device *dsidev)
1124 {
1125 int r;
1126 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1127
1128 DSSDBG("dsi_runtime_get\n");
1129
1130 r = pm_runtime_get_sync(&dsi->pdev->dev);
1131 WARN_ON(r < 0);
1132 return r < 0 ? r : 0;
1133 }
1134
1135 void dsi_runtime_put(struct platform_device *dsidev)
1136 {
1137 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1138 int r;
1139
1140 DSSDBG("dsi_runtime_put\n");
1141
1142 r = pm_runtime_put_sync(&dsi->pdev->dev);
1143 WARN_ON(r < 0 && r != -ENOSYS);
1144 }
1145
1146 static int dsi_regulator_init(struct platform_device *dsidev)
1147 {
1148 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1149 struct regulator *vdds_dsi;
1150
1151 if (dsi->vdds_dsi_reg != NULL)
1152 return 0;
1153
1154 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdds_dsi");
1155
1156 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1157 if (IS_ERR(vdds_dsi))
1158 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "VCXIO");
1159
1160 if (IS_ERR(vdds_dsi)) {
1161 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1162 DSSERR("can't get VDDS_DSI regulator\n");
1163 return PTR_ERR(vdds_dsi);
1164 }
1165
1166 dsi->vdds_dsi_reg = vdds_dsi;
1167
1168 return 0;
1169 }
1170
1171 /* source clock for DSI PLL. this could also be PCLKFREE */
1172 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1173 bool enable)
1174 {
1175 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1176
1177 if (enable)
1178 clk_prepare_enable(dsi->sys_clk);
1179 else
1180 clk_disable_unprepare(dsi->sys_clk);
1181
1182 if (enable && dsi->pll_locked) {
1183 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1184 DSSERR("cannot lock PLL when enabling clocks\n");
1185 }
1186 }
1187
1188 static void _dsi_print_reset_status(struct platform_device *dsidev)
1189 {
1190 u32 l;
1191 int b0, b1, b2;
1192
1193 /* A dummy read using the SCP interface to any DSIPHY register is
1194 * required after DSIPHY reset to complete the reset of the DSI complex
1195 * I/O. */
1196 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1197
1198 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1199 b0 = 28;
1200 b1 = 27;
1201 b2 = 26;
1202 } else {
1203 b0 = 24;
1204 b1 = 25;
1205 b2 = 26;
1206 }
1207
1208 #define DSI_FLD_GET(fld, start, end)\
1209 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1210
1211 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1212 DSI_FLD_GET(PLL_STATUS, 0, 0),
1213 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1214 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1215 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1216 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1217 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1218 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1219 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1220
1221 #undef DSI_FLD_GET
1222 }
1223
1224 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1225 {
1226 DSSDBG("dsi_if_enable(%d)\n", enable);
1227
1228 enable = enable ? 1 : 0;
1229 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1230
1231 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1232 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1233 return -EIO;
1234 }
1235
1236 return 0;
1237 }
1238
1239 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1240 {
1241 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1242
1243 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1244 }
1245
1246 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1247 {
1248 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1249
1250 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1251 }
1252
1253 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1254 {
1255 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1256
1257 return dsi->current_cinfo.clkin4ddr / 16;
1258 }
1259
1260 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1261 {
1262 unsigned long r;
1263 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1264
1265 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1266 /* DSI FCLK source is DSS_CLK_FCK */
1267 r = clk_get_rate(dsi->dss_clk);
1268 } else {
1269 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1270 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1271 }
1272
1273 return r;
1274 }
1275
1276 static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1277 unsigned long lp_clk_min, unsigned long lp_clk_max)
1278 {
1279 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1280 unsigned lp_clk_div;
1281 unsigned long lp_clk;
1282
1283 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1284 lp_clk = dsi_fclk / 2 / lp_clk_div;
1285
1286 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1287 return -EINVAL;
1288
1289 cinfo->lp_clk_div = lp_clk_div;
1290 cinfo->lp_clk = lp_clk;
1291
1292 return 0;
1293 }
1294
1295 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1296 {
1297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1298 unsigned long dsi_fclk;
1299 unsigned lp_clk_div;
1300 unsigned long lp_clk;
1301
1302 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1303
1304 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1305 return -EINVAL;
1306
1307 dsi_fclk = dsi_fclk_rate(dsidev);
1308
1309 lp_clk = dsi_fclk / 2 / lp_clk_div;
1310
1311 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1312 dsi->current_cinfo.lp_clk = lp_clk;
1313 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1314
1315 /* LP_CLK_DIVISOR */
1316 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1317
1318 /* LP_RX_SYNCHRO_ENABLE */
1319 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1320
1321 return 0;
1322 }
1323
1324 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1325 {
1326 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1327
1328 if (dsi->scp_clk_refcount++ == 0)
1329 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1330 }
1331
1332 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1333 {
1334 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1335
1336 WARN_ON(dsi->scp_clk_refcount == 0);
1337 if (--dsi->scp_clk_refcount == 0)
1338 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1339 }
1340
1341 enum dsi_pll_power_state {
1342 DSI_PLL_POWER_OFF = 0x0,
1343 DSI_PLL_POWER_ON_HSCLK = 0x1,
1344 DSI_PLL_POWER_ON_ALL = 0x2,
1345 DSI_PLL_POWER_ON_DIV = 0x3,
1346 };
1347
1348 static int dsi_pll_power(struct platform_device *dsidev,
1349 enum dsi_pll_power_state state)
1350 {
1351 int t = 0;
1352
1353 /* DSI-PLL power command 0x3 is not working */
1354 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1355 state == DSI_PLL_POWER_ON_DIV)
1356 state = DSI_PLL_POWER_ON_ALL;
1357
1358 /* PLL_PWR_CMD */
1359 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1360
1361 /* PLL_PWR_STATUS */
1362 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1363 if (++t > 1000) {
1364 DSSERR("Failed to set DSI PLL power mode to %d\n",
1365 state);
1366 return -ENODEV;
1367 }
1368 udelay(1);
1369 }
1370
1371 return 0;
1372 }
1373
1374 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1375 {
1376 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1377 return clk_get_rate(dsi->sys_clk);
1378 }
1379
1380 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1381 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1382 {
1383 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1384 int regm, regm_start, regm_stop;
1385 unsigned long out_max;
1386 unsigned long out;
1387
1388 out_min = out_min ? out_min : 1;
1389 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1390
1391 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1392 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1393
1394 for (regm = regm_start; regm <= regm_stop; ++regm) {
1395 out = pll / regm;
1396
1397 if (func(regm, out, data))
1398 return true;
1399 }
1400
1401 return false;
1402 }
1403
1404 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1405 unsigned long pll_min, unsigned long pll_max,
1406 dsi_pll_calc_func func, void *data)
1407 {
1408 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1409 int regn, regn_start, regn_stop;
1410 int regm, regm_start, regm_stop;
1411 unsigned long fint, pll;
1412 const unsigned long pll_hw_max = 1800000000;
1413 unsigned long fint_hw_min, fint_hw_max;
1414
1415 fint_hw_min = dsi->fint_min;
1416 fint_hw_max = dsi->fint_max;
1417
1418 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1419 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1420
1421 pll_max = pll_max ? pll_max : ULONG_MAX;
1422
1423 for (regn = regn_start; regn <= regn_stop; ++regn) {
1424 fint = clkin / regn;
1425
1426 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1427 1ul);
1428 regm_stop = min3(pll_max / fint / 2,
1429 pll_hw_max / fint / 2,
1430 dsi->regm_max);
1431
1432 for (regm = regm_start; regm <= regm_stop; ++regm) {
1433 pll = 2 * regm * fint;
1434
1435 if (func(regn, regm, fint, pll, data))
1436 return true;
1437 }
1438 }
1439
1440 return false;
1441 }
1442
1443 /* calculate clock rates using dividers in cinfo */
1444 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1445 struct dsi_clock_info *cinfo)
1446 {
1447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1448
1449 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1450 return -EINVAL;
1451
1452 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1453 return -EINVAL;
1454
1455 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1456 return -EINVAL;
1457
1458 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1459 return -EINVAL;
1460
1461 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1462 cinfo->fint = cinfo->clkin / cinfo->regn;
1463
1464 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1465 return -EINVAL;
1466
1467 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1468
1469 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1470 return -EINVAL;
1471
1472 if (cinfo->regm_dispc > 0)
1473 cinfo->dsi_pll_hsdiv_dispc_clk =
1474 cinfo->clkin4ddr / cinfo->regm_dispc;
1475 else
1476 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1477
1478 if (cinfo->regm_dsi > 0)
1479 cinfo->dsi_pll_hsdiv_dsi_clk =
1480 cinfo->clkin4ddr / cinfo->regm_dsi;
1481 else
1482 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1483
1484 return 0;
1485 }
1486
1487 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1488 {
1489 unsigned long max_dsi_fck;
1490
1491 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1492
1493 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1494 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1495 }
1496
1497 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1498 struct dsi_clock_info *cinfo)
1499 {
1500 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1501 int r = 0;
1502 u32 l;
1503 int f = 0;
1504 u8 regn_start, regn_end, regm_start, regm_end;
1505 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1506
1507 DSSDBG("DSI PLL clock config starts");
1508
1509 dsi->current_cinfo.clkin = cinfo->clkin;
1510 dsi->current_cinfo.fint = cinfo->fint;
1511 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1512 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1513 cinfo->dsi_pll_hsdiv_dispc_clk;
1514 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1515 cinfo->dsi_pll_hsdiv_dsi_clk;
1516
1517 dsi->current_cinfo.regn = cinfo->regn;
1518 dsi->current_cinfo.regm = cinfo->regm;
1519 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1520 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1521
1522 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1523
1524 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1525
1526 /* DSIPHY == CLKIN4DDR */
1527 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1528 cinfo->regm,
1529 cinfo->regn,
1530 cinfo->clkin,
1531 cinfo->clkin4ddr);
1532
1533 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1534 cinfo->clkin4ddr / 1000 / 1000 / 2);
1535
1536 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1537
1538 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1539 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1540 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1541 cinfo->dsi_pll_hsdiv_dispc_clk);
1542 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1543 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1544 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1545 cinfo->dsi_pll_hsdiv_dsi_clk);
1546
1547 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1548 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1549 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1550 &regm_dispc_end);
1551 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1552 &regm_dsi_end);
1553
1554 /* DSI_PLL_AUTOMODE = manual */
1555 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1556
1557 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1558 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1559 /* DSI_PLL_REGN */
1560 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1561 /* DSI_PLL_REGM */
1562 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1563 /* DSI_CLOCK_DIV */
1564 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1565 regm_dispc_start, regm_dispc_end);
1566 /* DSIPROTO_CLOCK_DIV */
1567 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1568 regm_dsi_start, regm_dsi_end);
1569 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1570
1571 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1572
1573 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1574
1575 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1576 f = cinfo->fint < 1000000 ? 0x3 :
1577 cinfo->fint < 1250000 ? 0x4 :
1578 cinfo->fint < 1500000 ? 0x5 :
1579 cinfo->fint < 1750000 ? 0x6 :
1580 0x7;
1581
1582 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1583 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1584 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1585
1586 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1587 }
1588
1589 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1590 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1591 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1592 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1593 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1594 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1595
1596 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1597
1598 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1599 DSSERR("dsi pll go bit not going down.\n");
1600 r = -EIO;
1601 goto err;
1602 }
1603
1604 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1605 DSSERR("cannot lock PLL\n");
1606 r = -EIO;
1607 goto err;
1608 }
1609
1610 dsi->pll_locked = 1;
1611
1612 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1613 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1614 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1615 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1616 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1617 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1618 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1619 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1620 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1621 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1622 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1623 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1624 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1625 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1626 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1627 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1628
1629 DSSDBG("PLL config done\n");
1630 err:
1631 return r;
1632 }
1633
1634 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1635 bool enable_hsdiv)
1636 {
1637 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1638 int r = 0;
1639 enum dsi_pll_power_state pwstate;
1640
1641 DSSDBG("PLL init\n");
1642
1643 /*
1644 * It seems that on many OMAPs we need to enable both to have a
1645 * functional HSDivider.
1646 */
1647 enable_hsclk = enable_hsdiv = true;
1648
1649 r = dsi_regulator_init(dsidev);
1650 if (r)
1651 return r;
1652
1653 dsi_enable_pll_clock(dsidev, 1);
1654 /*
1655 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1656 */
1657 dsi_enable_scp_clk(dsidev);
1658
1659 if (!dsi->vdds_dsi_enabled) {
1660 r = regulator_enable(dsi->vdds_dsi_reg);
1661 if (r)
1662 goto err0;
1663 dsi->vdds_dsi_enabled = true;
1664 }
1665
1666 /* XXX PLL does not come out of reset without this... */
1667 dispc_pck_free_enable(1);
1668
1669 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1670 DSSERR("PLL not coming out of reset.\n");
1671 r = -ENODEV;
1672 dispc_pck_free_enable(0);
1673 goto err1;
1674 }
1675
1676 /* XXX ... but if left on, we get problems when planes do not
1677 * fill the whole display. No idea about this */
1678 dispc_pck_free_enable(0);
1679
1680 if (enable_hsclk && enable_hsdiv)
1681 pwstate = DSI_PLL_POWER_ON_ALL;
1682 else if (enable_hsclk)
1683 pwstate = DSI_PLL_POWER_ON_HSCLK;
1684 else if (enable_hsdiv)
1685 pwstate = DSI_PLL_POWER_ON_DIV;
1686 else
1687 pwstate = DSI_PLL_POWER_OFF;
1688
1689 r = dsi_pll_power(dsidev, pwstate);
1690
1691 if (r)
1692 goto err1;
1693
1694 DSSDBG("PLL init done\n");
1695
1696 return 0;
1697 err1:
1698 if (dsi->vdds_dsi_enabled) {
1699 regulator_disable(dsi->vdds_dsi_reg);
1700 dsi->vdds_dsi_enabled = false;
1701 }
1702 err0:
1703 dsi_disable_scp_clk(dsidev);
1704 dsi_enable_pll_clock(dsidev, 0);
1705 return r;
1706 }
1707
1708 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1709 {
1710 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1711
1712 dsi->pll_locked = 0;
1713 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1714 if (disconnect_lanes) {
1715 WARN_ON(!dsi->vdds_dsi_enabled);
1716 regulator_disable(dsi->vdds_dsi_reg);
1717 dsi->vdds_dsi_enabled = false;
1718 }
1719
1720 dsi_disable_scp_clk(dsidev);
1721 dsi_enable_pll_clock(dsidev, 0);
1722
1723 DSSDBG("PLL uninit done\n");
1724 }
1725
1726 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1727 struct seq_file *s)
1728 {
1729 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1730 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1731 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1732 int dsi_module = dsi->module_id;
1733
1734 dispc_clk_src = dss_get_dispc_clk_source();
1735 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1736
1737 if (dsi_runtime_get(dsidev))
1738 return;
1739
1740 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1741
1742 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1743
1744 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1745
1746 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1747 cinfo->clkin4ddr, cinfo->regm);
1748
1749 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1750 dss_feat_get_clk_source_name(dsi_module == 0 ?
1751 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1752 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1753 cinfo->dsi_pll_hsdiv_dispc_clk,
1754 cinfo->regm_dispc,
1755 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1756 "off" : "on");
1757
1758 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1759 dss_feat_get_clk_source_name(dsi_module == 0 ?
1760 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1761 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1762 cinfo->dsi_pll_hsdiv_dsi_clk,
1763 cinfo->regm_dsi,
1764 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1765 "off" : "on");
1766
1767 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1768
1769 seq_printf(s, "dsi fclk source = %s (%s)\n",
1770 dss_get_generic_clk_source_name(dsi_clk_src),
1771 dss_feat_get_clk_source_name(dsi_clk_src));
1772
1773 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1774
1775 seq_printf(s, "DDR_CLK\t\t%lu\n",
1776 cinfo->clkin4ddr / 4);
1777
1778 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1779
1780 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1781
1782 dsi_runtime_put(dsidev);
1783 }
1784
1785 void dsi_dump_clocks(struct seq_file *s)
1786 {
1787 struct platform_device *dsidev;
1788 int i;
1789
1790 for (i = 0; i < MAX_NUM_DSI; i++) {
1791 dsidev = dsi_get_dsidev_from_id(i);
1792 if (dsidev)
1793 dsi_dump_dsidev_clocks(dsidev, s);
1794 }
1795 }
1796
1797 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1798 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1799 struct seq_file *s)
1800 {
1801 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1802 unsigned long flags;
1803 struct dsi_irq_stats stats;
1804
1805 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1806
1807 stats = dsi->irq_stats;
1808 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1809 dsi->irq_stats.last_reset = jiffies;
1810
1811 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1812
1813 seq_printf(s, "period %u ms\n",
1814 jiffies_to_msecs(jiffies - stats.last_reset));
1815
1816 seq_printf(s, "irqs %d\n", stats.irq_count);
1817 #define PIS(x) \
1818 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1819
1820 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1821 PIS(VC0);
1822 PIS(VC1);
1823 PIS(VC2);
1824 PIS(VC3);
1825 PIS(WAKEUP);
1826 PIS(RESYNC);
1827 PIS(PLL_LOCK);
1828 PIS(PLL_UNLOCK);
1829 PIS(PLL_RECALL);
1830 PIS(COMPLEXIO_ERR);
1831 PIS(HS_TX_TIMEOUT);
1832 PIS(LP_RX_TIMEOUT);
1833 PIS(TE_TRIGGER);
1834 PIS(ACK_TRIGGER);
1835 PIS(SYNC_LOST);
1836 PIS(LDO_POWER_GOOD);
1837 PIS(TA_TIMEOUT);
1838 #undef PIS
1839
1840 #define PIS(x) \
1841 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1842 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1843 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1844 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1845 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1846
1847 seq_printf(s, "-- VC interrupts --\n");
1848 PIS(CS);
1849 PIS(ECC_CORR);
1850 PIS(PACKET_SENT);
1851 PIS(FIFO_TX_OVF);
1852 PIS(FIFO_RX_OVF);
1853 PIS(BTA);
1854 PIS(ECC_NO_CORR);
1855 PIS(FIFO_TX_UDF);
1856 PIS(PP_BUSY_CHANGE);
1857 #undef PIS
1858
1859 #define PIS(x) \
1860 seq_printf(s, "%-20s %10d\n", #x, \
1861 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1862
1863 seq_printf(s, "-- CIO interrupts --\n");
1864 PIS(ERRSYNCESC1);
1865 PIS(ERRSYNCESC2);
1866 PIS(ERRSYNCESC3);
1867 PIS(ERRESC1);
1868 PIS(ERRESC2);
1869 PIS(ERRESC3);
1870 PIS(ERRCONTROL1);
1871 PIS(ERRCONTROL2);
1872 PIS(ERRCONTROL3);
1873 PIS(STATEULPS1);
1874 PIS(STATEULPS2);
1875 PIS(STATEULPS3);
1876 PIS(ERRCONTENTIONLP0_1);
1877 PIS(ERRCONTENTIONLP1_1);
1878 PIS(ERRCONTENTIONLP0_2);
1879 PIS(ERRCONTENTIONLP1_2);
1880 PIS(ERRCONTENTIONLP0_3);
1881 PIS(ERRCONTENTIONLP1_3);
1882 PIS(ULPSACTIVENOT_ALL0);
1883 PIS(ULPSACTIVENOT_ALL1);
1884 #undef PIS
1885 }
1886
1887 static void dsi1_dump_irqs(struct seq_file *s)
1888 {
1889 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1890
1891 dsi_dump_dsidev_irqs(dsidev, s);
1892 }
1893
1894 static void dsi2_dump_irqs(struct seq_file *s)
1895 {
1896 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1897
1898 dsi_dump_dsidev_irqs(dsidev, s);
1899 }
1900 #endif
1901
1902 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1903 struct seq_file *s)
1904 {
1905 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1906
1907 if (dsi_runtime_get(dsidev))
1908 return;
1909 dsi_enable_scp_clk(dsidev);
1910
1911 DUMPREG(DSI_REVISION);
1912 DUMPREG(DSI_SYSCONFIG);
1913 DUMPREG(DSI_SYSSTATUS);
1914 DUMPREG(DSI_IRQSTATUS);
1915 DUMPREG(DSI_IRQENABLE);
1916 DUMPREG(DSI_CTRL);
1917 DUMPREG(DSI_COMPLEXIO_CFG1);
1918 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1919 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1920 DUMPREG(DSI_CLK_CTRL);
1921 DUMPREG(DSI_TIMING1);
1922 DUMPREG(DSI_TIMING2);
1923 DUMPREG(DSI_VM_TIMING1);
1924 DUMPREG(DSI_VM_TIMING2);
1925 DUMPREG(DSI_VM_TIMING3);
1926 DUMPREG(DSI_CLK_TIMING);
1927 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1928 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1929 DUMPREG(DSI_COMPLEXIO_CFG2);
1930 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1931 DUMPREG(DSI_VM_TIMING4);
1932 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1933 DUMPREG(DSI_VM_TIMING5);
1934 DUMPREG(DSI_VM_TIMING6);
1935 DUMPREG(DSI_VM_TIMING7);
1936 DUMPREG(DSI_STOPCLK_TIMING);
1937
1938 DUMPREG(DSI_VC_CTRL(0));
1939 DUMPREG(DSI_VC_TE(0));
1940 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1941 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1942 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1943 DUMPREG(DSI_VC_IRQSTATUS(0));
1944 DUMPREG(DSI_VC_IRQENABLE(0));
1945
1946 DUMPREG(DSI_VC_CTRL(1));
1947 DUMPREG(DSI_VC_TE(1));
1948 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1949 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1950 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1951 DUMPREG(DSI_VC_IRQSTATUS(1));
1952 DUMPREG(DSI_VC_IRQENABLE(1));
1953
1954 DUMPREG(DSI_VC_CTRL(2));
1955 DUMPREG(DSI_VC_TE(2));
1956 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1957 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1958 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1959 DUMPREG(DSI_VC_IRQSTATUS(2));
1960 DUMPREG(DSI_VC_IRQENABLE(2));
1961
1962 DUMPREG(DSI_VC_CTRL(3));
1963 DUMPREG(DSI_VC_TE(3));
1964 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1965 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1966 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1967 DUMPREG(DSI_VC_IRQSTATUS(3));
1968 DUMPREG(DSI_VC_IRQENABLE(3));
1969
1970 DUMPREG(DSI_DSIPHY_CFG0);
1971 DUMPREG(DSI_DSIPHY_CFG1);
1972 DUMPREG(DSI_DSIPHY_CFG2);
1973 DUMPREG(DSI_DSIPHY_CFG5);
1974
1975 DUMPREG(DSI_PLL_CONTROL);
1976 DUMPREG(DSI_PLL_STATUS);
1977 DUMPREG(DSI_PLL_GO);
1978 DUMPREG(DSI_PLL_CONFIGURATION1);
1979 DUMPREG(DSI_PLL_CONFIGURATION2);
1980
1981 dsi_disable_scp_clk(dsidev);
1982 dsi_runtime_put(dsidev);
1983 #undef DUMPREG
1984 }
1985
1986 static void dsi1_dump_regs(struct seq_file *s)
1987 {
1988 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1989
1990 dsi_dump_dsidev_regs(dsidev, s);
1991 }
1992
1993 static void dsi2_dump_regs(struct seq_file *s)
1994 {
1995 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1996
1997 dsi_dump_dsidev_regs(dsidev, s);
1998 }
1999
2000 enum dsi_cio_power_state {
2001 DSI_COMPLEXIO_POWER_OFF = 0x0,
2002 DSI_COMPLEXIO_POWER_ON = 0x1,
2003 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2004 };
2005
2006 static int dsi_cio_power(struct platform_device *dsidev,
2007 enum dsi_cio_power_state state)
2008 {
2009 int t = 0;
2010
2011 /* PWR_CMD */
2012 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2013
2014 /* PWR_STATUS */
2015 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2016 26, 25) != state) {
2017 if (++t > 1000) {
2018 DSSERR("failed to set complexio power state to "
2019 "%d\n", state);
2020 return -ENODEV;
2021 }
2022 udelay(1);
2023 }
2024
2025 return 0;
2026 }
2027
2028 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2029 {
2030 int val;
2031
2032 /* line buffer on OMAP3 is 1024 x 24bits */
2033 /* XXX: for some reason using full buffer size causes
2034 * considerable TX slowdown with update sizes that fill the
2035 * whole buffer */
2036 if (!dss_has_feature(FEAT_DSI_GNQ))
2037 return 1023 * 3;
2038
2039 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2040
2041 switch (val) {
2042 case 1:
2043 return 512 * 3; /* 512x24 bits */
2044 case 2:
2045 return 682 * 3; /* 682x24 bits */
2046 case 3:
2047 return 853 * 3; /* 853x24 bits */
2048 case 4:
2049 return 1024 * 3; /* 1024x24 bits */
2050 case 5:
2051 return 1194 * 3; /* 1194x24 bits */
2052 case 6:
2053 return 1365 * 3; /* 1365x24 bits */
2054 case 7:
2055 return 1920 * 3; /* 1920x24 bits */
2056 default:
2057 BUG();
2058 return 0;
2059 }
2060 }
2061
2062 static int dsi_set_lane_config(struct platform_device *dsidev)
2063 {
2064 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2065 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2066 static const enum dsi_lane_function functions[] = {
2067 DSI_LANE_CLK,
2068 DSI_LANE_DATA1,
2069 DSI_LANE_DATA2,
2070 DSI_LANE_DATA3,
2071 DSI_LANE_DATA4,
2072 };
2073 u32 r;
2074 int i;
2075
2076 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2077
2078 for (i = 0; i < dsi->num_lanes_used; ++i) {
2079 unsigned offset = offsets[i];
2080 unsigned polarity, lane_number;
2081 unsigned t;
2082
2083 for (t = 0; t < dsi->num_lanes_supported; ++t)
2084 if (dsi->lanes[t].function == functions[i])
2085 break;
2086
2087 if (t == dsi->num_lanes_supported)
2088 return -EINVAL;
2089
2090 lane_number = t;
2091 polarity = dsi->lanes[t].polarity;
2092
2093 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2094 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2095 }
2096
2097 /* clear the unused lanes */
2098 for (; i < dsi->num_lanes_supported; ++i) {
2099 unsigned offset = offsets[i];
2100
2101 r = FLD_MOD(r, 0, offset + 2, offset);
2102 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2103 }
2104
2105 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2106
2107 return 0;
2108 }
2109
2110 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2111 {
2112 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2113
2114 /* convert time in ns to ddr ticks, rounding up */
2115 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2116 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2117 }
2118
2119 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2120 {
2121 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2122
2123 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2124 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2125 }
2126
2127 static void dsi_cio_timings(struct platform_device *dsidev)
2128 {
2129 u32 r;
2130 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2131 u32 tlpx_half, tclk_trail, tclk_zero;
2132 u32 tclk_prepare;
2133
2134 /* calculate timings */
2135
2136 /* 1 * DDR_CLK = 2 * UI */
2137
2138 /* min 40ns + 4*UI max 85ns + 6*UI */
2139 ths_prepare = ns2ddr(dsidev, 70) + 2;
2140
2141 /* min 145ns + 10*UI */
2142 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2143
2144 /* min max(8*UI, 60ns+4*UI) */
2145 ths_trail = ns2ddr(dsidev, 60) + 5;
2146
2147 /* min 100ns */
2148 ths_exit = ns2ddr(dsidev, 145);
2149
2150 /* tlpx min 50n */
2151 tlpx_half = ns2ddr(dsidev, 25);
2152
2153 /* min 60ns */
2154 tclk_trail = ns2ddr(dsidev, 60) + 2;
2155
2156 /* min 38ns, max 95ns */
2157 tclk_prepare = ns2ddr(dsidev, 65);
2158
2159 /* min tclk-prepare + tclk-zero = 300ns */
2160 tclk_zero = ns2ddr(dsidev, 260);
2161
2162 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2163 ths_prepare, ddr2ns(dsidev, ths_prepare),
2164 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2165 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2166 ths_trail, ddr2ns(dsidev, ths_trail),
2167 ths_exit, ddr2ns(dsidev, ths_exit));
2168
2169 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2170 "tclk_zero %u (%uns)\n",
2171 tlpx_half, ddr2ns(dsidev, tlpx_half),
2172 tclk_trail, ddr2ns(dsidev, tclk_trail),
2173 tclk_zero, ddr2ns(dsidev, tclk_zero));
2174 DSSDBG("tclk_prepare %u (%uns)\n",
2175 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2176
2177 /* program timings */
2178
2179 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2180 r = FLD_MOD(r, ths_prepare, 31, 24);
2181 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2182 r = FLD_MOD(r, ths_trail, 15, 8);
2183 r = FLD_MOD(r, ths_exit, 7, 0);
2184 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2185
2186 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2187 r = FLD_MOD(r, tlpx_half, 20, 16);
2188 r = FLD_MOD(r, tclk_trail, 15, 8);
2189 r = FLD_MOD(r, tclk_zero, 7, 0);
2190
2191 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2192 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2193 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2194 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2195 }
2196
2197 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2198
2199 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2200 r = FLD_MOD(r, tclk_prepare, 7, 0);
2201 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2202 }
2203
2204 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2205 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2206 unsigned mask_p, unsigned mask_n)
2207 {
2208 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2209 int i;
2210 u32 l;
2211 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2212
2213 l = 0;
2214
2215 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2216 unsigned p = dsi->lanes[i].polarity;
2217
2218 if (mask_p & (1 << i))
2219 l |= 1 << (i * 2 + (p ? 0 : 1));
2220
2221 if (mask_n & (1 << i))
2222 l |= 1 << (i * 2 + (p ? 1 : 0));
2223 }
2224
2225 /*
2226 * Bits in REGLPTXSCPDAT4TO0DXDY:
2227 * 17: DY0 18: DX0
2228 * 19: DY1 20: DX1
2229 * 21: DY2 22: DX2
2230 * 23: DY3 24: DX3
2231 * 25: DY4 26: DX4
2232 */
2233
2234 /* Set the lane override configuration */
2235
2236 /* REGLPTXSCPDAT4TO0DXDY */
2237 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2238
2239 /* Enable lane override */
2240
2241 /* ENLPTXSCPDAT */
2242 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2243 }
2244
2245 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2246 {
2247 /* Disable lane override */
2248 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2249 /* Reset the lane override configuration */
2250 /* REGLPTXSCPDAT4TO0DXDY */
2251 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2252 }
2253
2254 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2255 {
2256 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2257 int t, i;
2258 bool in_use[DSI_MAX_NR_LANES];
2259 static const u8 offsets_old[] = { 28, 27, 26 };
2260 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2261 const u8 *offsets;
2262
2263 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2264 offsets = offsets_old;
2265 else
2266 offsets = offsets_new;
2267
2268 for (i = 0; i < dsi->num_lanes_supported; ++i)
2269 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2270
2271 t = 100000;
2272 while (true) {
2273 u32 l;
2274 int ok;
2275
2276 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2277
2278 ok = 0;
2279 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2280 if (!in_use[i] || (l & (1 << offsets[i])))
2281 ok++;
2282 }
2283
2284 if (ok == dsi->num_lanes_supported)
2285 break;
2286
2287 if (--t == 0) {
2288 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2289 if (!in_use[i] || (l & (1 << offsets[i])))
2290 continue;
2291
2292 DSSERR("CIO TXCLKESC%d domain not coming " \
2293 "out of reset\n", i);
2294 }
2295 return -EIO;
2296 }
2297 }
2298
2299 return 0;
2300 }
2301
2302 /* return bitmask of enabled lanes, lane0 being the lsb */
2303 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2304 {
2305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2306 unsigned mask = 0;
2307 int i;
2308
2309 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2310 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2311 mask |= 1 << i;
2312 }
2313
2314 return mask;
2315 }
2316
2317 static int dsi_cio_init(struct platform_device *dsidev)
2318 {
2319 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2320 int r;
2321 u32 l;
2322
2323 DSSDBG("DSI CIO init starts");
2324
2325 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2326 if (r)
2327 return r;
2328
2329 dsi_enable_scp_clk(dsidev);
2330
2331 /* A dummy read using the SCP interface to any DSIPHY register is
2332 * required after DSIPHY reset to complete the reset of the DSI complex
2333 * I/O. */
2334 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2335
2336 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2337 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2338 r = -EIO;
2339 goto err_scp_clk_dom;
2340 }
2341
2342 r = dsi_set_lane_config(dsidev);
2343 if (r)
2344 goto err_scp_clk_dom;
2345
2346 /* set TX STOP MODE timer to maximum for this operation */
2347 l = dsi_read_reg(dsidev, DSI_TIMING1);
2348 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2349 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2350 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2351 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2352 dsi_write_reg(dsidev, DSI_TIMING1, l);
2353
2354 if (dsi->ulps_enabled) {
2355 unsigned mask_p;
2356 int i;
2357
2358 DSSDBG("manual ulps exit\n");
2359
2360 /* ULPS is exited by Mark-1 state for 1ms, followed by
2361 * stop state. DSS HW cannot do this via the normal
2362 * ULPS exit sequence, as after reset the DSS HW thinks
2363 * that we are not in ULPS mode, and refuses to send the
2364 * sequence. So we need to send the ULPS exit sequence
2365 * manually by setting positive lines high and negative lines
2366 * low for 1ms.
2367 */
2368
2369 mask_p = 0;
2370
2371 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2372 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2373 continue;
2374 mask_p |= 1 << i;
2375 }
2376
2377 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2378 }
2379
2380 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2381 if (r)
2382 goto err_cio_pwr;
2383
2384 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2385 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2386 r = -ENODEV;
2387 goto err_cio_pwr_dom;
2388 }
2389
2390 dsi_if_enable(dsidev, true);
2391 dsi_if_enable(dsidev, false);
2392 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2393
2394 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2395 if (r)
2396 goto err_tx_clk_esc_rst;
2397
2398 if (dsi->ulps_enabled) {
2399 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2400 ktime_t wait = ns_to_ktime(1000 * 1000);
2401 set_current_state(TASK_UNINTERRUPTIBLE);
2402 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2403
2404 /* Disable the override. The lanes should be set to Mark-11
2405 * state by the HW */
2406 dsi_cio_disable_lane_override(dsidev);
2407 }
2408
2409 /* FORCE_TX_STOP_MODE_IO */
2410 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2411
2412 dsi_cio_timings(dsidev);
2413
2414 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2415 /* DDR_CLK_ALWAYS_ON */
2416 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2417 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2418 }
2419
2420 dsi->ulps_enabled = false;
2421
2422 DSSDBG("CIO init done\n");
2423
2424 return 0;
2425
2426 err_tx_clk_esc_rst:
2427 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2428 err_cio_pwr_dom:
2429 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2430 err_cio_pwr:
2431 if (dsi->ulps_enabled)
2432 dsi_cio_disable_lane_override(dsidev);
2433 err_scp_clk_dom:
2434 dsi_disable_scp_clk(dsidev);
2435 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2436 return r;
2437 }
2438
2439 static void dsi_cio_uninit(struct platform_device *dsidev)
2440 {
2441 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2442
2443 /* DDR_CLK_ALWAYS_ON */
2444 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2445
2446 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2447 dsi_disable_scp_clk(dsidev);
2448 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2449 }
2450
2451 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2452 enum fifo_size size1, enum fifo_size size2,
2453 enum fifo_size size3, enum fifo_size size4)
2454 {
2455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2456 u32 r = 0;
2457 int add = 0;
2458 int i;
2459
2460 dsi->vc[0].tx_fifo_size = size1;
2461 dsi->vc[1].tx_fifo_size = size2;
2462 dsi->vc[2].tx_fifo_size = size3;
2463 dsi->vc[3].tx_fifo_size = size4;
2464
2465 for (i = 0; i < 4; i++) {
2466 u8 v;
2467 int size = dsi->vc[i].tx_fifo_size;
2468
2469 if (add + size > 4) {
2470 DSSERR("Illegal FIFO configuration\n");
2471 BUG();
2472 return;
2473 }
2474
2475 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2476 r |= v << (8 * i);
2477 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2478 add += size;
2479 }
2480
2481 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2482 }
2483
2484 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2485 enum fifo_size size1, enum fifo_size size2,
2486 enum fifo_size size3, enum fifo_size size4)
2487 {
2488 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2489 u32 r = 0;
2490 int add = 0;
2491 int i;
2492
2493 dsi->vc[0].rx_fifo_size = size1;
2494 dsi->vc[1].rx_fifo_size = size2;
2495 dsi->vc[2].rx_fifo_size = size3;
2496 dsi->vc[3].rx_fifo_size = size4;
2497
2498 for (i = 0; i < 4; i++) {
2499 u8 v;
2500 int size = dsi->vc[i].rx_fifo_size;
2501
2502 if (add + size > 4) {
2503 DSSERR("Illegal FIFO configuration\n");
2504 BUG();
2505 return;
2506 }
2507
2508 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2509 r |= v << (8 * i);
2510 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2511 add += size;
2512 }
2513
2514 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2515 }
2516
2517 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2518 {
2519 u32 r;
2520
2521 r = dsi_read_reg(dsidev, DSI_TIMING1);
2522 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2523 dsi_write_reg(dsidev, DSI_TIMING1, r);
2524
2525 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2526 DSSERR("TX_STOP bit not going down\n");
2527 return -EIO;
2528 }
2529
2530 return 0;
2531 }
2532
2533 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2534 {
2535 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2536 }
2537
2538 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2539 {
2540 struct dsi_packet_sent_handler_data *vp_data =
2541 (struct dsi_packet_sent_handler_data *) data;
2542 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2543 const int channel = dsi->update_channel;
2544 u8 bit = dsi->te_enabled ? 30 : 31;
2545
2546 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2547 complete(vp_data->completion);
2548 }
2549
2550 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2551 {
2552 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2553 DECLARE_COMPLETION_ONSTACK(completion);
2554 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2555 int r = 0;
2556 u8 bit;
2557
2558 bit = dsi->te_enabled ? 30 : 31;
2559
2560 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2561 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2562 if (r)
2563 goto err0;
2564
2565 /* Wait for completion only if TE_EN/TE_START is still set */
2566 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2567 if (wait_for_completion_timeout(&completion,
2568 msecs_to_jiffies(10)) == 0) {
2569 DSSERR("Failed to complete previous frame transfer\n");
2570 r = -EIO;
2571 goto err1;
2572 }
2573 }
2574
2575 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2576 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2577
2578 return 0;
2579 err1:
2580 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2581 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2582 err0:
2583 return r;
2584 }
2585
2586 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2587 {
2588 struct dsi_packet_sent_handler_data *l4_data =
2589 (struct dsi_packet_sent_handler_data *) data;
2590 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2591 const int channel = dsi->update_channel;
2592
2593 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2594 complete(l4_data->completion);
2595 }
2596
2597 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2598 {
2599 DECLARE_COMPLETION_ONSTACK(completion);
2600 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2601 int r = 0;
2602
2603 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2604 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2605 if (r)
2606 goto err0;
2607
2608 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2609 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2610 if (wait_for_completion_timeout(&completion,
2611 msecs_to_jiffies(10)) == 0) {
2612 DSSERR("Failed to complete previous l4 transfer\n");
2613 r = -EIO;
2614 goto err1;
2615 }
2616 }
2617
2618 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2619 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2620
2621 return 0;
2622 err1:
2623 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2624 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2625 err0:
2626 return r;
2627 }
2628
2629 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2630 {
2631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2632
2633 WARN_ON(!dsi_bus_is_locked(dsidev));
2634
2635 WARN_ON(in_interrupt());
2636
2637 if (!dsi_vc_is_enabled(dsidev, channel))
2638 return 0;
2639
2640 switch (dsi->vc[channel].source) {
2641 case DSI_VC_SOURCE_VP:
2642 return dsi_sync_vc_vp(dsidev, channel);
2643 case DSI_VC_SOURCE_L4:
2644 return dsi_sync_vc_l4(dsidev, channel);
2645 default:
2646 BUG();
2647 return -EINVAL;
2648 }
2649 }
2650
2651 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2652 bool enable)
2653 {
2654 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2655 channel, enable);
2656
2657 enable = enable ? 1 : 0;
2658
2659 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2660
2661 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2662 0, enable) != enable) {
2663 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2664 return -EIO;
2665 }
2666
2667 return 0;
2668 }
2669
2670 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2671 {
2672 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2673 u32 r;
2674
2675 DSSDBG("Initial config of virtual channel %d", channel);
2676
2677 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2678
2679 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2680 DSSERR("VC(%d) busy when trying to configure it!\n",
2681 channel);
2682
2683 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2684 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2685 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2686 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2687 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2688 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2689 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2690 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2691 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2692
2693 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2694 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2695
2696 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2697
2698 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2699 }
2700
2701 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2702 enum dsi_vc_source source)
2703 {
2704 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2705
2706 if (dsi->vc[channel].source == source)
2707 return 0;
2708
2709 DSSDBG("Source config of virtual channel %d", channel);
2710
2711 dsi_sync_vc(dsidev, channel);
2712
2713 dsi_vc_enable(dsidev, channel, 0);
2714
2715 /* VC_BUSY */
2716 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2717 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2718 return -EIO;
2719 }
2720
2721 /* SOURCE, 0 = L4, 1 = video port */
2722 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2723
2724 /* DCS_CMD_ENABLE */
2725 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2726 bool enable = source == DSI_VC_SOURCE_VP;
2727 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2728 }
2729
2730 dsi_vc_enable(dsidev, channel, 1);
2731
2732 dsi->vc[channel].source = source;
2733
2734 return 0;
2735 }
2736
2737 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2738 bool enable)
2739 {
2740 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2741 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2742
2743 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2744
2745 WARN_ON(!dsi_bus_is_locked(dsidev));
2746
2747 dsi_vc_enable(dsidev, channel, 0);
2748 dsi_if_enable(dsidev, 0);
2749
2750 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2751
2752 dsi_vc_enable(dsidev, channel, 1);
2753 dsi_if_enable(dsidev, 1);
2754
2755 dsi_force_tx_stop_mode_io(dsidev);
2756
2757 /* start the DDR clock by sending a NULL packet */
2758 if (dsi->vm_timings.ddr_clk_always_on && enable)
2759 dsi_vc_send_null(dssdev, channel);
2760 }
2761
2762 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2763 {
2764 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2765 u32 val;
2766 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2767 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2768 (val >> 0) & 0xff,
2769 (val >> 8) & 0xff,
2770 (val >> 16) & 0xff,
2771 (val >> 24) & 0xff);
2772 }
2773 }
2774
2775 static void dsi_show_rx_ack_with_err(u16 err)
2776 {
2777 DSSERR("\tACK with ERROR (%#x):\n", err);
2778 if (err & (1 << 0))
2779 DSSERR("\t\tSoT Error\n");
2780 if (err & (1 << 1))
2781 DSSERR("\t\tSoT Sync Error\n");
2782 if (err & (1 << 2))
2783 DSSERR("\t\tEoT Sync Error\n");
2784 if (err & (1 << 3))
2785 DSSERR("\t\tEscape Mode Entry Command Error\n");
2786 if (err & (1 << 4))
2787 DSSERR("\t\tLP Transmit Sync Error\n");
2788 if (err & (1 << 5))
2789 DSSERR("\t\tHS Receive Timeout Error\n");
2790 if (err & (1 << 6))
2791 DSSERR("\t\tFalse Control Error\n");
2792 if (err & (1 << 7))
2793 DSSERR("\t\t(reserved7)\n");
2794 if (err & (1 << 8))
2795 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2796 if (err & (1 << 9))
2797 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2798 if (err & (1 << 10))
2799 DSSERR("\t\tChecksum Error\n");
2800 if (err & (1 << 11))
2801 DSSERR("\t\tData type not recognized\n");
2802 if (err & (1 << 12))
2803 DSSERR("\t\tInvalid VC ID\n");
2804 if (err & (1 << 13))
2805 DSSERR("\t\tInvalid Transmission Length\n");
2806 if (err & (1 << 14))
2807 DSSERR("\t\t(reserved14)\n");
2808 if (err & (1 << 15))
2809 DSSERR("\t\tDSI Protocol Violation\n");
2810 }
2811
2812 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2813 int channel)
2814 {
2815 /* RX_FIFO_NOT_EMPTY */
2816 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2817 u32 val;
2818 u8 dt;
2819 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2820 DSSERR("\trawval %#08x\n", val);
2821 dt = FLD_GET(val, 5, 0);
2822 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2823 u16 err = FLD_GET(val, 23, 8);
2824 dsi_show_rx_ack_with_err(err);
2825 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2826 DSSERR("\tDCS short response, 1 byte: %#x\n",
2827 FLD_GET(val, 23, 8));
2828 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2829 DSSERR("\tDCS short response, 2 byte: %#x\n",
2830 FLD_GET(val, 23, 8));
2831 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2832 DSSERR("\tDCS long response, len %d\n",
2833 FLD_GET(val, 23, 8));
2834 dsi_vc_flush_long_data(dsidev, channel);
2835 } else {
2836 DSSERR("\tunknown datatype 0x%02x\n", dt);
2837 }
2838 }
2839 return 0;
2840 }
2841
2842 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2843 {
2844 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2845
2846 if (dsi->debug_write || dsi->debug_read)
2847 DSSDBG("dsi_vc_send_bta %d\n", channel);
2848
2849 WARN_ON(!dsi_bus_is_locked(dsidev));
2850
2851 /* RX_FIFO_NOT_EMPTY */
2852 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2853 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2854 dsi_vc_flush_receive_data(dsidev, channel);
2855 }
2856
2857 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2858
2859 /* flush posted write */
2860 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2861
2862 return 0;
2863 }
2864
2865 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2866 {
2867 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2868 DECLARE_COMPLETION_ONSTACK(completion);
2869 int r = 0;
2870 u32 err;
2871
2872 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2873 &completion, DSI_VC_IRQ_BTA);
2874 if (r)
2875 goto err0;
2876
2877 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2878 DSI_IRQ_ERROR_MASK);
2879 if (r)
2880 goto err1;
2881
2882 r = dsi_vc_send_bta(dsidev, channel);
2883 if (r)
2884 goto err2;
2885
2886 if (wait_for_completion_timeout(&completion,
2887 msecs_to_jiffies(500)) == 0) {
2888 DSSERR("Failed to receive BTA\n");
2889 r = -EIO;
2890 goto err2;
2891 }
2892
2893 err = dsi_get_errors(dsidev);
2894 if (err) {
2895 DSSERR("Error while sending BTA: %x\n", err);
2896 r = -EIO;
2897 goto err2;
2898 }
2899 err2:
2900 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2901 DSI_IRQ_ERROR_MASK);
2902 err1:
2903 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2904 &completion, DSI_VC_IRQ_BTA);
2905 err0:
2906 return r;
2907 }
2908
2909 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2910 int channel, u8 data_type, u16 len, u8 ecc)
2911 {
2912 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2913 u32 val;
2914 u8 data_id;
2915
2916 WARN_ON(!dsi_bus_is_locked(dsidev));
2917
2918 data_id = data_type | dsi->vc[channel].vc_id << 6;
2919
2920 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2921 FLD_VAL(ecc, 31, 24);
2922
2923 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2924 }
2925
2926 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2927 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2928 {
2929 u32 val;
2930
2931 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2932
2933 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2934 b1, b2, b3, b4, val); */
2935
2936 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2937 }
2938
2939 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2940 u8 data_type, u8 *data, u16 len, u8 ecc)
2941 {
2942 /*u32 val; */
2943 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2944 int i;
2945 u8 *p;
2946 int r = 0;
2947 u8 b1, b2, b3, b4;
2948
2949 if (dsi->debug_write)
2950 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2951
2952 /* len + header */
2953 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2954 DSSERR("unable to send long packet: packet too long.\n");
2955 return -EINVAL;
2956 }
2957
2958 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2959
2960 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2961
2962 p = data;
2963 for (i = 0; i < len >> 2; i++) {
2964 if (dsi->debug_write)
2965 DSSDBG("\tsending full packet %d\n", i);
2966
2967 b1 = *p++;
2968 b2 = *p++;
2969 b3 = *p++;
2970 b4 = *p++;
2971
2972 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2973 }
2974
2975 i = len % 4;
2976 if (i) {
2977 b1 = 0; b2 = 0; b3 = 0;
2978
2979 if (dsi->debug_write)
2980 DSSDBG("\tsending remainder bytes %d\n", i);
2981
2982 switch (i) {
2983 case 3:
2984 b1 = *p++;
2985 b2 = *p++;
2986 b3 = *p++;
2987 break;
2988 case 2:
2989 b1 = *p++;
2990 b2 = *p++;
2991 break;
2992 case 1:
2993 b1 = *p++;
2994 break;
2995 }
2996
2997 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2998 }
2999
3000 return r;
3001 }
3002
3003 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3004 u8 data_type, u16 data, u8 ecc)
3005 {
3006 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3007 u32 r;
3008 u8 data_id;
3009
3010 WARN_ON(!dsi_bus_is_locked(dsidev));
3011
3012 if (dsi->debug_write)
3013 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3014 channel,
3015 data_type, data & 0xff, (data >> 8) & 0xff);
3016
3017 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3018
3019 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3020 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3021 return -EINVAL;
3022 }
3023
3024 data_id = data_type | dsi->vc[channel].vc_id << 6;
3025
3026 r = (data_id << 0) | (data << 8) | (ecc << 24);
3027
3028 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3029
3030 return 0;
3031 }
3032
3033 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3034 {
3035 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3036
3037 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3038 0, 0);
3039 }
3040
3041 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3042 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3043 {
3044 int r;
3045
3046 if (len == 0) {
3047 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3048 r = dsi_vc_send_short(dsidev, channel,
3049 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3050 } else if (len == 1) {
3051 r = dsi_vc_send_short(dsidev, channel,
3052 type == DSS_DSI_CONTENT_GENERIC ?
3053 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3054 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3055 } else if (len == 2) {
3056 r = dsi_vc_send_short(dsidev, channel,
3057 type == DSS_DSI_CONTENT_GENERIC ?
3058 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3059 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3060 data[0] | (data[1] << 8), 0);
3061 } else {
3062 r = dsi_vc_send_long(dsidev, channel,
3063 type == DSS_DSI_CONTENT_GENERIC ?
3064 MIPI_DSI_GENERIC_LONG_WRITE :
3065 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3066 }
3067
3068 return r;
3069 }
3070
3071 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3072 u8 *data, int len)
3073 {
3074 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3075
3076 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3077 DSS_DSI_CONTENT_DCS);
3078 }
3079
3080 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3081 u8 *data, int len)
3082 {
3083 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3084
3085 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3086 DSS_DSI_CONTENT_GENERIC);
3087 }
3088
3089 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3090 u8 *data, int len, enum dss_dsi_content_type type)
3091 {
3092 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3093 int r;
3094
3095 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3096 if (r)
3097 goto err;
3098
3099 r = dsi_vc_send_bta_sync(dssdev, channel);
3100 if (r)
3101 goto err;
3102
3103 /* RX_FIFO_NOT_EMPTY */
3104 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3105 DSSERR("rx fifo not empty after write, dumping data:\n");
3106 dsi_vc_flush_receive_data(dsidev, channel);
3107 r = -EIO;
3108 goto err;
3109 }
3110
3111 return 0;
3112 err:
3113 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3114 channel, data[0], len);
3115 return r;
3116 }
3117
3118 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3119 int len)
3120 {
3121 return dsi_vc_write_common(dssdev, channel, data, len,
3122 DSS_DSI_CONTENT_DCS);
3123 }
3124
3125 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3126 int len)
3127 {
3128 return dsi_vc_write_common(dssdev, channel, data, len,
3129 DSS_DSI_CONTENT_GENERIC);
3130 }
3131
3132 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3133 int channel, u8 dcs_cmd)
3134 {
3135 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3136 int r;
3137
3138 if (dsi->debug_read)
3139 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3140 channel, dcs_cmd);
3141
3142 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3143 if (r) {
3144 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3145 " failed\n", channel, dcs_cmd);
3146 return r;
3147 }
3148
3149 return 0;
3150 }
3151
3152 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3153 int channel, u8 *reqdata, int reqlen)
3154 {
3155 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3156 u16 data;
3157 u8 data_type;
3158 int r;
3159
3160 if (dsi->debug_read)
3161 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3162 channel, reqlen);
3163
3164 if (reqlen == 0) {
3165 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3166 data = 0;
3167 } else if (reqlen == 1) {
3168 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3169 data = reqdata[0];
3170 } else if (reqlen == 2) {
3171 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3172 data = reqdata[0] | (reqdata[1] << 8);
3173 } else {
3174 BUG();
3175 return -EINVAL;
3176 }
3177
3178 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3179 if (r) {
3180 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3181 " failed\n", channel, reqlen);
3182 return r;
3183 }
3184
3185 return 0;
3186 }
3187
3188 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3189 u8 *buf, int buflen, enum dss_dsi_content_type type)
3190 {
3191 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3192 u32 val;
3193 u8 dt;
3194 int r;
3195
3196 /* RX_FIFO_NOT_EMPTY */
3197 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3198 DSSERR("RX fifo empty when trying to read.\n");
3199 r = -EIO;
3200 goto err;
3201 }
3202
3203 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3204 if (dsi->debug_read)
3205 DSSDBG("\theader: %08x\n", val);
3206 dt = FLD_GET(val, 5, 0);
3207 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3208 u16 err = FLD_GET(val, 23, 8);
3209 dsi_show_rx_ack_with_err(err);
3210 r = -EIO;
3211 goto err;
3212
3213 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3214 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3215 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3216 u8 data = FLD_GET(val, 15, 8);
3217 if (dsi->debug_read)
3218 DSSDBG("\t%s short response, 1 byte: %02x\n",
3219 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3220 "DCS", data);
3221
3222 if (buflen < 1) {
3223 r = -EIO;
3224 goto err;
3225 }
3226
3227 buf[0] = data;
3228
3229 return 1;
3230 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3231 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3232 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3233 u16 data = FLD_GET(val, 23, 8);
3234 if (dsi->debug_read)
3235 DSSDBG("\t%s short response, 2 byte: %04x\n",
3236 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3237 "DCS", data);
3238
3239 if (buflen < 2) {
3240 r = -EIO;
3241 goto err;
3242 }
3243
3244 buf[0] = data & 0xff;
3245 buf[1] = (data >> 8) & 0xff;
3246
3247 return 2;
3248 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3249 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3250 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3251 int w;
3252 int len = FLD_GET(val, 23, 8);
3253 if (dsi->debug_read)
3254 DSSDBG("\t%s long response, len %d\n",
3255 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3256 "DCS", len);
3257
3258 if (len > buflen) {
3259 r = -EIO;
3260 goto err;
3261 }
3262
3263 /* two byte checksum ends the packet, not included in len */
3264 for (w = 0; w < len + 2;) {
3265 int b;
3266 val = dsi_read_reg(dsidev,
3267 DSI_VC_SHORT_PACKET_HEADER(channel));
3268 if (dsi->debug_read)
3269 DSSDBG("\t\t%02x %02x %02x %02x\n",
3270 (val >> 0) & 0xff,
3271 (val >> 8) & 0xff,
3272 (val >> 16) & 0xff,
3273 (val >> 24) & 0xff);
3274
3275 for (b = 0; b < 4; ++b) {
3276 if (w < len)
3277 buf[w] = (val >> (b * 8)) & 0xff;
3278 /* we discard the 2 byte checksum */
3279 ++w;
3280 }
3281 }
3282
3283 return len;
3284 } else {
3285 DSSERR("\tunknown datatype 0x%02x\n", dt);
3286 r = -EIO;
3287 goto err;
3288 }
3289
3290 err:
3291 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3292 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3293
3294 return r;
3295 }
3296
3297 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3298 u8 *buf, int buflen)
3299 {
3300 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3301 int r;
3302
3303 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3304 if (r)
3305 goto err;
3306
3307 r = dsi_vc_send_bta_sync(dssdev, channel);
3308 if (r)
3309 goto err;
3310
3311 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3312 DSS_DSI_CONTENT_DCS);
3313 if (r < 0)
3314 goto err;
3315
3316 if (r != buflen) {
3317 r = -EIO;
3318 goto err;
3319 }
3320
3321 return 0;
3322 err:
3323 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3324 return r;
3325 }
3326
3327 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3328 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3329 {
3330 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3331 int r;
3332
3333 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3334 if (r)
3335 return r;
3336
3337 r = dsi_vc_send_bta_sync(dssdev, channel);
3338 if (r)
3339 return r;
3340
3341 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3342 DSS_DSI_CONTENT_GENERIC);
3343 if (r < 0)
3344 return r;
3345
3346 if (r != buflen) {
3347 r = -EIO;
3348 return r;
3349 }
3350
3351 return 0;
3352 }
3353
3354 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3355 u16 len)
3356 {
3357 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3358
3359 return dsi_vc_send_short(dsidev, channel,
3360 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3361 }
3362
3363 static int dsi_enter_ulps(struct platform_device *dsidev)
3364 {
3365 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3366 DECLARE_COMPLETION_ONSTACK(completion);
3367 int r, i;
3368 unsigned mask;
3369
3370 DSSDBG("Entering ULPS");
3371
3372 WARN_ON(!dsi_bus_is_locked(dsidev));
3373
3374 WARN_ON(dsi->ulps_enabled);
3375
3376 if (dsi->ulps_enabled)
3377 return 0;
3378
3379 /* DDR_CLK_ALWAYS_ON */
3380 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3381 dsi_if_enable(dsidev, 0);
3382 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3383 dsi_if_enable(dsidev, 1);
3384 }
3385
3386 dsi_sync_vc(dsidev, 0);
3387 dsi_sync_vc(dsidev, 1);
3388 dsi_sync_vc(dsidev, 2);
3389 dsi_sync_vc(dsidev, 3);
3390
3391 dsi_force_tx_stop_mode_io(dsidev);
3392
3393 dsi_vc_enable(dsidev, 0, false);
3394 dsi_vc_enable(dsidev, 1, false);
3395 dsi_vc_enable(dsidev, 2, false);
3396 dsi_vc_enable(dsidev, 3, false);
3397
3398 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3399 DSSERR("HS busy when enabling ULPS\n");
3400 return -EIO;
3401 }
3402
3403 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3404 DSSERR("LP busy when enabling ULPS\n");
3405 return -EIO;
3406 }
3407
3408 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3409 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3410 if (r)
3411 return r;
3412
3413 mask = 0;
3414
3415 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3416 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3417 continue;
3418 mask |= 1 << i;
3419 }
3420 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3421 /* LANEx_ULPS_SIG2 */
3422 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3423
3424 /* flush posted write and wait for SCP interface to finish the write */
3425 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3426
3427 if (wait_for_completion_timeout(&completion,
3428 msecs_to_jiffies(1000)) == 0) {
3429 DSSERR("ULPS enable timeout\n");
3430 r = -EIO;
3431 goto err;
3432 }
3433
3434 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3435 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3436
3437 /* Reset LANEx_ULPS_SIG2 */
3438 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3439
3440 /* flush posted write and wait for SCP interface to finish the write */
3441 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3442
3443 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3444
3445 dsi_if_enable(dsidev, false);
3446
3447 dsi->ulps_enabled = true;
3448
3449 return 0;
3450
3451 err:
3452 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3453 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3454 return r;
3455 }
3456
3457 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3458 unsigned ticks, bool x4, bool x16)
3459 {
3460 unsigned long fck;
3461 unsigned long total_ticks;
3462 u32 r;
3463
3464 BUG_ON(ticks > 0x1fff);
3465
3466 /* ticks in DSI_FCK */
3467 fck = dsi_fclk_rate(dsidev);
3468
3469 r = dsi_read_reg(dsidev, DSI_TIMING2);
3470 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3471 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3472 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3473 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3474 dsi_write_reg(dsidev, DSI_TIMING2, r);
3475
3476 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3477
3478 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3479 total_ticks,
3480 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3481 (total_ticks * 1000) / (fck / 1000 / 1000));
3482 }
3483
3484 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3485 bool x8, bool x16)
3486 {
3487 unsigned long fck;
3488 unsigned long total_ticks;
3489 u32 r;
3490
3491 BUG_ON(ticks > 0x1fff);
3492
3493 /* ticks in DSI_FCK */
3494 fck = dsi_fclk_rate(dsidev);
3495
3496 r = dsi_read_reg(dsidev, DSI_TIMING1);
3497 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3498 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3499 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3500 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3501 dsi_write_reg(dsidev, DSI_TIMING1, r);
3502
3503 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3504
3505 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3506 total_ticks,
3507 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3508 (total_ticks * 1000) / (fck / 1000 / 1000));
3509 }
3510
3511 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3512 unsigned ticks, bool x4, bool x16)
3513 {
3514 unsigned long fck;
3515 unsigned long total_ticks;
3516 u32 r;
3517
3518 BUG_ON(ticks > 0x1fff);
3519
3520 /* ticks in DSI_FCK */
3521 fck = dsi_fclk_rate(dsidev);
3522
3523 r = dsi_read_reg(dsidev, DSI_TIMING1);
3524 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3525 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3526 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3527 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3528 dsi_write_reg(dsidev, DSI_TIMING1, r);
3529
3530 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3531
3532 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3533 total_ticks,
3534 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3535 (total_ticks * 1000) / (fck / 1000 / 1000));
3536 }
3537
3538 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3539 unsigned ticks, bool x4, bool x16)
3540 {
3541 unsigned long fck;
3542 unsigned long total_ticks;
3543 u32 r;
3544
3545 BUG_ON(ticks > 0x1fff);
3546
3547 /* ticks in TxByteClkHS */
3548 fck = dsi_get_txbyteclkhs(dsidev);
3549
3550 r = dsi_read_reg(dsidev, DSI_TIMING2);
3551 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3552 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3553 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3554 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3555 dsi_write_reg(dsidev, DSI_TIMING2, r);
3556
3557 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3558
3559 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3560 total_ticks,
3561 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3562 (total_ticks * 1000) / (fck / 1000 / 1000));
3563 }
3564
3565 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3566 {
3567 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3568 int num_line_buffers;
3569
3570 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3571 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3572 struct omap_video_timings *timings = &dsi->timings;
3573 /*
3574 * Don't use line buffers if width is greater than the video
3575 * port's line buffer size
3576 */
3577 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3578 num_line_buffers = 0;
3579 else
3580 num_line_buffers = 2;
3581 } else {
3582 /* Use maximum number of line buffers in command mode */
3583 num_line_buffers = 2;
3584 }
3585
3586 /* LINE_BUFFER */
3587 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3588 }
3589
3590 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3591 {
3592 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3593 bool sync_end;
3594 u32 r;
3595
3596 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3597 sync_end = true;
3598 else
3599 sync_end = false;
3600
3601 r = dsi_read_reg(dsidev, DSI_CTRL);
3602 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3603 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3604 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3605 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3606 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3607 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3608 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3609 dsi_write_reg(dsidev, DSI_CTRL, r);
3610 }
3611
3612 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3613 {
3614 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3615 int blanking_mode = dsi->vm_timings.blanking_mode;
3616 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3617 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3618 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3619 u32 r;
3620
3621 /*
3622 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3623 * 1 = Long blanking packets are sent in corresponding blanking periods
3624 */
3625 r = dsi_read_reg(dsidev, DSI_CTRL);
3626 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3627 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3628 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3629 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3630 dsi_write_reg(dsidev, DSI_CTRL, r);
3631 }
3632
3633 /*
3634 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3635 * results in maximum transition time for data and clock lanes to enter and
3636 * exit HS mode. Hence, this is the scenario where the least amount of command
3637 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3638 * clock cycles that can be used to interleave command mode data in HS so that
3639 * all scenarios are satisfied.
3640 */
3641 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3642 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3643 {
3644 int transition;
3645
3646 /*
3647 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3648 * time of data lanes only, if it isn't set, we need to consider HS
3649 * transition time of both data and clock lanes. HS transition time
3650 * of Scenario 3 is considered.
3651 */
3652 if (ddr_alwon) {
3653 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3654 } else {
3655 int trans1, trans2;
3656 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3657 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3658 enter_hs + 1;
3659 transition = max(trans1, trans2);
3660 }
3661
3662 return blank > transition ? blank - transition : 0;
3663 }
3664
3665 /*
3666 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3667 * results in maximum transition time for data lanes to enter and exit LP mode.
3668 * Hence, this is the scenario where the least amount of command mode data can
3669 * be interleaved. We program the minimum amount of bytes that can be
3670 * interleaved in LP so that all scenarios are satisfied.
3671 */
3672 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3673 int lp_clk_div, int tdsi_fclk)
3674 {
3675 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3676 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3677 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3678 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3679 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3680
3681 /* maximum LP transition time according to Scenario 1 */
3682 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3683
3684 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3685 tlp_avail = thsbyte_clk * (blank - trans_lp);
3686
3687 ttxclkesc = tdsi_fclk * lp_clk_div;
3688
3689 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3690 26) / 16;
3691
3692 return max(lp_inter, 0);
3693 }
3694
3695 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3696 {
3697 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3698 int blanking_mode;
3699 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3700 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3701 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3702 int tclk_trail, ths_exit, exiths_clk;
3703 bool ddr_alwon;
3704 struct omap_video_timings *timings = &dsi->timings;
3705 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3706 int ndl = dsi->num_lanes_used - 1;
3707 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3708 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3709 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3710 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3711 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3712 u32 r;
3713
3714 r = dsi_read_reg(dsidev, DSI_CTRL);
3715 blanking_mode = FLD_GET(r, 20, 20);
3716 hfp_blanking_mode = FLD_GET(r, 21, 21);
3717 hbp_blanking_mode = FLD_GET(r, 22, 22);
3718 hsa_blanking_mode = FLD_GET(r, 23, 23);
3719
3720 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3721 hbp = FLD_GET(r, 11, 0);
3722 hfp = FLD_GET(r, 23, 12);
3723 hsa = FLD_GET(r, 31, 24);
3724
3725 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3726 ddr_clk_post = FLD_GET(r, 7, 0);
3727 ddr_clk_pre = FLD_GET(r, 15, 8);
3728
3729 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3730 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3731 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3732
3733 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3734 lp_clk_div = FLD_GET(r, 12, 0);
3735 ddr_alwon = FLD_GET(r, 13, 13);
3736
3737 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3738 ths_exit = FLD_GET(r, 7, 0);
3739
3740 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3741 tclk_trail = FLD_GET(r, 15, 8);
3742
3743 exiths_clk = ths_exit + tclk_trail;
3744
3745 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3746 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3747
3748 if (!hsa_blanking_mode) {
3749 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3750 enter_hs_mode_lat, exit_hs_mode_lat,
3751 exiths_clk, ddr_clk_pre, ddr_clk_post);
3752 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3753 enter_hs_mode_lat, exit_hs_mode_lat,
3754 lp_clk_div, dsi_fclk_hsdiv);
3755 }
3756
3757 if (!hfp_blanking_mode) {
3758 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3759 enter_hs_mode_lat, exit_hs_mode_lat,
3760 exiths_clk, ddr_clk_pre, ddr_clk_post);
3761 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3762 enter_hs_mode_lat, exit_hs_mode_lat,
3763 lp_clk_div, dsi_fclk_hsdiv);
3764 }
3765
3766 if (!hbp_blanking_mode) {
3767 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3768 enter_hs_mode_lat, exit_hs_mode_lat,
3769 exiths_clk, ddr_clk_pre, ddr_clk_post);
3770
3771 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3772 enter_hs_mode_lat, exit_hs_mode_lat,
3773 lp_clk_div, dsi_fclk_hsdiv);
3774 }
3775
3776 if (!blanking_mode) {
3777 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3778 enter_hs_mode_lat, exit_hs_mode_lat,
3779 exiths_clk, ddr_clk_pre, ddr_clk_post);
3780
3781 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3782 enter_hs_mode_lat, exit_hs_mode_lat,
3783 lp_clk_div, dsi_fclk_hsdiv);
3784 }
3785
3786 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3787 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3788 bl_interleave_hs);
3789
3790 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3791 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3792 bl_interleave_lp);
3793
3794 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3795 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3796 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3797 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3798 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3799
3800 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3801 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3802 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3803 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3804 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3805
3806 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3807 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3808 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3809 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3810 }
3811
3812 static int dsi_proto_config(struct platform_device *dsidev)
3813 {
3814 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3815 u32 r;
3816 int buswidth = 0;
3817
3818 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3819 DSI_FIFO_SIZE_32,
3820 DSI_FIFO_SIZE_32,
3821 DSI_FIFO_SIZE_32);
3822
3823 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3824 DSI_FIFO_SIZE_32,
3825 DSI_FIFO_SIZE_32,
3826 DSI_FIFO_SIZE_32);
3827
3828 /* XXX what values for the timeouts? */
3829 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3830 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3831 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3832 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3833
3834 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3835 case 16:
3836 buswidth = 0;
3837 break;
3838 case 18:
3839 buswidth = 1;
3840 break;
3841 case 24:
3842 buswidth = 2;
3843 break;
3844 default:
3845 BUG();
3846 return -EINVAL;
3847 }
3848
3849 r = dsi_read_reg(dsidev, DSI_CTRL);
3850 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3851 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3852 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3853 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3854 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3855 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3856 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3857 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3858 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3859 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3860 /* DCS_CMD_CODE, 1=start, 0=continue */
3861 r = FLD_MOD(r, 0, 25, 25);
3862 }
3863
3864 dsi_write_reg(dsidev, DSI_CTRL, r);
3865
3866 dsi_config_vp_num_line_buffers(dsidev);
3867
3868 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3869 dsi_config_vp_sync_events(dsidev);
3870 dsi_config_blanking_modes(dsidev);
3871 dsi_config_cmd_mode_interleaving(dsidev);
3872 }
3873
3874 dsi_vc_initial_config(dsidev, 0);
3875 dsi_vc_initial_config(dsidev, 1);
3876 dsi_vc_initial_config(dsidev, 2);
3877 dsi_vc_initial_config(dsidev, 3);
3878
3879 return 0;
3880 }
3881
3882 static void dsi_proto_timings(struct platform_device *dsidev)
3883 {
3884 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3885 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3886 unsigned tclk_pre, tclk_post;
3887 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3888 unsigned ths_trail, ths_exit;
3889 unsigned ddr_clk_pre, ddr_clk_post;
3890 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3891 unsigned ths_eot;
3892 int ndl = dsi->num_lanes_used - 1;
3893 u32 r;
3894
3895 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3896 ths_prepare = FLD_GET(r, 31, 24);
3897 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3898 ths_zero = ths_prepare_ths_zero - ths_prepare;
3899 ths_trail = FLD_GET(r, 15, 8);
3900 ths_exit = FLD_GET(r, 7, 0);
3901
3902 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3903 tlpx = FLD_GET(r, 20, 16) * 2;
3904 tclk_trail = FLD_GET(r, 15, 8);
3905 tclk_zero = FLD_GET(r, 7, 0);
3906
3907 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3908 tclk_prepare = FLD_GET(r, 7, 0);
3909
3910 /* min 8*UI */
3911 tclk_pre = 20;
3912 /* min 60ns + 52*UI */
3913 tclk_post = ns2ddr(dsidev, 60) + 26;
3914
3915 ths_eot = DIV_ROUND_UP(4, ndl);
3916
3917 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3918 4);
3919 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3920
3921 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3922 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3923
3924 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3925 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3926 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3927 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3928
3929 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3930 ddr_clk_pre,
3931 ddr_clk_post);
3932
3933 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3934 DIV_ROUND_UP(ths_prepare, 4) +
3935 DIV_ROUND_UP(ths_zero + 3, 4);
3936
3937 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3938
3939 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3940 FLD_VAL(exit_hs_mode_lat, 15, 0);
3941 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3942
3943 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3944 enter_hs_mode_lat, exit_hs_mode_lat);
3945
3946 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3947 /* TODO: Implement a video mode check_timings function */
3948 int hsa = dsi->vm_timings.hsa;
3949 int hfp = dsi->vm_timings.hfp;
3950 int hbp = dsi->vm_timings.hbp;
3951 int vsa = dsi->vm_timings.vsa;
3952 int vfp = dsi->vm_timings.vfp;
3953 int vbp = dsi->vm_timings.vbp;
3954 int window_sync = dsi->vm_timings.window_sync;
3955 bool hsync_end;
3956 struct omap_video_timings *timings = &dsi->timings;
3957 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3958 int tl, t_he, width_bytes;
3959
3960 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3961 t_he = hsync_end ?
3962 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3963
3964 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3965
3966 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3967 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3968 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3969
3970 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3971 hfp, hsync_end ? hsa : 0, tl);
3972 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3973 vsa, timings->y_res);
3974
3975 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3976 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3977 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3978 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3979 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3980
3981 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3982 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3983 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3984 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3985 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3986 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3987
3988 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3989 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3990 r = FLD_MOD(r, tl, 31, 16); /* TL */
3991 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3992 }
3993 }
3994
3995 static int dsi_configure_pins(struct omap_dss_device *dssdev,
3996 const struct omap_dsi_pin_config *pin_cfg)
3997 {
3998 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3999 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4000 int num_pins;
4001 const int *pins;
4002 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4003 int num_lanes;
4004 int i;
4005
4006 static const enum dsi_lane_function functions[] = {
4007 DSI_LANE_CLK,
4008 DSI_LANE_DATA1,
4009 DSI_LANE_DATA2,
4010 DSI_LANE_DATA3,
4011 DSI_LANE_DATA4,
4012 };
4013
4014 num_pins = pin_cfg->num_pins;
4015 pins = pin_cfg->pins;
4016
4017 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4018 || num_pins % 2 != 0)
4019 return -EINVAL;
4020
4021 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4022 lanes[i].function = DSI_LANE_UNUSED;
4023
4024 num_lanes = 0;
4025
4026 for (i = 0; i < num_pins; i += 2) {
4027 u8 lane, pol;
4028 int dx, dy;
4029
4030 dx = pins[i];
4031 dy = pins[i + 1];
4032
4033 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4034 return -EINVAL;
4035
4036 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4037 return -EINVAL;
4038
4039 if (dx & 1) {
4040 if (dy != dx - 1)
4041 return -EINVAL;
4042 pol = 1;
4043 } else {
4044 if (dy != dx + 1)
4045 return -EINVAL;
4046 pol = 0;
4047 }
4048
4049 lane = dx / 2;
4050
4051 lanes[lane].function = functions[i / 2];
4052 lanes[lane].polarity = pol;
4053 num_lanes++;
4054 }
4055
4056 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4057 dsi->num_lanes_used = num_lanes;
4058
4059 return 0;
4060 }
4061
4062 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4063 {
4064 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4066 struct omap_overlay_manager *mgr = dsi->output.manager;
4067 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4068 struct omap_dss_device *out = &dsi->output;
4069 u8 data_type;
4070 u16 word_count;
4071 int r;
4072
4073 if (out == NULL || out->manager == NULL) {
4074 DSSERR("failed to enable display: no output/manager\n");
4075 return -ENODEV;
4076 }
4077
4078 r = dsi_display_init_dispc(dsidev, mgr);
4079 if (r)
4080 goto err_init_dispc;
4081
4082 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4083 switch (dsi->pix_fmt) {
4084 case OMAP_DSS_DSI_FMT_RGB888:
4085 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4086 break;
4087 case OMAP_DSS_DSI_FMT_RGB666:
4088 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4089 break;
4090 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4091 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4092 break;
4093 case OMAP_DSS_DSI_FMT_RGB565:
4094 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4095 break;
4096 default:
4097 r = -EINVAL;
4098 goto err_pix_fmt;
4099 }
4100
4101 dsi_if_enable(dsidev, false);
4102 dsi_vc_enable(dsidev, channel, false);
4103
4104 /* MODE, 1 = video mode */
4105 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4106
4107 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4108
4109 dsi_vc_write_long_header(dsidev, channel, data_type,
4110 word_count, 0);
4111
4112 dsi_vc_enable(dsidev, channel, true);
4113 dsi_if_enable(dsidev, true);
4114 }
4115
4116 r = dss_mgr_enable(mgr);
4117 if (r)
4118 goto err_mgr_enable;
4119
4120 return 0;
4121
4122 err_mgr_enable:
4123 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4124 dsi_if_enable(dsidev, false);
4125 dsi_vc_enable(dsidev, channel, false);
4126 }
4127 err_pix_fmt:
4128 dsi_display_uninit_dispc(dsidev, mgr);
4129 err_init_dispc:
4130 return r;
4131 }
4132
4133 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4134 {
4135 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4136 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4137 struct omap_overlay_manager *mgr = dsi->output.manager;
4138
4139 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4140 dsi_if_enable(dsidev, false);
4141 dsi_vc_enable(dsidev, channel, false);
4142
4143 /* MODE, 0 = command mode */
4144 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4145
4146 dsi_vc_enable(dsidev, channel, true);
4147 dsi_if_enable(dsidev, true);
4148 }
4149
4150 dss_mgr_disable(mgr);
4151
4152 dsi_display_uninit_dispc(dsidev, mgr);
4153 }
4154
4155 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4156 {
4157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4158 struct omap_overlay_manager *mgr = dsi->output.manager;
4159 unsigned bytespp;
4160 unsigned bytespl;
4161 unsigned bytespf;
4162 unsigned total_len;
4163 unsigned packet_payload;
4164 unsigned packet_len;
4165 u32 l;
4166 int r;
4167 const unsigned channel = dsi->update_channel;
4168 const unsigned line_buf_size = dsi->line_buffer_size;
4169 u16 w = dsi->timings.x_res;
4170 u16 h = dsi->timings.y_res;
4171
4172 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4173
4174 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4175
4176 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4177 bytespl = w * bytespp;
4178 bytespf = bytespl * h;
4179
4180 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4181 * number of lines in a packet. See errata about VP_CLK_RATIO */
4182
4183 if (bytespf < line_buf_size)
4184 packet_payload = bytespf;
4185 else
4186 packet_payload = (line_buf_size) / bytespl * bytespl;
4187
4188 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4189 total_len = (bytespf / packet_payload) * packet_len;
4190
4191 if (bytespf % packet_payload)
4192 total_len += (bytespf % packet_payload) + 1;
4193
4194 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4195 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4196
4197 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4198 packet_len, 0);
4199
4200 if (dsi->te_enabled)
4201 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4202 else
4203 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4204 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4205
4206 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4207 * because DSS interrupts are not capable of waking up the CPU and the
4208 * framedone interrupt could be delayed for quite a long time. I think
4209 * the same goes for any DSS interrupts, but for some reason I have not
4210 * seen the problem anywhere else than here.
4211 */
4212 dispc_disable_sidle();
4213
4214 dsi_perf_mark_start(dsidev);
4215
4216 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4217 msecs_to_jiffies(250));
4218 BUG_ON(r == 0);
4219
4220 dss_mgr_set_timings(mgr, &dsi->timings);
4221
4222 dss_mgr_start_update(mgr);
4223
4224 if (dsi->te_enabled) {
4225 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4226 * for TE is longer than the timer allows */
4227 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4228
4229 dsi_vc_send_bta(dsidev, channel);
4230
4231 #ifdef DSI_CATCH_MISSING_TE
4232 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4233 #endif
4234 }
4235 }
4236
4237 #ifdef DSI_CATCH_MISSING_TE
4238 static void dsi_te_timeout(unsigned long arg)
4239 {
4240 DSSERR("TE not received for 250ms!\n");
4241 }
4242 #endif
4243
4244 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4245 {
4246 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4247
4248 /* SIDLEMODE back to smart-idle */
4249 dispc_enable_sidle();
4250
4251 if (dsi->te_enabled) {
4252 /* enable LP_RX_TO again after the TE */
4253 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4254 }
4255
4256 dsi->framedone_callback(error, dsi->framedone_data);
4257
4258 if (!error)
4259 dsi_perf_show(dsidev, "DISPC");
4260 }
4261
4262 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4263 {
4264 struct dsi_data *dsi = container_of(work, struct dsi_data,
4265 framedone_timeout_work.work);
4266 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4267 * 250ms which would conflict with this timeout work. What should be
4268 * done is first cancel the transfer on the HW, and then cancel the
4269 * possibly scheduled framedone work. However, cancelling the transfer
4270 * on the HW is buggy, and would probably require resetting the whole
4271 * DSI */
4272
4273 DSSERR("Framedone not received for 250ms!\n");
4274
4275 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4276 }
4277
4278 static void dsi_framedone_irq_callback(void *data)
4279 {
4280 struct platform_device *dsidev = (struct platform_device *) data;
4281 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4282
4283 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4284 * turns itself off. However, DSI still has the pixels in its buffers,
4285 * and is sending the data.
4286 */
4287
4288 cancel_delayed_work(&dsi->framedone_timeout_work);
4289
4290 dsi_handle_framedone(dsidev, 0);
4291 }
4292
4293 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4294 void (*callback)(int, void *), void *data)
4295 {
4296 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4298 u16 dw, dh;
4299
4300 dsi_perf_mark_setup(dsidev);
4301
4302 dsi->update_channel = channel;
4303
4304 dsi->framedone_callback = callback;
4305 dsi->framedone_data = data;
4306
4307 dw = dsi->timings.x_res;
4308 dh = dsi->timings.y_res;
4309
4310 #ifdef DSI_PERF_MEASURE
4311 dsi->update_bytes = dw * dh *
4312 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4313 #endif
4314 dsi_update_screen_dispc(dsidev);
4315
4316 return 0;
4317 }
4318
4319 /* Display funcs */
4320
4321 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4322 {
4323 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4324 struct dispc_clock_info dispc_cinfo;
4325 int r;
4326 unsigned long fck;
4327
4328 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4329
4330 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4331 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4332
4333 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4334 if (r) {
4335 DSSERR("Failed to calc dispc clocks\n");
4336 return r;
4337 }
4338
4339 dsi->mgr_config.clock_info = dispc_cinfo;
4340
4341 return 0;
4342 }
4343
4344 static int dsi_display_init_dispc(struct platform_device *dsidev,
4345 struct omap_overlay_manager *mgr)
4346 {
4347 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4348 int r;
4349
4350 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4351 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4352 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4353
4354 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4355 r = dss_mgr_register_framedone_handler(mgr,
4356 dsi_framedone_irq_callback, dsidev);
4357 if (r) {
4358 DSSERR("can't register FRAMEDONE handler\n");
4359 goto err;
4360 }
4361
4362 dsi->mgr_config.stallmode = true;
4363 dsi->mgr_config.fifohandcheck = true;
4364 } else {
4365 dsi->mgr_config.stallmode = false;
4366 dsi->mgr_config.fifohandcheck = false;
4367 }
4368
4369 /*
4370 * override interlace, logic level and edge related parameters in
4371 * omap_video_timings with default values
4372 */
4373 dsi->timings.interlace = false;
4374 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4375 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4376 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4377 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4378 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4379
4380 dss_mgr_set_timings(mgr, &dsi->timings);
4381
4382 r = dsi_configure_dispc_clocks(dsidev);
4383 if (r)
4384 goto err1;
4385
4386 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4387 dsi->mgr_config.video_port_width =
4388 dsi_get_pixel_size(dsi->pix_fmt);
4389 dsi->mgr_config.lcden_sig_polarity = 0;
4390
4391 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4392
4393 return 0;
4394 err1:
4395 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4396 dss_mgr_unregister_framedone_handler(mgr,
4397 dsi_framedone_irq_callback, dsidev);
4398 err:
4399 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4400 return r;
4401 }
4402
4403 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4404 struct omap_overlay_manager *mgr)
4405 {
4406 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4407
4408 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4409 dss_mgr_unregister_framedone_handler(mgr,
4410 dsi_framedone_irq_callback, dsidev);
4411
4412 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4413 }
4414
4415 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4416 {
4417 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4418 struct dsi_clock_info cinfo;
4419 int r;
4420
4421 cinfo = dsi->user_dsi_cinfo;
4422
4423 r = dsi_calc_clock_rates(dsidev, &cinfo);
4424 if (r) {
4425 DSSERR("Failed to calc dsi clocks\n");
4426 return r;
4427 }
4428
4429 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4430 if (r) {
4431 DSSERR("Failed to set dsi clocks\n");
4432 return r;
4433 }
4434
4435 return 0;
4436 }
4437
4438 static int dsi_display_init_dsi(struct platform_device *dsidev)
4439 {
4440 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4441 int r;
4442
4443 r = dsi_pll_init(dsidev, true, true);
4444 if (r)
4445 goto err0;
4446
4447 r = dsi_configure_dsi_clocks(dsidev);
4448 if (r)
4449 goto err1;
4450
4451 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4452 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4453 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4454
4455 DSSDBG("PLL OK\n");
4456
4457 r = dsi_cio_init(dsidev);
4458 if (r)
4459 goto err2;
4460
4461 _dsi_print_reset_status(dsidev);
4462
4463 dsi_proto_timings(dsidev);
4464 dsi_set_lp_clk_divisor(dsidev);
4465
4466 if (1)
4467 _dsi_print_reset_status(dsidev);
4468
4469 r = dsi_proto_config(dsidev);
4470 if (r)
4471 goto err3;
4472
4473 /* enable interface */
4474 dsi_vc_enable(dsidev, 0, 1);
4475 dsi_vc_enable(dsidev, 1, 1);
4476 dsi_vc_enable(dsidev, 2, 1);
4477 dsi_vc_enable(dsidev, 3, 1);
4478 dsi_if_enable(dsidev, 1);
4479 dsi_force_tx_stop_mode_io(dsidev);
4480
4481 return 0;
4482 err3:
4483 dsi_cio_uninit(dsidev);
4484 err2:
4485 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4486 err1:
4487 dsi_pll_uninit(dsidev, true);
4488 err0:
4489 return r;
4490 }
4491
4492 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4493 bool disconnect_lanes, bool enter_ulps)
4494 {
4495 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4496
4497 if (enter_ulps && !dsi->ulps_enabled)
4498 dsi_enter_ulps(dsidev);
4499
4500 /* disable interface */
4501 dsi_if_enable(dsidev, 0);
4502 dsi_vc_enable(dsidev, 0, 0);
4503 dsi_vc_enable(dsidev, 1, 0);
4504 dsi_vc_enable(dsidev, 2, 0);
4505 dsi_vc_enable(dsidev, 3, 0);
4506
4507 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4508 dsi_cio_uninit(dsidev);
4509 dsi_pll_uninit(dsidev, disconnect_lanes);
4510 }
4511
4512 static int dsi_display_enable(struct omap_dss_device *dssdev)
4513 {
4514 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4515 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4516 int r = 0;
4517
4518 DSSDBG("dsi_display_enable\n");
4519
4520 WARN_ON(!dsi_bus_is_locked(dsidev));
4521
4522 mutex_lock(&dsi->lock);
4523
4524 r = dsi_runtime_get(dsidev);
4525 if (r)
4526 goto err_get_dsi;
4527
4528 dsi_enable_pll_clock(dsidev, 1);
4529
4530 _dsi_initialize_irq(dsidev);
4531
4532 r = dsi_display_init_dsi(dsidev);
4533 if (r)
4534 goto err_init_dsi;
4535
4536 mutex_unlock(&dsi->lock);
4537
4538 return 0;
4539
4540 err_init_dsi:
4541 dsi_enable_pll_clock(dsidev, 0);
4542 dsi_runtime_put(dsidev);
4543 err_get_dsi:
4544 mutex_unlock(&dsi->lock);
4545 DSSDBG("dsi_display_enable FAILED\n");
4546 return r;
4547 }
4548
4549 static void dsi_display_disable(struct omap_dss_device *dssdev,
4550 bool disconnect_lanes, bool enter_ulps)
4551 {
4552 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4553 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4554
4555 DSSDBG("dsi_display_disable\n");
4556
4557 WARN_ON(!dsi_bus_is_locked(dsidev));
4558
4559 mutex_lock(&dsi->lock);
4560
4561 dsi_sync_vc(dsidev, 0);
4562 dsi_sync_vc(dsidev, 1);
4563 dsi_sync_vc(dsidev, 2);
4564 dsi_sync_vc(dsidev, 3);
4565
4566 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4567
4568 dsi_runtime_put(dsidev);
4569 dsi_enable_pll_clock(dsidev, 0);
4570
4571 mutex_unlock(&dsi->lock);
4572 }
4573
4574 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4575 {
4576 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4577 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4578
4579 dsi->te_enabled = enable;
4580 return 0;
4581 }
4582
4583 #ifdef PRINT_VERBOSE_VM_TIMINGS
4584 static void print_dsi_vm(const char *str,
4585 const struct omap_dss_dsi_videomode_timings *t)
4586 {
4587 unsigned long byteclk = t->hsclk / 4;
4588 int bl, wc, pps, tot;
4589
4590 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4591 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4592 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4593 tot = bl + pps;
4594
4595 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4596
4597 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4598 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4599 str,
4600 byteclk,
4601 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4602 bl, pps, tot,
4603 TO_DSI_T(t->hss),
4604 TO_DSI_T(t->hsa),
4605 TO_DSI_T(t->hse),
4606 TO_DSI_T(t->hbp),
4607 TO_DSI_T(pps),
4608 TO_DSI_T(t->hfp),
4609
4610 TO_DSI_T(bl),
4611 TO_DSI_T(pps),
4612
4613 TO_DSI_T(tot));
4614 #undef TO_DSI_T
4615 }
4616
4617 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4618 {
4619 unsigned long pck = t->pixel_clock * 1000;
4620 int hact, bl, tot;
4621
4622 hact = t->x_res;
4623 bl = t->hsw + t->hbp + t->hfp;
4624 tot = hact + bl;
4625
4626 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4627
4628 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4629 "%u/%u/%u/%u = %u + %u = %u\n",
4630 str,
4631 pck,
4632 t->hsw, t->hbp, hact, t->hfp,
4633 bl, hact, tot,
4634 TO_DISPC_T(t->hsw),
4635 TO_DISPC_T(t->hbp),
4636 TO_DISPC_T(hact),
4637 TO_DISPC_T(t->hfp),
4638 TO_DISPC_T(bl),
4639 TO_DISPC_T(hact),
4640 TO_DISPC_T(tot));
4641 #undef TO_DISPC_T
4642 }
4643
4644 /* note: this is not quite accurate */
4645 static void print_dsi_dispc_vm(const char *str,
4646 const struct omap_dss_dsi_videomode_timings *t)
4647 {
4648 struct omap_video_timings vm = { 0 };
4649 unsigned long byteclk = t->hsclk / 4;
4650 unsigned long pck;
4651 u64 dsi_tput;
4652 int dsi_hact, dsi_htot;
4653
4654 dsi_tput = (u64)byteclk * t->ndl * 8;
4655 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4656 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4657 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4658
4659 vm.pixel_clock = pck / 1000;
4660 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4661 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4662 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4663 vm.x_res = t->hact;
4664
4665 print_dispc_vm(str, &vm);
4666 }
4667 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4668
4669 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4670 unsigned long pck, void *data)
4671 {
4672 struct dsi_clk_calc_ctx *ctx = data;
4673 struct omap_video_timings *t = &ctx->dispc_vm;
4674
4675 ctx->dispc_cinfo.lck_div = lckd;
4676 ctx->dispc_cinfo.pck_div = pckd;
4677 ctx->dispc_cinfo.lck = lck;
4678 ctx->dispc_cinfo.pck = pck;
4679
4680 *t = *ctx->config->timings;
4681 t->pixel_clock = pck / 1000;
4682 t->x_res = ctx->config->timings->x_res;
4683 t->y_res = ctx->config->timings->y_res;
4684 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4685 t->vfp = t->vbp = 0;
4686
4687 return true;
4688 }
4689
4690 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4691 void *data)
4692 {
4693 struct dsi_clk_calc_ctx *ctx = data;
4694
4695 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4696 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4697
4698 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4699 dsi_cm_calc_dispc_cb, ctx);
4700 }
4701
4702 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4703 unsigned long pll, void *data)
4704 {
4705 struct dsi_clk_calc_ctx *ctx = data;
4706
4707 ctx->dsi_cinfo.regn = regn;
4708 ctx->dsi_cinfo.regm = regm;
4709 ctx->dsi_cinfo.fint = fint;
4710 ctx->dsi_cinfo.clkin4ddr = pll;
4711
4712 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4713 dsi_cm_calc_hsdiv_cb, ctx);
4714 }
4715
4716 static bool dsi_cm_calc(struct dsi_data *dsi,
4717 const struct omap_dss_dsi_config *cfg,
4718 struct dsi_clk_calc_ctx *ctx)
4719 {
4720 unsigned long clkin;
4721 int bitspp, ndl;
4722 unsigned long pll_min, pll_max;
4723 unsigned long pck, txbyteclk;
4724
4725 clkin = clk_get_rate(dsi->sys_clk);
4726 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4727 ndl = dsi->num_lanes_used - 1;
4728
4729 /*
4730 * Here we should calculate minimum txbyteclk to be able to send the
4731 * frame in time, and also to handle TE. That's not very simple, though,
4732 * especially as we go to LP between each pixel packet due to HW
4733 * "feature". So let's just estimate very roughly and multiply by 1.5.
4734 */
4735 pck = cfg->timings->pixel_clock * 1000;
4736 pck = pck * 3 / 2;
4737 txbyteclk = pck * bitspp / 8 / ndl;
4738
4739 memset(ctx, 0, sizeof(*ctx));
4740 ctx->dsidev = dsi->pdev;
4741 ctx->config = cfg;
4742 ctx->req_pck_min = pck;
4743 ctx->req_pck_nom = pck;
4744 ctx->req_pck_max = pck * 3 / 2;
4745 ctx->dsi_cinfo.clkin = clkin;
4746
4747 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4748 pll_max = cfg->hs_clk_max * 4;
4749
4750 return dsi_pll_calc(dsi->pdev, clkin,
4751 pll_min, pll_max,
4752 dsi_cm_calc_pll_cb, ctx);
4753 }
4754
4755 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4756 {
4757 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4758 const struct omap_dss_dsi_config *cfg = ctx->config;
4759 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4760 int ndl = dsi->num_lanes_used - 1;
4761 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4762 unsigned long byteclk = hsclk / 4;
4763
4764 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4765 int xres;
4766 int panel_htot, panel_hbl; /* pixels */
4767 int dispc_htot, dispc_hbl; /* pixels */
4768 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4769 int hfp, hsa, hbp;
4770 const struct omap_video_timings *req_vm;
4771 struct omap_video_timings *dispc_vm;
4772 struct omap_dss_dsi_videomode_timings *dsi_vm;
4773 u64 dsi_tput, dispc_tput;
4774
4775 dsi_tput = (u64)byteclk * ndl * 8;
4776
4777 req_vm = cfg->timings;
4778 req_pck_min = ctx->req_pck_min;
4779 req_pck_max = ctx->req_pck_max;
4780 req_pck_nom = ctx->req_pck_nom;
4781
4782 dispc_pck = ctx->dispc_cinfo.pck;
4783 dispc_tput = (u64)dispc_pck * bitspp;
4784
4785 xres = req_vm->x_res;
4786
4787 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4788 panel_htot = xres + panel_hbl;
4789
4790 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4791
4792 /*
4793 * When there are no line buffers, DISPC and DSI must have the
4794 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4795 */
4796 if (dsi->line_buffer_size < xres * bitspp / 8) {
4797 if (dispc_tput != dsi_tput)
4798 return false;
4799 } else {
4800 if (dispc_tput < dsi_tput)
4801 return false;
4802 }
4803
4804 /* DSI tput must be over the min requirement */
4805 if (dsi_tput < (u64)bitspp * req_pck_min)
4806 return false;
4807
4808 /* When non-burst mode, DSI tput must be below max requirement. */
4809 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4810 if (dsi_tput > (u64)bitspp * req_pck_max)
4811 return false;
4812 }
4813
4814 hss = DIV_ROUND_UP(4, ndl);
4815
4816 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4817 if (ndl == 3 && req_vm->hsw == 0)
4818 hse = 1;
4819 else
4820 hse = DIV_ROUND_UP(4, ndl);
4821 } else {
4822 hse = 0;
4823 }
4824
4825 /* DSI htot to match the panel's nominal pck */
4826 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4827
4828 /* fail if there would be no time for blanking */
4829 if (dsi_htot < hss + hse + dsi_hact)
4830 return false;
4831
4832 /* total DSI blanking needed to achieve panel's TL */
4833 dsi_hbl = dsi_htot - dsi_hact;
4834
4835 /* DISPC htot to match the DSI TL */
4836 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4837
4838 /* verify that the DSI and DISPC TLs are the same */
4839 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4840 return false;
4841
4842 dispc_hbl = dispc_htot - xres;
4843
4844 /* setup DSI videomode */
4845
4846 dsi_vm = &ctx->dsi_vm;
4847 memset(dsi_vm, 0, sizeof(*dsi_vm));
4848
4849 dsi_vm->hsclk = hsclk;
4850
4851 dsi_vm->ndl = ndl;
4852 dsi_vm->bitspp = bitspp;
4853
4854 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4855 hsa = 0;
4856 } else if (ndl == 3 && req_vm->hsw == 0) {
4857 hsa = 0;
4858 } else {
4859 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4860 hsa = max(hsa - hse, 1);
4861 }
4862
4863 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4864 hbp = max(hbp, 1);
4865
4866 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4867 if (hfp < 1) {
4868 int t;
4869 /* we need to take cycles from hbp */
4870
4871 t = 1 - hfp;
4872 hbp = max(hbp - t, 1);
4873 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4874
4875 if (hfp < 1 && hsa > 0) {
4876 /* we need to take cycles from hsa */
4877 t = 1 - hfp;
4878 hsa = max(hsa - t, 1);
4879 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4880 }
4881 }
4882
4883 if (hfp < 1)
4884 return false;
4885
4886 dsi_vm->hss = hss;
4887 dsi_vm->hsa = hsa;
4888 dsi_vm->hse = hse;
4889 dsi_vm->hbp = hbp;
4890 dsi_vm->hact = xres;
4891 dsi_vm->hfp = hfp;
4892
4893 dsi_vm->vsa = req_vm->vsw;
4894 dsi_vm->vbp = req_vm->vbp;
4895 dsi_vm->vact = req_vm->y_res;
4896 dsi_vm->vfp = req_vm->vfp;
4897
4898 dsi_vm->trans_mode = cfg->trans_mode;
4899
4900 dsi_vm->blanking_mode = 0;
4901 dsi_vm->hsa_blanking_mode = 1;
4902 dsi_vm->hfp_blanking_mode = 1;
4903 dsi_vm->hbp_blanking_mode = 1;
4904
4905 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4906 dsi_vm->window_sync = 4;
4907
4908 /* setup DISPC videomode */
4909
4910 dispc_vm = &ctx->dispc_vm;
4911 *dispc_vm = *req_vm;
4912 dispc_vm->pixel_clock = dispc_pck / 1000;
4913
4914 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4915 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4916 req_pck_nom);
4917 hsa = max(hsa, 1);
4918 } else {
4919 hsa = 1;
4920 }
4921
4922 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4923 hbp = max(hbp, 1);
4924
4925 hfp = dispc_hbl - hsa - hbp;
4926 if (hfp < 1) {
4927 int t;
4928 /* we need to take cycles from hbp */
4929
4930 t = 1 - hfp;
4931 hbp = max(hbp - t, 1);
4932 hfp = dispc_hbl - hsa - hbp;
4933
4934 if (hfp < 1) {
4935 /* we need to take cycles from hsa */
4936 t = 1 - hfp;
4937 hsa = max(hsa - t, 1);
4938 hfp = dispc_hbl - hsa - hbp;
4939 }
4940 }
4941
4942 if (hfp < 1)
4943 return false;
4944
4945 dispc_vm->hfp = hfp;
4946 dispc_vm->hsw = hsa;
4947 dispc_vm->hbp = hbp;
4948
4949 return true;
4950 }
4951
4952
4953 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4954 unsigned long pck, void *data)
4955 {
4956 struct dsi_clk_calc_ctx *ctx = data;
4957
4958 ctx->dispc_cinfo.lck_div = lckd;
4959 ctx->dispc_cinfo.pck_div = pckd;
4960 ctx->dispc_cinfo.lck = lck;
4961 ctx->dispc_cinfo.pck = pck;
4962
4963 if (dsi_vm_calc_blanking(ctx) == false)
4964 return false;
4965
4966 #ifdef PRINT_VERBOSE_VM_TIMINGS
4967 print_dispc_vm("dispc", &ctx->dispc_vm);
4968 print_dsi_vm("dsi ", &ctx->dsi_vm);
4969 print_dispc_vm("req ", ctx->config->timings);
4970 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4971 #endif
4972
4973 return true;
4974 }
4975
4976 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4977 void *data)
4978 {
4979 struct dsi_clk_calc_ctx *ctx = data;
4980 unsigned long pck_max;
4981
4982 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4983 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4984
4985 /*
4986 * In burst mode we can let the dispc pck be arbitrarily high, but it
4987 * limits our scaling abilities. So for now, don't aim too high.
4988 */
4989
4990 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
4991 pck_max = ctx->req_pck_max + 10000000;
4992 else
4993 pck_max = ctx->req_pck_max;
4994
4995 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
4996 dsi_vm_calc_dispc_cb, ctx);
4997 }
4998
4999 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
5000 unsigned long pll, void *data)
5001 {
5002 struct dsi_clk_calc_ctx *ctx = data;
5003
5004 ctx->dsi_cinfo.regn = regn;
5005 ctx->dsi_cinfo.regm = regm;
5006 ctx->dsi_cinfo.fint = fint;
5007 ctx->dsi_cinfo.clkin4ddr = pll;
5008
5009 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
5010 dsi_vm_calc_hsdiv_cb, ctx);
5011 }
5012
5013 static bool dsi_vm_calc(struct dsi_data *dsi,
5014 const struct omap_dss_dsi_config *cfg,
5015 struct dsi_clk_calc_ctx *ctx)
5016 {
5017 const struct omap_video_timings *t = cfg->timings;
5018 unsigned long clkin;
5019 unsigned long pll_min;
5020 unsigned long pll_max;
5021 int ndl = dsi->num_lanes_used - 1;
5022 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
5023 unsigned long byteclk_min;
5024
5025 clkin = clk_get_rate(dsi->sys_clk);
5026
5027 memset(ctx, 0, sizeof(*ctx));
5028 ctx->dsidev = dsi->pdev;
5029 ctx->config = cfg;
5030
5031 ctx->dsi_cinfo.clkin = clkin;
5032
5033 /* these limits should come from the panel driver */
5034 ctx->req_pck_min = t->pixel_clock * 1000 - 1000;
5035 ctx->req_pck_nom = t->pixel_clock * 1000;
5036 ctx->req_pck_max = t->pixel_clock * 1000 + 1000;
5037
5038 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5039 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5040
5041 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5042 pll_max = cfg->hs_clk_max * 4;
5043 } else {
5044 unsigned long byteclk_max;
5045 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5046 ndl * 8);
5047
5048 pll_max = byteclk_max * 4 * 4;
5049 }
5050
5051 return dsi_pll_calc(dsi->pdev, clkin,
5052 pll_min, pll_max,
5053 dsi_vm_calc_pll_cb, ctx);
5054 }
5055
5056 static int dsi_set_config(struct omap_dss_device *dssdev,
5057 const struct omap_dss_dsi_config *config)
5058 {
5059 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5060 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5061 struct dsi_clk_calc_ctx ctx;
5062 bool ok;
5063 int r;
5064
5065 mutex_lock(&dsi->lock);
5066
5067 dsi->pix_fmt = config->pixel_format;
5068 dsi->mode = config->mode;
5069
5070 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5071 ok = dsi_vm_calc(dsi, config, &ctx);
5072 else
5073 ok = dsi_cm_calc(dsi, config, &ctx);
5074
5075 if (!ok) {
5076 DSSERR("failed to find suitable DSI clock settings\n");
5077 r = -EINVAL;
5078 goto err;
5079 }
5080
5081 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5082
5083 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5084 config->lp_clk_max);
5085 if (r) {
5086 DSSERR("failed to find suitable DSI LP clock settings\n");
5087 goto err;
5088 }
5089
5090 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5091 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5092
5093 dsi->timings = ctx.dispc_vm;
5094 dsi->vm_timings = ctx.dsi_vm;
5095
5096 mutex_unlock(&dsi->lock);
5097
5098 return 0;
5099 err:
5100 mutex_unlock(&dsi->lock);
5101
5102 return r;
5103 }
5104
5105 /*
5106 * Return a hardcoded channel for the DSI output. This should work for
5107 * current use cases, but this can be later expanded to either resolve
5108 * the channel in some more dynamic manner, or get the channel as a user
5109 * parameter.
5110 */
5111 static enum omap_channel dsi_get_channel(int module_id)
5112 {
5113 switch (omapdss_get_version()) {
5114 case OMAPDSS_VER_OMAP24xx:
5115 DSSWARN("DSI not supported\n");
5116 return OMAP_DSS_CHANNEL_LCD;
5117
5118 case OMAPDSS_VER_OMAP34xx_ES1:
5119 case OMAPDSS_VER_OMAP34xx_ES3:
5120 case OMAPDSS_VER_OMAP3630:
5121 case OMAPDSS_VER_AM35xx:
5122 return OMAP_DSS_CHANNEL_LCD;
5123
5124 case OMAPDSS_VER_OMAP4430_ES1:
5125 case OMAPDSS_VER_OMAP4430_ES2:
5126 case OMAPDSS_VER_OMAP4:
5127 switch (module_id) {
5128 case 0:
5129 return OMAP_DSS_CHANNEL_LCD;
5130 case 1:
5131 return OMAP_DSS_CHANNEL_LCD2;
5132 default:
5133 DSSWARN("unsupported module id\n");
5134 return OMAP_DSS_CHANNEL_LCD;
5135 }
5136
5137 case OMAPDSS_VER_OMAP5:
5138 switch (module_id) {
5139 case 0:
5140 return OMAP_DSS_CHANNEL_LCD;
5141 case 1:
5142 return OMAP_DSS_CHANNEL_LCD3;
5143 default:
5144 DSSWARN("unsupported module id\n");
5145 return OMAP_DSS_CHANNEL_LCD;
5146 }
5147
5148 default:
5149 DSSWARN("unsupported DSS version\n");
5150 return OMAP_DSS_CHANNEL_LCD;
5151 }
5152 }
5153
5154 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5155 {
5156 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5158 int i;
5159
5160 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5161 if (!dsi->vc[i].dssdev) {
5162 dsi->vc[i].dssdev = dssdev;
5163 *channel = i;
5164 return 0;
5165 }
5166 }
5167
5168 DSSERR("cannot get VC for display %s", dssdev->name);
5169 return -ENOSPC;
5170 }
5171
5172 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5173 {
5174 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5175 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5176
5177 if (vc_id < 0 || vc_id > 3) {
5178 DSSERR("VC ID out of range\n");
5179 return -EINVAL;
5180 }
5181
5182 if (channel < 0 || channel > 3) {
5183 DSSERR("Virtual Channel out of range\n");
5184 return -EINVAL;
5185 }
5186
5187 if (dsi->vc[channel].dssdev != dssdev) {
5188 DSSERR("Virtual Channel not allocated to display %s\n",
5189 dssdev->name);
5190 return -EINVAL;
5191 }
5192
5193 dsi->vc[channel].vc_id = vc_id;
5194
5195 return 0;
5196 }
5197
5198 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5199 {
5200 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5201 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5202
5203 if ((channel >= 0 && channel <= 3) &&
5204 dsi->vc[channel].dssdev == dssdev) {
5205 dsi->vc[channel].dssdev = NULL;
5206 dsi->vc[channel].vc_id = 0;
5207 }
5208 }
5209
5210 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5211 {
5212 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5213 DSSERR("%s (%s) not active\n",
5214 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5215 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5216 }
5217
5218 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5219 {
5220 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5221 DSSERR("%s (%s) not active\n",
5222 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5223 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5224 }
5225
5226 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5227 {
5228 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5229
5230 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5231 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5232 dsi->regm_dispc_max =
5233 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5234 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5235 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5236 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5237 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5238 }
5239
5240 static int dsi_get_clocks(struct platform_device *dsidev)
5241 {
5242 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5243 struct clk *clk;
5244
5245 clk = devm_clk_get(&dsidev->dev, "fck");
5246 if (IS_ERR(clk)) {
5247 DSSERR("can't get fck\n");
5248 return PTR_ERR(clk);
5249 }
5250
5251 dsi->dss_clk = clk;
5252
5253 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5254 if (IS_ERR(clk)) {
5255 DSSERR("can't get sys_clk\n");
5256 return PTR_ERR(clk);
5257 }
5258
5259 dsi->sys_clk = clk;
5260
5261 return 0;
5262 }
5263
5264 static int dsi_connect(struct omap_dss_device *dssdev,
5265 struct omap_dss_device *dst)
5266 {
5267 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5268 struct omap_overlay_manager *mgr;
5269 int r;
5270
5271 r = dsi_regulator_init(dsidev);
5272 if (r)
5273 return r;
5274
5275 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
5276 if (!mgr)
5277 return -ENODEV;
5278
5279 r = dss_mgr_connect(mgr, dssdev);
5280 if (r)
5281 return r;
5282
5283 r = omapdss_output_set_device(dssdev, dst);
5284 if (r) {
5285 DSSERR("failed to connect output to new device: %s\n",
5286 dssdev->name);
5287 dss_mgr_disconnect(mgr, dssdev);
5288 return r;
5289 }
5290
5291 return 0;
5292 }
5293
5294 static void dsi_disconnect(struct omap_dss_device *dssdev,
5295 struct omap_dss_device *dst)
5296 {
5297 WARN_ON(dst != dssdev->dst);
5298
5299 if (dst != dssdev->dst)
5300 return;
5301
5302 omapdss_output_unset_device(dssdev);
5303
5304 if (dssdev->manager)
5305 dss_mgr_disconnect(dssdev->manager, dssdev);
5306 }
5307
5308 static const struct omapdss_dsi_ops dsi_ops = {
5309 .connect = dsi_connect,
5310 .disconnect = dsi_disconnect,
5311
5312 .bus_lock = dsi_bus_lock,
5313 .bus_unlock = dsi_bus_unlock,
5314
5315 .enable = dsi_display_enable,
5316 .disable = dsi_display_disable,
5317
5318 .enable_hs = dsi_vc_enable_hs,
5319
5320 .configure_pins = dsi_configure_pins,
5321 .set_config = dsi_set_config,
5322
5323 .enable_video_output = dsi_enable_video_output,
5324 .disable_video_output = dsi_disable_video_output,
5325
5326 .update = dsi_update,
5327
5328 .enable_te = dsi_enable_te,
5329
5330 .request_vc = dsi_request_vc,
5331 .set_vc_id = dsi_set_vc_id,
5332 .release_vc = dsi_release_vc,
5333
5334 .dcs_write = dsi_vc_dcs_write,
5335 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5336 .dcs_read = dsi_vc_dcs_read,
5337
5338 .gen_write = dsi_vc_generic_write,
5339 .gen_write_nosync = dsi_vc_generic_write_nosync,
5340 .gen_read = dsi_vc_generic_read,
5341
5342 .bta_sync = dsi_vc_send_bta_sync,
5343
5344 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5345 };
5346
5347 static void dsi_init_output(struct platform_device *dsidev)
5348 {
5349 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5350 struct omap_dss_device *out = &dsi->output;
5351
5352 out->dev = &dsidev->dev;
5353 out->id = dsi->module_id == 0 ?
5354 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5355
5356 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5357 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5358 out->dispc_channel = dsi_get_channel(dsi->module_id);
5359 out->ops.dsi = &dsi_ops;
5360 out->owner = THIS_MODULE;
5361
5362 omapdss_register_output(out);
5363 }
5364
5365 static void dsi_uninit_output(struct platform_device *dsidev)
5366 {
5367 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5368 struct omap_dss_device *out = &dsi->output;
5369
5370 omapdss_unregister_output(out);
5371 }
5372
5373 /* DSI1 HW IP initialisation */
5374 static int omap_dsihw_probe(struct platform_device *dsidev)
5375 {
5376 u32 rev;
5377 int r, i;
5378 struct dsi_data *dsi;
5379 struct resource *res;
5380 struct resource temp_res;
5381
5382 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5383 if (!dsi)
5384 return -ENOMEM;
5385
5386 dsi->module_id = dsidev->id;
5387 dsi->pdev = dsidev;
5388 dev_set_drvdata(&dsidev->dev, dsi);
5389
5390 spin_lock_init(&dsi->irq_lock);
5391 spin_lock_init(&dsi->errors_lock);
5392 dsi->errors = 0;
5393
5394 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5395 spin_lock_init(&dsi->irq_stats_lock);
5396 dsi->irq_stats.last_reset = jiffies;
5397 #endif
5398
5399 mutex_init(&dsi->lock);
5400 sema_init(&dsi->bus_lock, 1);
5401
5402 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5403 dsi_framedone_timeout_work_callback);
5404
5405 #ifdef DSI_CATCH_MISSING_TE
5406 init_timer(&dsi->te_timer);
5407 dsi->te_timer.function = dsi_te_timeout;
5408 dsi->te_timer.data = 0;
5409 #endif
5410
5411 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5412 if (!res) {
5413 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5414 if (!res) {
5415 DSSERR("can't get IORESOURCE_MEM DSI\n");
5416 return -EINVAL;
5417 }
5418
5419 temp_res.start = res->start;
5420 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5421 res = &temp_res;
5422 }
5423
5424 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5425 resource_size(res));
5426 if (!dsi->proto_base) {
5427 DSSERR("can't ioremap DSI protocol engine\n");
5428 return -ENOMEM;
5429 }
5430
5431 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5432 if (!res) {
5433 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5434 if (!res) {
5435 DSSERR("can't get IORESOURCE_MEM DSI\n");
5436 return -EINVAL;
5437 }
5438
5439 temp_res.start = res->start + DSI_PHY_OFFSET;
5440 temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5441 res = &temp_res;
5442 }
5443
5444 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5445 resource_size(res));
5446 if (!dsi->proto_base) {
5447 DSSERR("can't ioremap DSI PHY\n");
5448 return -ENOMEM;
5449 }
5450
5451 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5452 if (!res) {
5453 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5454 if (!res) {
5455 DSSERR("can't get IORESOURCE_MEM DSI\n");
5456 return -EINVAL;
5457 }
5458
5459 temp_res.start = res->start + DSI_PLL_OFFSET;
5460 temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5461 res = &temp_res;
5462 }
5463
5464 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5465 resource_size(res));
5466 if (!dsi->proto_base) {
5467 DSSERR("can't ioremap DSI PLL\n");
5468 return -ENOMEM;
5469 }
5470
5471 dsi->irq = platform_get_irq(dsi->pdev, 0);
5472 if (dsi->irq < 0) {
5473 DSSERR("platform_get_irq failed\n");
5474 return -ENODEV;
5475 }
5476
5477 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5478 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5479 if (r < 0) {
5480 DSSERR("request_irq failed\n");
5481 return r;
5482 }
5483
5484 /* DSI VCs initialization */
5485 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5486 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5487 dsi->vc[i].dssdev = NULL;
5488 dsi->vc[i].vc_id = 0;
5489 }
5490
5491 dsi_calc_clock_param_ranges(dsidev);
5492
5493 r = dsi_get_clocks(dsidev);
5494 if (r)
5495 return r;
5496
5497 pm_runtime_enable(&dsidev->dev);
5498
5499 r = dsi_runtime_get(dsidev);
5500 if (r)
5501 goto err_runtime_get;
5502
5503 rev = dsi_read_reg(dsidev, DSI_REVISION);
5504 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5505 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5506
5507 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5508 * of data to 3 by default */
5509 if (dss_has_feature(FEAT_DSI_GNQ))
5510 /* NB_DATA_LANES */
5511 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5512 else
5513 dsi->num_lanes_supported = 3;
5514
5515 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5516
5517 dsi_init_output(dsidev);
5518
5519 dsi_runtime_put(dsidev);
5520
5521 if (dsi->module_id == 0)
5522 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5523 else if (dsi->module_id == 1)
5524 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5525
5526 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5527 if (dsi->module_id == 0)
5528 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5529 else if (dsi->module_id == 1)
5530 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5531 #endif
5532 return 0;
5533
5534 err_runtime_get:
5535 pm_runtime_disable(&dsidev->dev);
5536 return r;
5537 }
5538
5539 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5540 {
5541 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5542
5543 WARN_ON(dsi->scp_clk_refcount > 0);
5544
5545 dsi_uninit_output(dsidev);
5546
5547 pm_runtime_disable(&dsidev->dev);
5548
5549 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5550 regulator_disable(dsi->vdds_dsi_reg);
5551 dsi->vdds_dsi_enabled = false;
5552 }
5553
5554 return 0;
5555 }
5556
5557 static int dsi_runtime_suspend(struct device *dev)
5558 {
5559 dispc_runtime_put();
5560
5561 return 0;
5562 }
5563
5564 static int dsi_runtime_resume(struct device *dev)
5565 {
5566 int r;
5567
5568 r = dispc_runtime_get();
5569 if (r)
5570 return r;
5571
5572 return 0;
5573 }
5574
5575 static const struct dev_pm_ops dsi_pm_ops = {
5576 .runtime_suspend = dsi_runtime_suspend,
5577 .runtime_resume = dsi_runtime_resume,
5578 };
5579
5580 static struct platform_driver omap_dsihw_driver = {
5581 .probe = omap_dsihw_probe,
5582 .remove = __exit_p(omap_dsihw_remove),
5583 .driver = {
5584 .name = "omapdss_dsi",
5585 .owner = THIS_MODULE,
5586 .pm = &dsi_pm_ops,
5587 },
5588 };
5589
5590 int __init dsi_init_platform_driver(void)
5591 {
5592 return platform_driver_register(&omap_dsihw_driver);
5593 }
5594
5595 void __exit dsi_uninit_platform_driver(void)
5596 {
5597 platform_driver_unregister(&omap_dsihw_driver);
5598 }
Linux kernel - Deliverables
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