drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern bool dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum dss_io_pad_mode {
 101         DSS_IO_PAD_MODE_RESET,
 102         DSS_IO_PAD_MODE_RFBI,
 103         DSS_IO_PAD_MODE_BYPASS,
 104 };
 105
 106 enum dss_hdmi_venc_clk_source_select {
 107         DSS_VENC_TV_CLK = 0,
 108         DSS_HDMI_M_PCLK = 1,
 109 };
 110
 111 enum dss_dsi_content_type {
 112         DSS_DSI_CONTENT_DCS,
 113         DSS_DSI_CONTENT_GENERIC,
 114 };
 115
 116 struct dss_clock_info {
 117         /* rates that we get with dividers below */
 118         unsigned long fck;
 119
 120         /* dividers */
 121         u16 fck_div;
 122 };
 123
 124 struct dispc_clock_info {
 125         /* rates that we get with dividers below */
 126         unsigned long lck;
 127         unsigned long pck;
 128
 129         /* dividers */
 130         u16 lck_div;
 131         u16 pck_div;
 132 };
 133
 134 struct dsi_clock_info {
 135         /* rates that we get with dividers below */
 136         unsigned long fint;
 137         unsigned long clkin4ddr;
 138         unsigned long clkin;
 139         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 140                                                  * OMAP4: PLLx_CLK1 */
 141         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 142                                                  * OMAP4: PLLx_CLK2 */
 143         unsigned long lp_clk;
 144
 145         /* dividers */
 146         u16 regn;
 147         u16 regm;
 148         u16 regm_dispc; /* OMAP3: REGM3
 149                          * OMAP4: REGM4 */
 150         u16 regm_dsi;   /* OMAP3: REGM4
 151                          * OMAP4: REGM5 */
 152         u16 lp_clk_div;
 153
 154         u8 highfreq;
 155         bool use_sys_clk;
 156 };
 157
 158 struct seq_file;
 159 struct platform_device;
 160
 161 /* core */
 162 struct bus_type *dss_get_bus(void);
 163 struct regulator *dss_get_vdds_dsi(void);
 164 struct regulator *dss_get_vdds_sdi(void);
 165
 166 /* display */
 167 int dss_suspend_all_devices(void);
 168 int dss_resume_all_devices(void);
 169 void dss_disable_all_devices(void);
 170
 171 void dss_init_device(struct platform_device *pdev,
 172                 struct omap_dss_device *dssdev);
 173 void dss_uninit_device(struct platform_device *pdev,
 174                 struct omap_dss_device *dssdev);
 175 bool dss_use_replication(struct omap_dss_device *dssdev,
 176                 enum omap_color_mode mode);
 177 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 178                 u32 fifo_size, u32 burst_size,
 179                 u32 *fifo_low, u32 *fifo_high);
 180
 181 /* manager */
 182 int dss_init_overlay_managers(struct platform_device *pdev);
 183 void dss_uninit_overlay_managers(struct platform_device *pdev);
 184 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 185 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 186                                 u16 *x, u16 *y, u16 *w, u16 *h,
 187                                 bool enlarge_update_area);
 188 void dss_start_update(struct omap_dss_device *dssdev);
 189
 190 /* overlay */
 191 void dss_init_overlays(struct platform_device *pdev);
 192 void dss_uninit_overlays(struct platform_device *pdev);
 193 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 194 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 195 #ifdef L4_EXAMPLE
 196 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 197 #endif
 198 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 199
 200 /* DSS */
 201 int dss_init_platform_driver(void);
 202 void dss_uninit_platform_driver(void);
 203
 204 int dss_runtime_get(void);
 205 void dss_runtime_put(void);
 206
 207 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 208 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
 209 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 210 void dss_dump_clocks(struct seq_file *s);
 211
 212 void dss_dump_regs(struct seq_file *s);
 213 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 214 void dss_debug_dump_clocks(struct seq_file *s);
 215 #endif
 216
 217 void dss_sdi_init(u8 datapairs);
 218 int dss_sdi_enable(void);
 219 void dss_sdi_disable(void);
 220
 221 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 222 void dss_select_dsi_clk_source(int dsi_module,
 223                 enum omap_dss_clk_source clk_src);
 224 void dss_select_lcd_clk_source(enum omap_channel channel,
 225                 enum omap_dss_clk_source clk_src);
 226 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 227 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 228 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 229
 230 void dss_set_venc_output(enum omap_dss_venc_type type);
 231 void dss_set_dac_pwrdn_bgz(bool enable);
 232
 233 unsigned long dss_get_dpll4_rate(void);
 234 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 235 int dss_set_clock_div(struct dss_clock_info *cinfo);
 236 int dss_get_clock_div(struct dss_clock_info *cinfo);
 237 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 238                 struct dss_clock_info *dss_cinfo,
 239                 struct dispc_clock_info *dispc_cinfo);
 240
 241 /* SDI */
 242 #ifdef CONFIG_OMAP2_DSS_SDI
 243 int sdi_init(void);
 244 void sdi_exit(void);
 245 int sdi_init_display(struct omap_dss_device *display);
 246 #else
 247 static inline int sdi_init(void)
 248 {
 249         return 0;
 250 }
 251 static inline void sdi_exit(void)
 252 {
 253 }
 254 #endif
 255
 256 /* DSI */
 257 #ifdef CONFIG_OMAP2_DSS_DSI
 258
 259 struct dentry;
 260 struct file_operations;
 261
 262 int dsi_init_platform_driver(void);
 263 void dsi_uninit_platform_driver(void);
 264
 265 int dsi_runtime_get(struct platform_device *dsidev);
 266 void dsi_runtime_put(struct platform_device *dsidev);
 267
 268 void dsi_dump_clocks(struct seq_file *s);
 269 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 270                 const struct file_operations *debug_fops);
 271 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 272                 const struct file_operations *debug_fops);
 273
 274 int dsi_init_display(struct omap_dss_device *display);
 275 void dsi_irq_handler(void);
 276 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 277
 278 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 279 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 280                 struct dsi_clock_info *cinfo);
 281 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 282                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 283                 struct dispc_clock_info *dispc_cinfo);
 284 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 285                 bool enable_hsdiv);
 286 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 287 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 288                 u32 fifo_size, u32 burst_size,
 289                 u32 *fifo_low, u32 *fifo_high);
 290 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 291 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 292 struct platform_device *dsi_get_dsidev_from_id(int module);
 293 #else
 294 static inline int dsi_init_platform_driver(void)
 295 {
 296         return 0;
 297 }
 298 static inline void dsi_uninit_platform_driver(void)
 299 {
 300 }
 301 static inline int dsi_runtime_get(struct platform_device *dsidev)
 302 {
 303         return 0;
 304 }
 305 static inline void dsi_runtime_put(struct platform_device *dsidev)
 306 {
 307 }
 308 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 309 {
 310         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 311         return 0;
 312 }
 313 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 314 {
 315         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 316         return 0;
 317 }
 318 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 319                 struct dsi_clock_info *cinfo)
 320 {
 321         WARN("%s: DSI not compiled in\n", __func__);
 322         return -ENODEV;
 323 }
 324 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 325                 bool is_tft, unsigned long req_pck,
 326                 struct dsi_clock_info *dsi_cinfo,
 327                 struct dispc_clock_info *dispc_cinfo)
 328 {
 329         WARN("%s: DSI not compiled in\n", __func__);
 330         return -ENODEV;
 331 }
 332 static inline int dsi_pll_init(struct platform_device *dsidev,
 333                 bool enable_hsclk, bool enable_hsdiv)
 334 {
 335         WARN("%s: DSI not compiled in\n", __func__);
 336         return -ENODEV;
 337 }
 338 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 339                 bool disconnect_lanes)
 340 {
 341 }
 342 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 343 {
 344 }
 345 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 346 {
 347 }
 348 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 349 {
 350         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 351                         __func__);
 352         return NULL;
 353 }
 354 #endif
 355
 356 /* DPI */
 357 #ifdef CONFIG_OMAP2_DSS_DPI
 358 int dpi_init(void);
 359 void dpi_exit(void);
 360 int dpi_init_display(struct omap_dss_device *dssdev);
 361 #else
 362 static inline int dpi_init(void)
 363 {
 364         return 0;
 365 }
 366 static inline void dpi_exit(void)
 367 {
 368 }
 369 #endif
 370
 371 /* DISPC */
 372 int dispc_init_platform_driver(void);
 373 void dispc_uninit_platform_driver(void);
 374 void dispc_dump_clocks(struct seq_file *s);
 375 void dispc_dump_irqs(struct seq_file *s);
 376 void dispc_dump_regs(struct seq_file *s);
 377 void dispc_irq_handler(void);
 378 void dispc_fake_vsync_irq(void);
 379
 380 int dispc_runtime_get(void);
 381 void dispc_runtime_put(void);
 382
 383 void dispc_enable_sidle(void);
 384 void dispc_disable_sidle(void);
 385
 386 void dispc_lcd_enable_signal_polarity(bool act_high);
 387 void dispc_lcd_enable_signal(bool enable);
 388 void dispc_pck_free_enable(bool enable);
 389 void dispc_set_digit_size(u16 width, u16 height);
 390 void dispc_enable_fifomerge(bool enable);
 391 void dispc_enable_gamma_table(bool enable);
 392 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 393
 394 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 395 unsigned long dispc_fclk_rate(void);
 396 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 397                 struct dispc_clock_info *cinfo);
 398 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 399                 struct dispc_clock_info *cinfo);
 400
 401
 402 u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
 403 u32 dispc_ovl_get_burst_size(enum omap_plane plane);
 404 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
 405                 bool ilace, enum omap_channel channel, bool replication,
 406                 u32 fifo_low, u32 fifo_high);
 407 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 408
 409
 410 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
 411 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 412 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable);
 413 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 414                 struct omap_dss_cpr_coefs *coefs);
 415 bool dispc_mgr_go_busy(enum omap_channel channel);
 416 void dispc_mgr_go(enum omap_channel channel);
 417 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 418 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
 419 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
 420 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
 421 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 422 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
 423                 enum omap_lcd_display_type type);
 424 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color);
 425 u32 dispc_mgr_get_default_color(enum omap_channel channel);
 426 void dispc_mgr_set_trans_key(enum omap_channel ch,
 427                 enum omap_dss_trans_key_type type,
 428                 u32 trans_key);
 429 void dispc_mgr_get_trans_key(enum omap_channel ch,
 430                 enum omap_dss_trans_key_type *type,
 431                 u32 *trans_key);
 432 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable);
 433 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable);
 434 bool dispc_mgr_trans_key_enabled(enum omap_channel ch);
 435 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch);
 436 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
 437                 struct omap_video_timings *timings);
 438 void dispc_mgr_set_pol_freq(enum omap_channel channel,
 439                 enum omap_panel_config config, u8 acbi, u8 acb);
 440 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 441 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 442 int dispc_mgr_set_clock_div(enum omap_channel channel,
 443                 struct dispc_clock_info *cinfo);
 444 int dispc_mgr_get_clock_div(enum omap_channel channel,
 445                 struct dispc_clock_info *cinfo);
 446
 447 /* VENC */
 448 #ifdef CONFIG_OMAP2_DSS_VENC
 449 int venc_init_platform_driver(void);
 450 void venc_uninit_platform_driver(void);
 451 void venc_dump_regs(struct seq_file *s);
 452 int venc_init_display(struct omap_dss_device *display);
 453 unsigned long venc_get_pixel_clock(void);
 454 #else
 455 static inline int venc_init_platform_driver(void)
 456 {
 457         return 0;
 458 }
 459 static inline void venc_uninit_platform_driver(void)
 460 {
 461 }
 462 static inline unsigned long venc_get_pixel_clock(void)
 463 {
 464         WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__);
 465         return 0;
 466 }
 467 #endif
 468
 469 /* HDMI */
 470 #ifdef CONFIG_OMAP4_DSS_HDMI
 471 int hdmi_init_platform_driver(void);
 472 void hdmi_uninit_platform_driver(void);
 473 int hdmi_init_display(struct omap_dss_device *dssdev);
 474 unsigned long hdmi_get_pixel_clock(void);
 475 void hdmi_dump_regs(struct seq_file *s);
 476 #else
 477 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 478 {
 479         return 0;
 480 }
 481 static inline int hdmi_init_platform_driver(void)
 482 {
 483         return 0;
 484 }
 485 static inline void hdmi_uninit_platform_driver(void)
 486 {
 487 }
 488 static inline unsigned long hdmi_get_pixel_clock(void)
 489 {
 490         WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__);
 491         return 0;
 492 }
 493 #endif
 494 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 495 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 496 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 497 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 498                                         struct omap_video_timings *timings);
 499 int omapdss_hdmi_read_edid(u8 *buf, int len);
 500 bool omapdss_hdmi_detect(void);
 501 int hdmi_panel_init(void);
 502 void hdmi_panel_exit(void);
 503
 504 /* RFBI */
 505 #ifdef CONFIG_OMAP2_DSS_RFBI
 506 int rfbi_init_platform_driver(void);
 507 void rfbi_uninit_platform_driver(void);
 508 void rfbi_dump_regs(struct seq_file *s);
 509 int rfbi_init_display(struct omap_dss_device *display);
 510 #else
 511 static inline int rfbi_init_platform_driver(void)
 512 {
 513         return 0;
 514 }
 515 static inline void rfbi_uninit_platform_driver(void)
 516 {
 517 }
 518 #endif
 519
 520
 521 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 522 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 523 {
 524         int b;
 525         for (b = 0; b < 32; ++b) {
 526                 if (irqstatus & (1 << b))
 527                         irq_arr[b]++;
 528         }
 529 }
 530 #endif
 531
 532 #endif