2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
31 extern unsigned int dss_debug
;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
38 #define DSSDBG(format, ...) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
51 #define DSSDBGF(format, ...) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
100 enum omap_burst_size
{
101 OMAP_DSS_BURST_4x32
= 0,
102 OMAP_DSS_BURST_8x32
= 1,
103 OMAP_DSS_BURST_16x32
= 2,
106 enum omap_parallel_interface_mode
{
107 OMAP_DSS_PARALLELMODE_BYPASS
, /* MIPI DPI */
108 OMAP_DSS_PARALLELMODE_RFBI
, /* MIPI DBI */
109 OMAP_DSS_PARALLELMODE_DSI
,
113 DSS_CLK_ICK
= 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */
114 DSS_CLK_FCK
= 1 << 1, /* DSS1_ALWON_FCLK */
115 DSS_CLK_SYSCK
= 1 << 2, /* DSS2_ALWON_FCLK */
116 DSS_CLK_TVFCK
= 1 << 3, /* DSS_TV_FCLK */
117 DSS_CLK_VIDFCK
= 1 << 4, /* DSS_96M_FCLK*/
120 enum dss_clk_source
{
121 DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC
, /* DSI1_PLL_FCLK */
122 DSS_CLK_SRC_DSI_PLL_HSDIV_DSI
, /* DSI2_PLL_FCLK */
123 DSS_CLK_SRC_FCK
, /* DSS1_ALWON_FCLK */
126 /* Correlates clock source name and dss_clk_source member */
127 struct dss_clk_source_name
{
128 enum dss_clk_source clksrc
;
129 const char *clksrc_name
;
132 struct dss_clock_info
{
133 /* rates that we get with dividers below */
140 struct dispc_clock_info
{
141 /* rates that we get with dividers below */
150 struct dsi_clock_info
{
151 /* rates that we get with dividers below */
153 unsigned long clkin4ddr
;
155 unsigned long dsi_pll_hsdiv_dispc_clk
; /* DSI1_PLL_CLK */
156 unsigned long dsi_pll_hsdiv_dsi_clk
; /* DSI2_PLL_CLK */
158 unsigned long lp_clk
;
163 u16 regm_dispc
; /* REGM3 */
164 u16 regm_dsi
; /* REGM4 */
173 struct platform_device
;
176 struct bus_type
*dss_get_bus(void);
177 struct regulator
*dss_get_vdds_dsi(void);
178 struct regulator
*dss_get_vdds_sdi(void);
181 int dss_suspend_all_devices(void);
182 int dss_resume_all_devices(void);
183 void dss_disable_all_devices(void);
185 void dss_init_device(struct platform_device
*pdev
,
186 struct omap_dss_device
*dssdev
);
187 void dss_uninit_device(struct platform_device
*pdev
,
188 struct omap_dss_device
*dssdev
);
189 bool dss_use_replication(struct omap_dss_device
*dssdev
,
190 enum omap_color_mode mode
);
191 void default_get_overlay_fifo_thresholds(enum omap_plane plane
,
192 u32 fifo_size
, enum omap_burst_size
*burst_size
,
193 u32
*fifo_low
, u32
*fifo_high
);
196 int dss_init_overlay_managers(struct platform_device
*pdev
);
197 void dss_uninit_overlay_managers(struct platform_device
*pdev
);
198 int dss_mgr_wait_for_go_ovl(struct omap_overlay
*ovl
);
199 void dss_setup_partial_planes(struct omap_dss_device
*dssdev
,
200 u16
*x
, u16
*y
, u16
*w
, u16
*h
,
201 bool enlarge_update_area
);
202 void dss_start_update(struct omap_dss_device
*dssdev
);
205 void dss_init_overlays(struct platform_device
*pdev
);
206 void dss_uninit_overlays(struct platform_device
*pdev
);
207 int dss_check_overlay(struct omap_overlay
*ovl
, struct omap_dss_device
*dssdev
);
208 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager
*mgr
);
210 void dss_overlay_setup_l4_manager(struct omap_overlay_manager
*mgr
);
212 void dss_recheck_connections(struct omap_dss_device
*dssdev
, bool force
);
215 int dss_init_platform_driver(void);
216 void dss_uninit_platform_driver(void);
218 void dss_save_context(void);
219 void dss_restore_context(void);
220 void dss_clk_enable(enum dss_clock clks
);
221 void dss_clk_disable(enum dss_clock clks
);
222 unsigned long dss_clk_get_rate(enum dss_clock clk
);
223 int dss_need_ctx_restore(void);
224 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src
);
225 void dss_dump_clocks(struct seq_file
*s
);
227 void dss_dump_regs(struct seq_file
*s
);
228 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
229 void dss_debug_dump_clocks(struct seq_file
*s
);
232 void dss_sdi_init(u8 datapairs
);
233 int dss_sdi_enable(void);
234 void dss_sdi_disable(void);
236 void dss_select_dispc_clk_source(enum dss_clk_source clk_src
);
237 void dss_select_dsi_clk_source(enum dss_clk_source clk_src
);
238 enum dss_clk_source
dss_get_dispc_clk_source(void);
239 enum dss_clk_source
dss_get_dsi_clk_source(void);
241 void dss_set_venc_output(enum omap_dss_venc_type type
);
242 void dss_set_dac_pwrdn_bgz(bool enable
);
244 unsigned long dss_get_dpll4_rate(void);
245 int dss_calc_clock_rates(struct dss_clock_info
*cinfo
);
246 int dss_set_clock_div(struct dss_clock_info
*cinfo
);
247 int dss_get_clock_div(struct dss_clock_info
*cinfo
);
248 int dss_calc_clock_div(bool is_tft
, unsigned long req_pck
,
249 struct dss_clock_info
*dss_cinfo
,
250 struct dispc_clock_info
*dispc_cinfo
);
253 #ifdef CONFIG_OMAP2_DSS_SDI
254 int sdi_init(bool skip_init
);
256 int sdi_init_display(struct omap_dss_device
*display
);
258 static inline int sdi_init(bool skip_init
)
262 static inline void sdi_exit(void)
268 #ifdef CONFIG_OMAP2_DSS_DSI
269 int dsi_init_platform_driver(void);
270 void dsi_uninit_platform_driver(void);
272 void dsi_dump_clocks(struct seq_file
*s
);
273 void dsi_dump_irqs(struct seq_file
*s
);
274 void dsi_dump_regs(struct seq_file
*s
);
276 void dsi_save_context(void);
277 void dsi_restore_context(void);
279 int dsi_init_display(struct omap_dss_device
*display
);
280 void dsi_irq_handler(void);
281 unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
282 int dsi_pll_set_clock_div(struct dsi_clock_info
*cinfo
);
283 int dsi_pll_calc_clock_div_pck(bool is_tft
, unsigned long req_pck
,
284 struct dsi_clock_info
*cinfo
,
285 struct dispc_clock_info
*dispc_cinfo
);
286 int dsi_pll_init(struct omap_dss_device
*dssdev
, bool enable_hsclk
,
288 void dsi_pll_uninit(void);
289 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
290 u32 fifo_size
, enum omap_burst_size
*burst_size
,
291 u32
*fifo_low
, u32
*fifo_high
);
292 void dsi_wait_pll_hsdiv_dispc_active(void);
293 void dsi_wait_pll_hsdiv_dsi_active(void);
295 static inline int dsi_init_platform_driver(void)
299 static inline void dsi_uninit_platform_driver(void)
302 static inline void dsi_wait_pll_hsdiv_dispc_active(void)
305 static inline void dsi_wait_pll_hsdiv_dsi_active(void)
311 #ifdef CONFIG_OMAP2_DSS_DPI
312 int dpi_init(struct platform_device
*pdev
);
314 int dpi_init_display(struct omap_dss_device
*dssdev
);
316 static inline int dpi_init(struct platform_device
*pdev
)
320 static inline void dpi_exit(void)
326 int dispc_init_platform_driver(void);
327 void dispc_uninit_platform_driver(void);
328 void dispc_dump_clocks(struct seq_file
*s
);
329 void dispc_dump_irqs(struct seq_file
*s
);
330 void dispc_dump_regs(struct seq_file
*s
);
331 void dispc_irq_handler(void);
332 void dispc_fake_vsync_irq(void);
334 void dispc_save_context(void);
335 void dispc_restore_context(void);
337 void dispc_enable_sidle(void);
338 void dispc_disable_sidle(void);
340 void dispc_lcd_enable_signal_polarity(bool act_high
);
341 void dispc_lcd_enable_signal(bool enable
);
342 void dispc_pck_free_enable(bool enable
);
343 void dispc_enable_fifohandcheck(enum omap_channel channel
, bool enable
);
345 void dispc_set_lcd_size(enum omap_channel channel
, u16 width
, u16 height
);
346 void dispc_set_digit_size(u16 width
, u16 height
);
347 u32
dispc_get_plane_fifo_size(enum omap_plane plane
);
348 void dispc_setup_plane_fifo(enum omap_plane plane
, u32 low
, u32 high
);
349 void dispc_enable_fifomerge(bool enable
);
350 void dispc_set_burst_size(enum omap_plane plane
,
351 enum omap_burst_size burst_size
);
353 void dispc_set_plane_ba0(enum omap_plane plane
, u32 paddr
);
354 void dispc_set_plane_ba1(enum omap_plane plane
, u32 paddr
);
355 void dispc_set_plane_pos(enum omap_plane plane
, u16 x
, u16 y
);
356 void dispc_set_plane_size(enum omap_plane plane
, u16 width
, u16 height
);
357 void dispc_set_channel_out(enum omap_plane plane
,
358 enum omap_channel channel_out
);
360 int dispc_setup_plane(enum omap_plane plane
,
361 u32 paddr
, u16 screen_width
,
362 u16 pos_x
, u16 pos_y
,
363 u16 width
, u16 height
,
364 u16 out_width
, u16 out_height
,
365 enum omap_color_mode color_mode
,
367 enum omap_dss_rotation_type rotation_type
,
368 u8 rotation
, bool mirror
,
369 u8 global_alpha
, u8 pre_mult_alpha
,
370 enum omap_channel channel
);
372 bool dispc_go_busy(enum omap_channel channel
);
373 void dispc_go(enum omap_channel channel
);
374 void dispc_enable_channel(enum omap_channel channel
, bool enable
);
375 bool dispc_is_channel_enabled(enum omap_channel channel
);
376 int dispc_enable_plane(enum omap_plane plane
, bool enable
);
377 void dispc_enable_replication(enum omap_plane plane
, bool enable
);
379 void dispc_set_parallel_interface_mode(enum omap_channel channel
,
380 enum omap_parallel_interface_mode mode
);
381 void dispc_set_tft_data_lines(enum omap_channel channel
, u8 data_lines
);
382 void dispc_set_lcd_display_type(enum omap_channel channel
,
383 enum omap_lcd_display_type type
);
384 void dispc_set_loadmode(enum omap_dss_load_mode mode
);
386 void dispc_set_default_color(enum omap_channel channel
, u32 color
);
387 u32
dispc_get_default_color(enum omap_channel channel
);
388 void dispc_set_trans_key(enum omap_channel ch
,
389 enum omap_dss_trans_key_type type
,
391 void dispc_get_trans_key(enum omap_channel ch
,
392 enum omap_dss_trans_key_type
*type
,
394 void dispc_enable_trans_key(enum omap_channel ch
, bool enable
);
395 void dispc_enable_alpha_blending(enum omap_channel ch
, bool enable
);
396 bool dispc_trans_key_enabled(enum omap_channel ch
);
397 bool dispc_alpha_blending_enabled(enum omap_channel ch
);
399 bool dispc_lcd_timings_ok(struct omap_video_timings
*timings
);
400 void dispc_set_lcd_timings(enum omap_channel channel
,
401 struct omap_video_timings
*timings
);
402 unsigned long dispc_fclk_rate(void);
403 unsigned long dispc_lclk_rate(enum omap_channel channel
);
404 unsigned long dispc_pclk_rate(enum omap_channel channel
);
405 void dispc_set_pol_freq(enum omap_channel channel
,
406 enum omap_panel_config config
, u8 acbi
, u8 acb
);
407 void dispc_find_clk_divs(bool is_tft
, unsigned long req_pck
, unsigned long fck
,
408 struct dispc_clock_info
*cinfo
);
409 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate
,
410 struct dispc_clock_info
*cinfo
);
411 int dispc_set_clock_div(enum omap_channel channel
,
412 struct dispc_clock_info
*cinfo
);
413 int dispc_get_clock_div(enum omap_channel channel
,
414 struct dispc_clock_info
*cinfo
);
418 #ifdef CONFIG_OMAP2_DSS_VENC
419 int venc_init_platform_driver(void);
420 void venc_uninit_platform_driver(void);
421 void venc_dump_regs(struct seq_file
*s
);
422 int venc_init_display(struct omap_dss_device
*display
);
424 static inline int venc_init_platform_driver(void)
428 static inline void venc_uninit_platform_driver(void)
434 #ifdef CONFIG_OMAP2_DSS_RFBI
435 int rfbi_init_platform_driver(void);
436 void rfbi_uninit_platform_driver(void);
437 void rfbi_dump_regs(struct seq_file
*s
);
439 int rfbi_configure(int rfbi_module
, int bpp
, int lines
);
440 void rfbi_enable_rfbi(bool enable
);
441 void rfbi_transfer_area(struct omap_dss_device
*dssdev
, u16 width
,
442 u16 height
, void (callback
)(void *data
), void *data
);
443 void rfbi_set_timings(int rfbi_module
, struct rfbi_timings
*t
);
444 unsigned long rfbi_get_max_tx_rate(void);
445 int rfbi_init_display(struct omap_dss_device
*display
);
447 static inline int rfbi_init_platform_driver(void)
451 static inline void rfbi_uninit_platform_driver(void)
457 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
458 static inline void dss_collect_irq_stats(u32 irqstatus
, unsigned *irq_arr
)
461 for (b
= 0; b
< 32; ++b
) {
462 if (irqstatus
& (1 << b
))