2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
31 extern unsigned int dss_debug
;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
38 #define DSSDBG(format, ...) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
51 #define DSSDBGF(format, ...) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
100 #define DISPC_MAX_FCK 173000000
102 enum omap_burst_size
{
103 OMAP_DSS_BURST_4x32
= 0,
104 OMAP_DSS_BURST_8x32
= 1,
105 OMAP_DSS_BURST_16x32
= 2,
108 enum omap_parallel_interface_mode
{
109 OMAP_DSS_PARALLELMODE_BYPASS
, /* MIPI DPI */
110 OMAP_DSS_PARALLELMODE_RFBI
, /* MIPI DBI */
111 OMAP_DSS_PARALLELMODE_DSI
,
115 DSS_CLK_ICK
= 1 << 0,
116 DSS_CLK_FCK1
= 1 << 1,
117 DSS_CLK_FCK2
= 1 << 2,
118 DSS_CLK_54M
= 1 << 3,
119 DSS_CLK_96M
= 1 << 4,
122 enum dss_clk_source
{
123 DSS_SRC_DSI1_PLL_FCLK
,
124 DSS_SRC_DSI2_PLL_FCLK
,
125 DSS_SRC_DSS1_ALWON_FCLK
,
128 struct dss_clock_info
{
129 /* rates that we get with dividers below */
136 struct dispc_clock_info
{
137 /* rates that we get with dividers below */
146 struct dsi_clock_info
{
147 /* rates that we get with dividers below */
149 unsigned long clkin4ddr
;
151 unsigned long dsi1_pll_fclk
;
152 unsigned long dsi2_pll_fclk
;
154 unsigned long lp_clk
;
169 struct platform_device
;
172 void dss_clk_enable(enum dss_clock clks
);
173 void dss_clk_disable(enum dss_clock clks
);
174 unsigned long dss_clk_get_rate(enum dss_clock clk
);
175 int dss_need_ctx_restore(void);
176 void dss_dump_clocks(struct seq_file
*s
);
177 struct bus_type
*dss_get_bus(void);
178 struct regulator
*dss_get_vdds_dsi(void);
179 struct regulator
*dss_get_vdds_sdi(void);
180 struct regulator
*dss_get_vdda_dac(void);
183 int dss_suspend_all_devices(void);
184 int dss_resume_all_devices(void);
185 void dss_disable_all_devices(void);
187 void dss_init_device(struct platform_device
*pdev
,
188 struct omap_dss_device
*dssdev
);
189 void dss_uninit_device(struct platform_device
*pdev
,
190 struct omap_dss_device
*dssdev
);
191 bool dss_use_replication(struct omap_dss_device
*dssdev
,
192 enum omap_color_mode mode
);
193 void default_get_overlay_fifo_thresholds(enum omap_plane plane
,
194 u32 fifo_size
, enum omap_burst_size
*burst_size
,
195 u32
*fifo_low
, u32
*fifo_high
);
198 int dss_init_overlay_managers(struct platform_device
*pdev
);
199 void dss_uninit_overlay_managers(struct platform_device
*pdev
);
200 int dss_mgr_wait_for_go_ovl(struct omap_overlay
*ovl
);
201 void dss_setup_partial_planes(struct omap_dss_device
*dssdev
,
202 u16
*x
, u16
*y
, u16
*w
, u16
*h
,
203 bool enlarge_update_area
);
204 void dss_start_update(struct omap_dss_device
*dssdev
);
207 void dss_init_overlays(struct platform_device
*pdev
);
208 void dss_uninit_overlays(struct platform_device
*pdev
);
209 int dss_check_overlay(struct omap_overlay
*ovl
, struct omap_dss_device
*dssdev
);
210 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager
*mgr
);
212 void dss_overlay_setup_l4_manager(struct omap_overlay_manager
*mgr
);
214 void dss_recheck_connections(struct omap_dss_device
*dssdev
, bool force
);
217 int dss_init(bool skip_init
);
220 void dss_save_context(void);
221 void dss_restore_context(void);
223 void dss_dump_regs(struct seq_file
*s
);
225 void dss_sdi_init(u8 datapairs
);
226 int dss_sdi_enable(void);
227 void dss_sdi_disable(void);
229 void dss_select_dispc_clk_source(enum dss_clk_source clk_src
);
230 void dss_select_dsi_clk_source(enum dss_clk_source clk_src
);
231 enum dss_clk_source
dss_get_dispc_clk_source(void);
232 enum dss_clk_source
dss_get_dsi_clk_source(void);
234 void dss_set_venc_output(enum omap_dss_venc_type type
);
235 void dss_set_dac_pwrdn_bgz(bool enable
);
237 unsigned long dss_get_dpll4_rate(void);
238 int dss_calc_clock_rates(struct dss_clock_info
*cinfo
);
239 int dss_set_clock_div(struct dss_clock_info
*cinfo
);
240 int dss_get_clock_div(struct dss_clock_info
*cinfo
);
241 int dss_calc_clock_div(bool is_tft
, unsigned long req_pck
,
242 struct dss_clock_info
*dss_cinfo
,
243 struct dispc_clock_info
*dispc_cinfo
);
246 #ifdef CONFIG_OMAP2_DSS_SDI
247 int sdi_init(bool skip_init
);
249 int sdi_init_display(struct omap_dss_device
*display
);
251 static inline int sdi_init(bool skip_init
)
255 static inline void sdi_exit(void)
261 #ifdef CONFIG_OMAP2_DSS_DSI
262 int dsi_init(struct platform_device
*pdev
);
265 void dsi_dump_clocks(struct seq_file
*s
);
266 void dsi_dump_irqs(struct seq_file
*s
);
267 void dsi_dump_regs(struct seq_file
*s
);
269 void dsi_save_context(void);
270 void dsi_restore_context(void);
272 int dsi_init_display(struct omap_dss_device
*display
);
273 void dsi_irq_handler(void);
274 unsigned long dsi_get_dsi1_pll_rate(void);
275 int dsi_pll_set_clock_div(struct dsi_clock_info
*cinfo
);
276 int dsi_pll_calc_clock_div_pck(bool is_tft
, unsigned long req_pck
,
277 struct dsi_clock_info
*cinfo
,
278 struct dispc_clock_info
*dispc_cinfo
);
279 int dsi_pll_init(struct omap_dss_device
*dssdev
, bool enable_hsclk
,
281 void dsi_pll_uninit(void);
282 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane
,
283 u32 fifo_size
, enum omap_burst_size
*burst_size
,
284 u32
*fifo_low
, u32
*fifo_high
);
285 void dsi_wait_dsi1_pll_active(void);
286 void dsi_wait_dsi2_pll_active(void);
288 static inline int dsi_init(struct platform_device
*pdev
)
292 static inline void dsi_exit(void)
295 static inline void dsi_wait_dsi1_pll_active(void)
298 static inline void dsi_wait_dsi2_pll_active(void)
304 #ifdef CONFIG_OMAP2_DSS_DPI
305 int dpi_init(struct platform_device
*pdev
);
307 int dpi_init_display(struct omap_dss_device
*dssdev
);
309 static inline int dpi_init(struct platform_device
*pdev
)
313 static inline void dpi_exit(void)
319 int dispc_init(void);
320 void dispc_exit(void);
321 void dispc_dump_clocks(struct seq_file
*s
);
322 void dispc_dump_irqs(struct seq_file
*s
);
323 void dispc_dump_regs(struct seq_file
*s
);
324 void dispc_irq_handler(void);
325 void dispc_fake_vsync_irq(void);
327 void dispc_save_context(void);
328 void dispc_restore_context(void);
330 void dispc_enable_sidle(void);
331 void dispc_disable_sidle(void);
333 void dispc_lcd_enable_signal_polarity(bool act_high
);
334 void dispc_lcd_enable_signal(bool enable
);
335 void dispc_pck_free_enable(bool enable
);
336 void dispc_enable_fifohandcheck(enum omap_channel channel
, bool enable
);
338 void dispc_set_lcd_size(enum omap_channel channel
, u16 width
, u16 height
);
339 void dispc_set_digit_size(u16 width
, u16 height
);
340 u32
dispc_get_plane_fifo_size(enum omap_plane plane
);
341 void dispc_setup_plane_fifo(enum omap_plane plane
, u32 low
, u32 high
);
342 void dispc_enable_fifomerge(bool enable
);
343 void dispc_set_burst_size(enum omap_plane plane
,
344 enum omap_burst_size burst_size
);
346 void dispc_set_plane_ba0(enum omap_plane plane
, u32 paddr
);
347 void dispc_set_plane_ba1(enum omap_plane plane
, u32 paddr
);
348 void dispc_set_plane_pos(enum omap_plane plane
, u16 x
, u16 y
);
349 void dispc_set_plane_size(enum omap_plane plane
, u16 width
, u16 height
);
350 void dispc_set_channel_out(enum omap_plane plane
,
351 enum omap_channel channel_out
);
353 int dispc_setup_plane(enum omap_plane plane
,
354 u32 paddr
, u16 screen_width
,
355 u16 pos_x
, u16 pos_y
,
356 u16 width
, u16 height
,
357 u16 out_width
, u16 out_height
,
358 enum omap_color_mode color_mode
,
360 enum omap_dss_rotation_type rotation_type
,
361 u8 rotation
, bool mirror
,
362 u8 global_alpha
, u8 pre_mult_alpha
,
363 enum omap_channel channel
);
365 bool dispc_go_busy(enum omap_channel channel
);
366 void dispc_go(enum omap_channel channel
);
367 void dispc_enable_channel(enum omap_channel channel
, bool enable
);
368 bool dispc_is_channel_enabled(enum omap_channel channel
);
369 int dispc_enable_plane(enum omap_plane plane
, bool enable
);
370 void dispc_enable_replication(enum omap_plane plane
, bool enable
);
372 void dispc_set_parallel_interface_mode(enum omap_channel channel
,
373 enum omap_parallel_interface_mode mode
);
374 void dispc_set_tft_data_lines(enum omap_channel channel
, u8 data_lines
);
375 void dispc_set_lcd_display_type(enum omap_channel channel
,
376 enum omap_lcd_display_type type
);
377 void dispc_set_loadmode(enum omap_dss_load_mode mode
);
379 void dispc_set_default_color(enum omap_channel channel
, u32 color
);
380 u32
dispc_get_default_color(enum omap_channel channel
);
381 void dispc_set_trans_key(enum omap_channel ch
,
382 enum omap_dss_trans_key_type type
,
384 void dispc_get_trans_key(enum omap_channel ch
,
385 enum omap_dss_trans_key_type
*type
,
387 void dispc_enable_trans_key(enum omap_channel ch
, bool enable
);
388 void dispc_enable_alpha_blending(enum omap_channel ch
, bool enable
);
389 bool dispc_trans_key_enabled(enum omap_channel ch
);
390 bool dispc_alpha_blending_enabled(enum omap_channel ch
);
392 bool dispc_lcd_timings_ok(struct omap_video_timings
*timings
);
393 void dispc_set_lcd_timings(enum omap_channel channel
,
394 struct omap_video_timings
*timings
);
395 unsigned long dispc_fclk_rate(void);
396 unsigned long dispc_lclk_rate(enum omap_channel channel
);
397 unsigned long dispc_pclk_rate(enum omap_channel channel
);
398 void dispc_set_pol_freq(enum omap_channel channel
,
399 enum omap_panel_config config
, u8 acbi
, u8 acb
);
400 void dispc_find_clk_divs(bool is_tft
, unsigned long req_pck
, unsigned long fck
,
401 struct dispc_clock_info
*cinfo
);
402 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate
,
403 struct dispc_clock_info
*cinfo
);
404 int dispc_set_clock_div(enum omap_channel channel
,
405 struct dispc_clock_info
*cinfo
);
406 int dispc_get_clock_div(enum omap_channel channel
,
407 struct dispc_clock_info
*cinfo
);
411 #ifdef CONFIG_OMAP2_DSS_VENC
412 int venc_init(struct platform_device
*pdev
);
413 void venc_exit(void);
414 void venc_dump_regs(struct seq_file
*s
);
415 int venc_init_display(struct omap_dss_device
*display
);
417 static inline int venc_init(struct platform_device
*pdev
)
421 static inline void venc_exit(void)
427 #ifdef CONFIG_OMAP2_DSS_RFBI
429 void rfbi_exit(void);
430 void rfbi_dump_regs(struct seq_file
*s
);
432 int rfbi_configure(int rfbi_module
, int bpp
, int lines
);
433 void rfbi_enable_rfbi(bool enable
);
434 void rfbi_transfer_area(struct omap_dss_device
*dssdev
, u16 width
,
435 u16 height
, void (callback
)(void *data
), void *data
);
436 void rfbi_set_timings(int rfbi_module
, struct rfbi_timings
*t
);
437 unsigned long rfbi_get_max_tx_rate(void);
438 int rfbi_init_display(struct omap_dss_device
*display
);
440 static inline int rfbi_init(void)
444 static inline void rfbi_exit(void)
450 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
451 static inline void dss_collect_irq_stats(u32 irqstatus
, unsigned *irq_arr
)
454 for (b
= 0; b
< 32; ++b
) {
455 if (irqstatus
& (1 << b
))