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[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
1 /*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "HDMI"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <video/omapdss.h>
38
39 #include "ti_hdmi.h"
40 #include "dss.h"
41 #include "dss_features.h"
42
43 #define HDMI_WP 0x0
44 #define HDMI_CORE_SYS 0x400
45 #define HDMI_CORE_AV 0x900
46 #define HDMI_PLLCTRL 0x200
47 #define HDMI_PHY 0x300
48
49 /* HDMI EDID Length move this */
50 #define HDMI_EDID_MAX_LENGTH 256
51 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
57 #define HDMI_DEFAULT_REGN 16
58 #define HDMI_DEFAULT_REGM2 1
59
60 static struct {
61 struct mutex lock;
62 struct platform_device *pdev;
63 struct hdmi_ip_data ip_data;
64
65 struct clk *sys_clk;
66 struct regulator *vdda_hdmi_dac_reg;
67
68 int ct_cp_hpd_gpio;
69 int ls_oe_gpio;
70 int hpd_gpio;
71
72 struct omap_dss_output output;
73 } hdmi;
74
75 /*
76 * Logic for the below structure :
77 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
78 * There is a correspondence between CEA/VESA timing and code, please
79 * refer to section 6.3 in HDMI 1.3 specification for timing code.
80 *
81 * In the below structure, cea_vesa_timings corresponds to all OMAP4
82 * supported CEA and VESA timing values.code_cea corresponds to the CEA
83 * code, It is used to get the timing from cea_vesa_timing array.Similarly
84 * with code_vesa. Code_index is used for back mapping, that is once EDID
85 * is read from the TV, EDID is parsed to find the timing values and then
86 * map it to corresponding CEA or VESA index.
87 */
88
89 static const struct hdmi_config cea_timings[] = {
90 {
91 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
92 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
93 false, },
94 { 1, HDMI_HDMI },
95 },
96 {
97 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
98 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
99 false, },
100 { 2, HDMI_HDMI },
101 },
102 {
103 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
104 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
105 false, },
106 { 4, HDMI_HDMI },
107 },
108 {
109 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
110 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
111 true, },
112 { 5, HDMI_HDMI },
113 },
114 {
115 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
116 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
117 true, },
118 { 6, HDMI_HDMI },
119 },
120 {
121 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
122 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
123 false, },
124 { 16, HDMI_HDMI },
125 },
126 {
127 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
128 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
129 false, },
130 { 17, HDMI_HDMI },
131 },
132 {
133 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
134 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
135 false, },
136 { 19, HDMI_HDMI },
137 },
138 {
139 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
140 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
141 true, },
142 { 20, HDMI_HDMI },
143 },
144 {
145 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
146 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
147 true, },
148 { 21, HDMI_HDMI },
149 },
150 {
151 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
152 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
153 false, },
154 { 29, HDMI_HDMI },
155 },
156 {
157 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
158 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
159 false, },
160 { 31, HDMI_HDMI },
161 },
162 {
163 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
164 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
165 false, },
166 { 32, HDMI_HDMI },
167 },
168 {
169 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
170 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
171 false, },
172 { 35, HDMI_HDMI },
173 },
174 {
175 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
176 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
177 false, },
178 { 37, HDMI_HDMI },
179 },
180 };
181
182 static const struct hdmi_config vesa_timings[] = {
183 /* VESA From Here */
184 {
185 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
186 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
187 false, },
188 { 4, HDMI_DVI },
189 },
190 {
191 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
192 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
193 false, },
194 { 9, HDMI_DVI },
195 },
196 {
197 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
198 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
199 false, },
200 { 0xE, HDMI_DVI },
201 },
202 {
203 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
204 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
205 false, },
206 { 0x17, HDMI_DVI },
207 },
208 {
209 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
210 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
211 false, },
212 { 0x1C, HDMI_DVI },
213 },
214 {
215 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
216 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
217 false, },
218 { 0x27, HDMI_DVI },
219 },
220 {
221 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
222 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
223 false, },
224 { 0x20, HDMI_DVI },
225 },
226 {
227 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
228 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
229 false, },
230 { 0x23, HDMI_DVI },
231 },
232 {
233 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
234 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
235 false, },
236 { 0x10, HDMI_DVI },
237 },
238 {
239 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
240 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
241 false, },
242 { 0x2A, HDMI_DVI },
243 },
244 {
245 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
246 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
247 false, },
248 { 0x2F, HDMI_DVI },
249 },
250 {
251 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
252 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
253 false, },
254 { 0x3A, HDMI_DVI },
255 },
256 {
257 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
258 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
259 false, },
260 { 0x51, HDMI_DVI },
261 },
262 {
263 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
264 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
265 false, },
266 { 0x52, HDMI_DVI },
267 },
268 {
269 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
270 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
271 false, },
272 { 0x16, HDMI_DVI },
273 },
274 {
275 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
276 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
277 false, },
278 { 0x29, HDMI_DVI },
279 },
280 {
281 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
282 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
283 false, },
284 { 0x39, HDMI_DVI },
285 },
286 {
287 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
288 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
289 false, },
290 { 0x1B, HDMI_DVI },
291 },
292 {
293 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
294 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
295 false, },
296 { 0x55, HDMI_DVI },
297 },
298 };
299
300 static int hdmi_runtime_get(void)
301 {
302 int r;
303
304 DSSDBG("hdmi_runtime_get\n");
305
306 r = pm_runtime_get_sync(&hdmi.pdev->dev);
307 WARN_ON(r < 0);
308 if (r < 0)
309 return r;
310
311 return 0;
312 }
313
314 static void hdmi_runtime_put(void)
315 {
316 int r;
317
318 DSSDBG("hdmi_runtime_put\n");
319
320 r = pm_runtime_put_sync(&hdmi.pdev->dev);
321 WARN_ON(r < 0 && r != -ENOSYS);
322 }
323
324 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
325 {
326 int r;
327
328 struct gpio gpios[] = {
329 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
330 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
331 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
332 };
333
334 DSSDBG("init_display\n");
335
336 dss_init_hdmi_ip_ops(&hdmi.ip_data);
337
338 if (hdmi.vdda_hdmi_dac_reg == NULL) {
339 struct regulator *reg;
340
341 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
342
343 if (IS_ERR(reg)) {
344 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
345 return PTR_ERR(reg);
346 }
347
348 hdmi.vdda_hdmi_dac_reg = reg;
349 }
350
351 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
352 if (r)
353 return r;
354
355 return 0;
356 }
357
358 static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
359 {
360 DSSDBG("uninit_display\n");
361
362 gpio_free(hdmi.ct_cp_hpd_gpio);
363 gpio_free(hdmi.ls_oe_gpio);
364 gpio_free(hdmi.hpd_gpio);
365 }
366
367 static const struct hdmi_config *hdmi_find_timing(
368 const struct hdmi_config *timings_arr,
369 int len)
370 {
371 int i;
372
373 for (i = 0; i < len; i++) {
374 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
375 return &timings_arr[i];
376 }
377 return NULL;
378 }
379
380 static const struct hdmi_config *hdmi_get_timings(void)
381 {
382 const struct hdmi_config *arr;
383 int len;
384
385 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
386 arr = vesa_timings;
387 len = ARRAY_SIZE(vesa_timings);
388 } else {
389 arr = cea_timings;
390 len = ARRAY_SIZE(cea_timings);
391 }
392
393 return hdmi_find_timing(arr, len);
394 }
395
396 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
397 const struct omap_video_timings *timing2)
398 {
399 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
400
401 if ((timing2->pixel_clock == timing1->pixel_clock) &&
402 (timing2->x_res == timing1->x_res) &&
403 (timing2->y_res == timing1->y_res)) {
404
405 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
406 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
407 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
408 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
409
410 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
411 "timing2_hsync = %d timing2_vsync = %d\n",
412 timing1_hsync, timing1_vsync,
413 timing2_hsync, timing2_vsync);
414
415 if ((timing1_hsync == timing2_hsync) &&
416 (timing1_vsync == timing2_vsync)) {
417 return true;
418 }
419 }
420 return false;
421 }
422
423 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
424 {
425 int i;
426 struct hdmi_cm cm = {-1};
427 DSSDBG("hdmi_get_code\n");
428
429 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
430 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
431 cm = cea_timings[i].cm;
432 goto end;
433 }
434 }
435 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
436 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
437 cm = vesa_timings[i].cm;
438 goto end;
439 }
440 }
441
442 end: return cm;
443
444 }
445
446 unsigned long hdmi_get_pixel_clock(void)
447 {
448 /* HDMI Pixel Clock in Mhz */
449 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
450 }
451
452 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
453 struct hdmi_pll_info *pi)
454 {
455 unsigned long clkin, refclk;
456 u32 mf;
457
458 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
459 /*
460 * Input clock is predivided by N + 1
461 * out put of which is reference clk
462 */
463 if (dssdev->clocks.hdmi.regn == 0)
464 pi->regn = HDMI_DEFAULT_REGN;
465 else
466 pi->regn = dssdev->clocks.hdmi.regn;
467
468 refclk = clkin / pi->regn;
469
470 if (dssdev->clocks.hdmi.regm2 == 0)
471 pi->regm2 = HDMI_DEFAULT_REGM2;
472 else
473 pi->regm2 = dssdev->clocks.hdmi.regm2;
474
475 /*
476 * multiplier is pixel_clk/ref_clk
477 * Multiplying by 100 to avoid fractional part removal
478 */
479 pi->regm = phy * pi->regm2 / refclk;
480
481 /*
482 * fractional multiplier is remainder of the difference between
483 * multiplier and actual phy(required pixel clock thus should be
484 * multiplied by 2^18(262144) divided by the reference clock
485 */
486 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
487 pi->regmf = pi->regm2 * mf / refclk;
488
489 /*
490 * Dcofreq should be set to 1 if required pixel clock
491 * is greater than 1000MHz
492 */
493 pi->dcofreq = phy > 1000 * 100;
494 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
495
496 /* Set the reference clock to sysclk reference */
497 pi->refsel = HDMI_REFSEL_SYSCLK;
498
499 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
500 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
501 }
502
503 static int hdmi_power_on(struct omap_dss_device *dssdev)
504 {
505 int r;
506 struct omap_video_timings *p;
507 unsigned long phy;
508
509 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
510 gpio_set_value(hdmi.ls_oe_gpio, 1);
511
512 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
513 udelay(300);
514
515 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
516 if (r)
517 goto err_vdac_enable;
518
519 r = hdmi_runtime_get();
520 if (r)
521 goto err_runtime_get;
522
523 dss_mgr_disable(dssdev->manager);
524
525 p = &hdmi.ip_data.cfg.timings;
526
527 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
528
529 phy = p->pixel_clock;
530
531 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
532
533 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
534
535 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
536 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
537 if (r) {
538 DSSDBG("Failed to lock PLL\n");
539 goto err_pll_enable;
540 }
541
542 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
543 if (r) {
544 DSSDBG("Failed to start PHY\n");
545 goto err_phy_enable;
546 }
547
548 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
549
550 /* Make selection of HDMI in DSS */
551 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
552
553 /* Select the dispc clock source as PRCM clock, to ensure that it is not
554 * DSI PLL source as the clock selected by DSI PLL might not be
555 * sufficient for the resolution selected / that can be changed
556 * dynamically by user. This can be moved to single location , say
557 * Boardfile.
558 */
559 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
560
561 /* bypass TV gamma table */
562 dispc_enable_gamma_table(0);
563
564 /* tv size */
565 dss_mgr_set_timings(dssdev->manager, p);
566
567 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
568 if (r)
569 goto err_vid_enable;
570
571 r = dss_mgr_enable(dssdev->manager);
572 if (r)
573 goto err_mgr_enable;
574
575 return 0;
576
577 err_mgr_enable:
578 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
579 err_vid_enable:
580 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
581 err_phy_enable:
582 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
583 err_pll_enable:
584 hdmi_runtime_put();
585 err_runtime_get:
586 regulator_disable(hdmi.vdda_hdmi_dac_reg);
587 err_vdac_enable:
588 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
589 gpio_set_value(hdmi.ls_oe_gpio, 0);
590 return -EIO;
591 }
592
593 static void hdmi_power_off(struct omap_dss_device *dssdev)
594 {
595 dss_mgr_disable(dssdev->manager);
596
597 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
598 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
599 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
600 hdmi_runtime_put();
601
602 regulator_disable(hdmi.vdda_hdmi_dac_reg);
603
604 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
605 gpio_set_value(hdmi.ls_oe_gpio, 0);
606 }
607
608 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
609 struct omap_video_timings *timings)
610 {
611 struct hdmi_cm cm;
612
613 cm = hdmi_get_code(timings);
614 if (cm.code == -1) {
615 return -EINVAL;
616 }
617
618 return 0;
619
620 }
621
622 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
623 struct omap_video_timings *timings)
624 {
625 struct hdmi_cm cm;
626 const struct hdmi_config *t;
627
628 mutex_lock(&hdmi.lock);
629
630 cm = hdmi_get_code(timings);
631 hdmi.ip_data.cfg.cm = cm;
632
633 t = hdmi_get_timings();
634 if (t != NULL)
635 hdmi.ip_data.cfg = *t;
636
637 mutex_unlock(&hdmi.lock);
638 }
639
640 static void hdmi_dump_regs(struct seq_file *s)
641 {
642 mutex_lock(&hdmi.lock);
643
644 if (hdmi_runtime_get())
645 return;
646
647 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
648 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
649 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
650 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
651
652 hdmi_runtime_put();
653 mutex_unlock(&hdmi.lock);
654 }
655
656 int omapdss_hdmi_read_edid(u8 *buf, int len)
657 {
658 int r;
659
660 mutex_lock(&hdmi.lock);
661
662 r = hdmi_runtime_get();
663 BUG_ON(r);
664
665 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
666
667 hdmi_runtime_put();
668 mutex_unlock(&hdmi.lock);
669
670 return r;
671 }
672
673 bool omapdss_hdmi_detect(void)
674 {
675 int r;
676
677 mutex_lock(&hdmi.lock);
678
679 r = hdmi_runtime_get();
680 BUG_ON(r);
681
682 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
683
684 hdmi_runtime_put();
685 mutex_unlock(&hdmi.lock);
686
687 return r == 1;
688 }
689
690 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
691 {
692 int r = 0;
693
694 DSSDBG("ENTER hdmi_display_enable\n");
695
696 mutex_lock(&hdmi.lock);
697
698 if (dssdev->manager == NULL) {
699 DSSERR("failed to enable display: no manager\n");
700 r = -ENODEV;
701 goto err0;
702 }
703
704 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
705
706 r = omap_dss_start_device(dssdev);
707 if (r) {
708 DSSERR("failed to start device\n");
709 goto err0;
710 }
711
712 r = hdmi_power_on(dssdev);
713 if (r) {
714 DSSERR("failed to power on device\n");
715 goto err1;
716 }
717
718 mutex_unlock(&hdmi.lock);
719 return 0;
720
721 err1:
722 omap_dss_stop_device(dssdev);
723 err0:
724 mutex_unlock(&hdmi.lock);
725 return r;
726 }
727
728 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
729 {
730 DSSDBG("Enter hdmi_display_disable\n");
731
732 mutex_lock(&hdmi.lock);
733
734 hdmi_power_off(dssdev);
735
736 omap_dss_stop_device(dssdev);
737
738 mutex_unlock(&hdmi.lock);
739 }
740
741 static int hdmi_get_clocks(struct platform_device *pdev)
742 {
743 struct clk *clk;
744
745 clk = clk_get(&pdev->dev, "sys_clk");
746 if (IS_ERR(clk)) {
747 DSSERR("can't get sys_clk\n");
748 return PTR_ERR(clk);
749 }
750
751 hdmi.sys_clk = clk;
752
753 return 0;
754 }
755
756 static void hdmi_put_clocks(void)
757 {
758 if (hdmi.sys_clk)
759 clk_put(hdmi.sys_clk);
760 }
761
762 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
763 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
764 {
765 u32 deep_color;
766 bool deep_color_correct = false;
767 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
768
769 if (n == NULL || cts == NULL)
770 return -EINVAL;
771
772 /* TODO: When implemented, query deep color mode here. */
773 deep_color = 100;
774
775 /*
776 * When using deep color, the default N value (as in the HDMI
777 * specification) yields to an non-integer CTS. Hence, we
778 * modify it while keeping the restrictions described in
779 * section 7.2.1 of the HDMI 1.4a specification.
780 */
781 switch (sample_freq) {
782 case 32000:
783 case 48000:
784 case 96000:
785 case 192000:
786 if (deep_color == 125)
787 if (pclk == 27027 || pclk == 74250)
788 deep_color_correct = true;
789 if (deep_color == 150)
790 if (pclk == 27027)
791 deep_color_correct = true;
792 break;
793 case 44100:
794 case 88200:
795 case 176400:
796 if (deep_color == 125)
797 if (pclk == 27027)
798 deep_color_correct = true;
799 break;
800 default:
801 return -EINVAL;
802 }
803
804 if (deep_color_correct) {
805 switch (sample_freq) {
806 case 32000:
807 *n = 8192;
808 break;
809 case 44100:
810 *n = 12544;
811 break;
812 case 48000:
813 *n = 8192;
814 break;
815 case 88200:
816 *n = 25088;
817 break;
818 case 96000:
819 *n = 16384;
820 break;
821 case 176400:
822 *n = 50176;
823 break;
824 case 192000:
825 *n = 32768;
826 break;
827 default:
828 return -EINVAL;
829 }
830 } else {
831 switch (sample_freq) {
832 case 32000:
833 *n = 4096;
834 break;
835 case 44100:
836 *n = 6272;
837 break;
838 case 48000:
839 *n = 6144;
840 break;
841 case 88200:
842 *n = 12544;
843 break;
844 case 96000:
845 *n = 12288;
846 break;
847 case 176400:
848 *n = 25088;
849 break;
850 case 192000:
851 *n = 24576;
852 break;
853 default:
854 return -EINVAL;
855 }
856 }
857 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
858 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
859
860 return 0;
861 }
862
863 int hdmi_audio_enable(void)
864 {
865 DSSDBG("audio_enable\n");
866
867 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
868 }
869
870 void hdmi_audio_disable(void)
871 {
872 DSSDBG("audio_disable\n");
873
874 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
875 }
876
877 int hdmi_audio_start(void)
878 {
879 DSSDBG("audio_start\n");
880
881 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
882 }
883
884 void hdmi_audio_stop(void)
885 {
886 DSSDBG("audio_stop\n");
887
888 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
889 }
890
891 bool hdmi_mode_has_audio(void)
892 {
893 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
894 return true;
895 else
896 return false;
897 }
898
899 int hdmi_audio_config(struct omap_dss_audio *audio)
900 {
901 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
902 }
903
904 #endif
905
906 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
907 {
908 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
909 const char *def_disp_name = dss_get_default_display_name();
910 struct omap_dss_device *def_dssdev;
911 int i;
912
913 def_dssdev = NULL;
914
915 for (i = 0; i < pdata->num_devices; ++i) {
916 struct omap_dss_device *dssdev = pdata->devices[i];
917
918 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
919 continue;
920
921 if (def_dssdev == NULL)
922 def_dssdev = dssdev;
923
924 if (def_disp_name != NULL &&
925 strcmp(dssdev->name, def_disp_name) == 0) {
926 def_dssdev = dssdev;
927 break;
928 }
929 }
930
931 return def_dssdev;
932 }
933
934 static void __init hdmi_probe_pdata(struct platform_device *pdev)
935 {
936 struct omap_dss_device *plat_dssdev;
937 struct omap_dss_device *dssdev;
938 struct omap_dss_hdmi_data *priv;
939 int r;
940
941 plat_dssdev = hdmi_find_dssdev(pdev);
942
943 if (!plat_dssdev)
944 return;
945
946 dssdev = dss_alloc_and_init_device(&pdev->dev);
947 if (!dssdev)
948 return;
949
950 dss_copy_device_pdata(dssdev, plat_dssdev);
951
952 priv = dssdev->data;
953
954 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
955 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
956 hdmi.hpd_gpio = priv->hpd_gpio;
957
958 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
959
960 r = hdmi_init_display(dssdev);
961 if (r) {
962 DSSERR("device %s init failed: %d\n", dssdev->name, r);
963 dss_put_device(dssdev);
964 return;
965 }
966
967 r = dss_add_device(dssdev);
968 if (r) {
969 DSSERR("device %s register failed: %d\n", dssdev->name, r);
970 dss_put_device(dssdev);
971 return;
972 }
973 }
974
975 static void __init hdmi_init_output(struct platform_device *pdev)
976 {
977 struct omap_dss_output *out = &hdmi.output;
978
979 out->pdev = pdev;
980 out->id = OMAP_DSS_OUTPUT_HDMI;
981 out->type = OMAP_DISPLAY_TYPE_HDMI;
982
983 dss_register_output(out);
984 }
985
986 static void __exit hdmi_uninit_output(struct platform_device *pdev)
987 {
988 struct omap_dss_output *out = &hdmi.output;
989
990 dss_unregister_output(out);
991 }
992
993 /* HDMI HW IP initialisation */
994 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
995 {
996 struct resource *hdmi_mem;
997 int r;
998
999 hdmi.pdev = pdev;
1000
1001 mutex_init(&hdmi.lock);
1002
1003 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1004 if (!hdmi_mem) {
1005 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1006 return -EINVAL;
1007 }
1008
1009 /* Base address taken from platform */
1010 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
1011 resource_size(hdmi_mem));
1012 if (!hdmi.ip_data.base_wp) {
1013 DSSERR("can't ioremap WP\n");
1014 return -ENOMEM;
1015 }
1016
1017 r = hdmi_get_clocks(pdev);
1018 if (r) {
1019 iounmap(hdmi.ip_data.base_wp);
1020 return r;
1021 }
1022
1023 pm_runtime_enable(&pdev->dev);
1024
1025 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1026 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1027 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1028 hdmi.ip_data.phy_offset = HDMI_PHY;
1029
1030 mutex_init(&hdmi.ip_data.lock);
1031
1032 hdmi_panel_init();
1033
1034 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1035
1036 hdmi_init_output(pdev);
1037
1038 hdmi_probe_pdata(pdev);
1039
1040 return 0;
1041 }
1042
1043 static int __exit hdmi_remove_child(struct device *dev, void *data)
1044 {
1045 struct omap_dss_device *dssdev = to_dss_device(dev);
1046 hdmi_uninit_display(dssdev);
1047 return 0;
1048 }
1049
1050 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1051 {
1052 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1053
1054 dss_unregister_child_devices(&pdev->dev);
1055
1056 hdmi_panel_exit();
1057
1058 hdmi_uninit_output(pdev);
1059
1060 pm_runtime_disable(&pdev->dev);
1061
1062 hdmi_put_clocks();
1063
1064 iounmap(hdmi.ip_data.base_wp);
1065
1066 return 0;
1067 }
1068
1069 static int hdmi_runtime_suspend(struct device *dev)
1070 {
1071 clk_disable_unprepare(hdmi.sys_clk);
1072
1073 dispc_runtime_put();
1074
1075 return 0;
1076 }
1077
1078 static int hdmi_runtime_resume(struct device *dev)
1079 {
1080 int r;
1081
1082 r = dispc_runtime_get();
1083 if (r < 0)
1084 return r;
1085
1086 clk_prepare_enable(hdmi.sys_clk);
1087
1088 return 0;
1089 }
1090
1091 static const struct dev_pm_ops hdmi_pm_ops = {
1092 .runtime_suspend = hdmi_runtime_suspend,
1093 .runtime_resume = hdmi_runtime_resume,
1094 };
1095
1096 static struct platform_driver omapdss_hdmihw_driver = {
1097 .remove = __exit_p(omapdss_hdmihw_remove),
1098 .driver = {
1099 .name = "omapdss_hdmi",
1100 .owner = THIS_MODULE,
1101 .pm = &hdmi_pm_ops,
1102 },
1103 };
1104
1105 int __init hdmi_init_platform_driver(void)
1106 {
1107 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
1108 }
1109
1110 void __exit hdmi_uninit_platform_driver(void)
1111 {
1112 platform_driver_unregister(&omapdss_hdmihw_driver);
1113 }
Linux kernel - Deliverables
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