drivers/video/omap2/dss/hdmi.c

   1 /*
   2  * hdmi.c
   3  *
   4  * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #define DSS_SUBSYS_NAME "HDMI"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/err.h>
  27 #include <linux/io.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/mutex.h>
  30 #include <linux/delay.h>
  31 #include <linux/string.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/clk.h>
  35 #include <linux/gpio.h>
  36 #include <linux/regulator/consumer.h>
  37 #include <video/omapdss.h>
  38
  39 #include "ti_hdmi.h"
  40 #include "dss.h"
  41 #include "dss_features.h"
  42
  43 #define HDMI_WP                 0x0
  44 #define HDMI_CORE_SYS           0x400
  45 #define HDMI_CORE_AV            0x900
  46 #define HDMI_PLLCTRL            0x200
  47 #define HDMI_PHY                0x300
  48
  49 /* HDMI EDID Length move this */
  50 #define HDMI_EDID_MAX_LENGTH                    256
  51 #define EDID_TIMING_DESCRIPTOR_SIZE             0x12
  52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS          0x36
  53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS          0x80
  54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR      4
  55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR      4
  56
  57 #define HDMI_DEFAULT_REGN 16
  58 #define HDMI_DEFAULT_REGM2 1
  59
  60 static struct {
  61         struct mutex lock;
  62         struct platform_device *pdev;
  63
  64         struct hdmi_ip_data ip_data;
  65
  66         struct clk *sys_clk;
  67         struct regulator *vdda_hdmi_dac_reg;
  68
  69         int ct_cp_hpd_gpio;
  70         int ls_oe_gpio;
  71         int hpd_gpio;
  72
  73         struct omap_dss_device output;
  74 } hdmi;
  75
  76 /*
  77  * Logic for the below structure :
  78  * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
  79  * There is a correspondence between CEA/VESA timing and code, please
  80  * refer to section 6.3 in HDMI 1.3 specification for timing code.
  81  *
  82  * In the below structure, cea_vesa_timings corresponds to all OMAP4
  83  * supported CEA and VESA timing values.code_cea corresponds to the CEA
  84  * code, It is used to get the timing from cea_vesa_timing array.Similarly
  85  * with code_vesa. Code_index is used for back mapping, that is once EDID
  86  * is read from the TV, EDID is parsed to find the timing values and then
  87  * map it to corresponding CEA or VESA index.
  88  */
  89
  90 static const struct hdmi_config cea_timings[] = {
  91         {
  92                 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
  93                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
  94                         false, },
  95                 { 1, HDMI_HDMI },
  96         },
  97         {
  98                 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
  99                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 100                         false, },
 101                 { 2, HDMI_HDMI },
 102         },
 103         {
 104                 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
 105                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 106                         false, },
 107                 { 4, HDMI_HDMI },
 108         },
 109         {
 110                 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
 111                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 112                         true, },
 113                 { 5, HDMI_HDMI },
 114         },
 115         {
 116                 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
 117                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 118                         true, },
 119                 { 6, HDMI_HDMI },
 120         },
 121         {
 122                 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
 123                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 124                         false, },
 125                 { 16, HDMI_HDMI },
 126         },
 127         {
 128                 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
 129                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 130                         false, },
 131                 { 17, HDMI_HDMI },
 132         },
 133         {
 134                 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
 135                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 136                         false, },
 137                 { 19, HDMI_HDMI },
 138         },
 139         {
 140                 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
 141                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 142                         true, },
 143                 { 20, HDMI_HDMI },
 144         },
 145         {
 146                 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
 147                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 148                         true, },
 149                 { 21, HDMI_HDMI },
 150         },
 151         {
 152                 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
 153                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 154                         false, },
 155                 { 29, HDMI_HDMI },
 156         },
 157         {
 158                 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
 159                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 160                         false, },
 161                 { 31, HDMI_HDMI },
 162         },
 163         {
 164                 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
 165                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 166                         false, },
 167                 { 32, HDMI_HDMI },
 168         },
 169         {
 170                 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
 171                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 172                         false, },
 173                 { 35, HDMI_HDMI },
 174         },
 175         {
 176                 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
 177                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 178                         false, },
 179                 { 37, HDMI_HDMI },
 180         },
 181 };
 182
 183 static const struct hdmi_config vesa_timings[] = {
 184 /* VESA From Here */
 185         {
 186                 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
 187                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 188                         false, },
 189                 { 4, HDMI_DVI },
 190         },
 191         {
 192                 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
 193                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 194                         false, },
 195                 { 9, HDMI_DVI },
 196         },
 197         {
 198                 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
 199                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 200                         false, },
 201                 { 0xE, HDMI_DVI },
 202         },
 203         {
 204                 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
 205                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
 206                         false, },
 207                 { 0x17, HDMI_DVI },
 208         },
 209         {
 210                 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
 211                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
 212                         false, },
 213                 { 0x1C, HDMI_DVI },
 214         },
 215         {
 216                 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
 217                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 218                         false, },
 219                 { 0x27, HDMI_DVI },
 220         },
 221         {
 222                 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
 223                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 224                         false, },
 225                 { 0x20, HDMI_DVI },
 226         },
 227         {
 228                 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
 229                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 230                         false, },
 231                 { 0x23, HDMI_DVI },
 232         },
 233         {
 234                 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
 235                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
 236                         false, },
 237                 { 0x10, HDMI_DVI },
 238         },
 239         {
 240                 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
 241                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
 242                         false, },
 243                 { 0x2A, HDMI_DVI },
 244         },
 245         {
 246                 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
 247                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
 248                         false, },
 249                 { 0x2F, HDMI_DVI },
 250         },
 251         {
 252                 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
 253                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
 254                         false, },
 255                 { 0x3A, HDMI_DVI },
 256         },
 257         {
 258                 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
 259                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 260                         false, },
 261                 { 0x51, HDMI_DVI },
 262         },
 263         {
 264                 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
 265                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 266                         false, },
 267                 { 0x52, HDMI_DVI },
 268         },
 269         {
 270                 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
 271                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
 272                         false, },
 273                 { 0x16, HDMI_DVI },
 274         },
 275         {
 276                 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
 277                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
 278                         false, },
 279                 { 0x29, HDMI_DVI },
 280         },
 281         {
 282                 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
 283                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
 284                         false, },
 285                 { 0x39, HDMI_DVI },
 286         },
 287         {
 288                 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
 289                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
 290                         false, },
 291                 { 0x1B, HDMI_DVI },
 292         },
 293         {
 294                 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
 295                         OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
 296                         false, },
 297                 { 0x55, HDMI_DVI },
 298         },
 299         {
 300                 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
 301                         OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
 302                         false, },
 303                 { 0x44, HDMI_DVI },
 304         },
 305 };
 306
 307 static int hdmi_runtime_get(void)
 308 {
 309         int r;
 310
 311         DSSDBG("hdmi_runtime_get\n");
 312
 313         r = pm_runtime_get_sync(&hdmi.pdev->dev);
 314         WARN_ON(r < 0);
 315         if (r < 0)
 316                 return r;
 317
 318         return 0;
 319 }
 320
 321 static void hdmi_runtime_put(void)
 322 {
 323         int r;
 324
 325         DSSDBG("hdmi_runtime_put\n");
 326
 327         r = pm_runtime_put_sync(&hdmi.pdev->dev);
 328         WARN_ON(r < 0 && r != -ENOSYS);
 329 }
 330
 331 static int hdmi_init_regulator(void)
 332 {
 333         struct regulator *reg;
 334
 335         if (hdmi.vdda_hdmi_dac_reg != NULL)
 336                 return 0;
 337
 338         reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
 339
 340         /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
 341         if (IS_ERR(reg))
 342                 reg = devm_regulator_get(&hdmi.pdev->dev, "VDAC");
 343
 344         if (IS_ERR(reg)) {
 345                 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
 346                 return PTR_ERR(reg);
 347         }
 348
 349         hdmi.vdda_hdmi_dac_reg = reg;
 350
 351         return 0;
 352 }
 353
 354 static int hdmi_init_display(struct omap_dss_device *dssdev)
 355 {
 356         int r;
 357
 358         struct gpio gpios[] = {
 359                 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
 360                 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
 361                 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
 362         };
 363
 364         DSSDBG("init_display\n");
 365
 366         dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
 367
 368         r = hdmi_init_regulator();
 369         if (r)
 370                 return r;
 371
 372         r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
 373         if (r)
 374                 return r;
 375
 376         return 0;
 377 }
 378
 379 static void hdmi_uninit_display(struct omap_dss_device *dssdev)
 380 {
 381         DSSDBG("uninit_display\n");
 382
 383         gpio_free(hdmi.ct_cp_hpd_gpio);
 384         gpio_free(hdmi.ls_oe_gpio);
 385         gpio_free(hdmi.hpd_gpio);
 386 }
 387
 388 static const struct hdmi_config *hdmi_find_timing(
 389                                         const struct hdmi_config *timings_arr,
 390                                         int len)
 391 {
 392         int i;
 393
 394         for (i = 0; i < len; i++) {
 395                 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
 396                         return &timings_arr[i];
 397         }
 398         return NULL;
 399 }
 400
 401 static const struct hdmi_config *hdmi_get_timings(void)
 402 {
 403        const struct hdmi_config *arr;
 404        int len;
 405
 406        if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
 407                arr = vesa_timings;
 408                len = ARRAY_SIZE(vesa_timings);
 409        } else {
 410                arr = cea_timings;
 411                len = ARRAY_SIZE(cea_timings);
 412        }
 413
 414        return hdmi_find_timing(arr, len);
 415 }
 416
 417 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
 418                                 const struct omap_video_timings *timing2)
 419 {
 420         int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
 421
 422         if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
 423                         DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
 424                 (timing2->x_res == timing1->x_res) &&
 425                 (timing2->y_res == timing1->y_res)) {
 426
 427                 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
 428                 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
 429                 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
 430                 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
 431
 432                 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
 433                         "timing2_hsync = %d timing2_vsync = %d\n",
 434                         timing1_hsync, timing1_vsync,
 435                         timing2_hsync, timing2_vsync);
 436
 437                 if ((timing1_hsync == timing2_hsync) &&
 438                         (timing1_vsync == timing2_vsync)) {
 439                         return true;
 440                 }
 441         }
 442         return false;
 443 }
 444
 445 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
 446 {
 447         int i;
 448         struct hdmi_cm cm = {-1};
 449         DSSDBG("hdmi_get_code\n");
 450
 451         for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
 452                 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
 453                         cm = cea_timings[i].cm;
 454                         goto end;
 455                 }
 456         }
 457         for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
 458                 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
 459                         cm = vesa_timings[i].cm;
 460                         goto end;
 461                 }
 462         }
 463
 464 end:    return cm;
 465
 466 }
 467
 468 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
 469                 struct hdmi_pll_info *pi)
 470 {
 471         unsigned long clkin, refclk;
 472         u32 mf;
 473
 474         clkin = clk_get_rate(hdmi.sys_clk) / 10000;
 475         /*
 476          * Input clock is predivided by N + 1
 477          * out put of which is reference clk
 478          */
 479
 480         pi->regn = HDMI_DEFAULT_REGN;
 481
 482         refclk = clkin / pi->regn;
 483
 484         pi->regm2 = HDMI_DEFAULT_REGM2;
 485
 486         /*
 487          * multiplier is pixel_clk/ref_clk
 488          * Multiplying by 100 to avoid fractional part removal
 489          */
 490         pi->regm = phy * pi->regm2 / refclk;
 491
 492         /*
 493          * fractional multiplier is remainder of the difference between
 494          * multiplier and actual phy(required pixel clock thus should be
 495          * multiplied by 2^18(262144) divided by the reference clock
 496          */
 497         mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
 498         pi->regmf = pi->regm2 * mf / refclk;
 499
 500         /*
 501          * Dcofreq should be set to 1 if required pixel clock
 502          * is greater than 1000MHz
 503          */
 504         pi->dcofreq = phy > 1000 * 100;
 505         pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
 506
 507         /* Set the reference clock to sysclk reference */
 508         pi->refsel = HDMI_REFSEL_SYSCLK;
 509
 510         DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
 511         DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
 512 }
 513
 514 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
 515 {
 516         int r;
 517
 518         gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
 519         gpio_set_value(hdmi.ls_oe_gpio, 1);
 520
 521         /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
 522         udelay(300);
 523
 524         r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
 525         if (r)
 526                 goto err_vdac_enable;
 527
 528         r = hdmi_runtime_get();
 529         if (r)
 530                 goto err_runtime_get;
 531
 532         /* Make selection of HDMI in DSS */
 533         dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
 534
 535         return 0;
 536
 537 err_runtime_get:
 538         regulator_disable(hdmi.vdda_hdmi_dac_reg);
 539 err_vdac_enable:
 540         gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
 541         gpio_set_value(hdmi.ls_oe_gpio, 0);
 542         return r;
 543 }
 544
 545 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
 546 {
 547         hdmi_runtime_put();
 548         regulator_disable(hdmi.vdda_hdmi_dac_reg);
 549         gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
 550         gpio_set_value(hdmi.ls_oe_gpio, 0);
 551 }
 552
 553 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
 554 {
 555         int r;
 556         struct omap_video_timings *p;
 557         struct omap_overlay_manager *mgr = hdmi.output.manager;
 558         unsigned long phy;
 559
 560         r = hdmi_power_on_core(dssdev);
 561         if (r)
 562                 return r;
 563
 564         dss_mgr_disable(mgr);
 565
 566         p = &hdmi.ip_data.cfg.timings;
 567
 568         DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
 569
 570         phy = p->pixel_clock;
 571
 572         hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
 573
 574         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
 575
 576         /* config the PLL and PHY hdmi_set_pll_pwrfirst */
 577         r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
 578         if (r) {
 579                 DSSDBG("Failed to lock PLL\n");
 580                 goto err_pll_enable;
 581         }
 582
 583         r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
 584         if (r) {
 585                 DSSDBG("Failed to start PHY\n");
 586                 goto err_phy_enable;
 587         }
 588
 589         hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
 590
 591         /* bypass TV gamma table */
 592         dispc_enable_gamma_table(0);
 593
 594         /* tv size */
 595         dss_mgr_set_timings(mgr, p);
 596
 597         r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
 598         if (r)
 599                 goto err_vid_enable;
 600
 601         r = dss_mgr_enable(mgr);
 602         if (r)
 603                 goto err_mgr_enable;
 604
 605         return 0;
 606
 607 err_mgr_enable:
 608         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
 609 err_vid_enable:
 610         hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
 611 err_phy_enable:
 612         hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
 613 err_pll_enable:
 614         hdmi_power_off_core(dssdev);
 615         return -EIO;
 616 }
 617
 618 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
 619 {
 620         struct omap_overlay_manager *mgr = hdmi.output.manager;
 621
 622         dss_mgr_disable(mgr);
 623
 624         hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
 625         hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
 626         hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
 627
 628         hdmi_power_off_core(dssdev);
 629 }
 630
 631 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 632                                         struct omap_video_timings *timings)
 633 {
 634         struct hdmi_cm cm;
 635
 636         cm = hdmi_get_code(timings);
 637         if (cm.code == -1) {
 638                 return -EINVAL;
 639         }
 640
 641         return 0;
 642
 643 }
 644
 645 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
 646                 struct omap_video_timings *timings)
 647 {
 648         struct hdmi_cm cm;
 649         const struct hdmi_config *t;
 650
 651         mutex_lock(&hdmi.lock);
 652
 653         cm = hdmi_get_code(timings);
 654         hdmi.ip_data.cfg.cm = cm;
 655
 656         t = hdmi_get_timings();
 657         if (t != NULL)
 658                 hdmi.ip_data.cfg = *t;
 659
 660         dispc_set_tv_pclk(t->timings.pixel_clock * 1000);
 661
 662         mutex_unlock(&hdmi.lock);
 663 }
 664
 665 static void hdmi_dump_regs(struct seq_file *s)
 666 {
 667         mutex_lock(&hdmi.lock);
 668
 669         if (hdmi_runtime_get()) {
 670                 mutex_unlock(&hdmi.lock);
 671                 return;
 672         }
 673
 674         hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
 675         hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
 676         hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
 677         hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
 678
 679         hdmi_runtime_put();
 680         mutex_unlock(&hdmi.lock);
 681 }
 682
 683 int omapdss_hdmi_read_edid(u8 *buf, int len)
 684 {
 685         int r;
 686
 687         mutex_lock(&hdmi.lock);
 688
 689         r = hdmi_runtime_get();
 690         BUG_ON(r);
 691
 692         r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
 693
 694         hdmi_runtime_put();
 695         mutex_unlock(&hdmi.lock);
 696
 697         return r;
 698 }
 699
 700 bool omapdss_hdmi_detect(void)
 701 {
 702         int r;
 703
 704         mutex_lock(&hdmi.lock);
 705
 706         r = hdmi_runtime_get();
 707         BUG_ON(r);
 708
 709         r = gpio_get_value(hdmi.hpd_gpio);
 710
 711         hdmi_runtime_put();
 712         mutex_unlock(&hdmi.lock);
 713
 714         return r == 1;
 715 }
 716
 717 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
 718 {
 719         struct omap_dss_device *out = &hdmi.output;
 720         int r = 0;
 721
 722         DSSDBG("ENTER hdmi_display_enable\n");
 723
 724         mutex_lock(&hdmi.lock);
 725
 726         if (out == NULL || out->manager == NULL) {
 727                 DSSERR("failed to enable display: no output/manager\n");
 728                 r = -ENODEV;
 729                 goto err0;
 730         }
 731
 732         r = hdmi_power_on_full(dssdev);
 733         if (r) {
 734                 DSSERR("failed to power on device\n");
 735                 goto err0;
 736         }
 737
 738         mutex_unlock(&hdmi.lock);
 739         return 0;
 740
 741 err0:
 742         mutex_unlock(&hdmi.lock);
 743         return r;
 744 }
 745
 746 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
 747 {
 748         DSSDBG("Enter hdmi_display_disable\n");
 749
 750         mutex_lock(&hdmi.lock);
 751
 752         hdmi_power_off_full(dssdev);
 753
 754         mutex_unlock(&hdmi.lock);
 755 }
 756
 757 int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
 758 {
 759         int r = 0;
 760
 761         DSSDBG("ENTER omapdss_hdmi_core_enable\n");
 762
 763         mutex_lock(&hdmi.lock);
 764
 765         r = hdmi_power_on_core(dssdev);
 766         if (r) {
 767                 DSSERR("failed to power on device\n");
 768                 goto err0;
 769         }
 770
 771         mutex_unlock(&hdmi.lock);
 772         return 0;
 773
 774 err0:
 775         mutex_unlock(&hdmi.lock);
 776         return r;
 777 }
 778
 779 void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
 780 {
 781         DSSDBG("Enter omapdss_hdmi_core_disable\n");
 782
 783         mutex_lock(&hdmi.lock);
 784
 785         hdmi_power_off_core(dssdev);
 786
 787         mutex_unlock(&hdmi.lock);
 788 }
 789
 790 static int hdmi_get_clocks(struct platform_device *pdev)
 791 {
 792         struct clk *clk;
 793
 794         clk = devm_clk_get(&pdev->dev, "sys_clk");
 795         if (IS_ERR(clk)) {
 796                 DSSERR("can't get sys_clk\n");
 797                 return PTR_ERR(clk);
 798         }
 799
 800         hdmi.sys_clk = clk;
 801
 802         return 0;
 803 }
 804
 805 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
 806 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
 807 {
 808         u32 deep_color;
 809         bool deep_color_correct = false;
 810         u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
 811
 812         if (n == NULL || cts == NULL)
 813                 return -EINVAL;
 814
 815         /* TODO: When implemented, query deep color mode here. */
 816         deep_color = 100;
 817
 818         /*
 819          * When using deep color, the default N value (as in the HDMI
 820          * specification) yields to an non-integer CTS. Hence, we
 821          * modify it while keeping the restrictions described in
 822          * section 7.2.1 of the HDMI 1.4a specification.
 823          */
 824         switch (sample_freq) {
 825         case 32000:
 826         case 48000:
 827         case 96000:
 828         case 192000:
 829                 if (deep_color == 125)
 830                         if (pclk == 27027 || pclk == 74250)
 831                                 deep_color_correct = true;
 832                 if (deep_color == 150)
 833                         if (pclk == 27027)
 834                                 deep_color_correct = true;
 835                 break;
 836         case 44100:
 837         case 88200:
 838         case 176400:
 839                 if (deep_color == 125)
 840                         if (pclk == 27027)
 841                                 deep_color_correct = true;
 842                 break;
 843         default:
 844                 return -EINVAL;
 845         }
 846
 847         if (deep_color_correct) {
 848                 switch (sample_freq) {
 849                 case 32000:
 850                         *n = 8192;
 851                         break;
 852                 case 44100:
 853                         *n = 12544;
 854                         break;
 855                 case 48000:
 856                         *n = 8192;
 857                         break;
 858                 case 88200:
 859                         *n = 25088;
 860                         break;
 861                 case 96000:
 862                         *n = 16384;
 863                         break;
 864                 case 176400:
 865                         *n = 50176;
 866                         break;
 867                 case 192000:
 868                         *n = 32768;
 869                         break;
 870                 default:
 871                         return -EINVAL;
 872                 }
 873         } else {
 874                 switch (sample_freq) {
 875                 case 32000:
 876                         *n = 4096;
 877                         break;
 878                 case 44100:
 879                         *n = 6272;
 880                         break;
 881                 case 48000:
 882                         *n = 6144;
 883                         break;
 884                 case 88200:
 885                         *n = 12544;
 886                         break;
 887                 case 96000:
 888                         *n = 12288;
 889                         break;
 890                 case 176400:
 891                         *n = 25088;
 892                         break;
 893                 case 192000:
 894                         *n = 24576;
 895                         break;
 896                 default:
 897                         return -EINVAL;
 898                 }
 899         }
 900         /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
 901         *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
 902
 903         return 0;
 904 }
 905
 906 int hdmi_audio_enable(void)
 907 {
 908         DSSDBG("audio_enable\n");
 909
 910         return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
 911 }
 912
 913 void hdmi_audio_disable(void)
 914 {
 915         DSSDBG("audio_disable\n");
 916
 917         hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
 918 }
 919
 920 int hdmi_audio_start(void)
 921 {
 922         DSSDBG("audio_start\n");
 923
 924         return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
 925 }
 926
 927 void hdmi_audio_stop(void)
 928 {
 929         DSSDBG("audio_stop\n");
 930
 931         hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
 932 }
 933
 934 bool hdmi_mode_has_audio(void)
 935 {
 936         if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
 937                 return true;
 938         else
 939                 return false;
 940 }
 941
 942 int hdmi_audio_config(struct omap_dss_audio *audio)
 943 {
 944         return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
 945 }
 946
 947 #endif
 948
 949 static struct omap_dss_device *hdmi_find_dssdev(struct platform_device *pdev)
 950 {
 951         struct omap_dss_board_info *pdata = pdev->dev.platform_data;
 952         const char *def_disp_name = omapdss_get_default_display_name();
 953         struct omap_dss_device *def_dssdev;
 954         int i;
 955
 956         def_dssdev = NULL;
 957
 958         for (i = 0; i < pdata->num_devices; ++i) {
 959                 struct omap_dss_device *dssdev = pdata->devices[i];
 960
 961                 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
 962                         continue;
 963
 964                 if (def_dssdev == NULL)
 965                         def_dssdev = dssdev;
 966
 967                 if (def_disp_name != NULL &&
 968                                 strcmp(dssdev->name, def_disp_name) == 0) {
 969                         def_dssdev = dssdev;
 970                         break;
 971                 }
 972         }
 973
 974         return def_dssdev;
 975 }
 976
 977 static int hdmi_probe_pdata(struct platform_device *pdev)
 978 {
 979         struct omap_dss_device *plat_dssdev;
 980         struct omap_dss_device *dssdev;
 981         struct omap_dss_hdmi_data *priv;
 982         int r;
 983
 984         plat_dssdev = hdmi_find_dssdev(pdev);
 985
 986         if (!plat_dssdev)
 987                 return 0;
 988
 989         dssdev = dss_alloc_and_init_device(&pdev->dev);
 990         if (!dssdev)
 991                 return -ENOMEM;
 992
 993         dss_copy_device_pdata(dssdev, plat_dssdev);
 994
 995         priv = dssdev->data;
 996
 997         hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
 998         hdmi.ls_oe_gpio = priv->ls_oe_gpio;
 999         hdmi.hpd_gpio = priv->hpd_gpio;
1000
1001         r = hdmi_init_display(dssdev);
1002         if (r) {
1003                 DSSERR("device %s init failed: %d\n", dssdev->name, r);
1004                 dss_put_device(dssdev);
1005                 return r;
1006         }
1007
1008         r = omapdss_output_set_device(&hdmi.output, dssdev);
1009         if (r) {
1010                 DSSERR("failed to connect output to new device: %s\n",
1011                                 dssdev->name);
1012                 dss_put_device(dssdev);
1013                 return r;
1014         }
1015
1016         r = dss_add_device(dssdev);
1017         if (r) {
1018                 DSSERR("device %s register failed: %d\n", dssdev->name, r);
1019                 omapdss_output_unset_device(&hdmi.output);
1020                 hdmi_uninit_display(dssdev);
1021                 dss_put_device(dssdev);
1022                 return r;
1023         }
1024
1025         return 0;
1026 }
1027
1028 static void hdmi_init_output(struct platform_device *pdev)
1029 {
1030         struct omap_dss_device *out = &hdmi.output;
1031
1032         out->dev = &pdev->dev;
1033         out->id = OMAP_DSS_OUTPUT_HDMI;
1034         out->output_type = OMAP_DISPLAY_TYPE_HDMI;
1035         out->name = "hdmi.0";
1036         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
1037         out->owner = THIS_MODULE;
1038
1039         omapdss_register_output(out);
1040 }
1041
1042 static void __exit hdmi_uninit_output(struct platform_device *pdev)
1043 {
1044         struct omap_dss_device *out = &hdmi.output;
1045
1046         omapdss_unregister_output(out);
1047 }
1048
1049 /* HDMI HW IP initialisation */
1050 static int omapdss_hdmihw_probe(struct platform_device *pdev)
1051 {
1052         struct resource *res;
1053         int r;
1054
1055         hdmi.pdev = pdev;
1056
1057         mutex_init(&hdmi.lock);
1058         mutex_init(&hdmi.ip_data.lock);
1059
1060         res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1061
1062         /* Base address taken from platform */
1063         hdmi.ip_data.base_wp = devm_ioremap_resource(&pdev->dev, res);
1064         if (IS_ERR(hdmi.ip_data.base_wp))
1065                 return PTR_ERR(hdmi.ip_data.base_wp);
1066
1067         hdmi.ip_data.irq = platform_get_irq(pdev, 0);
1068         if (hdmi.ip_data.irq < 0) {
1069                 DSSERR("platform_get_irq failed\n");
1070                 return -ENODEV;
1071         }
1072
1073         r = hdmi_get_clocks(pdev);
1074         if (r) {
1075                 DSSERR("can't get clocks\n");
1076                 return r;
1077         }
1078
1079         pm_runtime_enable(&pdev->dev);
1080
1081         hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1082         hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1083         hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1084         hdmi.ip_data.phy_offset = HDMI_PHY;
1085
1086         hdmi_init_output(pdev);
1087
1088         r = hdmi_panel_init();
1089         if (r) {
1090                 DSSERR("can't init panel\n");
1091                 return r;
1092         }
1093
1094         dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1095
1096         if (pdev->dev.platform_data) {
1097                 r = hdmi_probe_pdata(pdev);
1098                 if (r)
1099                         goto err_probe;
1100         }
1101
1102         return 0;
1103
1104 err_probe:
1105         hdmi_panel_exit();
1106         hdmi_uninit_output(pdev);
1107         pm_runtime_disable(&pdev->dev);
1108         return r;
1109 }
1110
1111 static int __exit hdmi_remove_child(struct device *dev, void *data)
1112 {
1113         struct omap_dss_device *dssdev = to_dss_device(dev);
1114         hdmi_uninit_display(dssdev);
1115         return 0;
1116 }
1117
1118 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1119 {
1120         device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1121
1122         dss_unregister_child_devices(&pdev->dev);
1123
1124         hdmi_panel_exit();
1125
1126         hdmi_uninit_output(pdev);
1127
1128         pm_runtime_disable(&pdev->dev);
1129
1130         return 0;
1131 }
1132
1133 static int hdmi_runtime_suspend(struct device *dev)
1134 {
1135         clk_disable_unprepare(hdmi.sys_clk);
1136
1137         dispc_runtime_put();
1138
1139         return 0;
1140 }
1141
1142 static int hdmi_runtime_resume(struct device *dev)
1143 {
1144         int r;
1145
1146         r = dispc_runtime_get();
1147         if (r < 0)
1148                 return r;
1149
1150         clk_prepare_enable(hdmi.sys_clk);
1151
1152         return 0;
1153 }
1154
1155 static const struct dev_pm_ops hdmi_pm_ops = {
1156         .runtime_suspend = hdmi_runtime_suspend,
1157         .runtime_resume = hdmi_runtime_resume,
1158 };
1159
1160 static struct platform_driver omapdss_hdmihw_driver = {
1161         .probe          = omapdss_hdmihw_probe,
1162         .remove         = __exit_p(omapdss_hdmihw_remove),
1163         .driver         = {
1164                 .name   = "omapdss_hdmi",
1165                 .owner  = THIS_MODULE,
1166                 .pm     = &hdmi_pm_ops,
1167         },
1168 };
1169
1170 int __init hdmi_init_platform_driver(void)
1171 {
1172         return platform_driver_register(&omapdss_hdmihw_driver);
1173 }
1174
1175 void __exit hdmi_uninit_platform_driver(void)
1176 {
1177         platform_driver_unregister(&omapdss_hdmihw_driver);
1178 }