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OMAP: DSS2: remove extra includes from include/video/omapdss.h
[deliverable/linux.git] / drivers / video / omap2 / dss / hdmi.c
1 /*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #define DSS_SUBSYS_NAME "HDMI"
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
27 #include <linux/io.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <video/omapdss.h>
34 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
35 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
36 #include <sound/soc.h>
37 #include <sound/pcm_params.h>
38 #endif
39
40 #include "dss.h"
41 #include "hdmi.h"
42 #include "dss_features.h"
43
44 static struct {
45 struct mutex lock;
46 struct omap_display_platform_data *pdata;
47 struct platform_device *pdev;
48 void __iomem *base_wp; /* HDMI wrapper */
49 int code;
50 int mode;
51 u8 edid[HDMI_EDID_MAX_LENGTH];
52 u8 edid_set;
53 bool custom_set;
54 struct hdmi_config cfg;
55 } hdmi;
56
57 /*
58 * Logic for the below structure :
59 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
60 * There is a correspondence between CEA/VESA timing and code, please
61 * refer to section 6.3 in HDMI 1.3 specification for timing code.
62 *
63 * In the below structure, cea_vesa_timings corresponds to all OMAP4
64 * supported CEA and VESA timing values.code_cea corresponds to the CEA
65 * code, It is used to get the timing from cea_vesa_timing array.Similarly
66 * with code_vesa. Code_index is used for back mapping, that is once EDID
67 * is read from the TV, EDID is parsed to find the timing values and then
68 * map it to corresponding CEA or VESA index.
69 */
70
71 static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
72 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
73 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
74 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
75 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
76 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
77 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
78 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
79 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
80 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
81 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
82 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
83 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
84 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
85 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
86 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
87 /* VESA From Here */
88 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
89 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
90 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
91 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
92 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
93 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
94 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
95 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
96 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
97 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
98 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
99 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
100 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
101 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
102 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
103 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
104 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
105 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
106 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
107 };
108
109 /*
110 * This is a static mapping array which maps the timing values
111 * with corresponding CEA / VESA code
112 */
113 static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
114 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
115 /* <--15 CEA 17--> vesa*/
116 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
117 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
118 };
119
120 /*
121 * This is reverse static mapping which maps the CEA / VESA code
122 * to the corresponding timing values
123 */
124 static const int code_cea[39] = {
125 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
126 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
127 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
128 11, 12, 14, -1, -1, 13, 13, 4, 4
129 };
130
131 static const int code_vesa[85] = {
132 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
133 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
134 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
135 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
136 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
137 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
138 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
139 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
140 -1, 27, 28, -1, 33};
141
142 static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
143
144 static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val)
145 {
146 __raw_writel(val, hdmi.base_wp + idx.idx);
147 }
148
149 static inline u32 hdmi_read_reg(const struct hdmi_reg idx)
150 {
151 return __raw_readl(hdmi.base_wp + idx.idx);
152 }
153
154 static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx,
155 int b2, int b1, u32 val)
156 {
157 u32 t = 0;
158 while (val != REG_GET(idx, b2, b1)) {
159 udelay(1);
160 if (t++ > 10000)
161 return !val;
162 }
163 return val;
164 }
165
166 int hdmi_init_display(struct omap_dss_device *dssdev)
167 {
168 DSSDBG("init_display\n");
169
170 return 0;
171 }
172
173 static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq,
174 struct hdmi_pll_info *fmt, u16 sd)
175 {
176 u32 r;
177
178 /* PLL start always use manual mode */
179 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
180
181 r = hdmi_read_reg(PLLCTRL_CFG1);
182 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
183 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
184
185 hdmi_write_reg(PLLCTRL_CFG1, r);
186
187 r = hdmi_read_reg(PLLCTRL_CFG2);
188
189 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
190 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
191 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
192
193 if (dcofreq) {
194 /* divider programming for frequency beyond 1000Mhz */
195 REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10);
196 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
197 } else {
198 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
199 }
200
201 hdmi_write_reg(PLLCTRL_CFG2, r);
202
203 r = hdmi_read_reg(PLLCTRL_CFG4);
204 r = FLD_MOD(r, fmt->regm2, 24, 18);
205 r = FLD_MOD(r, fmt->regmf, 17, 0);
206
207 hdmi_write_reg(PLLCTRL_CFG4, r);
208
209 /* go now */
210 REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0);
211
212 /* wait for bit change */
213 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) {
214 DSSERR("PLL GO bit not set\n");
215 return -ETIMEDOUT;
216 }
217
218 /* Wait till the lock bit is set in PLL status */
219 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
220 DSSWARN("cannot lock PLL\n");
221 DSSWARN("CFG1 0x%x\n",
222 hdmi_read_reg(PLLCTRL_CFG1));
223 DSSWARN("CFG2 0x%x\n",
224 hdmi_read_reg(PLLCTRL_CFG2));
225 DSSWARN("CFG4 0x%x\n",
226 hdmi_read_reg(PLLCTRL_CFG4));
227 return -ETIMEDOUT;
228 }
229
230 DSSDBG("PLL locked!\n");
231
232 return 0;
233 }
234
235 /* PHY_PWR_CMD */
236 static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val)
237 {
238 /* Command for power control of HDMI PHY */
239 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6);
240
241 /* Status of the power control of HDMI PHY */
242 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
243 DSSERR("Failed to set PHY power mode to %d\n", val);
244 return -ETIMEDOUT;
245 }
246
247 return 0;
248 }
249
250 /* PLL_PWR_CMD */
251 static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val)
252 {
253 /* Command for power control of HDMI PLL */
254 REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2);
255
256 /* wait till PHY_PWR_STATUS is set */
257 if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) {
258 DSSERR("Failed to set PHY_PWR_STATUS\n");
259 return -ETIMEDOUT;
260 }
261
262 return 0;
263 }
264
265 static int hdmi_pll_reset(void)
266 {
267 /* SYSRESET controlled by power FSM */
268 REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
269
270 /* READ 0x0 reset is in progress */
271 if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
272 DSSERR("Failed to sysreset PLL\n");
273 return -ETIMEDOUT;
274 }
275
276 return 0;
277 }
278
279 static int hdmi_phy_init(void)
280 {
281 u16 r = 0;
282
283 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON);
284 if (r)
285 return r;
286
287 r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON);
288 if (r)
289 return r;
290
291 /*
292 * Read address 0 in order to get the SCP reset done completed
293 * Dummy access performed to make sure reset is done
294 */
295 hdmi_read_reg(HDMI_TXPHY_TX_CTRL);
296
297 /*
298 * Write to phy address 0 to configure the clock
299 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
300 */
301 REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
302
303 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
304 hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
305
306 /* Setup max LDO voltage */
307 REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
308
309 /* Write to phy address 3 to change the polarity control */
310 REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
311
312 return 0;
313 }
314
315 static int hdmi_wait_softreset(void)
316 {
317 /* reset W1 */
318 REG_FLD_MOD(HDMI_WP_SYSCONFIG, 0x1, 0, 0);
319
320 /* wait till SOFTRESET == 0 */
321 if (hdmi_wait_for_bit_change(HDMI_WP_SYSCONFIG, 0, 0, 0) != 0) {
322 DSSERR("sysconfig reset failed\n");
323 return -ETIMEDOUT;
324 }
325
326 return 0;
327 }
328
329 static int hdmi_pll_program(struct hdmi_pll_info *fmt)
330 {
331 u16 r = 0;
332 enum hdmi_clk_refsel refsel;
333
334 /* wait for wrapper reset */
335 r = hdmi_wait_softreset();
336 if (r)
337 return r;
338
339 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
340 if (r)
341 return r;
342
343 r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
344 if (r)
345 return r;
346
347 r = hdmi_pll_reset();
348 if (r)
349 return r;
350
351 refsel = HDMI_REFSEL_SYSCLK;
352
353 r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd);
354 if (r)
355 return r;
356
357 return 0;
358 }
359
360 static void hdmi_phy_off(void)
361 {
362 hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF);
363 }
364
365 static int hdmi_core_ddc_edid(u8 *pedid, int ext)
366 {
367 u32 i, j;
368 char checksum = 0;
369 u32 offset = 0;
370
371 /* Turn on CLK for DDC */
372 REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0);
373
374 /*
375 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
376 * right shifted values( The behavior is not consistent and seen only
377 * with some TV's)
378 */
379 usleep_range(800, 1000);
380
381 if (!ext) {
382 /* Clk SCL Devices */
383 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0);
384
385 /* HDMI_CORE_DDC_STATUS_IN_PROG */
386 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
387 4, 4, 0) != 0) {
388 DSSERR("Failed to program DDC\n");
389 return -ETIMEDOUT;
390 }
391
392 /* Clear FIFO */
393 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0);
394
395 /* HDMI_CORE_DDC_STATUS_IN_PROG */
396 if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS,
397 4, 4, 0) != 0) {
398 DSSERR("Failed to program DDC\n");
399 return -ETIMEDOUT;
400 }
401
402 } else {
403 if (ext % 2 != 0)
404 offset = 0x80;
405 }
406
407 /* Load Segment Address Register */
408 REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
409
410 /* Load Slave Address Register */
411 REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
412
413 /* Load Offset Address Register */
414 REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0);
415
416 /* Load Byte Count */
417 REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
418 REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
419
420 /* Set DDC_CMD */
421 if (ext)
422 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0);
423 else
424 REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0);
425
426 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
427 if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
428 DSSWARN("I2C Bus Low?\n");
429 return -EIO;
430 }
431 /* HDMI_CORE_DDC_STATUS_NO_ACK */
432 if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
433 DSSWARN("I2C No Ack\n");
434 return -EIO;
435 }
436
437 i = ext * 128;
438 j = 0;
439 while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
440 (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) &&
441 j < 128) {
442
443 if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
444 /* FIFO not empty */
445 pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0);
446 j++;
447 }
448 }
449
450 for (j = 0; j < 128; j++)
451 checksum += pedid[j];
452
453 if (checksum != 0) {
454 DSSERR("E-EDID checksum failed!!\n");
455 return -EIO;
456 }
457
458 return 0;
459 }
460
461 static int read_edid(u8 *pedid, u16 max_length)
462 {
463 int r = 0, n = 0, i = 0;
464 int max_ext_blocks = (max_length / 128) - 1;
465
466 r = hdmi_core_ddc_edid(pedid, 0);
467 if (r) {
468 return r;
469 } else {
470 n = pedid[0x7e];
471
472 /*
473 * README: need to comply with max_length set by the caller.
474 * Better implementation should be to allocate necessary
475 * memory to store EDID according to nb_block field found
476 * in first block
477 */
478 if (n > max_ext_blocks)
479 n = max_ext_blocks;
480
481 for (i = 1; i <= n; i++) {
482 r = hdmi_core_ddc_edid(pedid, i);
483 if (r)
484 return r;
485 }
486 }
487 return 0;
488 }
489
490 static int get_timings_index(void)
491 {
492 int code;
493
494 if (hdmi.mode == 0)
495 code = code_vesa[hdmi.code];
496 else
497 code = code_cea[hdmi.code];
498
499 if (code == -1) {
500 /* HDMI code 4 corresponds to 640 * 480 VGA */
501 hdmi.code = 4;
502 /* DVI mode 1 corresponds to HDMI 0 to DVI */
503 hdmi.mode = HDMI_DVI;
504
505 code = code_vesa[hdmi.code];
506 }
507 return code;
508 }
509
510 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
511 {
512 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
513 int timing_vsync = 0, timing_hsync = 0;
514 struct omap_video_timings temp;
515 struct hdmi_cm cm = {-1};
516 DSSDBG("hdmi_get_code\n");
517
518 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
519 temp = cea_vesa_timings[i].timings;
520 if ((temp.pixel_clock == timing->pixel_clock) &&
521 (temp.x_res == timing->x_res) &&
522 (temp.y_res == timing->y_res)) {
523
524 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
525 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
526 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
527 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
528
529 DSSDBG("temp_hsync = %d , temp_vsync = %d"
530 "timing_hsync = %d, timing_vsync = %d\n",
531 temp_hsync, temp_hsync,
532 timing_hsync, timing_vsync);
533
534 if ((temp_hsync == timing_hsync) &&
535 (temp_vsync == timing_vsync)) {
536 code = i;
537 cm.code = code_index[i];
538 if (code < 14)
539 cm.mode = HDMI_HDMI;
540 else
541 cm.mode = HDMI_DVI;
542 DSSDBG("Hdmi_code = %d mode = %d\n",
543 cm.code, cm.mode);
544 break;
545 }
546 }
547 }
548
549 return cm;
550 }
551
552 static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
553 struct omap_video_timings *timings)
554 {
555 /* X and Y resolution */
556 timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
557 edid[current_descriptor_addrs + 2]);
558 timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
559 edid[current_descriptor_addrs + 5]);
560
561 timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
562 edid[current_descriptor_addrs]);
563
564 timings->pixel_clock = 10 * timings->pixel_clock;
565
566 /* HORIZONTAL FRONT PORCH */
567 timings->hfp = edid[current_descriptor_addrs + 8] |
568 ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
569 /* HORIZONTAL SYNC WIDTH */
570 timings->hsw = edid[current_descriptor_addrs + 9] |
571 ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
572 /* HORIZONTAL BACK PORCH */
573 timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
574 edid[current_descriptor_addrs + 3]) -
575 (timings->hfp + timings->hsw);
576 /* VERTICAL FRONT PORCH */
577 timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
578 ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
579 /* VERTICAL SYNC WIDTH */
580 timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
581 ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
582 /* VERTICAL BACK PORCH */
583 timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
584 edid[current_descriptor_addrs + 6]) -
585 (timings->vfp + timings->vsw);
586
587 }
588
589 /* Description : This function gets the resolution information from EDID */
590 static void get_edid_timing_data(u8 *edid)
591 {
592 u8 count;
593 u16 current_descriptor_addrs;
594 struct hdmi_cm cm;
595 struct omap_video_timings edid_timings;
596
597 /* search block 0, there are 4 DTDs arranged in priority order */
598 for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
599 current_descriptor_addrs =
600 EDID_DESCRIPTOR_BLOCK0_ADDRESS +
601 count * EDID_TIMING_DESCRIPTOR_SIZE;
602 get_horz_vert_timing_info(current_descriptor_addrs,
603 edid, &edid_timings);
604 cm = hdmi_get_code(&edid_timings);
605 DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
606 count, cm.code, cm.mode);
607 if (cm.code == -1) {
608 continue;
609 } else {
610 hdmi.code = cm.code;
611 hdmi.mode = cm.mode;
612 DSSDBG("code = %d , mode = %d\n",
613 hdmi.code, hdmi.mode);
614 return;
615 }
616 }
617 if (edid[0x7e] != 0x00) {
618 for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
619 count++) {
620 current_descriptor_addrs =
621 EDID_DESCRIPTOR_BLOCK1_ADDRESS +
622 count * EDID_TIMING_DESCRIPTOR_SIZE;
623 get_horz_vert_timing_info(current_descriptor_addrs,
624 edid, &edid_timings);
625 cm = hdmi_get_code(&edid_timings);
626 DSSDBG("Block1[%d] value matches code = %d, mode = %d",
627 count, cm.code, cm.mode);
628 if (cm.code == -1) {
629 continue;
630 } else {
631 hdmi.code = cm.code;
632 hdmi.mode = cm.mode;
633 DSSDBG("code = %d , mode = %d\n",
634 hdmi.code, hdmi.mode);
635 return;
636 }
637 }
638 }
639
640 DSSINFO("no valid timing found , falling back to VGA\n");
641 hdmi.code = 4; /* setting default value of 640 480 VGA */
642 hdmi.mode = HDMI_DVI;
643 }
644
645 static void hdmi_read_edid(struct omap_video_timings *dp)
646 {
647 int ret = 0, code;
648
649 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
650
651 if (!hdmi.edid_set)
652 ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH);
653
654 if (!ret) {
655 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
656 /* search for timings of default resolution */
657 get_edid_timing_data(hdmi.edid);
658 hdmi.edid_set = true;
659 }
660 } else {
661 DSSWARN("failed to read E-EDID\n");
662 }
663
664 if (!hdmi.edid_set) {
665 DSSINFO("fallback to VGA\n");
666 hdmi.code = 4; /* setting default value of 640 480 VGA */
667 hdmi.mode = HDMI_DVI;
668 }
669
670 code = get_timings_index();
671
672 *dp = cea_vesa_timings[code].timings;
673 }
674
675 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
676 struct hdmi_core_infoframe_avi *avi_cfg,
677 struct hdmi_core_packet_enable_repeat *repeat_cfg)
678 {
679 DSSDBG("Enter hdmi_core_init\n");
680
681 /* video core */
682 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
683 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
684 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
685 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
686 video_cfg->hdmi_dvi = HDMI_DVI;
687 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
688
689 /* info frame */
690 avi_cfg->db1_format = 0;
691 avi_cfg->db1_active_info = 0;
692 avi_cfg->db1_bar_info_dv = 0;
693 avi_cfg->db1_scan_info = 0;
694 avi_cfg->db2_colorimetry = 0;
695 avi_cfg->db2_aspect_ratio = 0;
696 avi_cfg->db2_active_fmt_ar = 0;
697 avi_cfg->db3_itc = 0;
698 avi_cfg->db3_ec = 0;
699 avi_cfg->db3_q_range = 0;
700 avi_cfg->db3_nup_scaling = 0;
701 avi_cfg->db4_videocode = 0;
702 avi_cfg->db5_pixel_repeat = 0;
703 avi_cfg->db6_7_line_eoftop = 0 ;
704 avi_cfg->db8_9_line_sofbottom = 0;
705 avi_cfg->db10_11_pixel_eofleft = 0;
706 avi_cfg->db12_13_pixel_sofright = 0;
707
708 /* packet enable and repeat */
709 repeat_cfg->audio_pkt = 0;
710 repeat_cfg->audio_pkt_repeat = 0;
711 repeat_cfg->avi_infoframe = 0;
712 repeat_cfg->avi_infoframe_repeat = 0;
713 repeat_cfg->gen_cntrl_pkt = 0;
714 repeat_cfg->gen_cntrl_pkt_repeat = 0;
715 repeat_cfg->generic_pkt = 0;
716 repeat_cfg->generic_pkt_repeat = 0;
717 }
718
719 static void hdmi_core_powerdown_disable(void)
720 {
721 DSSDBG("Enter hdmi_core_powerdown_disable\n");
722 REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0);
723 }
724
725 static void hdmi_core_swreset_release(void)
726 {
727 DSSDBG("Enter hdmi_core_swreset_release\n");
728 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0);
729 }
730
731 static void hdmi_core_swreset_assert(void)
732 {
733 DSSDBG("Enter hdmi_core_swreset_assert\n");
734 REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0);
735 }
736
737 /* DSS_HDMI_CORE_VIDEO_CONFIG */
738 static void hdmi_core_video_config(struct hdmi_core_video_config *cfg)
739 {
740 u32 r = 0;
741
742 /* sys_ctrl1 default configuration not tunable */
743 r = hdmi_read_reg(HDMI_CORE_CTRL1);
744 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
745 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
746 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
747 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
748 hdmi_write_reg(HDMI_CORE_CTRL1, r);
749
750 REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
751
752 /* Vid_Mode */
753 r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE);
754
755 /* dither truncation configuration */
756 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
757 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
758 r = FLD_MOD(r, 1, 5, 5);
759 } else {
760 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
761 r = FLD_MOD(r, 0, 5, 5);
762 }
763 hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r);
764
765 /* HDMI_Ctrl */
766 r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL);
767 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
768 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
769 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
770 hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r);
771
772 /* TMDS_CTRL */
773 REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL,
774 cfg->tclk_sel_clkmult, 6, 5);
775 }
776
777 static void hdmi_core_aux_infoframe_avi_config(
778 struct hdmi_core_infoframe_avi info_avi)
779 {
780 u32 val;
781 char sum = 0, checksum = 0;
782
783 sum += 0x82 + 0x002 + 0x00D;
784 hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082);
785 hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002);
786 hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D);
787
788 val = (info_avi.db1_format << 5) |
789 (info_avi.db1_active_info << 4) |
790 (info_avi.db1_bar_info_dv << 2) |
791 (info_avi.db1_scan_info);
792 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val);
793 sum += val;
794
795 val = (info_avi.db2_colorimetry << 6) |
796 (info_avi.db2_aspect_ratio << 4) |
797 (info_avi.db2_active_fmt_ar);
798 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val);
799 sum += val;
800
801 val = (info_avi.db3_itc << 7) |
802 (info_avi.db3_ec << 4) |
803 (info_avi.db3_q_range << 2) |
804 (info_avi.db3_nup_scaling);
805 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val);
806 sum += val;
807
808 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode);
809 sum += info_avi.db4_videocode;
810
811 val = info_avi.db5_pixel_repeat;
812 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val);
813 sum += val;
814
815 val = info_avi.db6_7_line_eoftop & 0x00FF;
816 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val);
817 sum += val;
818
819 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
820 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val);
821 sum += val;
822
823 val = info_avi.db8_9_line_sofbottom & 0x00FF;
824 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val);
825 sum += val;
826
827 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
828 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val);
829 sum += val;
830
831 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
832 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val);
833 sum += val;
834
835 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
836 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val);
837 sum += val;
838
839 val = info_avi.db12_13_pixel_sofright & 0x00FF;
840 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val);
841 sum += val;
842
843 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
844 hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val);
845 sum += val;
846
847 checksum = 0x100 - sum;
848 hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum);
849 }
850
851 static void hdmi_core_av_packet_config(
852 struct hdmi_core_packet_enable_repeat repeat_cfg)
853 {
854 /* enable/repeat the infoframe */
855 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1,
856 (repeat_cfg.audio_pkt << 5) |
857 (repeat_cfg.audio_pkt_repeat << 4) |
858 (repeat_cfg.avi_infoframe << 1) |
859 (repeat_cfg.avi_infoframe_repeat));
860
861 /* enable/repeat the packet */
862 hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2,
863 (repeat_cfg.gen_cntrl_pkt << 3) |
864 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
865 (repeat_cfg.generic_pkt << 1) |
866 (repeat_cfg.generic_pkt_repeat));
867 }
868
869 static void hdmi_wp_init(struct omap_video_timings *timings,
870 struct hdmi_video_format *video_fmt,
871 struct hdmi_video_interface *video_int)
872 {
873 DSSDBG("Enter hdmi_wp_init\n");
874
875 timings->hbp = 0;
876 timings->hfp = 0;
877 timings->hsw = 0;
878 timings->vbp = 0;
879 timings->vfp = 0;
880 timings->vsw = 0;
881
882 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
883 video_fmt->y_res = 0;
884 video_fmt->x_res = 0;
885
886 video_int->vsp = 0;
887 video_int->hsp = 0;
888
889 video_int->interlacing = 0;
890 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
891
892 }
893
894 static void hdmi_wp_video_start(bool start)
895 {
896 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31);
897 }
898
899 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
900 struct omap_video_timings *timings, struct hdmi_config *param)
901 {
902 DSSDBG("Enter hdmi_wp_video_init_format\n");
903
904 video_fmt->y_res = param->timings.timings.y_res;
905 video_fmt->x_res = param->timings.timings.x_res;
906
907 timings->hbp = param->timings.timings.hbp;
908 timings->hfp = param->timings.timings.hfp;
909 timings->hsw = param->timings.timings.hsw;
910 timings->vbp = param->timings.timings.vbp;
911 timings->vfp = param->timings.timings.vfp;
912 timings->vsw = param->timings.timings.vsw;
913 }
914
915 static void hdmi_wp_video_config_format(
916 struct hdmi_video_format *video_fmt)
917 {
918 u32 l = 0;
919
920 REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8);
921
922 l |= FLD_VAL(video_fmt->y_res, 31, 16);
923 l |= FLD_VAL(video_fmt->x_res, 15, 0);
924 hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l);
925 }
926
927 static void hdmi_wp_video_config_interface(
928 struct hdmi_video_interface *video_int)
929 {
930 u32 r;
931 DSSDBG("Enter hdmi_wp_video_config_interface\n");
932
933 r = hdmi_read_reg(HDMI_WP_VIDEO_CFG);
934 r = FLD_MOD(r, video_int->vsp, 7, 7);
935 r = FLD_MOD(r, video_int->hsp, 6, 6);
936 r = FLD_MOD(r, video_int->interlacing, 3, 3);
937 r = FLD_MOD(r, video_int->tm, 1, 0);
938 hdmi_write_reg(HDMI_WP_VIDEO_CFG, r);
939 }
940
941 static void hdmi_wp_video_config_timing(
942 struct omap_video_timings *timings)
943 {
944 u32 timing_h = 0;
945 u32 timing_v = 0;
946
947 DSSDBG("Enter hdmi_wp_video_config_timing\n");
948
949 timing_h |= FLD_VAL(timings->hbp, 31, 20);
950 timing_h |= FLD_VAL(timings->hfp, 19, 8);
951 timing_h |= FLD_VAL(timings->hsw, 7, 0);
952 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h);
953
954 timing_v |= FLD_VAL(timings->vbp, 31, 20);
955 timing_v |= FLD_VAL(timings->vfp, 19, 8);
956 timing_v |= FLD_VAL(timings->vsw, 7, 0);
957 hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v);
958 }
959
960 static void hdmi_basic_configure(struct hdmi_config *cfg)
961 {
962 /* HDMI */
963 struct omap_video_timings video_timing;
964 struct hdmi_video_format video_format;
965 struct hdmi_video_interface video_interface;
966 /* HDMI core */
967 struct hdmi_core_infoframe_avi avi_cfg;
968 struct hdmi_core_video_config v_core_cfg;
969 struct hdmi_core_packet_enable_repeat repeat_cfg;
970
971 hdmi_wp_init(&video_timing, &video_format,
972 &video_interface);
973
974 hdmi_core_init(&v_core_cfg,
975 &avi_cfg,
976 &repeat_cfg);
977
978 hdmi_wp_video_init_format(&video_format,
979 &video_timing, cfg);
980
981 hdmi_wp_video_config_timing(&video_timing);
982
983 /* video config */
984 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
985
986 hdmi_wp_video_config_format(&video_format);
987
988 video_interface.vsp = cfg->timings.vsync_pol;
989 video_interface.hsp = cfg->timings.hsync_pol;
990 video_interface.interlacing = cfg->interlace;
991 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
992
993 hdmi_wp_video_config_interface(&video_interface);
994
995 /*
996 * configure core video part
997 * set software reset in the core
998 */
999 hdmi_core_swreset_assert();
1000
1001 /* power down off */
1002 hdmi_core_powerdown_disable();
1003
1004 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
1005 v_core_cfg.hdmi_dvi = cfg->cm.mode;
1006
1007 hdmi_core_video_config(&v_core_cfg);
1008
1009 /* release software reset in the core */
1010 hdmi_core_swreset_release();
1011
1012 /*
1013 * configure packet
1014 * info frame video see doc CEA861-D page 65
1015 */
1016 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
1017 avi_cfg.db1_active_info =
1018 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
1019 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
1020 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
1021 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
1022 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
1023 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
1024 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
1025 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
1026 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
1027 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
1028 avi_cfg.db4_videocode = cfg->cm.code;
1029 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
1030 avi_cfg.db6_7_line_eoftop = 0;
1031 avi_cfg.db8_9_line_sofbottom = 0;
1032 avi_cfg.db10_11_pixel_eofleft = 0;
1033 avi_cfg.db12_13_pixel_sofright = 0;
1034
1035 hdmi_core_aux_infoframe_avi_config(avi_cfg);
1036
1037 /* enable/repeat the infoframe */
1038 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
1039 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
1040 /* wakeup */
1041 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
1042 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
1043 hdmi_core_av_packet_config(repeat_cfg);
1044 }
1045
1046 static void update_hdmi_timings(struct hdmi_config *cfg,
1047 struct omap_video_timings *timings, int code)
1048 {
1049 cfg->timings.timings.x_res = timings->x_res;
1050 cfg->timings.timings.y_res = timings->y_res;
1051 cfg->timings.timings.hbp = timings->hbp;
1052 cfg->timings.timings.hfp = timings->hfp;
1053 cfg->timings.timings.hsw = timings->hsw;
1054 cfg->timings.timings.vbp = timings->vbp;
1055 cfg->timings.timings.vfp = timings->vfp;
1056 cfg->timings.timings.vsw = timings->vsw;
1057 cfg->timings.timings.pixel_clock = timings->pixel_clock;
1058 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
1059 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
1060 }
1061
1062 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
1063 struct hdmi_pll_info *pi)
1064 {
1065 unsigned long clkin, refclk;
1066 u32 mf;
1067
1068 clkin = dss_clk_get_rate(DSS_CLK_SYSCK) / 10000;
1069 /*
1070 * Input clock is predivided by N + 1
1071 * out put of which is reference clk
1072 */
1073 pi->regn = dssdev->clocks.hdmi.regn;
1074 refclk = clkin / (pi->regn + 1);
1075
1076 /*
1077 * multiplier is pixel_clk/ref_clk
1078 * Multiplying by 100 to avoid fractional part removal
1079 */
1080 pi->regm = (phy * 100 / (refclk)) / 100;
1081 pi->regm2 = dssdev->clocks.hdmi.regm2;
1082
1083 /*
1084 * fractional multiplier is remainder of the difference between
1085 * multiplier and actual phy(required pixel clock thus should be
1086 * multiplied by 2^18(262144) divided by the reference clock
1087 */
1088 mf = (phy - pi->regm * refclk) * 262144;
1089 pi->regmf = mf / (refclk);
1090
1091 /*
1092 * Dcofreq should be set to 1 if required pixel clock
1093 * is greater than 1000MHz
1094 */
1095 pi->dcofreq = phy > 1000 * 100;
1096 pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
1097
1098 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
1099 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
1100 }
1101
1102 static void hdmi_enable_clocks(int enable)
1103 {
1104 if (enable)
1105 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK |
1106 DSS_CLK_SYSCK | DSS_CLK_VIDFCK);
1107 else
1108 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK |
1109 DSS_CLK_SYSCK | DSS_CLK_VIDFCK);
1110 }
1111
1112 static int hdmi_power_on(struct omap_dss_device *dssdev)
1113 {
1114 int r, code = 0;
1115 struct hdmi_pll_info pll_data;
1116 struct omap_video_timings *p;
1117 unsigned long phy;
1118
1119 hdmi_enable_clocks(1);
1120
1121 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
1122
1123 p = &dssdev->panel.timings;
1124
1125 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
1126 dssdev->panel.timings.x_res,
1127 dssdev->panel.timings.y_res);
1128
1129 if (!hdmi.custom_set) {
1130 DSSDBG("Read EDID as no EDID is not set on poweron\n");
1131 hdmi_read_edid(p);
1132 }
1133 code = get_timings_index();
1134 dssdev->panel.timings = cea_vesa_timings[code].timings;
1135 update_hdmi_timings(&hdmi.cfg, p, code);
1136
1137 phy = p->pixel_clock;
1138
1139 hdmi_compute_pll(dssdev, phy, &pll_data);
1140
1141 hdmi_wp_video_start(0);
1142
1143 /* config the PLL and PHY first */
1144 r = hdmi_pll_program(&pll_data);
1145 if (r) {
1146 DSSDBG("Failed to lock PLL\n");
1147 goto err;
1148 }
1149
1150 r = hdmi_phy_init();
1151 if (r) {
1152 DSSDBG("Failed to start PHY\n");
1153 goto err;
1154 }
1155
1156 hdmi.cfg.cm.mode = hdmi.mode;
1157 hdmi.cfg.cm.code = hdmi.code;
1158 hdmi_basic_configure(&hdmi.cfg);
1159
1160 /* Make selection of HDMI in DSS */
1161 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
1162
1163 /* Select the dispc clock source as PRCM clock, to ensure that it is not
1164 * DSI PLL source as the clock selected by DSI PLL might not be
1165 * sufficient for the resolution selected / that can be changed
1166 * dynamically by user. This can be moved to single location , say
1167 * Boardfile.
1168 */
1169 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
1170
1171 /* bypass TV gamma table */
1172 dispc_enable_gamma_table(0);
1173
1174 /* tv size */
1175 dispc_set_digit_size(dssdev->panel.timings.x_res,
1176 dssdev->panel.timings.y_res);
1177
1178 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1);
1179
1180 hdmi_wp_video_start(1);
1181
1182 return 0;
1183 err:
1184 hdmi_enable_clocks(0);
1185 return -EIO;
1186 }
1187
1188 static void hdmi_power_off(struct omap_dss_device *dssdev)
1189 {
1190 dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0);
1191
1192 hdmi_wp_video_start(0);
1193 hdmi_phy_off();
1194 hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF);
1195 hdmi_enable_clocks(0);
1196
1197 hdmi.edid_set = 0;
1198 }
1199
1200 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
1201 struct omap_video_timings *timings)
1202 {
1203 struct hdmi_cm cm;
1204
1205 cm = hdmi_get_code(timings);
1206 if (cm.code == -1) {
1207 DSSERR("Invalid timing entered\n");
1208 return -EINVAL;
1209 }
1210
1211 return 0;
1212
1213 }
1214
1215 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
1216 {
1217 struct hdmi_cm cm;
1218
1219 hdmi.custom_set = 1;
1220 cm = hdmi_get_code(&dssdev->panel.timings);
1221 hdmi.code = cm.code;
1222 hdmi.mode = cm.mode;
1223 omapdss_hdmi_display_enable(dssdev);
1224 hdmi.custom_set = 0;
1225 }
1226
1227 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
1228 {
1229 int r = 0;
1230
1231 DSSDBG("ENTER hdmi_display_enable\n");
1232
1233 mutex_lock(&hdmi.lock);
1234
1235 r = omap_dss_start_device(dssdev);
1236 if (r) {
1237 DSSERR("failed to start device\n");
1238 goto err0;
1239 }
1240
1241 if (dssdev->platform_enable) {
1242 r = dssdev->platform_enable(dssdev);
1243 if (r) {
1244 DSSERR("failed to enable GPIO's\n");
1245 goto err1;
1246 }
1247 }
1248
1249 r = hdmi_power_on(dssdev);
1250 if (r) {
1251 DSSERR("failed to power on device\n");
1252 goto err2;
1253 }
1254
1255 mutex_unlock(&hdmi.lock);
1256 return 0;
1257
1258 err2:
1259 if (dssdev->platform_disable)
1260 dssdev->platform_disable(dssdev);
1261 err1:
1262 omap_dss_stop_device(dssdev);
1263 err0:
1264 mutex_unlock(&hdmi.lock);
1265 return r;
1266 }
1267
1268 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1269 {
1270 DSSDBG("Enter hdmi_display_disable\n");
1271
1272 mutex_lock(&hdmi.lock);
1273
1274 hdmi_power_off(dssdev);
1275
1276 if (dssdev->platform_disable)
1277 dssdev->platform_disable(dssdev);
1278
1279 omap_dss_stop_device(dssdev);
1280
1281 mutex_unlock(&hdmi.lock);
1282 }
1283
1284 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1285 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1286 static void hdmi_wp_audio_config_format(
1287 struct hdmi_audio_format *aud_fmt)
1288 {
1289 u32 r;
1290
1291 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1292
1293 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG);
1294 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1295 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1296 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1297 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1298 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1299 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1300 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1301 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1302 hdmi_write_reg(HDMI_WP_AUDIO_CFG, r);
1303 }
1304
1305 static void hdmi_wp_audio_config_dma(struct hdmi_audio_dma *aud_dma)
1306 {
1307 u32 r;
1308
1309 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1310
1311 r = hdmi_read_reg(HDMI_WP_AUDIO_CFG2);
1312 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1313 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1314 hdmi_write_reg(HDMI_WP_AUDIO_CFG2, r);
1315
1316 r = hdmi_read_reg(HDMI_WP_AUDIO_CTRL);
1317 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1318 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1319 hdmi_write_reg(HDMI_WP_AUDIO_CTRL, r);
1320 }
1321
1322 static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg)
1323 {
1324 u32 r;
1325
1326 /* audio clock recovery parameters */
1327 r = hdmi_read_reg(HDMI_CORE_AV_ACR_CTRL);
1328 r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1329 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1330 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1331 hdmi_write_reg(HDMI_CORE_AV_ACR_CTRL, r);
1332
1333 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1334 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1335 REG_FLD_MOD(HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1336
1337 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1338 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1339 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1340 REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1341 } else {
1342 /*
1343 * HDMI IP uses this configuration to divide the MCLK to
1344 * update CTS value.
1345 */
1346 REG_FLD_MOD(HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1347
1348 /* Configure clock for audio packets */
1349 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1350 cfg->aud_par_busclk, 7, 0);
1351 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1352 (cfg->aud_par_busclk >> 8), 7, 0);
1353 REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1354 (cfg->aud_par_busclk >> 16), 7, 0);
1355 }
1356
1357 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1358 REG_FLD_MOD(HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1);
1359
1360 /* I2S parameters */
1361 REG_FLD_MOD(HDMI_CORE_AV_I2S_CHST4, cfg->freq_sample, 3, 0);
1362
1363 r = hdmi_read_reg(HDMI_CORE_AV_I2S_IN_CTRL);
1364 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1365 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1366 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1367 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1368 r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1369 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1370 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1371 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1372 hdmi_write_reg(HDMI_CORE_AV_I2S_IN_CTRL, r);
1373
1374 r = hdmi_read_reg(HDMI_CORE_AV_I2S_CHST5);
1375 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1376 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1377 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1378 hdmi_write_reg(HDMI_CORE_AV_I2S_CHST5, r);
1379
1380 REG_FLD_MOD(HDMI_CORE_AV_I2S_IN_LEN, cfg->i2s_cfg.in_length_bits, 3, 0);
1381
1382 /* Audio channels and mode parameters */
1383 REG_FLD_MOD(HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1384 r = hdmi_read_reg(HDMI_CORE_AV_AUD_MODE);
1385 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1386 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1387 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1388 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1389 hdmi_write_reg(HDMI_CORE_AV_AUD_MODE, r);
1390 }
1391
1392 static void hdmi_core_audio_infoframe_config(
1393 struct hdmi_core_infoframe_audio *info_aud)
1394 {
1395 u8 val;
1396 u8 sum = 0, checksum = 0;
1397
1398 /*
1399 * Set audio info frame type, version and length as
1400 * described in HDMI 1.4a Section 8.2.2 specification.
1401 * Checksum calculation is defined in Section 5.3.5.
1402 */
1403 hdmi_write_reg(HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1404 hdmi_write_reg(HDMI_CORE_AV_AUDIO_VERS, 0x01);
1405 hdmi_write_reg(HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1406 sum += 0x84 + 0x001 + 0x00a;
1407
1408 val = (info_aud->db1_coding_type << 4)
1409 | (info_aud->db1_channel_count - 1);
1410 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(0), val);
1411 sum += val;
1412
1413 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1414 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(1), val);
1415 sum += val;
1416
1417 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1418
1419 val = info_aud->db4_channel_alloc;
1420 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(3), val);
1421 sum += val;
1422
1423 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1424 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(4), val);
1425 sum += val;
1426
1427 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1428 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1429 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1430 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1431 hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1432
1433 checksum = 0x100 - sum;
1434 hdmi_write_reg(HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1435
1436 /*
1437 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1438 * is available.
1439 */
1440 }
1441
1442 static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts)
1443 {
1444 u32 r;
1445 u32 deep_color = 0;
1446 u32 pclk = hdmi.cfg.timings.timings.pixel_clock;
1447
1448 if (n == NULL || cts == NULL)
1449 return -EINVAL;
1450 /*
1451 * Obtain current deep color configuration. This needed
1452 * to calculate the TMDS clock based on the pixel clock.
1453 */
1454 r = REG_GET(HDMI_WP_VIDEO_CFG, 1, 0);
1455 switch (r) {
1456 case 1: /* No deep color selected */
1457 deep_color = 100;
1458 break;
1459 case 2: /* 10-bit deep color selected */
1460 deep_color = 125;
1461 break;
1462 case 3: /* 12-bit deep color selected */
1463 deep_color = 150;
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468
1469 switch (sample_freq) {
1470 case 32000:
1471 if ((deep_color == 125) && ((pclk == 54054)
1472 || (pclk == 74250)))
1473 *n = 8192;
1474 else
1475 *n = 4096;
1476 break;
1477 case 44100:
1478 *n = 6272;
1479 break;
1480 case 48000:
1481 if ((deep_color == 125) && ((pclk == 54054)
1482 || (pclk == 74250)))
1483 *n = 8192;
1484 else
1485 *n = 6144;
1486 break;
1487 default:
1488 *n = 0;
1489 return -EINVAL;
1490 }
1491
1492 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1493 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1494
1495 return 0;
1496 }
1497
1498 static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1499 struct snd_pcm_hw_params *params,
1500 struct snd_soc_dai *dai)
1501 {
1502 struct hdmi_audio_format audio_format;
1503 struct hdmi_audio_dma audio_dma;
1504 struct hdmi_core_audio_config core_cfg;
1505 struct hdmi_core_infoframe_audio aud_if_cfg;
1506 int err, n, cts;
1507 enum hdmi_core_audio_sample_freq sample_freq;
1508
1509 switch (params_format(params)) {
1510 case SNDRV_PCM_FORMAT_S16_LE:
1511 core_cfg.i2s_cfg.word_max_length =
1512 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
1513 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
1514 core_cfg.i2s_cfg.in_length_bits =
1515 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
1516 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1517 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1518 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1519 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1520 audio_dma.transfer_size = 0x10;
1521 break;
1522 case SNDRV_PCM_FORMAT_S24_LE:
1523 core_cfg.i2s_cfg.word_max_length =
1524 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
1525 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
1526 core_cfg.i2s_cfg.in_length_bits =
1527 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
1528 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1529 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1530 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1531 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1532 audio_dma.transfer_size = 0x20;
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537
1538 switch (params_rate(params)) {
1539 case 32000:
1540 sample_freq = HDMI_AUDIO_FS_32000;
1541 break;
1542 case 44100:
1543 sample_freq = HDMI_AUDIO_FS_44100;
1544 break;
1545 case 48000:
1546 sample_freq = HDMI_AUDIO_FS_48000;
1547 break;
1548 default:
1549 return -EINVAL;
1550 }
1551
1552 err = hdmi_config_audio_acr(params_rate(params), &n, &cts);
1553 if (err < 0)
1554 return err;
1555
1556 /* Audio wrapper config */
1557 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1558 audio_format.active_chnnls_msk = 0x03;
1559 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1560 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1561 /* Disable start/stop signals of IEC 60958 blocks */
1562 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
1563
1564 audio_dma.block_size = 0xC0;
1565 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1566 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1567
1568 hdmi_wp_audio_config_dma(&audio_dma);
1569 hdmi_wp_audio_config_format(&audio_format);
1570
1571 /*
1572 * I2S config
1573 */
1574 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
1575 /* Only used with high bitrate audio */
1576 core_cfg.i2s_cfg.cbit_order = false;
1577 /* Serial data and word select should change on sck rising edge */
1578 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1579 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1580 /* Set I2S word select polarity */
1581 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
1582 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1583 /* Set serial data to word select shift. See Phillips spec. */
1584 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1585 /* Enable one of the four available serial data channels */
1586 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1587
1588 /* Core audio config */
1589 core_cfg.freq_sample = sample_freq;
1590 core_cfg.n = n;
1591 core_cfg.cts = cts;
1592 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1593 core_cfg.aud_par_busclk = 0;
1594 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1595 core_cfg.use_mclk = false;
1596 } else {
1597 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
1598 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1599 core_cfg.use_mclk = true;
1600 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1601 }
1602 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
1603 core_cfg.en_spdif = false;
1604 /* Use sample frequency from channel status word */
1605 core_cfg.fs_override = true;
1606 /* Enable ACR packets */
1607 core_cfg.en_acr_pkt = true;
1608 /* Disable direct streaming digital audio */
1609 core_cfg.en_dsd_audio = false;
1610 /* Use parallel audio interface */
1611 core_cfg.en_parallel_aud_input = true;
1612
1613 hdmi_core_audio_config(&core_cfg);
1614
1615 /*
1616 * Configure packet
1617 * info frame audio see doc CEA861-D page 74
1618 */
1619 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
1620 aud_if_cfg.db1_channel_count = 2;
1621 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
1622 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
1623 aud_if_cfg.db4_channel_alloc = 0x00;
1624 aud_if_cfg.db5_downmix_inh = false;
1625 aud_if_cfg.db5_lsv = 0;
1626
1627 hdmi_core_audio_infoframe_config(&aud_if_cfg);
1628 return 0;
1629 }
1630
1631 static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1632 struct snd_soc_dai *dai)
1633 {
1634 int err = 0;
1635 switch (cmd) {
1636 case SNDRV_PCM_TRIGGER_START:
1637 case SNDRV_PCM_TRIGGER_RESUME:
1638 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1639 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 1, 0, 0);
1640 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 31, 31);
1641 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 30, 30);
1642 break;
1643
1644 case SNDRV_PCM_TRIGGER_STOP:
1645 case SNDRV_PCM_TRIGGER_SUSPEND:
1646 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1647 REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 0, 0, 0);
1648 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 30, 30);
1649 REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 31, 31);
1650 break;
1651 default:
1652 err = -EINVAL;
1653 }
1654 return err;
1655 }
1656
1657 static int hdmi_audio_startup(struct snd_pcm_substream *substream,
1658 struct snd_soc_dai *dai)
1659 {
1660 if (!hdmi.mode) {
1661 pr_err("Current video settings do not support audio.\n");
1662 return -EIO;
1663 }
1664 return 0;
1665 }
1666
1667 static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
1668 };
1669
1670 static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
1671 .hw_params = hdmi_audio_hw_params,
1672 .trigger = hdmi_audio_trigger,
1673 .startup = hdmi_audio_startup,
1674 };
1675
1676 static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
1677 .name = "hdmi-audio-codec",
1678 .playback = {
1679 .channels_min = 2,
1680 .channels_max = 2,
1681 .rates = SNDRV_PCM_RATE_32000 |
1682 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1683 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1684 SNDRV_PCM_FMTBIT_S24_LE,
1685 },
1686 .ops = &hdmi_audio_codec_ops,
1687 };
1688 #endif
1689
1690 /* HDMI HW IP initialisation */
1691 static int omapdss_hdmihw_probe(struct platform_device *pdev)
1692 {
1693 struct resource *hdmi_mem;
1694 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1695 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1696 int ret;
1697 #endif
1698
1699 hdmi.pdata = pdev->dev.platform_data;
1700 hdmi.pdev = pdev;
1701
1702 mutex_init(&hdmi.lock);
1703
1704 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1705 if (!hdmi_mem) {
1706 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1707 return -EINVAL;
1708 }
1709
1710 /* Base address taken from platform */
1711 hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem));
1712 if (!hdmi.base_wp) {
1713 DSSERR("can't ioremap WP\n");
1714 return -ENOMEM;
1715 }
1716
1717 hdmi_panel_init();
1718
1719 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1720 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1721
1722 /* Register ASoC codec DAI */
1723 ret = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
1724 &hdmi_codec_dai_drv, 1);
1725 if (ret) {
1726 DSSERR("can't register ASoC HDMI audio codec\n");
1727 return ret;
1728 }
1729 #endif
1730 return 0;
1731 }
1732
1733 static int omapdss_hdmihw_remove(struct platform_device *pdev)
1734 {
1735 hdmi_panel_exit();
1736
1737 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1738 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1739 snd_soc_unregister_codec(&pdev->dev);
1740 #endif
1741
1742 iounmap(hdmi.base_wp);
1743
1744 return 0;
1745 }
1746
1747 static struct platform_driver omapdss_hdmihw_driver = {
1748 .probe = omapdss_hdmihw_probe,
1749 .remove = omapdss_hdmihw_remove,
1750 .driver = {
1751 .name = "omapdss_hdmi",
1752 .owner = THIS_MODULE,
1753 },
1754 };
1755
1756 int hdmi_init_platform_driver(void)
1757 {
1758 return platform_driver_register(&omapdss_hdmihw_driver);
1759 }
1760
1761 void hdmi_uninit_platform_driver(void)
1762 {
1763 return platform_driver_unregister(&omapdss_hdmihw_driver);
1764 }
Linux kernel - Deliverables
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