4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <video/omapdss.h>
36 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38 #include <sound/soc.h>
39 #include <sound/pcm_params.h>
40 #include "ti_hdmi_4xxx_ip.h"
45 #include "dss_features.h"
48 #define HDMI_CORE_SYS 0x400
49 #define HDMI_CORE_AV 0x900
50 #define HDMI_PLLCTRL 0x200
51 #define HDMI_PHY 0x300
53 /* HDMI EDID Length move this */
54 #define HDMI_EDID_MAX_LENGTH 256
55 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
56 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
57 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
58 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
59 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
61 #define HDMI_DEFAULT_REGN 16
62 #define HDMI_DEFAULT_REGM2 1
66 struct platform_device
*pdev
;
67 struct hdmi_ip_data ip_data
;
73 * Logic for the below structure :
74 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
75 * There is a correspondence between CEA/VESA timing and code, please
76 * refer to section 6.3 in HDMI 1.3 specification for timing code.
78 * In the below structure, cea_vesa_timings corresponds to all OMAP4
79 * supported CEA and VESA timing values.code_cea corresponds to the CEA
80 * code, It is used to get the timing from cea_vesa_timing array.Similarly
81 * with code_vesa. Code_index is used for back mapping, that is once EDID
82 * is read from the TV, EDID is parsed to find the timing values and then
83 * map it to corresponding CEA or VESA index.
86 static const struct hdmi_config cea_timings
[] = {
87 { {640, 480, 25200, 96, 16, 48, 2, 10, 33, 0, 0, 0}, {1, HDMI_HDMI
} },
88 { {720, 480, 27027, 62, 16, 60, 6, 9, 30, 0, 0, 0}, {2, HDMI_HDMI
} },
89 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {4, HDMI_HDMI
} },
90 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15, 1, 1, 1}, {5, HDMI_HDMI
} },
91 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15, 0, 0, 1}, {6, HDMI_HDMI
} },
92 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36, 1, 1, 0}, {16, HDMI_HDMI
} },
93 { {720, 576, 27000, 64, 12, 68, 5, 5, 39, 0, 0, 0}, {17, HDMI_HDMI
} },
94 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20, 1, 1, 0}, {19, HDMI_HDMI
} },
95 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15, 1, 1, 1}, {20, HDMI_HDMI
} },
96 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19, 0, 0, 1}, {21, HDMI_HDMI
} },
97 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39, 0, 0, 0}, {29, HDMI_HDMI
} },
98 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36, 1, 1, 0}, {31, HDMI_HDMI
} },
99 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36, 1, 1, 0}, {32, HDMI_HDMI
} },
100 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30, 0, 0, 0}, {35, HDMI_HDMI
} },
101 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39, 0, 0, 0}, {37, HDMI_HDMI
} },
103 static const struct hdmi_config vesa_timings
[] = {
105 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31, 0, 0, 0}, {4, HDMI_DVI
} },
106 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23, 1, 1, 0}, {9, HDMI_DVI
} },
107 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23, 1, 1, 0}, {0xE, HDMI_DVI
} },
108 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20, 1, 0, 0}, {0x17, HDMI_DVI
} },
109 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22, 1, 0, 0}, {0x1C, HDMI_DVI
} },
110 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18, 1, 1, 0}, {0x27, HDMI_DVI
} },
111 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36, 1, 1, 0}, {0x20, HDMI_DVI
} },
112 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38, 1, 1, 0}, {0x23, HDMI_DVI
} },
113 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29, 0, 0, 0}, {0x10, HDMI_DVI
} },
114 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32, 1, 0, 0}, {0x2A, HDMI_DVI
} },
115 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25, 1, 0, 0}, {0x2F, HDMI_DVI
} },
116 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, 1, 0, 0}, {0x3A, HDMI_DVI
} },
117 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24, 1, 1, 0}, {0x51, HDMI_DVI
} },
118 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36, 1, 1, 0}, {0x52, HDMI_DVI
} },
119 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12, 0, 1, 0}, {0x16, HDMI_DVI
} },
120 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23, 0, 1, 0}, {0x29, HDMI_DVI
} },
121 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21, 0, 1, 0}, {0x39, HDMI_DVI
} },
122 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14, 0, 1, 0}, {0x1B, HDMI_DVI
} },
123 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20, 1, 1, 0}, {0x55, HDMI_DVI
} }
126 static int hdmi_runtime_get(void)
130 DSSDBG("hdmi_runtime_get\n");
132 r
= pm_runtime_get_sync(&hdmi
.pdev
->dev
);
140 static void hdmi_runtime_put(void)
144 DSSDBG("hdmi_runtime_put\n");
146 r
= pm_runtime_put_sync(&hdmi
.pdev
->dev
);
150 int hdmi_init_display(struct omap_dss_device
*dssdev
)
152 DSSDBG("init_display\n");
154 dss_init_hdmi_ip_ops(&hdmi
.ip_data
);
158 static const struct hdmi_config
*hdmi_find_timing(
159 const struct hdmi_config
*timings_arr
,
164 for (i
= 0; i
< len
; i
++) {
165 if (timings_arr
[i
].cm
.code
== hdmi
.ip_data
.cfg
.cm
.code
)
166 return &timings_arr
[i
];
171 static const struct hdmi_config
*hdmi_get_timings(void)
173 const struct hdmi_config
*arr
;
176 if (hdmi
.ip_data
.cfg
.cm
.mode
== HDMI_DVI
) {
178 len
= ARRAY_SIZE(vesa_timings
);
181 len
= ARRAY_SIZE(cea_timings
);
184 return hdmi_find_timing(arr
, len
);
187 static bool hdmi_timings_compare(struct omap_video_timings
*timing1
,
188 const struct hdmi_video_timings
*timing2
)
190 int timing1_vsync
, timing1_hsync
, timing2_vsync
, timing2_hsync
;
192 if ((timing2
->pixel_clock
== timing1
->pixel_clock
) &&
193 (timing2
->x_res
== timing1
->x_res
) &&
194 (timing2
->y_res
== timing1
->y_res
)) {
196 timing2_hsync
= timing2
->hfp
+ timing2
->hsw
+ timing2
->hbp
;
197 timing1_hsync
= timing1
->hfp
+ timing1
->hsw
+ timing1
->hbp
;
198 timing2_vsync
= timing2
->vfp
+ timing2
->vsw
+ timing2
->vbp
;
199 timing1_vsync
= timing2
->vfp
+ timing2
->vsw
+ timing2
->vbp
;
201 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
202 "timing2_hsync = %d timing2_vsync = %d\n",
203 timing1_hsync
, timing1_vsync
,
204 timing2_hsync
, timing2_vsync
);
206 if ((timing1_hsync
== timing2_hsync
) &&
207 (timing1_vsync
== timing2_vsync
)) {
214 static struct hdmi_cm
hdmi_get_code(struct omap_video_timings
*timing
)
217 struct hdmi_cm cm
= {-1};
218 DSSDBG("hdmi_get_code\n");
220 for (i
= 0; i
< ARRAY_SIZE(cea_timings
); i
++) {
221 if (hdmi_timings_compare(timing
, &cea_timings
[i
].timings
)) {
222 cm
= cea_timings
[i
].cm
;
226 for (i
= 0; i
< ARRAY_SIZE(vesa_timings
); i
++) {
227 if (hdmi_timings_compare(timing
, &vesa_timings
[i
].timings
)) {
228 cm
= vesa_timings
[i
].cm
;
237 unsigned long hdmi_get_pixel_clock(void)
239 /* HDMI Pixel Clock in Mhz */
240 return hdmi
.ip_data
.cfg
.timings
.pixel_clock
* 1000;
243 static void hdmi_compute_pll(struct omap_dss_device
*dssdev
, int phy
,
244 struct hdmi_pll_info
*pi
)
246 unsigned long clkin
, refclk
;
249 clkin
= clk_get_rate(hdmi
.sys_clk
) / 10000;
251 * Input clock is predivided by N + 1
252 * out put of which is reference clk
254 if (dssdev
->clocks
.hdmi
.regn
== 0)
255 pi
->regn
= HDMI_DEFAULT_REGN
;
257 pi
->regn
= dssdev
->clocks
.hdmi
.regn
;
259 refclk
= clkin
/ pi
->regn
;
261 if (dssdev
->clocks
.hdmi
.regm2
== 0)
262 pi
->regm2
= HDMI_DEFAULT_REGM2
;
264 pi
->regm2
= dssdev
->clocks
.hdmi
.regm2
;
267 * multiplier is pixel_clk/ref_clk
268 * Multiplying by 100 to avoid fractional part removal
270 pi
->regm
= phy
* pi
->regm2
/ refclk
;
273 * fractional multiplier is remainder of the difference between
274 * multiplier and actual phy(required pixel clock thus should be
275 * multiplied by 2^18(262144) divided by the reference clock
277 mf
= (phy
- pi
->regm
/ pi
->regm2
* refclk
) * 262144;
278 pi
->regmf
= pi
->regm2
* mf
/ refclk
;
281 * Dcofreq should be set to 1 if required pixel clock
282 * is greater than 1000MHz
284 pi
->dcofreq
= phy
> 1000 * 100;
285 pi
->regsd
= ((pi
->regm
* clkin
/ 10) / (pi
->regn
* 250) + 5) / 10;
287 /* Set the reference clock to sysclk reference */
288 pi
->refsel
= HDMI_REFSEL_SYSCLK
;
290 DSSDBG("M = %d Mf = %d\n", pi
->regm
, pi
->regmf
);
291 DSSDBG("range = %d sd = %d\n", pi
->dcofreq
, pi
->regsd
);
294 static int hdmi_power_on(struct omap_dss_device
*dssdev
)
297 const struct hdmi_config
*timing
;
298 struct omap_video_timings
*p
;
301 r
= hdmi_runtime_get();
305 dss_mgr_disable(dssdev
->manager
);
307 p
= &dssdev
->panel
.timings
;
309 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
310 dssdev
->panel
.timings
.x_res
,
311 dssdev
->panel
.timings
.y_res
);
313 timing
= hdmi_get_timings();
314 if (timing
== NULL
) {
315 /* HDMI code 4 corresponds to 640 * 480 VGA */
316 hdmi
.ip_data
.cfg
.cm
.code
= 4;
317 /* DVI mode 1 corresponds to HDMI 0 to DVI */
318 hdmi
.ip_data
.cfg
.cm
.mode
= HDMI_DVI
;
319 hdmi
.ip_data
.cfg
= vesa_timings
[0];
321 hdmi
.ip_data
.cfg
= *timing
;
323 phy
= p
->pixel_clock
;
325 hdmi_compute_pll(dssdev
, phy
, &hdmi
.ip_data
.pll_data
);
327 hdmi
.ip_data
.ops
->video_enable(&hdmi
.ip_data
, 0);
329 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
330 r
= hdmi
.ip_data
.ops
->pll_enable(&hdmi
.ip_data
);
332 DSSDBG("Failed to lock PLL\n");
336 r
= hdmi
.ip_data
.ops
->phy_enable(&hdmi
.ip_data
);
338 DSSDBG("Failed to start PHY\n");
342 hdmi
.ip_data
.ops
->video_configure(&hdmi
.ip_data
);
344 /* Make selection of HDMI in DSS */
345 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK
);
347 /* Select the dispc clock source as PRCM clock, to ensure that it is not
348 * DSI PLL source as the clock selected by DSI PLL might not be
349 * sufficient for the resolution selected / that can be changed
350 * dynamically by user. This can be moved to single location , say
353 dss_select_dispc_clk_source(dssdev
->clocks
.dispc
.dispc_fclk_src
);
355 /* bypass TV gamma table */
356 dispc_enable_gamma_table(0);
359 dss_mgr_set_timings(dssdev
->manager
, &dssdev
->panel
.timings
);
361 hdmi
.ip_data
.ops
->video_enable(&hdmi
.ip_data
, 1);
363 r
= dss_mgr_enable(dssdev
->manager
);
370 hdmi
.ip_data
.ops
->video_enable(&hdmi
.ip_data
, 0);
371 hdmi
.ip_data
.ops
->phy_disable(&hdmi
.ip_data
);
372 hdmi
.ip_data
.ops
->pll_disable(&hdmi
.ip_data
);
378 static void hdmi_power_off(struct omap_dss_device
*dssdev
)
380 dss_mgr_disable(dssdev
->manager
);
382 hdmi
.ip_data
.ops
->video_enable(&hdmi
.ip_data
, 0);
383 hdmi
.ip_data
.ops
->phy_disable(&hdmi
.ip_data
);
384 hdmi
.ip_data
.ops
->pll_disable(&hdmi
.ip_data
);
388 int omapdss_hdmi_display_check_timing(struct omap_dss_device
*dssdev
,
389 struct omap_video_timings
*timings
)
393 cm
= hdmi_get_code(timings
);
402 void omapdss_hdmi_display_set_timing(struct omap_dss_device
*dssdev
)
406 cm
= hdmi_get_code(&dssdev
->panel
.timings
);
407 hdmi
.ip_data
.cfg
.cm
.code
= cm
.code
;
408 hdmi
.ip_data
.cfg
.cm
.mode
= cm
.mode
;
410 if (dssdev
->state
== OMAP_DSS_DISPLAY_ACTIVE
) {
413 hdmi_power_off(dssdev
);
415 r
= hdmi_power_on(dssdev
);
417 DSSERR("failed to power on device\n");
419 dss_mgr_set_timings(dssdev
->manager
, &dssdev
->panel
.timings
);
423 static void hdmi_dump_regs(struct seq_file
*s
)
425 mutex_lock(&hdmi
.lock
);
427 if (hdmi_runtime_get())
430 hdmi
.ip_data
.ops
->dump_wrapper(&hdmi
.ip_data
, s
);
431 hdmi
.ip_data
.ops
->dump_pll(&hdmi
.ip_data
, s
);
432 hdmi
.ip_data
.ops
->dump_phy(&hdmi
.ip_data
, s
);
433 hdmi
.ip_data
.ops
->dump_core(&hdmi
.ip_data
, s
);
436 mutex_unlock(&hdmi
.lock
);
439 int omapdss_hdmi_read_edid(u8
*buf
, int len
)
443 mutex_lock(&hdmi
.lock
);
445 r
= hdmi_runtime_get();
448 r
= hdmi
.ip_data
.ops
->read_edid(&hdmi
.ip_data
, buf
, len
);
451 mutex_unlock(&hdmi
.lock
);
456 bool omapdss_hdmi_detect(void)
460 mutex_lock(&hdmi
.lock
);
462 r
= hdmi_runtime_get();
465 r
= hdmi
.ip_data
.ops
->detect(&hdmi
.ip_data
);
468 mutex_unlock(&hdmi
.lock
);
473 int omapdss_hdmi_display_enable(struct omap_dss_device
*dssdev
)
475 struct omap_dss_hdmi_data
*priv
= dssdev
->data
;
478 DSSDBG("ENTER hdmi_display_enable\n");
480 mutex_lock(&hdmi
.lock
);
482 if (dssdev
->manager
== NULL
) {
483 DSSERR("failed to enable display: no manager\n");
488 hdmi
.ip_data
.hpd_gpio
= priv
->hpd_gpio
;
490 r
= omap_dss_start_device(dssdev
);
492 DSSERR("failed to start device\n");
496 if (dssdev
->platform_enable
) {
497 r
= dssdev
->platform_enable(dssdev
);
499 DSSERR("failed to enable GPIO's\n");
504 r
= hdmi_power_on(dssdev
);
506 DSSERR("failed to power on device\n");
510 mutex_unlock(&hdmi
.lock
);
514 if (dssdev
->platform_disable
)
515 dssdev
->platform_disable(dssdev
);
517 omap_dss_stop_device(dssdev
);
519 mutex_unlock(&hdmi
.lock
);
523 void omapdss_hdmi_display_disable(struct omap_dss_device
*dssdev
)
525 DSSDBG("Enter hdmi_display_disable\n");
527 mutex_lock(&hdmi
.lock
);
529 hdmi_power_off(dssdev
);
531 if (dssdev
->platform_disable
)
532 dssdev
->platform_disable(dssdev
);
534 omap_dss_stop_device(dssdev
);
536 mutex_unlock(&hdmi
.lock
);
539 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
540 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
542 static int hdmi_audio_trigger(struct snd_pcm_substream
*substream
, int cmd
,
543 struct snd_soc_dai
*dai
)
545 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
546 struct snd_soc_codec
*codec
= rtd
->codec
;
547 struct platform_device
*pdev
= to_platform_device(codec
->dev
);
548 struct hdmi_ip_data
*ip_data
= snd_soc_codec_get_drvdata(codec
);
551 if (!(ip_data
->ops
) && !(ip_data
->ops
->audio_enable
)) {
552 dev_err(&pdev
->dev
, "Cannot enable/disable audio\n");
557 case SNDRV_PCM_TRIGGER_START
:
558 case SNDRV_PCM_TRIGGER_RESUME
:
559 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
560 ip_data
->ops
->audio_enable(ip_data
, true);
562 case SNDRV_PCM_TRIGGER_STOP
:
563 case SNDRV_PCM_TRIGGER_SUSPEND
:
564 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
565 ip_data
->ops
->audio_enable(ip_data
, false);
573 static int hdmi_audio_hw_params(struct snd_pcm_substream
*substream
,
574 struct snd_pcm_hw_params
*params
,
575 struct snd_soc_dai
*dai
)
577 struct snd_soc_pcm_runtime
*rtd
= substream
->private_data
;
578 struct snd_soc_codec
*codec
= rtd
->codec
;
579 struct hdmi_ip_data
*ip_data
= snd_soc_codec_get_drvdata(codec
);
580 struct hdmi_audio_format audio_format
;
581 struct hdmi_audio_dma audio_dma
;
582 struct hdmi_core_audio_config core_cfg
;
583 struct hdmi_core_infoframe_audio aud_if_cfg
;
585 enum hdmi_core_audio_sample_freq sample_freq
;
587 switch (params_format(params
)) {
588 case SNDRV_PCM_FORMAT_S16_LE
:
589 core_cfg
.i2s_cfg
.word_max_length
=
590 HDMI_AUDIO_I2S_MAX_WORD_20BITS
;
591 core_cfg
.i2s_cfg
.word_length
= HDMI_AUDIO_I2S_CHST_WORD_16_BITS
;
592 core_cfg
.i2s_cfg
.in_length_bits
=
593 HDMI_AUDIO_I2S_INPUT_LENGTH_16
;
594 core_cfg
.i2s_cfg
.justification
= HDMI_AUDIO_JUSTIFY_LEFT
;
595 audio_format
.samples_per_word
= HDMI_AUDIO_ONEWORD_TWOSAMPLES
;
596 audio_format
.sample_size
= HDMI_AUDIO_SAMPLE_16BITS
;
597 audio_format
.justification
= HDMI_AUDIO_JUSTIFY_LEFT
;
598 audio_dma
.transfer_size
= 0x10;
600 case SNDRV_PCM_FORMAT_S24_LE
:
601 core_cfg
.i2s_cfg
.word_max_length
=
602 HDMI_AUDIO_I2S_MAX_WORD_24BITS
;
603 core_cfg
.i2s_cfg
.word_length
= HDMI_AUDIO_I2S_CHST_WORD_24_BITS
;
604 core_cfg
.i2s_cfg
.in_length_bits
=
605 HDMI_AUDIO_I2S_INPUT_LENGTH_24
;
606 audio_format
.samples_per_word
= HDMI_AUDIO_ONEWORD_ONESAMPLE
;
607 audio_format
.sample_size
= HDMI_AUDIO_SAMPLE_24BITS
;
608 audio_format
.justification
= HDMI_AUDIO_JUSTIFY_RIGHT
;
609 core_cfg
.i2s_cfg
.justification
= HDMI_AUDIO_JUSTIFY_RIGHT
;
610 audio_dma
.transfer_size
= 0x20;
616 switch (params_rate(params
)) {
618 sample_freq
= HDMI_AUDIO_FS_32000
;
621 sample_freq
= HDMI_AUDIO_FS_44100
;
624 sample_freq
= HDMI_AUDIO_FS_48000
;
630 err
= hdmi_config_audio_acr(ip_data
, params_rate(params
), &n
, &cts
);
634 /* Audio wrapper config */
635 audio_format
.stereo_channels
= HDMI_AUDIO_STEREO_ONECHANNEL
;
636 audio_format
.active_chnnls_msk
= 0x03;
637 audio_format
.type
= HDMI_AUDIO_TYPE_LPCM
;
638 audio_format
.sample_order
= HDMI_AUDIO_SAMPLE_LEFT_FIRST
;
639 /* Disable start/stop signals of IEC 60958 blocks */
640 audio_format
.en_sig_blk_strt_end
= HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF
;
642 audio_dma
.block_size
= 0xC0;
643 audio_dma
.mode
= HDMI_AUDIO_TRANSF_DMA
;
644 audio_dma
.fifo_threshold
= 0x20; /* in number of samples */
646 hdmi_wp_audio_config_dma(ip_data
, &audio_dma
);
647 hdmi_wp_audio_config_format(ip_data
, &audio_format
);
652 core_cfg
.i2s_cfg
.en_high_bitrate_aud
= false;
653 /* Only used with high bitrate audio */
654 core_cfg
.i2s_cfg
.cbit_order
= false;
655 /* Serial data and word select should change on sck rising edge */
656 core_cfg
.i2s_cfg
.sck_edge_mode
= HDMI_AUDIO_I2S_SCK_EDGE_RISING
;
657 core_cfg
.i2s_cfg
.vbit
= HDMI_AUDIO_I2S_VBIT_FOR_PCM
;
658 /* Set I2S word select polarity */
659 core_cfg
.i2s_cfg
.ws_polarity
= HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT
;
660 core_cfg
.i2s_cfg
.direction
= HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST
;
661 /* Set serial data to word select shift. See Phillips spec. */
662 core_cfg
.i2s_cfg
.shift
= HDMI_AUDIO_I2S_FIRST_BIT_SHIFT
;
663 /* Enable one of the four available serial data channels */
664 core_cfg
.i2s_cfg
.active_sds
= HDMI_AUDIO_I2S_SD0_EN
;
666 /* Core audio config */
667 core_cfg
.freq_sample
= sample_freq
;
670 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE
)) {
671 core_cfg
.aud_par_busclk
= 0;
672 core_cfg
.cts_mode
= HDMI_AUDIO_CTS_MODE_SW
;
673 core_cfg
.use_mclk
= dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK
);
675 core_cfg
.aud_par_busclk
= (((128 * 31) - 1) << 8);
676 core_cfg
.cts_mode
= HDMI_AUDIO_CTS_MODE_HW
;
677 core_cfg
.use_mclk
= true;
680 if (core_cfg
.use_mclk
)
681 core_cfg
.mclk_mode
= HDMI_AUDIO_MCLK_128FS
;
682 core_cfg
.layout
= HDMI_AUDIO_LAYOUT_2CH
;
683 core_cfg
.en_spdif
= false;
684 /* Use sample frequency from channel status word */
685 core_cfg
.fs_override
= true;
686 /* Enable ACR packets */
687 core_cfg
.en_acr_pkt
= true;
688 /* Disable direct streaming digital audio */
689 core_cfg
.en_dsd_audio
= false;
690 /* Use parallel audio interface */
691 core_cfg
.en_parallel_aud_input
= true;
693 hdmi_core_audio_config(ip_data
, &core_cfg
);
697 * info frame audio see doc CEA861-D page 74
699 aud_if_cfg
.db1_coding_type
= HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM
;
700 aud_if_cfg
.db1_channel_count
= 2;
701 aud_if_cfg
.db2_sample_freq
= HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM
;
702 aud_if_cfg
.db2_sample_size
= HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM
;
703 aud_if_cfg
.db4_channel_alloc
= 0x00;
704 aud_if_cfg
.db5_downmix_inh
= false;
705 aud_if_cfg
.db5_lsv
= 0;
707 hdmi_core_audio_infoframe_config(ip_data
, &aud_if_cfg
);
711 static int hdmi_audio_startup(struct snd_pcm_substream
*substream
,
712 struct snd_soc_dai
*dai
)
714 if (!hdmi
.ip_data
.cfg
.cm
.mode
) {
715 pr_err("Current video settings do not support audio.\n");
721 static int hdmi_audio_codec_probe(struct snd_soc_codec
*codec
)
723 struct hdmi_ip_data
*priv
= &hdmi
.ip_data
;
725 snd_soc_codec_set_drvdata(codec
, priv
);
729 static struct snd_soc_codec_driver hdmi_audio_codec_drv
= {
730 .probe
= hdmi_audio_codec_probe
,
733 static struct snd_soc_dai_ops hdmi_audio_codec_ops
= {
734 .hw_params
= hdmi_audio_hw_params
,
735 .trigger
= hdmi_audio_trigger
,
736 .startup
= hdmi_audio_startup
,
739 static struct snd_soc_dai_driver hdmi_codec_dai_drv
= {
740 .name
= "hdmi-audio-codec",
744 .rates
= SNDRV_PCM_RATE_32000
|
745 SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
746 .formats
= SNDRV_PCM_FMTBIT_S16_LE
|
747 SNDRV_PCM_FMTBIT_S24_LE
,
749 .ops
= &hdmi_audio_codec_ops
,
753 static int hdmi_get_clocks(struct platform_device
*pdev
)
757 clk
= clk_get(&pdev
->dev
, "sys_clk");
759 DSSERR("can't get sys_clk\n");
768 static void hdmi_put_clocks(void)
771 clk_put(hdmi
.sys_clk
);
774 /* HDMI HW IP initialisation */
775 static int omapdss_hdmihw_probe(struct platform_device
*pdev
)
777 struct resource
*hdmi_mem
;
782 mutex_init(&hdmi
.lock
);
784 hdmi_mem
= platform_get_resource(hdmi
.pdev
, IORESOURCE_MEM
, 0);
786 DSSERR("can't get IORESOURCE_MEM HDMI\n");
790 /* Base address taken from platform */
791 hdmi
.ip_data
.base_wp
= ioremap(hdmi_mem
->start
,
792 resource_size(hdmi_mem
));
793 if (!hdmi
.ip_data
.base_wp
) {
794 DSSERR("can't ioremap WP\n");
798 r
= hdmi_get_clocks(pdev
);
800 iounmap(hdmi
.ip_data
.base_wp
);
804 pm_runtime_enable(&pdev
->dev
);
806 hdmi
.ip_data
.core_sys_offset
= HDMI_CORE_SYS
;
807 hdmi
.ip_data
.core_av_offset
= HDMI_CORE_AV
;
808 hdmi
.ip_data
.pll_offset
= HDMI_PLLCTRL
;
809 hdmi
.ip_data
.phy_offset
= HDMI_PHY
;
813 dss_debugfs_create_file("hdmi", hdmi_dump_regs
);
815 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
816 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
818 /* Register ASoC codec DAI */
819 r
= snd_soc_register_codec(&pdev
->dev
, &hdmi_audio_codec_drv
,
820 &hdmi_codec_dai_drv
, 1);
822 DSSERR("can't register ASoC HDMI audio codec\n");
829 static int omapdss_hdmihw_remove(struct platform_device
*pdev
)
833 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
834 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
835 snd_soc_unregister_codec(&pdev
->dev
);
838 pm_runtime_disable(&pdev
->dev
);
842 iounmap(hdmi
.ip_data
.base_wp
);
847 static int hdmi_runtime_suspend(struct device
*dev
)
849 clk_disable(hdmi
.sys_clk
);
856 static int hdmi_runtime_resume(struct device
*dev
)
860 r
= dispc_runtime_get();
864 clk_enable(hdmi
.sys_clk
);
869 static const struct dev_pm_ops hdmi_pm_ops
= {
870 .runtime_suspend
= hdmi_runtime_suspend
,
871 .runtime_resume
= hdmi_runtime_resume
,
874 static struct platform_driver omapdss_hdmihw_driver
= {
875 .remove
= omapdss_hdmihw_remove
,
877 .name
= "omapdss_hdmi",
878 .owner
= THIS_MODULE
,
883 int hdmi_init_platform_driver(void)
885 return platform_driver_probe(&omapdss_hdmihw_driver
, omapdss_hdmihw_probe
);
888 void hdmi_uninit_platform_driver(void)
890 platform_driver_unregister(&omapdss_hdmihw_driver
);