4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <video/omapdss.h>
41 #include "dss_features.h"
44 #define HDMI_CORE_SYS 0x400
45 #define HDMI_CORE_AV 0x900
46 #define HDMI_PLLCTRL 0x200
47 #define HDMI_PHY 0x300
49 /* HDMI EDID Length move this */
50 #define HDMI_EDID_MAX_LENGTH 256
51 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
57 #define HDMI_DEFAULT_REGN 16
58 #define HDMI_DEFAULT_REGM2 1
62 struct platform_device
*pdev
;
64 struct hdmi_ip_data ip_data
;
67 struct regulator
*vdda_hdmi_dac_reg
;
73 struct omap_dss_device output
;
77 * Logic for the below structure :
78 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
79 * There is a correspondence between CEA/VESA timing and code, please
80 * refer to section 6.3 in HDMI 1.3 specification for timing code.
82 * In the below structure, cea_vesa_timings corresponds to all OMAP4
83 * supported CEA and VESA timing values.code_cea corresponds to the CEA
84 * code, It is used to get the timing from cea_vesa_timing array.Similarly
85 * with code_vesa. Code_index is used for back mapping, that is once EDID
86 * is read from the TV, EDID is parsed to find the timing values and then
87 * map it to corresponding CEA or VESA index.
90 static const struct hdmi_config cea_timings
[] = {
92 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
93 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
98 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
99 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
104 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
105 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
110 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
111 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
116 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
117 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
122 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
123 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
128 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
129 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
134 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
135 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
140 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
141 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
146 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
147 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
152 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
153 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
158 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
159 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
164 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
165 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
170 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
171 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
176 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
177 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
183 static const struct hdmi_config vesa_timings
[] = {
186 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
187 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
192 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
193 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
198 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
199 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
204 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
205 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_LOW
,
210 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
211 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_LOW
,
216 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
217 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
222 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
223 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
228 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
229 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
234 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
235 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_LOW
,
240 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
241 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_LOW
,
246 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
247 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_LOW
,
252 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
253 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_LOW
,
258 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
259 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
264 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
265 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
270 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
271 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_HIGH
,
276 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
277 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_HIGH
,
282 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
283 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_HIGH
,
288 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
289 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_HIGH
,
294 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
295 OMAPDSS_SIG_ACTIVE_HIGH
, OMAPDSS_SIG_ACTIVE_HIGH
,
300 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
301 OMAPDSS_SIG_ACTIVE_LOW
, OMAPDSS_SIG_ACTIVE_HIGH
,
307 static int hdmi_runtime_get(void)
311 DSSDBG("hdmi_runtime_get\n");
313 r
= pm_runtime_get_sync(&hdmi
.pdev
->dev
);
321 static void hdmi_runtime_put(void)
325 DSSDBG("hdmi_runtime_put\n");
327 r
= pm_runtime_put_sync(&hdmi
.pdev
->dev
);
328 WARN_ON(r
< 0 && r
!= -ENOSYS
);
331 static int hdmi_init_regulator(void)
333 struct regulator
*reg
;
335 if (hdmi
.vdda_hdmi_dac_reg
!= NULL
)
338 reg
= devm_regulator_get(&hdmi
.pdev
->dev
, "vdda_hdmi_dac");
340 /* DT HACK: try VDAC to make omapdss work for o4 sdp/panda */
342 reg
= devm_regulator_get(&hdmi
.pdev
->dev
, "VDAC");
345 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
349 hdmi
.vdda_hdmi_dac_reg
= reg
;
354 static int hdmi_init_display(struct omap_dss_device
*dssdev
)
358 struct gpio gpios
[] = {
359 { hdmi
.ct_cp_hpd_gpio
, GPIOF_OUT_INIT_LOW
, "hdmi_ct_cp_hpd" },
360 { hdmi
.ls_oe_gpio
, GPIOF_OUT_INIT_LOW
, "hdmi_ls_oe" },
361 { hdmi
.hpd_gpio
, GPIOF_DIR_IN
, "hdmi_hpd" },
364 DSSDBG("init_display\n");
366 dss_init_hdmi_ip_ops(&hdmi
.ip_data
, omapdss_get_version());
368 r
= hdmi_init_regulator();
372 r
= gpio_request_array(gpios
, ARRAY_SIZE(gpios
));
379 static void hdmi_uninit_display(struct omap_dss_device
*dssdev
)
381 DSSDBG("uninit_display\n");
383 gpio_free(hdmi
.ct_cp_hpd_gpio
);
384 gpio_free(hdmi
.ls_oe_gpio
);
385 gpio_free(hdmi
.hpd_gpio
);
388 static const struct hdmi_config
*hdmi_find_timing(
389 const struct hdmi_config
*timings_arr
,
394 for (i
= 0; i
< len
; i
++) {
395 if (timings_arr
[i
].cm
.code
== hdmi
.ip_data
.cfg
.cm
.code
)
396 return &timings_arr
[i
];
401 static const struct hdmi_config
*hdmi_get_timings(void)
403 const struct hdmi_config
*arr
;
406 if (hdmi
.ip_data
.cfg
.cm
.mode
== HDMI_DVI
) {
408 len
= ARRAY_SIZE(vesa_timings
);
411 len
= ARRAY_SIZE(cea_timings
);
414 return hdmi_find_timing(arr
, len
);
417 static bool hdmi_timings_compare(struct omap_video_timings
*timing1
,
418 const struct omap_video_timings
*timing2
)
420 int timing1_vsync
, timing1_hsync
, timing2_vsync
, timing2_hsync
;
422 if ((DIV_ROUND_CLOSEST(timing2
->pixel_clock
, 1000) ==
423 DIV_ROUND_CLOSEST(timing1
->pixel_clock
, 1000)) &&
424 (timing2
->x_res
== timing1
->x_res
) &&
425 (timing2
->y_res
== timing1
->y_res
)) {
427 timing2_hsync
= timing2
->hfp
+ timing2
->hsw
+ timing2
->hbp
;
428 timing1_hsync
= timing1
->hfp
+ timing1
->hsw
+ timing1
->hbp
;
429 timing2_vsync
= timing2
->vfp
+ timing2
->vsw
+ timing2
->vbp
;
430 timing1_vsync
= timing2
->vfp
+ timing2
->vsw
+ timing2
->vbp
;
432 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
433 "timing2_hsync = %d timing2_vsync = %d\n",
434 timing1_hsync
, timing1_vsync
,
435 timing2_hsync
, timing2_vsync
);
437 if ((timing1_hsync
== timing2_hsync
) &&
438 (timing1_vsync
== timing2_vsync
)) {
445 static struct hdmi_cm
hdmi_get_code(struct omap_video_timings
*timing
)
448 struct hdmi_cm cm
= {-1};
449 DSSDBG("hdmi_get_code\n");
451 for (i
= 0; i
< ARRAY_SIZE(cea_timings
); i
++) {
452 if (hdmi_timings_compare(timing
, &cea_timings
[i
].timings
)) {
453 cm
= cea_timings
[i
].cm
;
457 for (i
= 0; i
< ARRAY_SIZE(vesa_timings
); i
++) {
458 if (hdmi_timings_compare(timing
, &vesa_timings
[i
].timings
)) {
459 cm
= vesa_timings
[i
].cm
;
468 static void hdmi_compute_pll(struct omap_dss_device
*dssdev
, int phy
,
469 struct hdmi_pll_info
*pi
)
471 unsigned long clkin
, refclk
;
474 clkin
= clk_get_rate(hdmi
.sys_clk
) / 10000;
476 * Input clock is predivided by N + 1
477 * out put of which is reference clk
480 pi
->regn
= HDMI_DEFAULT_REGN
;
482 refclk
= clkin
/ pi
->regn
;
484 pi
->regm2
= HDMI_DEFAULT_REGM2
;
487 * multiplier is pixel_clk/ref_clk
488 * Multiplying by 100 to avoid fractional part removal
490 pi
->regm
= phy
* pi
->regm2
/ refclk
;
493 * fractional multiplier is remainder of the difference between
494 * multiplier and actual phy(required pixel clock thus should be
495 * multiplied by 2^18(262144) divided by the reference clock
497 mf
= (phy
- pi
->regm
/ pi
->regm2
* refclk
) * 262144;
498 pi
->regmf
= pi
->regm2
* mf
/ refclk
;
501 * Dcofreq should be set to 1 if required pixel clock
502 * is greater than 1000MHz
504 pi
->dcofreq
= phy
> 1000 * 100;
505 pi
->regsd
= ((pi
->regm
* clkin
/ 10) / (pi
->regn
* 250) + 5) / 10;
507 /* Set the reference clock to sysclk reference */
508 pi
->refsel
= HDMI_REFSEL_SYSCLK
;
510 DSSDBG("M = %d Mf = %d\n", pi
->regm
, pi
->regmf
);
511 DSSDBG("range = %d sd = %d\n", pi
->dcofreq
, pi
->regsd
);
514 static int hdmi_power_on_core(struct omap_dss_device
*dssdev
)
518 gpio_set_value(hdmi
.ct_cp_hpd_gpio
, 1);
519 gpio_set_value(hdmi
.ls_oe_gpio
, 1);
521 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
524 r
= regulator_enable(hdmi
.vdda_hdmi_dac_reg
);
526 goto err_vdac_enable
;
528 r
= hdmi_runtime_get();
530 goto err_runtime_get
;
532 /* Make selection of HDMI in DSS */
533 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK
);
538 regulator_disable(hdmi
.vdda_hdmi_dac_reg
);
540 gpio_set_value(hdmi
.ct_cp_hpd_gpio
, 0);
541 gpio_set_value(hdmi
.ls_oe_gpio
, 0);
545 static void hdmi_power_off_core(struct omap_dss_device
*dssdev
)
548 regulator_disable(hdmi
.vdda_hdmi_dac_reg
);
549 gpio_set_value(hdmi
.ct_cp_hpd_gpio
, 0);
550 gpio_set_value(hdmi
.ls_oe_gpio
, 0);
553 static int hdmi_power_on_full(struct omap_dss_device
*dssdev
)
556 struct omap_video_timings
*p
;
557 struct omap_overlay_manager
*mgr
= hdmi
.output
.manager
;
560 r
= hdmi_power_on_core(dssdev
);
564 dss_mgr_disable(mgr
);
566 p
= &hdmi
.ip_data
.cfg
.timings
;
568 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p
->x_res
, p
->y_res
);
570 phy
= p
->pixel_clock
;
572 hdmi_compute_pll(dssdev
, phy
, &hdmi
.ip_data
.pll_data
);
574 hdmi
.ip_data
.ops
->video_disable(&hdmi
.ip_data
);
576 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
577 r
= hdmi
.ip_data
.ops
->pll_enable(&hdmi
.ip_data
);
579 DSSDBG("Failed to lock PLL\n");
583 r
= hdmi
.ip_data
.ops
->phy_enable(&hdmi
.ip_data
);
585 DSSDBG("Failed to start PHY\n");
589 hdmi
.ip_data
.ops
->video_configure(&hdmi
.ip_data
);
591 /* bypass TV gamma table */
592 dispc_enable_gamma_table(0);
595 dss_mgr_set_timings(mgr
, p
);
597 r
= hdmi
.ip_data
.ops
->video_enable(&hdmi
.ip_data
);
601 r
= dss_mgr_enable(mgr
);
608 hdmi
.ip_data
.ops
->video_disable(&hdmi
.ip_data
);
610 hdmi
.ip_data
.ops
->phy_disable(&hdmi
.ip_data
);
612 hdmi
.ip_data
.ops
->pll_disable(&hdmi
.ip_data
);
614 hdmi_power_off_core(dssdev
);
618 static void hdmi_power_off_full(struct omap_dss_device
*dssdev
)
620 struct omap_overlay_manager
*mgr
= hdmi
.output
.manager
;
622 dss_mgr_disable(mgr
);
624 hdmi
.ip_data
.ops
->video_disable(&hdmi
.ip_data
);
625 hdmi
.ip_data
.ops
->phy_disable(&hdmi
.ip_data
);
626 hdmi
.ip_data
.ops
->pll_disable(&hdmi
.ip_data
);
628 hdmi_power_off_core(dssdev
);
631 int omapdss_hdmi_display_check_timing(struct omap_dss_device
*dssdev
,
632 struct omap_video_timings
*timings
)
636 cm
= hdmi_get_code(timings
);
645 void omapdss_hdmi_display_set_timing(struct omap_dss_device
*dssdev
,
646 struct omap_video_timings
*timings
)
649 const struct hdmi_config
*t
;
651 mutex_lock(&hdmi
.lock
);
653 cm
= hdmi_get_code(timings
);
654 hdmi
.ip_data
.cfg
.cm
= cm
;
656 t
= hdmi_get_timings();
658 hdmi
.ip_data
.cfg
= *t
;
660 dispc_set_tv_pclk(t
->timings
.pixel_clock
* 1000);
662 mutex_unlock(&hdmi
.lock
);
665 static void hdmi_dump_regs(struct seq_file
*s
)
667 mutex_lock(&hdmi
.lock
);
669 if (hdmi_runtime_get()) {
670 mutex_unlock(&hdmi
.lock
);
674 hdmi
.ip_data
.ops
->dump_wrapper(&hdmi
.ip_data
, s
);
675 hdmi
.ip_data
.ops
->dump_pll(&hdmi
.ip_data
, s
);
676 hdmi
.ip_data
.ops
->dump_phy(&hdmi
.ip_data
, s
);
677 hdmi
.ip_data
.ops
->dump_core(&hdmi
.ip_data
, s
);
680 mutex_unlock(&hdmi
.lock
);
683 int omapdss_hdmi_read_edid(u8
*buf
, int len
)
687 mutex_lock(&hdmi
.lock
);
689 r
= hdmi_runtime_get();
692 r
= hdmi
.ip_data
.ops
->read_edid(&hdmi
.ip_data
, buf
, len
);
695 mutex_unlock(&hdmi
.lock
);
700 bool omapdss_hdmi_detect(void)
704 mutex_lock(&hdmi
.lock
);
706 r
= hdmi_runtime_get();
709 r
= gpio_get_value(hdmi
.hpd_gpio
);
712 mutex_unlock(&hdmi
.lock
);
717 int omapdss_hdmi_display_enable(struct omap_dss_device
*dssdev
)
719 struct omap_dss_device
*out
= &hdmi
.output
;
722 DSSDBG("ENTER hdmi_display_enable\n");
724 mutex_lock(&hdmi
.lock
);
726 if (out
== NULL
|| out
->manager
== NULL
) {
727 DSSERR("failed to enable display: no output/manager\n");
732 r
= hdmi_power_on_full(dssdev
);
734 DSSERR("failed to power on device\n");
738 mutex_unlock(&hdmi
.lock
);
742 mutex_unlock(&hdmi
.lock
);
746 void omapdss_hdmi_display_disable(struct omap_dss_device
*dssdev
)
748 DSSDBG("Enter hdmi_display_disable\n");
750 mutex_lock(&hdmi
.lock
);
752 hdmi_power_off_full(dssdev
);
754 mutex_unlock(&hdmi
.lock
);
757 int omapdss_hdmi_core_enable(struct omap_dss_device
*dssdev
)
761 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
763 mutex_lock(&hdmi
.lock
);
765 r
= hdmi_power_on_core(dssdev
);
767 DSSERR("failed to power on device\n");
771 mutex_unlock(&hdmi
.lock
);
775 mutex_unlock(&hdmi
.lock
);
779 void omapdss_hdmi_core_disable(struct omap_dss_device
*dssdev
)
781 DSSDBG("Enter omapdss_hdmi_core_disable\n");
783 mutex_lock(&hdmi
.lock
);
785 hdmi_power_off_core(dssdev
);
787 mutex_unlock(&hdmi
.lock
);
790 static int hdmi_get_clocks(struct platform_device
*pdev
)
794 clk
= devm_clk_get(&pdev
->dev
, "sys_clk");
796 DSSERR("can't get sys_clk\n");
805 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
806 int hdmi_compute_acr(u32 sample_freq
, u32
*n
, u32
*cts
)
809 bool deep_color_correct
= false;
810 u32 pclk
= hdmi
.ip_data
.cfg
.timings
.pixel_clock
;
812 if (n
== NULL
|| cts
== NULL
)
815 /* TODO: When implemented, query deep color mode here. */
819 * When using deep color, the default N value (as in the HDMI
820 * specification) yields to an non-integer CTS. Hence, we
821 * modify it while keeping the restrictions described in
822 * section 7.2.1 of the HDMI 1.4a specification.
824 switch (sample_freq
) {
829 if (deep_color
== 125)
830 if (pclk
== 27027 || pclk
== 74250)
831 deep_color_correct
= true;
832 if (deep_color
== 150)
834 deep_color_correct
= true;
839 if (deep_color
== 125)
841 deep_color_correct
= true;
847 if (deep_color_correct
) {
848 switch (sample_freq
) {
874 switch (sample_freq
) {
900 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
901 *cts
= pclk
* (*n
/ 128) * deep_color
/ (sample_freq
/ 10);
906 int hdmi_audio_enable(void)
908 DSSDBG("audio_enable\n");
910 return hdmi
.ip_data
.ops
->audio_enable(&hdmi
.ip_data
);
913 void hdmi_audio_disable(void)
915 DSSDBG("audio_disable\n");
917 hdmi
.ip_data
.ops
->audio_disable(&hdmi
.ip_data
);
920 int hdmi_audio_start(void)
922 DSSDBG("audio_start\n");
924 return hdmi
.ip_data
.ops
->audio_start(&hdmi
.ip_data
);
927 void hdmi_audio_stop(void)
929 DSSDBG("audio_stop\n");
931 hdmi
.ip_data
.ops
->audio_stop(&hdmi
.ip_data
);
934 bool hdmi_mode_has_audio(void)
936 if (hdmi
.ip_data
.cfg
.cm
.mode
== HDMI_HDMI
)
942 int hdmi_audio_config(struct omap_dss_audio
*audio
)
944 return hdmi
.ip_data
.ops
->audio_config(&hdmi
.ip_data
, audio
);
949 static struct omap_dss_device
*hdmi_find_dssdev(struct platform_device
*pdev
)
951 struct omap_dss_board_info
*pdata
= pdev
->dev
.platform_data
;
952 const char *def_disp_name
= omapdss_get_default_display_name();
953 struct omap_dss_device
*def_dssdev
;
958 for (i
= 0; i
< pdata
->num_devices
; ++i
) {
959 struct omap_dss_device
*dssdev
= pdata
->devices
[i
];
961 if (dssdev
->type
!= OMAP_DISPLAY_TYPE_HDMI
)
964 if (def_dssdev
== NULL
)
967 if (def_disp_name
!= NULL
&&
968 strcmp(dssdev
->name
, def_disp_name
) == 0) {
977 static int hdmi_probe_pdata(struct platform_device
*pdev
)
979 struct omap_dss_device
*plat_dssdev
;
980 struct omap_dss_device
*dssdev
;
981 struct omap_dss_hdmi_data
*priv
;
984 plat_dssdev
= hdmi_find_dssdev(pdev
);
989 dssdev
= dss_alloc_and_init_device(&pdev
->dev
);
993 dss_copy_device_pdata(dssdev
, plat_dssdev
);
997 hdmi
.ct_cp_hpd_gpio
= priv
->ct_cp_hpd_gpio
;
998 hdmi
.ls_oe_gpio
= priv
->ls_oe_gpio
;
999 hdmi
.hpd_gpio
= priv
->hpd_gpio
;
1001 r
= hdmi_init_display(dssdev
);
1003 DSSERR("device %s init failed: %d\n", dssdev
->name
, r
);
1004 dss_put_device(dssdev
);
1008 r
= omapdss_output_set_device(&hdmi
.output
, dssdev
);
1010 DSSERR("failed to connect output to new device: %s\n",
1012 dss_put_device(dssdev
);
1016 r
= dss_add_device(dssdev
);
1018 DSSERR("device %s register failed: %d\n", dssdev
->name
, r
);
1019 omapdss_output_unset_device(&hdmi
.output
);
1020 hdmi_uninit_display(dssdev
);
1021 dss_put_device(dssdev
);
1028 static void hdmi_init_output(struct platform_device
*pdev
)
1030 struct omap_dss_device
*out
= &hdmi
.output
;
1032 out
->dev
= &pdev
->dev
;
1033 out
->id
= OMAP_DSS_OUTPUT_HDMI
;
1034 out
->output_type
= OMAP_DISPLAY_TYPE_HDMI
;
1035 out
->name
= "hdmi.0";
1036 out
->dispc_channel
= OMAP_DSS_CHANNEL_DIGIT
;
1037 out
->owner
= THIS_MODULE
;
1039 omapdss_register_output(out
);
1042 static void __exit
hdmi_uninit_output(struct platform_device
*pdev
)
1044 struct omap_dss_device
*out
= &hdmi
.output
;
1046 omapdss_unregister_output(out
);
1049 /* HDMI HW IP initialisation */
1050 static int omapdss_hdmihw_probe(struct platform_device
*pdev
)
1052 struct resource
*res
;
1057 mutex_init(&hdmi
.lock
);
1058 mutex_init(&hdmi
.ip_data
.lock
);
1060 res
= platform_get_resource(hdmi
.pdev
, IORESOURCE_MEM
, 0);
1062 /* Base address taken from platform */
1063 hdmi
.ip_data
.base_wp
= devm_ioremap_resource(&pdev
->dev
, res
);
1064 if (IS_ERR(hdmi
.ip_data
.base_wp
))
1065 return PTR_ERR(hdmi
.ip_data
.base_wp
);
1067 hdmi
.ip_data
.irq
= platform_get_irq(pdev
, 0);
1068 if (hdmi
.ip_data
.irq
< 0) {
1069 DSSERR("platform_get_irq failed\n");
1073 r
= hdmi_get_clocks(pdev
);
1075 DSSERR("can't get clocks\n");
1079 pm_runtime_enable(&pdev
->dev
);
1081 hdmi
.ip_data
.core_sys_offset
= HDMI_CORE_SYS
;
1082 hdmi
.ip_data
.core_av_offset
= HDMI_CORE_AV
;
1083 hdmi
.ip_data
.pll_offset
= HDMI_PLLCTRL
;
1084 hdmi
.ip_data
.phy_offset
= HDMI_PHY
;
1086 hdmi_init_output(pdev
);
1088 r
= hdmi_panel_init();
1090 DSSERR("can't init panel\n");
1094 dss_debugfs_create_file("hdmi", hdmi_dump_regs
);
1096 if (pdev
->dev
.platform_data
) {
1097 r
= hdmi_probe_pdata(pdev
);
1106 hdmi_uninit_output(pdev
);
1107 pm_runtime_disable(&pdev
->dev
);
1111 static int __exit
hdmi_remove_child(struct device
*dev
, void *data
)
1113 struct omap_dss_device
*dssdev
= to_dss_device(dev
);
1114 hdmi_uninit_display(dssdev
);
1118 static int __exit
omapdss_hdmihw_remove(struct platform_device
*pdev
)
1120 device_for_each_child(&pdev
->dev
, NULL
, hdmi_remove_child
);
1122 dss_unregister_child_devices(&pdev
->dev
);
1126 hdmi_uninit_output(pdev
);
1128 pm_runtime_disable(&pdev
->dev
);
1133 static int hdmi_runtime_suspend(struct device
*dev
)
1135 clk_disable_unprepare(hdmi
.sys_clk
);
1137 dispc_runtime_put();
1142 static int hdmi_runtime_resume(struct device
*dev
)
1146 r
= dispc_runtime_get();
1150 clk_prepare_enable(hdmi
.sys_clk
);
1155 static const struct dev_pm_ops hdmi_pm_ops
= {
1156 .runtime_suspend
= hdmi_runtime_suspend
,
1157 .runtime_resume
= hdmi_runtime_resume
,
1160 static struct platform_driver omapdss_hdmihw_driver
= {
1161 .probe
= omapdss_hdmihw_probe
,
1162 .remove
= __exit_p(omapdss_hdmihw_remove
),
1164 .name
= "omapdss_hdmi",
1165 .owner
= THIS_MODULE
,
1170 int __init
hdmi_init_platform_driver(void)
1172 return platform_driver_register(&omapdss_hdmihw_driver
);
1175 void __exit
hdmi_uninit_platform_driver(void)
1177 platform_driver_unregister(&omapdss_hdmihw_driver
);