drivers/video/omap2/dss/hdmi_wp.c

   1 /*
   2  * HDMI wrapper
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #define DSS_SUBSYS_NAME "HDMIWP"
  12
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/io.h>
  16 #include <linux/platform_device.h>
  17 #include <video/omapdss.h>
  18
  19 #include "dss.h"
  20 #include "hdmi.h"
  21
  22 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
  23 {
  24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
  25
  26         DUMPREG(HDMI_WP_REVISION);
  27         DUMPREG(HDMI_WP_SYSCONFIG);
  28         DUMPREG(HDMI_WP_IRQSTATUS_RAW);
  29         DUMPREG(HDMI_WP_IRQSTATUS);
  30         DUMPREG(HDMI_WP_IRQENABLE_SET);
  31         DUMPREG(HDMI_WP_IRQENABLE_CLR);
  32         DUMPREG(HDMI_WP_IRQWAKEEN);
  33         DUMPREG(HDMI_WP_PWR_CTRL);
  34         DUMPREG(HDMI_WP_DEBOUNCE);
  35         DUMPREG(HDMI_WP_VIDEO_CFG);
  36         DUMPREG(HDMI_WP_VIDEO_SIZE);
  37         DUMPREG(HDMI_WP_VIDEO_TIMING_H);
  38         DUMPREG(HDMI_WP_VIDEO_TIMING_V);
  39         DUMPREG(HDMI_WP_CLK);
  40         DUMPREG(HDMI_WP_AUDIO_CFG);
  41         DUMPREG(HDMI_WP_AUDIO_CFG2);
  42         DUMPREG(HDMI_WP_AUDIO_CTRL);
  43         DUMPREG(HDMI_WP_AUDIO_DATA);
  44 }
  45
  46 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
  47 {
  48         return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
  49 }
  50
  51 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
  52 {
  53         hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
  54         /* flush posted write */
  55         hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
  56 }
  57
  58 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
  59 {
  60         hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
  61 }
  62
  63 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
  64 {
  65         hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
  66 }
  67
  68 /* PHY_PWR_CMD */
  69 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
  70 {
  71         /* Return if already the state */
  72         if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
  73                 return 0;
  74
  75         /* Command for power control of HDMI PHY */
  76         REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
  77
  78         /* Status of the power control of HDMI PHY */
  79         if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
  80                         != val) {
  81                 DSSERR("Failed to set PHY power mode to %d\n", val);
  82                 return -ETIMEDOUT;
  83         }
  84
  85         return 0;
  86 }
  87
  88 /* PLL_PWR_CMD */
  89 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
  90 {
  91         /* Command for power control of HDMI PLL */
  92         REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
  93
  94         /* wait till PHY_PWR_STATUS is set */
  95         if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
  96                         != val) {
  97                 DSSERR("Failed to set PLL_PWR_STATUS\n");
  98                 return -ETIMEDOUT;
  99         }
 100
 101         return 0;
 102 }
 103
 104 int hdmi_wp_video_start(struct hdmi_wp_data *wp)
 105 {
 106         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
 107
 108         return 0;
 109 }
 110
 111 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
 112 {
 113         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
 114 }
 115
 116 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
 117                 struct hdmi_video_format *video_fmt)
 118 {
 119         u32 l = 0;
 120
 121         REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
 122                 10, 8);
 123
 124         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 125         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 126         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
 127 }
 128
 129 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
 130                 struct omap_video_timings *timings)
 131 {
 132         u32 r;
 133         bool vsync_pol, hsync_pol;
 134         DSSDBG("Enter hdmi_wp_video_config_interface\n");
 135
 136         vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
 137         hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
 138
 139         r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
 140         r = FLD_MOD(r, vsync_pol, 7, 7);
 141         r = FLD_MOD(r, hsync_pol, 6, 6);
 142         r = FLD_MOD(r, timings->interlace, 3, 3);
 143         r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
 144         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
 145 }
 146
 147 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
 148                 struct omap_video_timings *timings)
 149 {
 150         u32 timing_h = 0;
 151         u32 timing_v = 0;
 152
 153         DSSDBG("Enter hdmi_wp_video_config_timing\n");
 154
 155         timing_h |= FLD_VAL(timings->hbp, 31, 20);
 156         timing_h |= FLD_VAL(timings->hfp, 19, 8);
 157         timing_h |= FLD_VAL(timings->hsw, 7, 0);
 158         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
 159
 160         timing_v |= FLD_VAL(timings->vbp, 31, 20);
 161         timing_v |= FLD_VAL(timings->vfp, 19, 8);
 162         timing_v |= FLD_VAL(timings->vsw, 7, 0);
 163         hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
 164 }
 165
 166 void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
 167                 struct omap_video_timings *timings, struct hdmi_config *param)
 168 {
 169         DSSDBG("Enter hdmi_wp_video_init_format\n");
 170
 171         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 172         video_fmt->y_res = param->timings.y_res;
 173         video_fmt->x_res = param->timings.x_res;
 174         if (param->timings.interlace)
 175                 video_fmt->y_res /= 2;
 176
 177         timings->hbp = param->timings.hbp;
 178         timings->hfp = param->timings.hfp;
 179         timings->hsw = param->timings.hsw;
 180         timings->vbp = param->timings.vbp;
 181         timings->vfp = param->timings.vfp;
 182         timings->vsw = param->timings.vsw;
 183         timings->vsync_level = param->timings.vsync_level;
 184         timings->hsync_level = param->timings.hsync_level;
 185         timings->interlace = param->timings.interlace;
 186 }
 187
 188 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
 189 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
 190                 struct hdmi_audio_format *aud_fmt)
 191 {
 192         u32 r;
 193
 194         DSSDBG("Enter hdmi_wp_audio_config_format\n");
 195
 196         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
 197         r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
 198         r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
 199         r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
 200         r = FLD_MOD(r, aud_fmt->type, 4, 4);
 201         r = FLD_MOD(r, aud_fmt->justification, 3, 3);
 202         r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
 203         r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
 204         r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
 205         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
 206 }
 207
 208 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
 209                 struct hdmi_audio_dma *aud_dma)
 210 {
 211         u32 r;
 212
 213         DSSDBG("Enter hdmi_wp_audio_config_dma\n");
 214
 215         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
 216         r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
 217         r = FLD_MOD(r, aud_dma->block_size, 7, 0);
 218         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
 219
 220         r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
 221         r = FLD_MOD(r, aud_dma->mode, 9, 9);
 222         r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
 223         hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
 224 }
 225
 226 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
 227 {
 228         REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
 229
 230         return 0;
 231 }
 232
 233 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
 234 {
 235         REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
 236
 237         return 0;
 238 }
 239 #endif
 240
 241 #define WP_SIZE 0x200
 242
 243 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
 244 {
 245         struct resource *res;
 246         struct resource temp_res;
 247
 248         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
 249         if (!res) {
 250                 DSSDBG("can't get WP mem resource by name\n");
 251                 /*
 252                  * if hwmod/DT doesn't have the memory resource information
 253                  * split into HDMI sub blocks by name, we try again by getting
 254                  * the platform's first resource. this code will be removed when
 255                  * the driver can get the mem resources by name
 256                  */
 257                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258                 if (!res) {
 259                         DSSERR("can't get WP mem resource\n");
 260                         return -EINVAL;
 261                 }
 262
 263                 temp_res.start = res->start;
 264                 temp_res.end = temp_res.start + WP_SIZE - 1;
 265                 res = &temp_res;
 266         }
 267
 268         wp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 269         if (!wp->base) {
 270                 DSSERR("can't ioremap HDMI WP\n");
 271                 return -ENOMEM;
 272         }
 273
 274         return 0;
 275 }