drivers/video/omap2/dss/sdi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/sdi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "SDI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/export.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/string.h>
  29
  30 #include <video/omapdss.h>
  31 #include "dss.h"
  32
  33 static struct {
  34         struct platform_device *pdev;
  35
  36         bool update_enabled;
  37         struct regulator *vdds_sdi_reg;
  38
  39         struct dss_lcd_mgr_config mgr_config;
  40         struct omap_video_timings timings;
  41         int datapairs;
  42
  43         struct omap_dss_device output;
  44 } sdi;
  45
  46 struct sdi_clk_calc_ctx {
  47         unsigned long pck_min, pck_max;
  48
  49         struct dss_clock_info dss_cinfo;
  50         struct dispc_clock_info dispc_cinfo;
  51 };
  52
  53 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
  54                 unsigned long pck, void *data)
  55 {
  56         struct sdi_clk_calc_ctx *ctx = data;
  57
  58         ctx->dispc_cinfo.lck_div = lckd;
  59         ctx->dispc_cinfo.pck_div = pckd;
  60         ctx->dispc_cinfo.lck = lck;
  61         ctx->dispc_cinfo.pck = pck;
  62
  63         return true;
  64 }
  65
  66 static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
  67 {
  68         struct sdi_clk_calc_ctx *ctx = data;
  69
  70         ctx->dss_cinfo.fck = fck;
  71         ctx->dss_cinfo.fck_div = fckd;
  72
  73         return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
  74                         dpi_calc_dispc_cb, ctx);
  75 }
  76
  77 static int sdi_calc_clock_div(unsigned long pclk,
  78                 struct dss_clock_info *dss_cinfo,
  79                 struct dispc_clock_info *dispc_cinfo)
  80 {
  81         int i;
  82         struct sdi_clk_calc_ctx ctx;
  83
  84         /*
  85          * DSS fclk gives us very few possibilities, so finding a good pixel
  86          * clock may not be possible. We try multiple times to find the clock,
  87          * each time widening the pixel clock range we look for, up to
  88          * +/- 1MHz.
  89          */
  90
  91         for (i = 0; i < 10; ++i) {
  92                 bool ok;
  93
  94                 memset(&ctx, 0, sizeof(ctx));
  95                 if (pclk > 1000 * i * i * i)
  96                         ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
  97                 else
  98                         ctx.pck_min = 0;
  99                 ctx.pck_max = pclk + 1000 * i * i * i;
 100
 101                 ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx);
 102                 if (ok) {
 103                         *dss_cinfo = ctx.dss_cinfo;
 104                         *dispc_cinfo = ctx.dispc_cinfo;
 105                         return 0;
 106                 }
 107         }
 108
 109         return -EINVAL;
 110 }
 111
 112 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
 113 {
 114         struct omap_overlay_manager *mgr = sdi.output.manager;
 115
 116         sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
 117
 118         sdi.mgr_config.stallmode = false;
 119         sdi.mgr_config.fifohandcheck = false;
 120
 121         sdi.mgr_config.video_port_width = 24;
 122         sdi.mgr_config.lcden_sig_polarity = 1;
 123
 124         dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
 125 }
 126
 127 static int sdi_display_enable(struct omap_dss_device *dssdev)
 128 {
 129         struct omap_dss_device *out = &sdi.output;
 130         struct omap_video_timings *t = &sdi.timings;
 131         struct dss_clock_info dss_cinfo;
 132         struct dispc_clock_info dispc_cinfo;
 133         unsigned long pck;
 134         int r;
 135
 136         if (out == NULL || out->manager == NULL) {
 137                 DSSERR("failed to enable display: no output/manager\n");
 138                 return -ENODEV;
 139         }
 140
 141         r = regulator_enable(sdi.vdds_sdi_reg);
 142         if (r)
 143                 goto err_reg_enable;
 144
 145         r = dispc_runtime_get();
 146         if (r)
 147                 goto err_get_dispc;
 148
 149         /* 15.5.9.1.2 */
 150         t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
 151         t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
 152
 153         r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
 154         if (r)
 155                 goto err_calc_clock_div;
 156
 157         sdi.mgr_config.clock_info = dispc_cinfo;
 158
 159         pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
 160
 161         if (pck != t->pixel_clock) {
 162                 DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
 163                                 "got %lu kHz\n",
 164                                 t->pixel_clock, pck);
 165
 166                 t->pixel_clock = pck;
 167         }
 168
 169
 170         dss_mgr_set_timings(out->manager, t);
 171
 172         r = dss_set_clock_div(&dss_cinfo);
 173         if (r)
 174                 goto err_set_dss_clock_div;
 175
 176         sdi_config_lcd_manager(dssdev);
 177
 178         /*
 179          * LCLK and PCLK divisors are located in shadow registers, and we
 180          * normally write them to DISPC registers when enabling the output.
 181          * However, SDI uses pck-free as source clock for its PLL, and pck-free
 182          * is affected by the divisors. And as we need the PLL before enabling
 183          * the output, we need to write the divisors early.
 184          *
 185          * It seems just writing to the DISPC register is enough, and we don't
 186          * need to care about the shadow register mechanism for pck-free. The
 187          * exact reason for this is unknown.
 188          */
 189         dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
 190
 191         dss_sdi_init(sdi.datapairs);
 192         r = dss_sdi_enable();
 193         if (r)
 194                 goto err_sdi_enable;
 195         mdelay(2);
 196
 197         r = dss_mgr_enable(out->manager);
 198         if (r)
 199                 goto err_mgr_enable;
 200
 201         return 0;
 202
 203 err_mgr_enable:
 204         dss_sdi_disable();
 205 err_sdi_enable:
 206 err_set_dss_clock_div:
 207 err_calc_clock_div:
 208         dispc_runtime_put();
 209 err_get_dispc:
 210         regulator_disable(sdi.vdds_sdi_reg);
 211 err_reg_enable:
 212         return r;
 213 }
 214
 215 static void sdi_display_disable(struct omap_dss_device *dssdev)
 216 {
 217         struct omap_overlay_manager *mgr = sdi.output.manager;
 218
 219         dss_mgr_disable(mgr);
 220
 221         dss_sdi_disable();
 222
 223         dispc_runtime_put();
 224
 225         regulator_disable(sdi.vdds_sdi_reg);
 226 }
 227
 228 static void sdi_set_timings(struct omap_dss_device *dssdev,
 229                 struct omap_video_timings *timings)
 230 {
 231         sdi.timings = *timings;
 232 }
 233
 234 static void sdi_get_timings(struct omap_dss_device *dssdev,
 235                 struct omap_video_timings *timings)
 236 {
 237         *timings = sdi.timings;
 238 }
 239
 240 static int sdi_check_timings(struct omap_dss_device *dssdev,
 241                         struct omap_video_timings *timings)
 242 {
 243         struct omap_overlay_manager *mgr = sdi.output.manager;
 244
 245         if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
 246                 return -EINVAL;
 247
 248         if (timings->pixel_clock == 0)
 249                 return -EINVAL;
 250
 251         return 0;
 252 }
 253
 254 static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
 255 {
 256         sdi.datapairs = datapairs;
 257 }
 258
 259 static int sdi_init_regulator(void)
 260 {
 261         struct regulator *vdds_sdi;
 262
 263         if (sdi.vdds_sdi_reg)
 264                 return 0;
 265
 266         vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
 267         if (IS_ERR(vdds_sdi)) {
 268                 DSSERR("can't get VDDS_SDI regulator\n");
 269                 return PTR_ERR(vdds_sdi);
 270         }
 271
 272         sdi.vdds_sdi_reg = vdds_sdi;
 273
 274         return 0;
 275 }
 276
 277 static int sdi_connect(struct omap_dss_device *dssdev,
 278                 struct omap_dss_device *dst)
 279 {
 280         struct omap_overlay_manager *mgr;
 281         int r;
 282
 283         r = sdi_init_regulator();
 284         if (r)
 285                 return r;
 286
 287         mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
 288         if (!mgr)
 289                 return -ENODEV;
 290
 291         r = dss_mgr_connect(mgr, dssdev);
 292         if (r)
 293                 return r;
 294
 295         r = omapdss_output_set_device(dssdev, dst);
 296         if (r) {
 297                 DSSERR("failed to connect output to new device: %s\n",
 298                                 dst->name);
 299                 dss_mgr_disconnect(mgr, dssdev);
 300                 return r;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static void sdi_disconnect(struct omap_dss_device *dssdev,
 307                 struct omap_dss_device *dst)
 308 {
 309         WARN_ON(dst != dssdev->dst);
 310
 311         if (dst != dssdev->dst)
 312                 return;
 313
 314         omapdss_output_unset_device(dssdev);
 315
 316         if (dssdev->manager)
 317                 dss_mgr_disconnect(dssdev->manager, dssdev);
 318 }
 319
 320 static const struct omapdss_sdi_ops sdi_ops = {
 321         .connect = sdi_connect,
 322         .disconnect = sdi_disconnect,
 323
 324         .enable = sdi_display_enable,
 325         .disable = sdi_display_disable,
 326
 327         .check_timings = sdi_check_timings,
 328         .set_timings = sdi_set_timings,
 329         .get_timings = sdi_get_timings,
 330
 331         .set_datapairs = sdi_set_datapairs,
 332 };
 333
 334 static void sdi_init_output(struct platform_device *pdev)
 335 {
 336         struct omap_dss_device *out = &sdi.output;
 337
 338         out->dev = &pdev->dev;
 339         out->id = OMAP_DSS_OUTPUT_SDI;
 340         out->output_type = OMAP_DISPLAY_TYPE_SDI;
 341         out->name = "sdi.0";
 342         out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
 343         out->ops.sdi = &sdi_ops;
 344         out->owner = THIS_MODULE;
 345
 346         omapdss_register_output(out);
 347 }
 348
 349 static void __exit sdi_uninit_output(struct platform_device *pdev)
 350 {
 351         struct omap_dss_device *out = &sdi.output;
 352
 353         omapdss_unregister_output(out);
 354 }
 355
 356 static int omap_sdi_probe(struct platform_device *pdev)
 357 {
 358         sdi.pdev = pdev;
 359
 360         sdi_init_output(pdev);
 361
 362         return 0;
 363 }
 364
 365 static int __exit omap_sdi_remove(struct platform_device *pdev)
 366 {
 367         sdi_uninit_output(pdev);
 368
 369         return 0;
 370 }
 371
 372 static struct platform_driver omap_sdi_driver = {
 373         .probe          = omap_sdi_probe,
 374         .remove         = __exit_p(omap_sdi_remove),
 375         .driver         = {
 376                 .name   = "omapdss_sdi",
 377                 .owner  = THIS_MODULE,
 378         },
 379 };
 380
 381 int __init sdi_init_platform_driver(void)
 382 {
 383         return platform_driver_register(&omap_sdi_driver);
 384 }
 385
 386 void __exit sdi_uninit_platform_driver(void)
 387 {
 388         platform_driver_unregister(&omap_sdi_driver);
 389 }