4 * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef _HDMI_TI_4xxx_H_
22 #define _HDMI_TI_4xxx_H_
24 #include <linux/string.h>
25 #include <video/omapdss.h>
27 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
28 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
29 #include <sound/soc.h>
30 #include <sound/pcm_params.h>
33 struct hdmi_reg
{ u16 idx
; };
35 #define HDMI_REG(idx) ((const struct hdmi_reg) { idx })
39 #define HDMI_WP_REVISION HDMI_REG(0x0)
40 #define HDMI_WP_SYSCONFIG HDMI_REG(0x10)
41 #define HDMI_WP_IRQSTATUS_RAW HDMI_REG(0x24)
42 #define HDMI_WP_IRQSTATUS HDMI_REG(0x28)
43 #define HDMI_WP_PWR_CTRL HDMI_REG(0x40)
44 #define HDMI_WP_IRQENABLE_SET HDMI_REG(0x2C)
45 #define HDMI_WP_VIDEO_CFG HDMI_REG(0x50)
46 #define HDMI_WP_VIDEO_SIZE HDMI_REG(0x60)
47 #define HDMI_WP_VIDEO_TIMING_H HDMI_REG(0x68)
48 #define HDMI_WP_VIDEO_TIMING_V HDMI_REG(0x6C)
49 #define HDMI_WP_WP_CLK HDMI_REG(0x70)
50 #define HDMI_WP_AUDIO_CFG HDMI_REG(0x80)
51 #define HDMI_WP_AUDIO_CFG2 HDMI_REG(0x84)
52 #define HDMI_WP_AUDIO_CTRL HDMI_REG(0x88)
53 #define HDMI_WP_AUDIO_DATA HDMI_REG(0x8C)
55 /* HDMI IP Core System */
57 #define HDMI_CORE_SYS_VND_IDL HDMI_REG(0x0)
58 #define HDMI_CORE_SYS_DEV_IDL HDMI_REG(0x8)
59 #define HDMI_CORE_SYS_DEV_IDH HDMI_REG(0xC)
60 #define HDMI_CORE_SYS_DEV_REV HDMI_REG(0x10)
61 #define HDMI_CORE_SYS_SRST HDMI_REG(0x14)
62 #define HDMI_CORE_CTRL1 HDMI_REG(0x20)
63 #define HDMI_CORE_SYS_SYS_STAT HDMI_REG(0x24)
64 #define HDMI_CORE_SYS_VID_ACEN HDMI_REG(0x124)
65 #define HDMI_CORE_SYS_VID_MODE HDMI_REG(0x128)
66 #define HDMI_CORE_SYS_INTR_STATE HDMI_REG(0x1C0)
67 #define HDMI_CORE_SYS_INTR1 HDMI_REG(0x1C4)
68 #define HDMI_CORE_SYS_INTR2 HDMI_REG(0x1C8)
69 #define HDMI_CORE_SYS_INTR3 HDMI_REG(0x1CC)
70 #define HDMI_CORE_SYS_INTR4 HDMI_REG(0x1D0)
71 #define HDMI_CORE_SYS_UMASK1 HDMI_REG(0x1D4)
72 #define HDMI_CORE_SYS_TMDS_CTRL HDMI_REG(0x208)
73 #define HDMI_CORE_SYS_DE_DLY HDMI_REG(0xC8)
74 #define HDMI_CORE_SYS_DE_CTRL HDMI_REG(0xCC)
75 #define HDMI_CORE_SYS_DE_TOP HDMI_REG(0xD0)
76 #define HDMI_CORE_SYS_DE_CNTL HDMI_REG(0xD8)
77 #define HDMI_CORE_SYS_DE_CNTH HDMI_REG(0xDC)
78 #define HDMI_CORE_SYS_DE_LINL HDMI_REG(0xE0)
79 #define HDMI_CORE_SYS_DE_LINH_1 HDMI_REG(0xE4)
80 #define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
81 #define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
82 #define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
83 #define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
86 #define HDMI_CORE_DDC_CMD HDMI_REG(0x3CC)
87 #define HDMI_CORE_DDC_STATUS HDMI_REG(0x3C8)
88 #define HDMI_CORE_DDC_ADDR HDMI_REG(0x3B4)
89 #define HDMI_CORE_DDC_OFFSET HDMI_REG(0x3BC)
90 #define HDMI_CORE_DDC_COUNT1 HDMI_REG(0x3C0)
91 #define HDMI_CORE_DDC_COUNT2 HDMI_REG(0x3C4)
92 #define HDMI_CORE_DDC_DATA HDMI_REG(0x3D0)
93 #define HDMI_CORE_DDC_SEGM HDMI_REG(0x3B8)
95 /* HDMI IP Core Audio Video */
97 #define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
98 #define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
99 #define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
100 #define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
101 #define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
102 #define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
103 #define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
104 #define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
105 #define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_REG(n * 4 + 0x110)
106 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_REG(15)
107 #define HDMI_CORE_AV_SPD_DBYTE HDMI_REG(0x190)
108 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_REG(27)
109 #define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_REG(n * 4 + 0x210)
110 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_REG(10)
111 #define HDMI_CORE_AV_MPEG_DBYTE HDMI_REG(0x290)
112 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_REG(27)
113 #define HDMI_CORE_AV_GEN_DBYTE HDMI_REG(0x300)
114 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_REG(31)
115 #define HDMI_CORE_AV_GEN2_DBYTE HDMI_REG(0x380)
116 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_REG(31)
117 #define HDMI_CORE_AV_ACR_CTRL HDMI_REG(0x4)
118 #define HDMI_CORE_AV_FREQ_SVAL HDMI_REG(0x8)
119 #define HDMI_CORE_AV_N_SVAL1 HDMI_REG(0xC)
120 #define HDMI_CORE_AV_N_SVAL2 HDMI_REG(0x10)
121 #define HDMI_CORE_AV_N_SVAL3 HDMI_REG(0x14)
122 #define HDMI_CORE_AV_CTS_SVAL1 HDMI_REG(0x18)
123 #define HDMI_CORE_AV_CTS_SVAL2 HDMI_REG(0x1C)
124 #define HDMI_CORE_AV_CTS_SVAL3 HDMI_REG(0x20)
125 #define HDMI_CORE_AV_CTS_HVAL1 HDMI_REG(0x24)
126 #define HDMI_CORE_AV_CTS_HVAL2 HDMI_REG(0x28)
127 #define HDMI_CORE_AV_CTS_HVAL3 HDMI_REG(0x2C)
128 #define HDMI_CORE_AV_AUD_MODE HDMI_REG(0x50)
129 #define HDMI_CORE_AV_SPDIF_CTRL HDMI_REG(0x54)
130 #define HDMI_CORE_AV_HW_SPDIF_FS HDMI_REG(0x60)
131 #define HDMI_CORE_AV_SWAP_I2S HDMI_REG(0x64)
132 #define HDMI_CORE_AV_SPDIF_ERTH HDMI_REG(0x6C)
133 #define HDMI_CORE_AV_I2S_IN_MAP HDMI_REG(0x70)
134 #define HDMI_CORE_AV_I2S_IN_CTRL HDMI_REG(0x74)
135 #define HDMI_CORE_AV_I2S_CHST0 HDMI_REG(0x78)
136 #define HDMI_CORE_AV_I2S_CHST1 HDMI_REG(0x7C)
137 #define HDMI_CORE_AV_I2S_CHST2 HDMI_REG(0x80)
138 #define HDMI_CORE_AV_I2S_CHST4 HDMI_REG(0x84)
139 #define HDMI_CORE_AV_I2S_CHST5 HDMI_REG(0x88)
140 #define HDMI_CORE_AV_ASRC HDMI_REG(0x8C)
141 #define HDMI_CORE_AV_I2S_IN_LEN HDMI_REG(0x90)
142 #define HDMI_CORE_AV_HDMI_CTRL HDMI_REG(0xBC)
143 #define HDMI_CORE_AV_AUDO_TXSTAT HDMI_REG(0xC0)
144 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_REG(0xCC)
145 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_REG(0xD0)
146 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_REG(0xD4)
147 #define HDMI_CORE_AV_TEST_TXCTRL HDMI_REG(0xF0)
148 #define HDMI_CORE_AV_DPD HDMI_REG(0xF4)
149 #define HDMI_CORE_AV_PB_CTRL1 HDMI_REG(0xF8)
150 #define HDMI_CORE_AV_PB_CTRL2 HDMI_REG(0xFC)
151 #define HDMI_CORE_AV_AVI_TYPE HDMI_REG(0x100)
152 #define HDMI_CORE_AV_AVI_VERS HDMI_REG(0x104)
153 #define HDMI_CORE_AV_AVI_LEN HDMI_REG(0x108)
154 #define HDMI_CORE_AV_AVI_CHSUM HDMI_REG(0x10C)
155 #define HDMI_CORE_AV_SPD_TYPE HDMI_REG(0x180)
156 #define HDMI_CORE_AV_SPD_VERS HDMI_REG(0x184)
157 #define HDMI_CORE_AV_SPD_LEN HDMI_REG(0x188)
158 #define HDMI_CORE_AV_SPD_CHSUM HDMI_REG(0x18C)
159 #define HDMI_CORE_AV_AUDIO_TYPE HDMI_REG(0x200)
160 #define HDMI_CORE_AV_AUDIO_VERS HDMI_REG(0x204)
161 #define HDMI_CORE_AV_AUDIO_LEN HDMI_REG(0x208)
162 #define HDMI_CORE_AV_AUDIO_CHSUM HDMI_REG(0x20C)
163 #define HDMI_CORE_AV_MPEG_TYPE HDMI_REG(0x280)
164 #define HDMI_CORE_AV_MPEG_VERS HDMI_REG(0x284)
165 #define HDMI_CORE_AV_MPEG_LEN HDMI_REG(0x288)
166 #define HDMI_CORE_AV_MPEG_CHSUM HDMI_REG(0x28C)
167 #define HDMI_CORE_AV_CP_BYTE1 HDMI_REG(0x37C)
168 #define HDMI_CORE_AV_CEC_ADDR_ID HDMI_REG(0x3FC)
169 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
170 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
171 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
172 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
176 #define PLLCTRL_PLL_CONTROL HDMI_REG(0x0)
177 #define PLLCTRL_PLL_STATUS HDMI_REG(0x4)
178 #define PLLCTRL_PLL_GO HDMI_REG(0x8)
179 #define PLLCTRL_CFG1 HDMI_REG(0xC)
180 #define PLLCTRL_CFG2 HDMI_REG(0x10)
181 #define PLLCTRL_CFG3 HDMI_REG(0x14)
182 #define PLLCTRL_CFG4 HDMI_REG(0x20)
186 #define HDMI_TXPHY_TX_CTRL HDMI_REG(0x0)
187 #define HDMI_TXPHY_DIGITAL_CTRL HDMI_REG(0x4)
188 #define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8)
189 #define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC)
191 #define REG_FLD_MOD(base, idx, val, start, end) \
192 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
194 #define REG_GET(base, idx, start, end) \
195 FLD_GET(hdmi_read_reg(base, idx), start, end)
198 HDMI_PHYPWRCMD_OFF
= 0,
199 HDMI_PHYPWRCMD_LDOON
= 1,
200 HDMI_PHYPWRCMD_TXON
= 2
203 enum hdmi_core_inputbus_width
{
205 HDMI_INPUT_10BIT
= 1,
209 enum hdmi_core_dither_trunc
{
210 HDMI_OUTPUTTRUNCATION_8BIT
= 0,
211 HDMI_OUTPUTTRUNCATION_10BIT
= 1,
212 HDMI_OUTPUTTRUNCATION_12BIT
= 2,
213 HDMI_OUTPUTDITHER_8BIT
= 3,
214 HDMI_OUTPUTDITHER_10BIT
= 4,
215 HDMI_OUTPUTDITHER_12BIT
= 5
218 enum hdmi_core_deepcolor_ed
{
219 HDMI_DEEPCOLORPACKECTDISABLE
= 0,
220 HDMI_DEEPCOLORPACKECTENABLE
= 1
223 enum hdmi_core_packet_mode
{
224 HDMI_PACKETMODERESERVEDVALUE
= 0,
225 HDMI_PACKETMODE24BITPERPIXEL
= 4,
226 HDMI_PACKETMODE30BITPERPIXEL
= 5,
227 HDMI_PACKETMODE36BITPERPIXEL
= 6,
228 HDMI_PACKETMODE48BITPERPIXEL
= 7
231 enum hdmi_core_tclkselclkmult
{
238 enum hdmi_core_packet_ctrl
{
239 HDMI_PACKETENABLE
= 1,
240 HDMI_PACKETDISABLE
= 0,
241 HDMI_PACKETREPEATON
= 1,
242 HDMI_PACKETREPEATOFF
= 0
245 /* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
246 enum hdmi_core_infoframe
{
247 HDMI_INFOFRAME_AVI_DB1Y_RGB
= 0,
248 HDMI_INFOFRAME_AVI_DB1Y_YUV422
= 1,
249 HDMI_INFOFRAME_AVI_DB1Y_YUV444
= 2,
250 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF
= 0,
251 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON
= 1,
252 HDMI_INFOFRAME_AVI_DB1B_NO
= 0,
253 HDMI_INFOFRAME_AVI_DB1B_VERT
= 1,
254 HDMI_INFOFRAME_AVI_DB1B_HORI
= 2,
255 HDMI_INFOFRAME_AVI_DB1B_VERTHORI
= 3,
256 HDMI_INFOFRAME_AVI_DB1S_0
= 0,
257 HDMI_INFOFRAME_AVI_DB1S_1
= 1,
258 HDMI_INFOFRAME_AVI_DB1S_2
= 2,
259 HDMI_INFOFRAME_AVI_DB2C_NO
= 0,
260 HDMI_INFOFRAME_AVI_DB2C_ITU601
= 1,
261 HDMI_INFOFRAME_AVI_DB2C_ITU709
= 2,
262 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED
= 3,
263 HDMI_INFOFRAME_AVI_DB2M_NO
= 0,
264 HDMI_INFOFRAME_AVI_DB2M_43
= 1,
265 HDMI_INFOFRAME_AVI_DB2M_169
= 2,
266 HDMI_INFOFRAME_AVI_DB2R_SAME
= 8,
267 HDMI_INFOFRAME_AVI_DB2R_43
= 9,
268 HDMI_INFOFRAME_AVI_DB2R_169
= 10,
269 HDMI_INFOFRAME_AVI_DB2R_149
= 11,
270 HDMI_INFOFRAME_AVI_DB3ITC_NO
= 0,
271 HDMI_INFOFRAME_AVI_DB3ITC_YES
= 1,
272 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601
= 0,
273 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709
= 1,
274 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT
= 0,
275 HDMI_INFOFRAME_AVI_DB3Q_LR
= 1,
276 HDMI_INFOFRAME_AVI_DB3Q_FR
= 2,
277 HDMI_INFOFRAME_AVI_DB3SC_NO
= 0,
278 HDMI_INFOFRAME_AVI_DB3SC_HORI
= 1,
279 HDMI_INFOFRAME_AVI_DB3SC_VERT
= 2,
280 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT
= 3,
281 HDMI_INFOFRAME_AVI_DB5PR_NO
= 0,
282 HDMI_INFOFRAME_AVI_DB5PR_2
= 1,
283 HDMI_INFOFRAME_AVI_DB5PR_3
= 2,
284 HDMI_INFOFRAME_AVI_DB5PR_4
= 3,
285 HDMI_INFOFRAME_AVI_DB5PR_5
= 4,
286 HDMI_INFOFRAME_AVI_DB5PR_6
= 5,
287 HDMI_INFOFRAME_AVI_DB5PR_7
= 6,
288 HDMI_INFOFRAME_AVI_DB5PR_8
= 7,
289 HDMI_INFOFRAME_AVI_DB5PR_9
= 8,
290 HDMI_INFOFRAME_AVI_DB5PR_10
= 9,
291 HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM
= 0,
292 HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958
= 1,
293 HDMI_INFOFRAME_AUDIO_DB1CT_AC3
= 2,
294 HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1
= 3,
295 HDMI_INFOFRAME_AUDIO_DB1CT_MP3
= 4,
296 HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH
= 5,
297 HDMI_INFOFRAME_AUDIO_DB1CT_AAC
= 6,
298 HDMI_INFOFRAME_AUDIO_DB1CT_DTS
= 7,
299 HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC
= 8,
300 HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT
= 9,
301 HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS
= 10,
302 HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD
= 11,
303 HDMI_INFOFRAME_AUDIO_DB1CT_MAT
= 12,
304 HDMI_INFOFRAME_AUDIO_DB1CT_DST
= 13,
305 HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO
= 14,
306 HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM
= 0,
307 HDMI_INFOFRAME_AUDIO_DB2SF_32000
= 1,
308 HDMI_INFOFRAME_AUDIO_DB2SF_44100
= 2,
309 HDMI_INFOFRAME_AUDIO_DB2SF_48000
= 3,
310 HDMI_INFOFRAME_AUDIO_DB2SF_88200
= 4,
311 HDMI_INFOFRAME_AUDIO_DB2SF_96000
= 5,
312 HDMI_INFOFRAME_AUDIO_DB2SF_176400
= 6,
313 HDMI_INFOFRAME_AUDIO_DB2SF_192000
= 7,
314 HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM
= 0,
315 HDMI_INFOFRAME_AUDIO_DB2SS_16BIT
= 1,
316 HDMI_INFOFRAME_AUDIO_DB2SS_20BIT
= 2,
317 HDMI_INFOFRAME_AUDIO_DB2SS_24BIT
= 3,
318 HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED
= 0,
319 HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED
= 1
322 enum hdmi_packing_mode
{
323 HDMI_PACK_10b_RGB_YUV444
= 0,
324 HDMI_PACK_24b_RGB_YUV444_YUV422
= 1,
325 HDMI_PACK_20b_YUV422
= 2,
326 HDMI_PACK_ALREADYPACKED
= 7
329 enum hdmi_core_audio_sample_freq
{
330 HDMI_AUDIO_FS_32000
= 0x3,
331 HDMI_AUDIO_FS_44100
= 0x0,
332 HDMI_AUDIO_FS_48000
= 0x2,
333 HDMI_AUDIO_FS_88200
= 0x8,
334 HDMI_AUDIO_FS_96000
= 0xA,
335 HDMI_AUDIO_FS_176400
= 0xC,
336 HDMI_AUDIO_FS_192000
= 0xE,
337 HDMI_AUDIO_FS_NOT_INDICATED
= 0x1
340 enum hdmi_core_audio_layout
{
341 HDMI_AUDIO_LAYOUT_2CH
= 0,
342 HDMI_AUDIO_LAYOUT_8CH
= 1
345 enum hdmi_core_cts_mode
{
346 HDMI_AUDIO_CTS_MODE_HW
= 0,
347 HDMI_AUDIO_CTS_MODE_SW
= 1
350 enum hdmi_stereo_channels
{
351 HDMI_AUDIO_STEREO_NOCHANNELS
= 0,
352 HDMI_AUDIO_STEREO_ONECHANNEL
= 1,
353 HDMI_AUDIO_STEREO_TWOCHANNELS
= 2,
354 HDMI_AUDIO_STEREO_THREECHANNELS
= 3,
355 HDMI_AUDIO_STEREO_FOURCHANNELS
= 4
358 enum hdmi_audio_type
{
359 HDMI_AUDIO_TYPE_LPCM
= 0,
360 HDMI_AUDIO_TYPE_IEC
= 1
363 enum hdmi_audio_justify
{
364 HDMI_AUDIO_JUSTIFY_LEFT
= 0,
365 HDMI_AUDIO_JUSTIFY_RIGHT
= 1
368 enum hdmi_audio_sample_order
{
369 HDMI_AUDIO_SAMPLE_RIGHT_FIRST
= 0,
370 HDMI_AUDIO_SAMPLE_LEFT_FIRST
= 1
373 enum hdmi_audio_samples_perword
{
374 HDMI_AUDIO_ONEWORD_ONESAMPLE
= 0,
375 HDMI_AUDIO_ONEWORD_TWOSAMPLES
= 1
378 enum hdmi_audio_sample_size
{
379 HDMI_AUDIO_SAMPLE_16BITS
= 0,
380 HDMI_AUDIO_SAMPLE_24BITS
= 1
383 enum hdmi_audio_transf_mode
{
384 HDMI_AUDIO_TRANSF_DMA
= 0,
385 HDMI_AUDIO_TRANSF_IRQ
= 1
388 enum hdmi_audio_blk_strt_end_sig
{
389 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON
= 0,
390 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF
= 1
393 enum hdmi_audio_i2s_config
{
394 HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT
= 0,
395 HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT
= 1,
396 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST
= 0,
397 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST
= 1,
398 HDMI_AUDIO_I2S_MAX_WORD_20BITS
= 0,
399 HDMI_AUDIO_I2S_MAX_WORD_24BITS
= 1,
400 HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED
= 0,
401 HDMI_AUDIO_I2S_CHST_WORD_16_BITS
= 1,
402 HDMI_AUDIO_I2S_CHST_WORD_17_BITS
= 6,
403 HDMI_AUDIO_I2S_CHST_WORD_18_BITS
= 2,
404 HDMI_AUDIO_I2S_CHST_WORD_19_BITS
= 4,
405 HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX
= 5,
406 HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX
= 1,
407 HDMI_AUDIO_I2S_CHST_WORD_21_BITS
= 6,
408 HDMI_AUDIO_I2S_CHST_WORD_22_BITS
= 2,
409 HDMI_AUDIO_I2S_CHST_WORD_23_BITS
= 4,
410 HDMI_AUDIO_I2S_CHST_WORD_24_BITS
= 5,
411 HDMI_AUDIO_I2S_SCK_EDGE_FALLING
= 0,
412 HDMI_AUDIO_I2S_SCK_EDGE_RISING
= 1,
413 HDMI_AUDIO_I2S_VBIT_FOR_PCM
= 0,
414 HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED
= 1,
415 HDMI_AUDIO_I2S_INPUT_LENGTH_NA
= 0,
416 HDMI_AUDIO_I2S_INPUT_LENGTH_16
= 2,
417 HDMI_AUDIO_I2S_INPUT_LENGTH_17
= 12,
418 HDMI_AUDIO_I2S_INPUT_LENGTH_18
= 4,
419 HDMI_AUDIO_I2S_INPUT_LENGTH_19
= 8,
420 HDMI_AUDIO_I2S_INPUT_LENGTH_20
= 10,
421 HDMI_AUDIO_I2S_INPUT_LENGTH_21
= 13,
422 HDMI_AUDIO_I2S_INPUT_LENGTH_22
= 5,
423 HDMI_AUDIO_I2S_INPUT_LENGTH_23
= 9,
424 HDMI_AUDIO_I2S_INPUT_LENGTH_24
= 11,
425 HDMI_AUDIO_I2S_FIRST_BIT_SHIFT
= 0,
426 HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT
= 1,
427 HDMI_AUDIO_I2S_SD0_EN
= 1,
428 HDMI_AUDIO_I2S_SD1_EN
= 1 << 1,
429 HDMI_AUDIO_I2S_SD2_EN
= 1 << 2,
430 HDMI_AUDIO_I2S_SD3_EN
= 1 << 3,
433 enum hdmi_audio_mclk_mode
{
434 HDMI_AUDIO_MCLK_128FS
= 0,
435 HDMI_AUDIO_MCLK_256FS
= 1,
436 HDMI_AUDIO_MCLK_384FS
= 2,
437 HDMI_AUDIO_MCLK_512FS
= 3,
438 HDMI_AUDIO_MCLK_768FS
= 4,
439 HDMI_AUDIO_MCLK_1024FS
= 5,
440 HDMI_AUDIO_MCLK_1152FS
= 6,
441 HDMI_AUDIO_MCLK_192FS
= 7
444 struct hdmi_core_video_config
{
445 enum hdmi_core_inputbus_width ip_bus_width
;
446 enum hdmi_core_dither_trunc op_dither_truc
;
447 enum hdmi_core_deepcolor_ed deep_color_pkt
;
448 enum hdmi_core_packet_mode pkt_mode
;
449 enum hdmi_core_hdmi_dvi hdmi_dvi
;
450 enum hdmi_core_tclkselclkmult tclk_sel_clkmult
;
454 * Refer to section 8.2 in HDMI 1.3 specification for
455 * details about infoframe databytes
457 struct hdmi_core_infoframe_avi
{
459 /* Y0, Y1 rgb,yCbCr */
461 /* A0 Active information Present */
463 /* B0, B1 Bar info data valid */
465 /* S0, S1 scan information */
467 /* C0, C1 colorimetry */
469 /* M0, M1 Aspect ratio (4:3, 16:9) */
470 u8 db2_active_fmt_ar
;
471 /* R0...R3 Active format aspect ratio */
473 /* ITC IT content. */
475 /* EC0, EC1, EC2 Extended colorimetry */
477 /* Q1, Q0 Quantization range */
479 /* SC1, SC0 Non-uniform picture scaling */
481 /* VIC0..6 Video format identification */
483 /* PR0..PR3 Pixel repetition factor */
484 u16 db6_7_line_eoftop
;
485 /* Line number end of top bar */
486 u16 db8_9_line_sofbottom
;
487 /* Line number start of bottom bar */
488 u16 db10_11_pixel_eofleft
;
489 /* Pixel number end of left bar */
490 u16 db12_13_pixel_sofright
;
491 /* Pixel number start of right bar */
494 * Refer to section 8.2 in HDMI 1.3 specification for
495 * details about infoframe databytes
497 struct hdmi_core_infoframe_audio
{
499 u8 db1_channel_count
;
502 u8 db4_channel_alloc
;
503 bool db5_downmix_inh
;
504 u8 db5_lsv
; /* Level shift values for downmix */
507 struct hdmi_core_packet_enable_repeat
{
509 u32 audio_pkt_repeat
;
511 u32 avi_infoframe_repeat
;
513 u32 gen_cntrl_pkt_repeat
;
515 u32 generic_pkt_repeat
;
518 struct hdmi_video_format
{
519 enum hdmi_packing_mode packing_mode
;
520 u32 y_res
; /* Line per panel */
521 u32 x_res
; /* pixel per line */
524 struct hdmi_video_interface
{
525 int vsp
; /* Vsync polarity */
526 int hsp
; /* Hsync polarity */
528 int tm
; /* Timing mode */
531 struct hdmi_audio_format
{
532 enum hdmi_stereo_channels stereo_channels
;
533 u8 active_chnnls_msk
;
534 enum hdmi_audio_type type
;
535 enum hdmi_audio_justify justification
;
536 enum hdmi_audio_sample_order sample_order
;
537 enum hdmi_audio_samples_perword samples_per_word
;
538 enum hdmi_audio_sample_size sample_size
;
539 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end
;
542 struct hdmi_audio_dma
{
545 enum hdmi_audio_transf_mode mode
;
549 struct hdmi_core_audio_i2s_config
{
554 u8 en_high_bitrate_aud
;
564 struct hdmi_core_audio_config
{
565 struct hdmi_core_audio_i2s_config i2s_cfg
;
566 enum hdmi_core_audio_sample_freq freq_sample
;
571 enum hdmi_core_audio_layout layout
;
572 enum hdmi_core_cts_mode cts_mode
;
574 enum hdmi_audio_mclk_mode mclk_mode
;
577 bool en_parallel_aud_input
;
581 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
582 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
583 int hdmi_audio_trigger(struct hdmi_ip_data
*ip_data
,
584 struct snd_pcm_substream
*substream
, int cmd
,
585 struct snd_soc_dai
*dai
);
586 int hdmi_config_audio_acr(struct hdmi_ip_data
*ip_data
,
587 u32 sample_freq
, u32
*n
, u32
*cts
);
588 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data
*ip_data
,
589 struct hdmi_core_infoframe_audio
*info_aud
);
590 void hdmi_core_audio_config(struct hdmi_ip_data
*ip_data
,
591 struct hdmi_core_audio_config
*cfg
);
592 void hdmi_wp_audio_config_dma(struct hdmi_ip_data
*ip_data
,
593 struct hdmi_audio_dma
*aud_dma
);
594 void hdmi_wp_audio_config_format(struct hdmi_ip_data
*ip_data
,
595 struct hdmi_audio_format
*aud_fmt
);