2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
42 #include <video/permedia2.h>
43 #include <video/cvisionppc.h>
45 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46 #error "The endianness of the target host has not been defined."
49 #if !defined(CONFIG_PCI)
50 #error "Only generic PCI cards supported."
53 #undef PM2FB_MASTER_DEBUG
54 #ifdef PM2FB_MASTER_DEBUG
55 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
57 #define DPRINTK(a,b...)
63 static char *mode __devinitdata
= NULL
;
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
78 * The hardware state of the graphics card that isn't part of the
83 pm2type_t type
; /* Board type */
84 u32 fb_size
; /* framebuffer memory size */
85 unsigned char __iomem
*v_fb
; /* virtual address of frame buffer */
86 unsigned char __iomem
*v_regs
;/* virtual address of p_regs */
87 u32 memclock
; /* memclock */
88 u32 video
; /* video flags before blanking */
89 u32 mem_config
; /* MemConfig reg at probe */
90 u32 mem_control
; /* MemControl reg at probe */
91 u32 boot_address
; /* BootAddress reg at probe */
96 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
97 * if we don't use modedb.
99 static struct fb_fix_screeninfo pm2fb_fix __devinitdata
= {
101 .type
= FB_TYPE_PACKED_PIXELS
,
102 .visual
= FB_VISUAL_PSEUDOCOLOR
,
106 .accel
= FB_ACCEL_3DLABS_PERMEDIA2
,
110 * Default video mode. In case the modedb doesn't work.
112 static struct fb_var_screeninfo pm2fb_var __devinitdata
= {
113 /* "640x480, 8 bpp @ 60 Hz */
122 .activate
= FB_ACTIVATE_NOW
,
133 .vmode
= FB_VMODE_NONINTERLACED
140 static inline u32
RD32(unsigned char __iomem
*base
, s32 off
)
142 return fb_readl(base
+ off
);
145 static inline void WR32(unsigned char __iomem
*base
, s32 off
, u32 v
)
147 fb_writel(v
, base
+ off
);
150 static inline u32
pm2_RD(struct pm2fb_par
* p
, s32 off
)
152 return RD32(p
->v_regs
, off
);
155 static inline void pm2_WR(struct pm2fb_par
* p
, s32 off
, u32 v
)
157 WR32(p
->v_regs
, off
, v
);
160 static inline u32
pm2_RDAC_RD(struct pm2fb_par
* p
, s32 idx
)
162 int index
= PM2R_RD_INDEXED_DATA
;
164 case PM2_TYPE_PERMEDIA2
:
165 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
167 case PM2_TYPE_PERMEDIA2V
:
168 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
169 index
= PM2VR_RD_INDEXED_DATA
;
173 return pm2_RD(p
, index
);
176 static inline void pm2_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
178 int index
= PM2R_RD_INDEXED_DATA
;
180 case PM2_TYPE_PERMEDIA2
:
181 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, idx
);
183 case PM2_TYPE_PERMEDIA2V
:
184 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
185 index
= PM2VR_RD_INDEXED_DATA
;
192 static inline void pm2v_RDAC_WR(struct pm2fb_par
* p
, s32 idx
, u32 v
)
194 pm2_WR(p
, PM2VR_RD_INDEX_LOW
, idx
& 0xff);
196 pm2_WR(p
, PM2VR_RD_INDEXED_DATA
, v
);
199 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
200 #define WAIT_FIFO(p,a)
202 static inline void WAIT_FIFO(struct pm2fb_par
* p
, u32 a
)
204 while( pm2_RD(p
, PM2R_IN_FIFO_SPACE
) < a
);
209 static void wait_pm2(struct pm2fb_par
* par
) {
212 pm2_WR(par
, PM2R_SYNC
, 0);
215 while (pm2_RD(par
, PM2R_OUT_FIFO_WORDS
) == 0);
217 } while (pm2_RD(par
, PM2R_OUT_FIFO
) != PM2TAG(PM2R_SYNC
));
221 * partial products for the supported horizontal resolutions.
223 #define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
224 static const struct {
228 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
229 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
230 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
231 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
232 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
233 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
234 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
235 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
236 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
237 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
238 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
239 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
240 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
241 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
242 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
243 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
246 static u32
partprod(u32 xres
)
250 for (i
= 0; pp_table
[i
].width
&& pp_table
[i
].width
!= xres
; i
++)
252 if ( pp_table
[i
].width
== 0 )
253 DPRINTK("invalid width %u\n", xres
);
254 return pp_table
[i
].pp
;
257 static u32
to3264(u32 timing
, int bpp
, int is64
)
267 timing
= (timing
* 3) >> (2 + is64
);
277 static void pm2_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
288 for (n
= 2; n
< 15; n
++) {
289 for (m
= 2; m
; m
++) {
290 f
= PM2_REFERENCE_CLOCK
* m
/ n
;
291 if (f
>= 150000 && f
<= 300000) {
292 for ( p
= 0; p
< 5; p
++, f
>>= 1) {
293 curr
= ( clk
> f
) ? clk
- f
: f
- clk
;
294 if ( curr
< delta
) {
306 static void pm2v_mnp(u32 clk
, unsigned char* mm
, unsigned char* nn
,
316 for ( m
= 1; m
< 128; m
++) {
317 for (n
= 2 * m
+ 1; n
; n
++) {
318 for ( p
= 0; p
< 2; p
++) {
319 f
= ( PM2_REFERENCE_CLOCK
>> ( p
+ 1 )) * n
/ m
;
320 if ( clk
> f
- delta
&& clk
< f
+ delta
) {
321 delta
= ( clk
> f
) ? clk
- f
: f
- clk
;
331 static void clear_palette(struct pm2fb_par
* p
) {
335 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, 0);
339 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
340 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
341 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, 0);
345 static void reset_card(struct pm2fb_par
* p
)
347 if (p
->type
== PM2_TYPE_PERMEDIA2V
)
348 pm2_WR(p
, PM2VR_RD_INDEX_HIGH
, 0);
349 pm2_WR(p
, PM2R_RESET_STATUS
, 0);
351 while (pm2_RD(p
, PM2R_RESET_STATUS
) & PM2F_BEING_RESET
)
354 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
355 DPRINTK("FIFO disconnect enabled\n");
356 pm2_WR(p
, PM2R_FIFO_DISCON
, 1);
360 /* Restore stashed memory config information from probe */
362 pm2_WR(p
, PM2R_MEM_CONTROL
, p
->mem_control
);
363 pm2_WR(p
, PM2R_BOOT_ADDRESS
, p
->boot_address
);
365 pm2_WR(p
, PM2R_MEM_CONFIG
, p
->mem_config
);
368 static void reset_config(struct pm2fb_par
* p
)
371 pm2_WR(p
, PM2R_CHIP_CONFIG
, pm2_RD(p
, PM2R_CHIP_CONFIG
)&
372 ~(PM2F_VGA_ENABLE
|PM2F_VGA_FIXED
));
373 pm2_WR(p
, PM2R_BYPASS_WRITE_MASK
, ~(0L));
374 pm2_WR(p
, PM2R_FRAMEBUFFER_WRITE_MASK
, ~(0L));
375 pm2_WR(p
, PM2R_FIFO_CONTROL
, 0);
376 pm2_WR(p
, PM2R_APERTURE_ONE
, 0);
377 pm2_WR(p
, PM2R_APERTURE_TWO
, 0);
378 pm2_WR(p
, PM2R_RASTERIZER_MODE
, 0);
379 pm2_WR(p
, PM2R_DELTA_MODE
, PM2F_DELTA_ORDER_RGB
);
380 pm2_WR(p
, PM2R_LB_READ_FORMAT
, 0);
381 pm2_WR(p
, PM2R_LB_WRITE_FORMAT
, 0);
382 pm2_WR(p
, PM2R_LB_READ_MODE
, 0);
383 pm2_WR(p
, PM2R_LB_SOURCE_OFFSET
, 0);
384 pm2_WR(p
, PM2R_FB_SOURCE_OFFSET
, 0);
385 pm2_WR(p
, PM2R_FB_PIXEL_OFFSET
, 0);
386 pm2_WR(p
, PM2R_FB_WINDOW_BASE
, 0);
387 pm2_WR(p
, PM2R_LB_WINDOW_BASE
, 0);
388 pm2_WR(p
, PM2R_FB_SOFT_WRITE_MASK
, ~(0L));
389 pm2_WR(p
, PM2R_FB_HARD_WRITE_MASK
, ~(0L));
390 pm2_WR(p
, PM2R_FB_READ_PIXEL
, 0);
391 pm2_WR(p
, PM2R_DITHER_MODE
, 0);
392 pm2_WR(p
, PM2R_AREA_STIPPLE_MODE
, 0);
393 pm2_WR(p
, PM2R_DEPTH_MODE
, 0);
394 pm2_WR(p
, PM2R_STENCIL_MODE
, 0);
395 pm2_WR(p
, PM2R_TEXTURE_ADDRESS_MODE
, 0);
396 pm2_WR(p
, PM2R_TEXTURE_READ_MODE
, 0);
397 pm2_WR(p
, PM2R_TEXEL_LUT_MODE
, 0);
398 pm2_WR(p
, PM2R_YUV_MODE
, 0);
399 pm2_WR(p
, PM2R_COLOR_DDA_MODE
, 0);
400 pm2_WR(p
, PM2R_TEXTURE_COLOR_MODE
, 0);
401 pm2_WR(p
, PM2R_FOG_MODE
, 0);
402 pm2_WR(p
, PM2R_ALPHA_BLEND_MODE
, 0);
403 pm2_WR(p
, PM2R_LOGICAL_OP_MODE
, 0);
404 pm2_WR(p
, PM2R_STATISTICS_MODE
, 0);
405 pm2_WR(p
, PM2R_SCISSOR_MODE
, 0);
406 pm2_WR(p
, PM2R_FILTER_MODE
, PM2F_SYNCHRONIZATION
);
408 case PM2_TYPE_PERMEDIA2
:
409 pm2_RDAC_WR(p
, PM2I_RD_MODE_CONTROL
, 0); /* no overlay */
410 pm2_RDAC_WR(p
, PM2I_RD_CURSOR_CONTROL
, 0);
411 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, PM2F_RD_PALETTE_WIDTH_8
);
413 case PM2_TYPE_PERMEDIA2V
:
414 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1); /* 8bit */
417 pm2_RDAC_WR(p
, PM2I_RD_COLOR_KEY_CONTROL
, 0);
418 pm2_RDAC_WR(p
, PM2I_RD_OVERLAY_KEY
, 0);
419 pm2_RDAC_WR(p
, PM2I_RD_RED_KEY
, 0);
420 pm2_RDAC_WR(p
, PM2I_RD_GREEN_KEY
, 0);
421 pm2_RDAC_WR(p
, PM2I_RD_BLUE_KEY
, 0);
424 static void set_aperture(struct pm2fb_par
* p
, u32 depth
)
427 * The hardware is little-endian. When used in big-endian
428 * hosts, the on-chip aperture settings are used where
429 * possible to translate from host to card byte order.
432 #ifdef __LITTLE_ENDIAN
433 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
436 case 24: /* RGB->BGR */
438 * We can't use the aperture to translate host to
439 * card byte order here, so we switch to BGR mode
440 * in pm2fb_set_par().
443 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_STANDARD
);
445 case 16: /* HL->LH */
446 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_HALFWORDSWAP
);
448 case 32: /* RGBA->ABGR */
449 pm2_WR(p
, PM2R_APERTURE_ONE
, PM2F_APERTURE_BYTESWAP
);
454 // We don't use aperture two, so this may be superflous
455 pm2_WR(p
, PM2R_APERTURE_TWO
, PM2F_APERTURE_STANDARD
);
458 static void set_color(struct pm2fb_par
* p
, unsigned char regno
,
459 unsigned char r
, unsigned char g
, unsigned char b
)
462 pm2_WR(p
, PM2R_RD_PALETTE_WRITE_ADDRESS
, regno
);
464 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, r
);
466 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, g
);
468 pm2_WR(p
, PM2R_RD_PALETTE_DATA
, b
);
471 static void set_memclock(struct pm2fb_par
* par
, u32 clk
)
474 unsigned char m
, n
, p
;
477 case PM2_TYPE_PERMEDIA2V
:
478 pm2v_mnp(clk
/2, &m
, &n
, &p
);
480 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_MCLK_CONTROL
>> 8);
481 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 0);
483 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_PRESCALE
, m
);
484 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_FEEDBACK
, n
);
485 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_POSTSCALE
, p
);
487 pm2v_RDAC_WR(par
, PM2VI_RD_MCLK_CONTROL
, 1);
490 i
&& !(pm2_RDAC_RD(par
, PM2VI_RD_MCLK_CONTROL
) & 2);
493 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
495 case PM2_TYPE_PERMEDIA2
:
496 pm2_mnp(clk
, &m
, &n
, &p
);
498 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 6);
500 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_1
, m
);
501 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_2
, n
);
503 pm2_RDAC_WR(par
, PM2I_RD_MEMORY_CLOCK_3
, 8|p
);
505 pm2_RDAC_RD(par
, PM2I_RD_MEMORY_CLOCK_STATUS
);
508 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
515 static void set_pixclock(struct pm2fb_par
* par
, u32 clk
)
518 unsigned char m
, n
, p
;
521 case PM2_TYPE_PERMEDIA2
:
522 pm2_mnp(clk
, &m
, &n
, &p
);
524 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 0);
526 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A1
, m
);
527 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A2
, n
);
529 pm2_RDAC_WR(par
, PM2I_RD_PIXEL_CLOCK_A3
, 8|p
);
531 pm2_RDAC_RD(par
, PM2I_RD_PIXEL_CLOCK_STATUS
);
534 i
&& !(pm2_RD(par
, PM2R_RD_INDEXED_DATA
) & PM2F_PLL_LOCKED
);
538 case PM2_TYPE_PERMEDIA2V
:
539 pm2v_mnp(clk
/2, &m
, &n
, &p
);
541 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, PM2VI_RD_CLK0_PRESCALE
>> 8);
542 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_PRESCALE
, m
);
543 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_FEEDBACK
, n
);
544 pm2v_RDAC_WR(par
, PM2VI_RD_CLK0_POSTSCALE
, p
);
545 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
550 static void set_video(struct pm2fb_par
* p
, u32 video
) {
556 DPRINTK("video = 0x%x\n", video
);
559 * The hardware cursor needs +vsync to recognise vert retrace.
560 * We may not be using the hardware cursor, but the X Glint
561 * driver may well. So always set +hsync/+vsync and then set
562 * the RAMDAC to invert the sync if necessary.
564 vsync
&= ~(PM2F_HSYNC_MASK
|PM2F_VSYNC_MASK
);
565 vsync
|= PM2F_HSYNC_ACT_HIGH
|PM2F_VSYNC_ACT_HIGH
;
568 pm2_WR(p
, PM2R_VIDEO_CONTROL
, vsync
);
571 case PM2_TYPE_PERMEDIA2
:
572 tmp
= PM2F_RD_PALETTE_WIDTH_8
;
573 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
574 tmp
|= 4; /* invert hsync */
575 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
576 tmp
|= 8; /* invert vsync */
577 pm2_RDAC_WR(p
, PM2I_RD_MISC_CONTROL
, tmp
);
579 case PM2_TYPE_PERMEDIA2V
:
581 if ((video
& PM2F_HSYNC_MASK
) == PM2F_HSYNC_ACT_LOW
)
582 tmp
|= 1; /* invert hsync */
583 if ((video
& PM2F_VSYNC_MASK
) == PM2F_VSYNC_ACT_LOW
)
584 tmp
|= 4; /* invert vsync */
585 pm2v_RDAC_WR(p
, PM2VI_RD_SYNC_CONTROL
, tmp
);
586 pm2v_RDAC_WR(p
, PM2VI_RD_MISC_CONTROL
, 1);
596 * pm2fb_check_var - Optional function. Validates a var passed in.
597 * @var: frame buffer variable screen structure
598 * @info: frame buffer structure that represents a single frame buffer
600 * Checks to see if the hardware supports the state requested by
603 * Returns negative errno on error, or zero on success.
605 static int pm2fb_check_var(struct fb_var_screeninfo
*var
, struct fb_info
*info
)
609 if (var
->bits_per_pixel
!= 8 && var
->bits_per_pixel
!= 16 &&
610 var
->bits_per_pixel
!= 24 && var
->bits_per_pixel
!= 32) {
611 DPRINTK("depth not supported: %u\n", var
->bits_per_pixel
);
615 if (var
->xres
!= var
->xres_virtual
) {
616 DPRINTK("virtual x resolution != physical x resolution not supported\n");
620 if (var
->yres
> var
->yres_virtual
) {
621 DPRINTK("virtual y resolution < physical y resolution not possible\n");
626 DPRINTK("xoffset not supported\n");
630 if ((var
->vmode
& FB_VMODE_MASK
) == FB_VMODE_INTERLACED
) {
631 DPRINTK("interlace not supported\n");
635 var
->xres
= (var
->xres
+ 15) & ~15; /* could sometimes be 8 */
636 lpitch
= var
->xres
* ((var
->bits_per_pixel
+ 7)>>3);
638 if (var
->xres
< 320 || var
->xres
> 1600) {
639 DPRINTK("width not supported: %u\n", var
->xres
);
643 if (var
->yres
< 200 || var
->yres
> 1200) {
644 DPRINTK("height not supported: %u\n", var
->yres
);
648 if (lpitch
* var
->yres_virtual
> info
->fix
.smem_len
) {
649 DPRINTK("no memory for screen (%ux%ux%u)\n",
650 var
->xres
, var
->yres_virtual
, var
->bits_per_pixel
);
654 if (PICOS2KHZ(var
->pixclock
) > PM2_MAX_PIXCLOCK
) {
655 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var
->pixclock
));
659 var
->transp
.offset
= 0;
660 var
->transp
.length
= 0;
661 switch(var
->bits_per_pixel
) {
663 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
666 var
->red
.offset
= 11;
668 var
->green
.offset
= 5;
669 var
->green
.length
= 6;
670 var
->blue
.offset
= 0;
671 var
->blue
.length
= 5;
674 var
->transp
.offset
= 24;
675 var
->transp
.length
= 8;
676 var
->red
.offset
= 16;
677 var
->green
.offset
= 8;
678 var
->blue
.offset
= 0;
679 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
684 var
->blue
.offset
= 16;
686 var
->red
.offset
= 16;
687 var
->blue
.offset
= 0;
689 var
->green
.offset
= 8;
690 var
->red
.length
= var
->green
.length
= var
->blue
.length
= 8;
693 var
->height
= var
->width
= -1;
695 var
->accel_flags
= 0; /* Can't mmap if this is on */
697 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
698 var
->xres
, var
->yres
, var
->bits_per_pixel
);
703 * pm2fb_set_par - Alters the hardware state.
704 * @info: frame buffer structure that represents a single frame buffer
706 * Using the fb_var_screeninfo in fb_info we set the resolution of the
707 * this particular framebuffer.
709 static int pm2fb_set_par(struct fb_info
*info
)
711 struct pm2fb_par
*par
= info
->par
;
713 u32 width
, height
, depth
;
714 u32 hsstart
, hsend
, hbend
, htotal
;
715 u32 vsstart
, vsend
, vbend
, vtotal
;
719 u32 clrmode
= PM2F_RD_COLOR_MODE_RGB
| PM2F_RD_GUI_ACTIVE
;
730 set_memclock(par
, par
->memclock
);
732 width
= (info
->var
.xres_virtual
+ 7) & ~7;
733 height
= info
->var
.yres_virtual
;
734 depth
= (info
->var
.bits_per_pixel
+ 7) & ~7;
735 depth
= (depth
> 32) ? 32 : depth
;
736 data64
= depth
> 8 || par
->type
== PM2_TYPE_PERMEDIA2V
;
738 xres
= (info
->var
.xres
+ 31) & ~31;
739 pixclock
= PICOS2KHZ(info
->var
.pixclock
);
740 if (pixclock
> PM2_MAX_PIXCLOCK
) {
741 DPRINTK("pixclock too high (%uKHz)\n", pixclock
);
745 hsstart
= to3264(info
->var
.right_margin
, depth
, data64
);
746 hsend
= hsstart
+ to3264(info
->var
.hsync_len
, depth
, data64
);
747 hbend
= hsend
+ to3264(info
->var
.left_margin
, depth
, data64
);
748 htotal
= to3264(xres
, depth
, data64
) + hbend
- 1;
749 vsstart
= (info
->var
.lower_margin
)
750 ? info
->var
.lower_margin
- 1
752 vsend
= info
->var
.lower_margin
+ info
->var
.vsync_len
- 1;
753 vbend
= info
->var
.lower_margin
+ info
->var
.vsync_len
+ info
->var
.upper_margin
;
754 vtotal
= info
->var
.yres
+ vbend
- 1;
755 stride
= to3264(width
, depth
, 1);
756 base
= to3264(info
->var
.yoffset
* xres
+ info
->var
.xoffset
, depth
, 1);
758 video
|= PM2F_DATA_64_ENABLE
;
760 if (info
->var
.sync
& FB_SYNC_HOR_HIGH_ACT
) {
762 DPRINTK("ignoring +hsync, using -hsync.\n");
763 video
|= PM2F_HSYNC_ACT_LOW
;
765 video
|= PM2F_HSYNC_ACT_HIGH
;
768 video
|= PM2F_HSYNC_ACT_LOW
;
769 if (info
->var
.sync
& FB_SYNC_VERT_HIGH_ACT
) {
771 DPRINTK("ignoring +vsync, using -vsync.\n");
772 video
|= PM2F_VSYNC_ACT_LOW
;
774 video
|= PM2F_VSYNC_ACT_HIGH
;
777 video
|= PM2F_VSYNC_ACT_LOW
;
778 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_INTERLACED
) {
779 DPRINTK("interlaced not supported\n");
782 if ((info
->var
.vmode
& FB_VMODE_MASK
)==FB_VMODE_DOUBLE
)
783 video
|= PM2F_LINE_DOUBLE
;
784 if ((info
->var
.activate
& FB_ACTIVATE_MASK
)==FB_ACTIVATE_NOW
)
785 video
|= PM2F_VIDEO_ENABLE
;
789 (depth
== 8) ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR
;
790 info
->fix
.line_length
= info
->var
.xres
* depth
/ 8;
791 info
->cmap
.len
= 256;
794 * Settings calculated. Now write them out.
796 if (par
->type
== PM2_TYPE_PERMEDIA2V
) {
798 pm2_WR(par
, PM2VR_RD_INDEX_HIGH
, 0);
801 set_aperture(par
, depth
);
805 pm2_RDAC_WR(par
, PM2I_RD_COLOR_KEY_CONTROL
,
806 ( depth
== 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF
);
809 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 0);
813 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 1);
814 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB565
;
815 txtmap
= PM2F_TEXTEL_SIZE_16
;
820 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 2);
821 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGBA8888
;
822 txtmap
= PM2F_TEXTEL_SIZE_32
;
827 pm2_WR(par
, PM2R_FB_READ_PIXEL
, 4);
828 clrmode
|= PM2F_RD_TRUECOLOR
| PM2F_RD_PIXELFORMAT_RGB888
;
829 txtmap
= PM2F_TEXTEL_SIZE_24
;
834 pm2_WR(par
, PM2R_FB_WRITE_MODE
, PM2F_FB_WRITE_ENABLE
);
835 pm2_WR(par
, PM2R_FB_READ_MODE
, partprod(xres
));
836 pm2_WR(par
, PM2R_LB_READ_MODE
, partprod(xres
));
837 pm2_WR(par
, PM2R_TEXTURE_MAP_FORMAT
, txtmap
| partprod(xres
));
838 pm2_WR(par
, PM2R_H_TOTAL
, htotal
);
839 pm2_WR(par
, PM2R_HS_START
, hsstart
);
840 pm2_WR(par
, PM2R_HS_END
, hsend
);
841 pm2_WR(par
, PM2R_HG_END
, hbend
);
842 pm2_WR(par
, PM2R_HB_END
, hbend
);
843 pm2_WR(par
, PM2R_V_TOTAL
, vtotal
);
844 pm2_WR(par
, PM2R_VS_START
, vsstart
);
845 pm2_WR(par
, PM2R_VS_END
, vsend
);
846 pm2_WR(par
, PM2R_VB_END
, vbend
);
847 pm2_WR(par
, PM2R_SCREEN_STRIDE
, stride
);
849 pm2_WR(par
, PM2R_WINDOW_ORIGIN
, 0);
850 pm2_WR(par
, PM2R_SCREEN_SIZE
, (height
<< 16) | width
);
851 pm2_WR(par
, PM2R_SCISSOR_MODE
, PM2F_SCREEN_SCISSOR_ENABLE
);
853 pm2_WR(par
, PM2R_SCREEN_BASE
, base
);
855 set_video(par
, video
);
858 case PM2_TYPE_PERMEDIA2
:
859 pm2_RDAC_WR(par
, PM2I_RD_COLOR_MODE
, clrmode
);
861 case PM2_TYPE_PERMEDIA2V
:
862 pm2v_RDAC_WR(par
, PM2VI_RD_PIXEL_SIZE
, pixsize
);
863 pm2v_RDAC_WR(par
, PM2VI_RD_COLOR_FORMAT
, clrformat
);
866 set_pixclock(par
, pixclock
);
867 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
868 info
->var
.xres
, info
->var
.yres
, info
->var
.bits_per_pixel
);
873 * pm2fb_setcolreg - Sets a color register.
874 * @regno: boolean, 0 copy local, 1 get_user() function
875 * @red: frame buffer colormap structure
876 * @green: The green value which can be up to 16 bits wide
877 * @blue: The blue value which can be up to 16 bits wide.
878 * @transp: If supported the alpha value which can be up to 16 bits wide.
879 * @info: frame buffer info structure
881 * Set a single color register. The values supplied have a 16 bit
882 * magnitude which needs to be scaled in this function for the hardware.
883 * Pretty much a direct lift from tdfxfb.c.
885 * Returns negative errno on error, or zero on success.
887 static int pm2fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
,
888 unsigned blue
, unsigned transp
,
889 struct fb_info
*info
)
891 struct pm2fb_par
*par
= info
->par
;
893 if (regno
>= info
->cmap
.len
) /* no. of hw registers */
896 * Program hardware... do anything you want with transp
899 /* grayscale works only partially under directcolor */
900 if (info
->var
.grayscale
) {
901 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
902 red
= green
= blue
= (red
* 77 + green
* 151 + blue
* 28) >> 8;
906 * var->{color}.offset contains start of bitfield
907 * var->{color}.length contains length of bitfield
908 * {hardwarespecific} contains width of DAC
909 * cmap[X] is programmed to
910 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
911 * RAMDAC[X] is programmed to (red, green, blue)
914 * uses offset = 0 && length = DAC register width.
915 * var->{color}.offset is 0
916 * var->{color}.length contains widht of DAC
918 * DAC[X] is programmed to (red, green, blue)
920 * does not use RAMDAC (usually has 3 of them).
921 * var->{color}.offset contains start of bitfield
922 * var->{color}.length contains length of bitfield
923 * cmap is programmed to
924 * (red << red.offset) | (green << green.offset) |
925 * (blue << blue.offset) | (transp << transp.offset)
926 * RAMDAC does not exist
928 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
929 switch (info
->fix
.visual
) {
930 case FB_VISUAL_TRUECOLOR
:
931 case FB_VISUAL_PSEUDOCOLOR
:
932 red
= CNVT_TOHW(red
, info
->var
.red
.length
);
933 green
= CNVT_TOHW(green
, info
->var
.green
.length
);
934 blue
= CNVT_TOHW(blue
, info
->var
.blue
.length
);
935 transp
= CNVT_TOHW(transp
, info
->var
.transp
.length
);
937 case FB_VISUAL_DIRECTCOLOR
:
938 /* example here assumes 8 bit DAC. Might be different
939 * for your hardware */
940 red
= CNVT_TOHW(red
, 8);
941 green
= CNVT_TOHW(green
, 8);
942 blue
= CNVT_TOHW(blue
, 8);
943 /* hey, there is bug in transp handling... */
944 transp
= CNVT_TOHW(transp
, 8);
948 /* Truecolor has hardware independent palette */
949 if (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) {
955 v
= (red
<< info
->var
.red
.offset
) |
956 (green
<< info
->var
.green
.offset
) |
957 (blue
<< info
->var
.blue
.offset
) |
958 (transp
<< info
->var
.transp
.offset
);
960 switch (info
->var
.bits_per_pixel
) {
966 par
->palette
[regno
] = v
;
971 else if (info
->fix
.visual
== FB_VISUAL_PSEUDOCOLOR
)
972 set_color(par
, regno
, red
, green
, blue
);
978 * pm2fb_pan_display - Pans the display.
979 * @var: frame buffer variable screen structure
980 * @info: frame buffer structure that represents a single frame buffer
982 * Pan (or wrap, depending on the `vmode' field) the display using the
983 * `xoffset' and `yoffset' fields of the `var' structure.
984 * If the values don't fit, return -EINVAL.
986 * Returns negative errno on error, or zero on success.
989 static int pm2fb_pan_display(struct fb_var_screeninfo
*var
,
990 struct fb_info
*info
)
992 struct pm2fb_par
*p
= info
->par
;
997 xres
= (var
->xres
+ 31) & ~31;
998 depth
= (var
->bits_per_pixel
+ 7) & ~7;
999 depth
= (depth
> 32) ? 32 : depth
;
1000 base
= to3264(var
->yoffset
* xres
+ var
->xoffset
, depth
, 1);
1002 pm2_WR(p
, PM2R_SCREEN_BASE
, base
);
1007 * pm2fb_blank - Blanks the display.
1008 * @blank_mode: the blank mode we want.
1009 * @info: frame buffer structure that represents a single frame buffer
1011 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
1012 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1013 * video mode which doesn't support it. Implements VESA suspend
1014 * and powerdown modes on hardware that supports disabling hsync/vsync:
1015 * blank_mode == 2: suspend vsync
1016 * blank_mode == 3: suspend hsync
1017 * blank_mode == 4: powerdown
1019 * Returns negative errno on error, or zero on success.
1022 static int pm2fb_blank(int blank_mode
, struct fb_info
*info
)
1024 struct pm2fb_par
*par
= info
->par
;
1025 u32 video
= par
->video
;
1027 DPRINTK("blank_mode %d\n", blank_mode
);
1029 switch (blank_mode
) {
1030 case FB_BLANK_UNBLANK
:
1032 video
|= PM2F_VIDEO_ENABLE
;
1034 case FB_BLANK_NORMAL
:
1036 video
&= ~PM2F_VIDEO_ENABLE
;
1038 case FB_BLANK_VSYNC_SUSPEND
:
1040 video
&= ~(PM2F_VSYNC_MASK
| PM2F_BLANK_LOW
);
1042 case FB_BLANK_HSYNC_SUSPEND
:
1044 video
&= ~(PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1046 case FB_BLANK_POWERDOWN
:
1047 /* HSync: Off, VSync: Off */
1048 video
&= ~(PM2F_VSYNC_MASK
| PM2F_HSYNC_MASK
| PM2F_BLANK_LOW
);
1051 set_video(par
, video
);
1056 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1058 static void pm2fb_block_op(struct pm2fb_par
* par
, int copy
,
1060 s32 x
, s32 y
, s32 w
, s32 h
,
1066 pm2_WR(par
, PM2R_CONFIG
, PM2F_CONFIG_FB_WRITE_ENABLE
|
1067 PM2F_CONFIG_FB_READ_SOURCE_ENABLE
);
1068 pm2_WR(par
, PM2R_FB_PIXEL_OFFSET
, 0);
1070 pm2_WR(par
, PM2R_FB_SOURCE_DELTA
,
1071 ((ysrc
-y
) & 0xfff) << 16 | ((xsrc
-x
) & 0xfff));
1073 pm2_WR(par
, PM2R_FB_BLOCK_COLOR
, color
);
1074 pm2_WR(par
, PM2R_RECTANGLE_ORIGIN
, (y
<< 16) | x
);
1075 pm2_WR(par
, PM2R_RECTANGLE_SIZE
, (h
<< 16) | w
);
1077 pm2_WR(par
, PM2R_RENDER
,PM2F_RENDER_RECTANGLE
|
1078 (x
<xsrc
? PM2F_INCREASE_X
: 0) |
1079 (y
<ysrc
? PM2F_INCREASE_Y
: 0) |
1080 (copy
? 0 : PM2F_RENDER_FASTFILL
));
1084 static void pm2fb_fillrect (struct fb_info
*info
,
1085 const struct fb_fillrect
*region
)
1087 struct pm2fb_par
*par
= info
->par
;
1088 struct fb_fillrect modded
;
1090 u32 color
= (info
->fix
.visual
== FB_VISUAL_TRUECOLOR
) ?
1091 ((u32
*)info
->pseudo_palette
)[region
->color
] : region
->color
;
1093 if (info
->state
!= FBINFO_STATE_RUNNING
)
1095 if ((info
->flags
& FBINFO_HWACCEL_DISABLED
) ||
1096 region
->rop
!= ROP_COPY
) {
1097 cfb_fillrect(info
, region
);
1101 vxres
= info
->var
.xres_virtual
;
1102 vyres
= info
->var
.yres_virtual
;
1104 memcpy(&modded
, region
, sizeof(struct fb_fillrect
));
1106 if(!modded
.width
|| !modded
.height
||
1107 modded
.dx
>= vxres
|| modded
.dy
>= vyres
)
1110 if(modded
.dx
+ modded
.width
> vxres
)
1111 modded
.width
= vxres
- modded
.dx
;
1112 if(modded
.dy
+ modded
.height
> vyres
)
1113 modded
.height
= vyres
- modded
.dy
;
1115 if(info
->var
.bits_per_pixel
== 8)
1116 color
|= color
<< 8;
1117 if(info
->var
.bits_per_pixel
<= 16)
1118 color
|= color
<< 16;
1120 if(info
->var
.bits_per_pixel
!= 24)
1121 pm2fb_block_op(par
, 0, 0, 0,
1122 modded
.dx
, modded
.dy
,
1123 modded
.width
, modded
.height
, color
);
1125 cfb_fillrect(info
, region
);
1128 static void pm2fb_copyarea(struct fb_info
*info
,
1129 const struct fb_copyarea
*area
)
1131 struct pm2fb_par
*par
= info
->par
;
1132 struct fb_copyarea modded
;
1135 if (info
->state
!= FBINFO_STATE_RUNNING
)
1137 if (info
->flags
& FBINFO_HWACCEL_DISABLED
) {
1138 cfb_copyarea(info
, area
);
1142 memcpy(&modded
, area
, sizeof(struct fb_copyarea
));
1144 vxres
= info
->var
.xres_virtual
;
1145 vyres
= info
->var
.yres_virtual
;
1147 if(!modded
.width
|| !modded
.height
||
1148 modded
.sx
>= vxres
|| modded
.sy
>= vyres
||
1149 modded
.dx
>= vxres
|| modded
.dy
>= vyres
)
1152 if(modded
.sx
+ modded
.width
> vxres
)
1153 modded
.width
= vxres
- modded
.sx
;
1154 if(modded
.dx
+ modded
.width
> vxres
)
1155 modded
.width
= vxres
- modded
.dx
;
1156 if(modded
.sy
+ modded
.height
> vyres
)
1157 modded
.height
= vyres
- modded
.sy
;
1158 if(modded
.dy
+ modded
.height
> vyres
)
1159 modded
.height
= vyres
- modded
.dy
;
1161 pm2fb_block_op(par
, 1, modded
.sx
, modded
.sy
,
1162 modded
.dx
, modded
.dy
,
1163 modded
.width
, modded
.height
, 0);
1166 /* ------------ Hardware Independent Functions ------------ */
1169 * Frame buffer operations
1172 static struct fb_ops pm2fb_ops
= {
1173 .owner
= THIS_MODULE
,
1174 .fb_check_var
= pm2fb_check_var
,
1175 .fb_set_par
= pm2fb_set_par
,
1176 .fb_setcolreg
= pm2fb_setcolreg
,
1177 .fb_blank
= pm2fb_blank
,
1178 .fb_pan_display
= pm2fb_pan_display
,
1179 .fb_fillrect
= pm2fb_fillrect
,
1180 .fb_copyarea
= pm2fb_copyarea
,
1181 .fb_imageblit
= cfb_imageblit
,
1190 * Device initialisation
1192 * Initialise and allocate resource for PCI device.
1194 * @param pdev PCI device.
1195 * @param id PCI device ID.
1197 static int __devinit
pm2fb_probe(struct pci_dev
*pdev
,
1198 const struct pci_device_id
*id
)
1200 struct pm2fb_par
*default_par
;
1201 struct fb_info
*info
;
1202 int err
, err_retval
= -ENXIO
;
1204 err
= pci_enable_device(pdev
);
1206 printk(KERN_WARNING
"pm2fb: Can't enable pdev: %d\n", err
);
1210 info
= framebuffer_alloc(sizeof(struct pm2fb_par
), &pdev
->dev
);
1213 default_par
= info
->par
;
1215 switch (pdev
->device
) {
1216 case PCI_DEVICE_ID_TI_TVP4020
:
1217 strcpy(pm2fb_fix
.id
, "TVP4020");
1218 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1220 case PCI_DEVICE_ID_3DLABS_PERMEDIA2
:
1221 strcpy(pm2fb_fix
.id
, "Permedia2");
1222 default_par
->type
= PM2_TYPE_PERMEDIA2
;
1224 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V
:
1225 strcpy(pm2fb_fix
.id
, "Permedia2v");
1226 default_par
->type
= PM2_TYPE_PERMEDIA2V
;
1230 pm2fb_fix
.mmio_start
= pci_resource_start(pdev
, 0);
1231 pm2fb_fix
.mmio_len
= PM2_REGS_SIZE
;
1233 #if defined(__BIG_ENDIAN)
1235 * PM2 has a 64k register file, mapped twice in 128k. Lower
1236 * map is little-endian, upper map is big-endian.
1238 pm2fb_fix
.mmio_start
+= PM2_REGS_SIZE
;
1239 DPRINTK("Adjusting register base for big-endian.\n");
1241 DPRINTK("Register base at 0x%lx\n", pm2fb_fix
.mmio_start
);
1243 /* Registers - request region and map it. */
1244 if ( !request_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
,
1245 "pm2fb regbase") ) {
1246 printk(KERN_WARNING
"pm2fb: Can't reserve regbase.\n");
1247 goto err_exit_neither
;
1249 default_par
->v_regs
=
1250 ioremap_nocache(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1251 if ( !default_par
->v_regs
) {
1252 printk(KERN_WARNING
"pm2fb: Can't remap %s register area.\n",
1254 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1255 goto err_exit_neither
;
1258 /* Stash away memory register info for use when we reset the board */
1259 default_par
->mem_control
= pm2_RD(default_par
, PM2R_MEM_CONTROL
);
1260 default_par
->boot_address
= pm2_RD(default_par
, PM2R_BOOT_ADDRESS
);
1261 default_par
->mem_config
= pm2_RD(default_par
, PM2R_MEM_CONFIG
);
1262 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1263 default_par
->mem_control
, default_par
->boot_address
,
1264 default_par
->mem_config
);
1266 if(default_par
->mem_control
== 0 &&
1267 default_par
->boot_address
== 0x31 &&
1268 default_par
->mem_config
== 0x259fffff) {
1269 default_par
->memclock
= CVPPC_MEMCLOCK
;
1270 default_par
->mem_control
=0;
1271 default_par
->boot_address
=0x20;
1272 default_par
->mem_config
=0xe6002021;
1273 if (pdev
->subsystem_vendor
== 0x1048 &&
1274 pdev
->subsystem_device
== 0x0a31) {
1275 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1276 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1277 DPRINTK("We have not been initialized by VGA BIOS "
1278 "and are running on an Elsa Winner 2000 Office\n");
1279 DPRINTK("Initializing card timings manually...\n");
1280 default_par
->memclock
=70000;
1282 if (pdev
->subsystem_vendor
== 0x3d3d &&
1283 pdev
->subsystem_device
== 0x0100) {
1284 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1285 pdev
->subsystem_vendor
, pdev
->subsystem_device
);
1286 DPRINTK("We have not been initialized by VGA BIOS "
1287 "and are running on an 3dlabs reference board\n");
1288 DPRINTK("Initializing card timings manually...\n");
1289 default_par
->memclock
=74894;
1293 /* Now work out how big lfb is going to be. */
1294 switch(default_par
->mem_config
& PM2F_MEM_CONFIG_RAM_MASK
) {
1295 case PM2F_MEM_BANKS_1
:
1296 default_par
->fb_size
=0x200000;
1298 case PM2F_MEM_BANKS_2
:
1299 default_par
->fb_size
=0x400000;
1301 case PM2F_MEM_BANKS_3
:
1302 default_par
->fb_size
=0x600000;
1304 case PM2F_MEM_BANKS_4
:
1305 default_par
->fb_size
=0x800000;
1308 pm2fb_fix
.smem_start
= pci_resource_start(pdev
, 1);
1309 pm2fb_fix
.smem_len
= default_par
->fb_size
;
1311 /* Linear frame buffer - request region and map it. */
1312 if ( !request_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
,
1314 printk(KERN_WARNING
"pm2fb: Can't reserve smem.\n");
1317 info
->screen_base
= default_par
->v_fb
=
1318 ioremap_nocache(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1319 if ( !default_par
->v_fb
) {
1320 printk(KERN_WARNING
"pm2fb: Can't ioremap smem area.\n");
1321 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1325 info
->fbops
= &pm2fb_ops
;
1326 info
->fix
= pm2fb_fix
;
1327 info
->pseudo_palette
= default_par
->palette
;
1328 info
->flags
= FBINFO_DEFAULT
|
1329 FBINFO_HWACCEL_YPAN
|
1330 FBINFO_HWACCEL_COPYAREA
|
1331 FBINFO_HWACCEL_FILLRECT
;
1334 mode
= "640x480@60";
1336 err
= fb_find_mode(&info
->var
, info
, mode
, NULL
, 0, NULL
, 8);
1337 if (!err
|| err
== 4)
1338 info
->var
= pm2fb_var
;
1340 if (fb_alloc_cmap(&info
->cmap
, 256, 0) < 0)
1343 if (register_framebuffer(info
) < 0)
1346 printk(KERN_INFO
"fb%d: %s frame buffer device, memory = %dK.\n",
1347 info
->node
, info
->fix
.id
, default_par
->fb_size
/ 1024);
1352 pci_set_drvdata(pdev
, info
);
1357 fb_dealloc_cmap(&info
->cmap
);
1359 iounmap(info
->screen_base
);
1360 release_mem_region(pm2fb_fix
.smem_start
, pm2fb_fix
.smem_len
);
1362 iounmap(default_par
->v_regs
);
1363 release_mem_region(pm2fb_fix
.mmio_start
, pm2fb_fix
.mmio_len
);
1365 framebuffer_release(info
);
1372 * Release all device resources.
1374 * @param pdev PCI device to clean up.
1376 static void __devexit
pm2fb_remove(struct pci_dev
*pdev
)
1378 struct fb_info
* info
= pci_get_drvdata(pdev
);
1379 struct fb_fix_screeninfo
* fix
= &info
->fix
;
1380 struct pm2fb_par
*par
= info
->par
;
1382 unregister_framebuffer(info
);
1384 iounmap(info
->screen_base
);
1385 release_mem_region(fix
->smem_start
, fix
->smem_len
);
1386 iounmap(par
->v_regs
);
1387 release_mem_region(fix
->mmio_start
, fix
->mmio_len
);
1389 pci_set_drvdata(pdev
, NULL
);
1393 static struct pci_device_id pm2fb_id_table
[] = {
1394 { PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_TVP4020
,
1395 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1397 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2
,
1398 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1400 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1401 PCI_ANY_ID
, PCI_ANY_ID
, PCI_BASE_CLASS_DISPLAY
<< 16,
1403 { PCI_VENDOR_ID_3DLABS
, PCI_DEVICE_ID_3DLABS_PERMEDIA2V
,
1404 PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
<< 8,
1409 static struct pci_driver pm2fb_driver
= {
1411 .id_table
= pm2fb_id_table
,
1412 .probe
= pm2fb_probe
,
1413 .remove
= __devexit_p(pm2fb_remove
),
1416 MODULE_DEVICE_TABLE(pci
, pm2fb_id_table
);
1421 * Parse user speficied options.
1423 * This is, comma-separated options following `video=pm2fb:'.
1425 static int __init
pm2fb_setup(char *options
)
1429 if (!options
|| !*options
)
1432 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
1435 if(!strcmp(this_opt
, "lowhsync")) {
1437 } else if(!strcmp(this_opt
, "lowvsync")) {
1448 static int __init
pm2fb_init(void)
1451 char *option
= NULL
;
1453 if (fb_get_options("pm2fb", &option
))
1455 pm2fb_setup(option
);
1458 return pci_register_driver(&pm2fb_driver
);
1461 module_init(pm2fb_init
);
1468 static void __exit
pm2fb_exit(void)
1470 pci_unregister_driver(&pm2fb_driver
);
1475 module_exit(pm2fb_exit
);
1477 module_param(mode
, charp
, 0);
1478 MODULE_PARM_DESC(mode
, "Preferred video mode e.g. '648x480-8@60'");
1479 module_param(lowhsync
, bool, 0);
1480 MODULE_PARM_DESC(lowhsync
, "Force horizontal sync low regardless of mode");
1481 module_param(lowvsync
, bool, 0);
1482 MODULE_PARM_DESC(lowvsync
, "Force vertical sync low regardless of mode");
1484 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1485 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1486 MODULE_LICENSE("GPL");