2 * Renesas SH-mobile MIPI DSI support
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 * This is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
11 #include <linux/bitmap.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/types.h>
21 #include <linux/module.h>
23 #include <video/mipi_display.h>
24 #include <video/sh_mipi_dsi.h>
25 #include <video/sh_mobile_lcdc.h>
27 #include "sh_mobile_lcdcfb.h"
29 #define SYSCTRL 0x0000
30 #define SYSCONF 0x0004
32 #define RESREQSET0 0x0018
33 #define RESREQSET1 0x001c
34 #define HSTTOVSET 0x0020
35 #define LPRTOVSET 0x0024
36 #define TATOVSET 0x0028
37 #define PRTOVSET 0x002c
38 #define DSICTRL 0x0030
39 #define DSIINTE 0x0060
40 #define PHYCTRL 0x0070
42 /* relative to linkbase */
48 #define CMTSRTREQ 0x0070
49 #define CMTSRTCTR 0x00d0
51 /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
52 #define MAX_SH_MIPI_DSI 2
55 struct sh_mobile_lcdc_entity entity
;
58 void __iomem
*linkbase
;
60 struct platform_device
*pdev
;
63 #define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
65 static struct sh_mipi
*mipi_dsi
[MAX_SH_MIPI_DSI
];
67 /* Protect the above array */
68 static DEFINE_MUTEX(array_lock
);
70 static struct sh_mipi
*sh_mipi_by_handle(int handle
)
72 if (handle
>= ARRAY_SIZE(mipi_dsi
) || handle
< 0)
75 return mipi_dsi
[handle
];
78 static int sh_mipi_send_short(struct sh_mipi
*mipi
, u8 dsi_cmd
,
81 u32 data
= (dsi_cmd
<< 24) | (cmd
<< 16) | (param
<< 8);
84 /* transmit a short packet to LCD panel */
85 iowrite32(1 | data
, mipi
->linkbase
+ CMTSRTCTR
);
86 iowrite32(1, mipi
->linkbase
+ CMTSRTREQ
);
88 while ((ioread32(mipi
->linkbase
+ CMTSRTREQ
) & 1) && --cnt
)
91 return cnt
? 0 : -ETIMEDOUT
;
94 #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
97 static int sh_mipi_dcs(int handle
, u8 cmd
)
99 struct sh_mipi
*mipi
= sh_mipi_by_handle(LCD_CHAN2MIPI(handle
));
102 return sh_mipi_send_short(mipi
, MIPI_DSI_DCS_SHORT_WRITE
, cmd
, 0);
105 static int sh_mipi_dcs_param(int handle
, u8 cmd
, u8 param
)
107 struct sh_mipi
*mipi
= sh_mipi_by_handle(LCD_CHAN2MIPI(handle
));
110 return sh_mipi_send_short(mipi
, MIPI_DSI_DCS_SHORT_WRITE_PARAM
, cmd
,
114 static void sh_mipi_dsi_enable(struct sh_mipi
*mipi
, bool enable
)
117 * enable LCDC data tx, transition to LPS after completion of each HS
120 iowrite32(0x00000002 | enable
, mipi
->linkbase
+ DTCTR
);
123 static void sh_mipi_shutdown(struct platform_device
*pdev
)
125 struct sh_mipi
*mipi
= to_sh_mipi(platform_get_drvdata(pdev
));
127 sh_mipi_dsi_enable(mipi
, false);
130 static int __init
sh_mipi_setup(struct sh_mipi
*mipi
,
131 struct sh_mipi_dsi_info
*pdata
)
133 void __iomem
*base
= mipi
->base
;
134 struct sh_mobile_lcdc_chan_cfg
*ch
= pdata
->lcd_chan
;
135 u32 pctype
, datatype
, pixfmt
, linelength
, vmctr2
;
136 u32 tmp
, top
, bottom
, delay
, div
;
141 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
142 * the default videomode. If this ever becomes a problem, We'll have to
143 * move this to mipi_display_on() above and use info->var.xres
145 switch (pdata
->data_format
) {
148 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
149 pixfmt
= MIPI_DCS_PIXEL_FMT_24BIT
;
150 linelength
= ch
->lcd_modes
[0].xres
* 3;
155 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
156 pixfmt
= MIPI_DCS_PIXEL_FMT_16BIT
;
157 linelength
= ch
->lcd_modes
[0].xres
* 2;
162 datatype
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
163 pixfmt
= MIPI_DCS_PIXEL_FMT_24BIT
;
164 linelength
= ch
->lcd_modes
[0].xres
* 3;
169 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
170 pixfmt
= MIPI_DCS_PIXEL_FMT_18BIT
;
171 linelength
= (ch
->lcd_modes
[0].xres
* 18 + 7) / 8;
176 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_24
;
177 pixfmt
= MIPI_DCS_PIXEL_FMT_24BIT
;
178 linelength
= ch
->lcd_modes
[0].xres
* 3;
183 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_16
;
184 pixfmt
= MIPI_DCS_PIXEL_FMT_16BIT
;
185 linelength
= ch
->lcd_modes
[0].xres
* 2;
190 datatype
= MIPI_DSI_PIXEL_STREAM_3BYTE_18
;
191 pixfmt
= MIPI_DCS_PIXEL_FMT_24BIT
;
192 linelength
= ch
->lcd_modes
[0].xres
* 3;
197 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_18
;
198 pixfmt
= MIPI_DCS_PIXEL_FMT_18BIT
;
199 linelength
= (ch
->lcd_modes
[0].xres
* 18 + 7) / 8;
204 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16
;
205 pixfmt
= MIPI_DCS_PIXEL_FMT_16BIT
;
206 linelength
= ch
->lcd_modes
[0].xres
* 2;
211 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16
;
212 pixfmt
= MIPI_DCS_PIXEL_FMT_16BIT
;
213 linelength
= ch
->lcd_modes
[0].xres
* 2;
218 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12
;
219 pixfmt
= MIPI_DCS_PIXEL_FMT_12BIT
;
220 linelength
= (ch
->lcd_modes
[0].xres
* 12 + 7) / 8;
225 datatype
= MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12
;
226 pixfmt
= MIPI_DCS_PIXEL_FMT_12BIT
;
227 /* Length of U/V line */
228 linelength
= (ch
->lcd_modes
[0].xres
+ 1) / 2;
235 if ((yuv
&& ch
->interface_type
!= YUV422
) ||
236 (!yuv
&& ch
->interface_type
!= RGB24
))
243 iowrite32(0x00000001, base
+ SYSCTRL
);
244 /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
246 iowrite32(0x00000000, base
+ SYSCTRL
);
257 iowrite32(0x70003332, base
+ TIMSET
);
258 /* no responses requested */
259 iowrite32(0x00000000, base
+ RESREQSET0
);
260 /* request response to packets of type 0x28 */
261 iowrite32(0x00000100, base
+ RESREQSET1
);
262 /* High-speed transmission timeout, default 0xffffffff */
263 iowrite32(0x0fffffff, base
+ HSTTOVSET
);
264 /* LP reception timeout, default 0xffffffff */
265 iowrite32(0x0fffffff, base
+ LPRTOVSET
);
266 /* Turn-around timeout, default 0xffffffff */
267 iowrite32(0x0fffffff, base
+ TATOVSET
);
268 /* Peripheral reset timeout, default 0xffffffff */
269 iowrite32(0x0fffffff, base
+ PRTOVSET
);
270 /* Interrupts not used, disable all */
271 iowrite32(0, base
+ DSIINTE
);
273 iowrite32(0x00000001, base
+ PHYCTRL
);
275 /* Deassert resets, power on */
276 iowrite32(0x03070001 | pdata
->phyctrl
, base
+ PHYCTRL
);
279 * Default = ULPS enable |
280 * Contention detection enabled |
281 * EoT packet transmission enable |
285 bitmap_fill((unsigned long *)&tmp
, pdata
->lane
);
287 iowrite32(tmp
, base
+ SYSCONF
);
292 * Enable transmission of all packets,
293 * transmit LPS after each HS packet completion
295 iowrite32(0x00000006, mipi
->linkbase
+ DTCTR
);
296 /* VSYNC width = 2 (<< 17) */
297 iowrite32((ch
->lcd_modes
[0].vsync_len
<< pdata
->vsynw_offset
) |
298 (pdata
->clksrc
<< 16) | (pctype
<< 12) | datatype
,
299 mipi
->linkbase
+ VMCTR1
);
302 * Non-burst mode with sync pulses: VSE and HSE are output,
303 * HSA period allowed, no commands in LP
306 if (pdata
->flags
& SH_MIPI_DSI_VSEE
)
308 if (pdata
->flags
& SH_MIPI_DSI_HSEE
)
310 if (pdata
->flags
& SH_MIPI_DSI_HSAE
)
312 if (pdata
->flags
& SH_MIPI_DSI_BL2E
)
314 if (pdata
->flags
& SH_MIPI_DSI_HSABM
)
316 if (pdata
->flags
& SH_MIPI_DSI_HBPBM
)
318 if (pdata
->flags
& SH_MIPI_DSI_HFPBM
)
320 iowrite32(vmctr2
, mipi
->linkbase
+ VMCTR2
);
323 * VMLEN1 = RGBLEN | HSALEN
326 * Video mode - Blanking Packet setting
328 top
= linelength
<< 16; /* RGBLEN */
330 if (pdata
->flags
& SH_MIPI_DSI_HSABM
) /* HSALEN */
331 bottom
= (pdata
->lane
* ch
->lcd_modes
[0].hsync_len
) - 10;
332 iowrite32(top
| bottom
, mipi
->linkbase
+ VMLEN1
);
335 * VMLEN2 = HBPLEN | HFPLEN
338 * Video mode - Blanking Packet setting
344 div
= 1; /* HSbyteCLK is calculation base
345 * HS4divCLK = HSbyteCLK/2
346 * HS6divCLK is not supported for now */
347 if (pdata
->flags
& SH_MIPI_DSI_HS4divCLK
)
350 if (pdata
->flags
& SH_MIPI_DSI_HFPBM
) { /* HBPLEN */
351 top
= ch
->lcd_modes
[0].hsync_len
+ ch
->lcd_modes
[0].left_margin
;
352 top
= ((pdata
->lane
* top
/ div
) - 10) << 16;
354 if (pdata
->flags
& SH_MIPI_DSI_HBPBM
) { /* HFPLEN */
355 bottom
= ch
->lcd_modes
[0].right_margin
;
356 bottom
= (pdata
->lane
* bottom
/ div
) - 12;
359 bpp
= linelength
/ ch
->lcd_modes
[0].xres
; /* byte / pixel */
360 if ((pdata
->lane
/ div
) > bpp
) {
361 tmp
= ch
->lcd_modes
[0].xres
/ bpp
; /* output cycle */
362 tmp
= ch
->lcd_modes
[0].xres
- tmp
; /* (input - output) cycle */
363 delay
= (pdata
->lane
* tmp
);
366 iowrite32(top
| (bottom
+ delay
) , mipi
->linkbase
+ VMLEN2
);
370 /* setup LCD panel */
372 /* cf. drivers/video/omap/lcd_mipid.c */
373 sh_mipi_dcs(ch
->chan
, MIPI_DCS_EXIT_SLEEP_MODE
);
376 * [7] - Page Address Mode
377 * [6] - Column Address Mode
378 * [5] - Page / Column Address Mode
379 * [4] - Display Device Line Refresh Order
380 * [3] - RGB/BGR Order
381 * [2] - Display Data Latch Data Order
382 * [1] - Flip Horizontal
383 * [0] - Flip Vertical
385 sh_mipi_dcs_param(ch
->chan
, MIPI_DCS_SET_ADDRESS_MODE
, 0x00);
386 /* cf. set_data_lines() */
387 sh_mipi_dcs_param(ch
->chan
, MIPI_DCS_SET_PIXEL_FORMAT
,
389 sh_mipi_dcs(ch
->chan
, MIPI_DCS_SET_DISPLAY_ON
);
391 /* Enable timeout counters */
392 iowrite32(0x00000f00, base
+ DSICTRL
);
397 static int mipi_display_on(struct sh_mobile_lcdc_entity
*entity
)
399 struct sh_mipi
*mipi
= to_sh_mipi(entity
);
400 struct sh_mipi_dsi_info
*pdata
= mipi
->pdev
->dev
.platform_data
;
403 pm_runtime_get_sync(&mipi
->pdev
->dev
);
405 ret
= pdata
->set_dot_clock(mipi
->pdev
, mipi
->base
, 1);
407 goto mipi_display_on_fail1
;
409 ret
= sh_mipi_setup(mipi
, pdata
);
411 goto mipi_display_on_fail2
;
413 sh_mipi_dsi_enable(mipi
, true);
415 return SH_MOBILE_LCDC_DISPLAY_CONNECTED
;
417 mipi_display_on_fail1
:
418 pm_runtime_put_sync(&mipi
->pdev
->dev
);
419 mipi_display_on_fail2
:
420 pdata
->set_dot_clock(mipi
->pdev
, mipi
->base
, 0);
425 static void mipi_display_off(struct sh_mobile_lcdc_entity
*entity
)
427 struct sh_mipi
*mipi
= to_sh_mipi(entity
);
428 struct sh_mipi_dsi_info
*pdata
= mipi
->pdev
->dev
.platform_data
;
430 sh_mipi_dsi_enable(mipi
, false);
432 pdata
->set_dot_clock(mipi
->pdev
, mipi
->base
, 0);
434 pm_runtime_put_sync(&mipi
->pdev
->dev
);
437 static const struct sh_mobile_lcdc_entity_ops mipi_ops
= {
438 .display_on
= mipi_display_on
,
439 .display_off
= mipi_display_off
,
442 static int __init
sh_mipi_probe(struct platform_device
*pdev
)
444 struct sh_mipi
*mipi
;
445 struct sh_mipi_dsi_info
*pdata
= pdev
->dev
.platform_data
;
446 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
447 struct resource
*res2
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
448 unsigned long rate
, f_current
;
449 int idx
= pdev
->id
, ret
;
451 if (!res
|| !res2
|| idx
>= ARRAY_SIZE(mipi_dsi
) || !pdata
)
454 if (!pdata
->set_dot_clock
)
457 mutex_lock(&array_lock
);
459 for (idx
= 0; idx
< ARRAY_SIZE(mipi_dsi
) && mipi_dsi
[idx
]; idx
++)
462 if (idx
== ARRAY_SIZE(mipi_dsi
)) {
467 mipi
= kzalloc(sizeof(*mipi
), GFP_KERNEL
);
473 mipi
->entity
.owner
= THIS_MODULE
;
474 mipi
->entity
.ops
= &mipi_ops
;
476 if (!request_mem_region(res
->start
, resource_size(res
), pdev
->name
)) {
477 dev_err(&pdev
->dev
, "MIPI register region already claimed\n");
482 mipi
->base
= ioremap(res
->start
, resource_size(res
));
488 if (!request_mem_region(res2
->start
, resource_size(res2
), pdev
->name
)) {
489 dev_err(&pdev
->dev
, "MIPI register region 2 already claimed\n");
494 mipi
->linkbase
= ioremap(res2
->start
, resource_size(res2
));
495 if (!mipi
->linkbase
) {
502 mipi
->dsit_clk
= clk_get(&pdev
->dev
, "dsit_clk");
503 if (IS_ERR(mipi
->dsit_clk
)) {
504 ret
= PTR_ERR(mipi
->dsit_clk
);
508 f_current
= clk_get_rate(mipi
->dsit_clk
);
509 /* 80MHz required by the datasheet */
510 rate
= clk_round_rate(mipi
->dsit_clk
, 80000000);
511 if (rate
> 0 && rate
!= f_current
)
512 ret
= clk_set_rate(mipi
->dsit_clk
, rate
);
518 dev_dbg(&pdev
->dev
, "DSI-T clk %lu -> %lu\n", f_current
, rate
);
520 ret
= clk_enable(mipi
->dsit_clk
);
524 mipi_dsi
[idx
] = mipi
;
526 pm_runtime_enable(&pdev
->dev
);
527 pm_runtime_resume(&pdev
->dev
);
529 mutex_unlock(&array_lock
);
530 platform_set_drvdata(pdev
, &mipi
->entity
);
536 clk_put(mipi
->dsit_clk
);
538 iounmap(mipi
->linkbase
);
540 release_mem_region(res2
->start
, resource_size(res2
));
544 release_mem_region(res
->start
, resource_size(res
));
549 mutex_unlock(&array_lock
);
554 static int __exit
sh_mipi_remove(struct platform_device
*pdev
)
556 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
557 struct resource
*res2
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
558 struct sh_mipi
*mipi
= to_sh_mipi(platform_get_drvdata(pdev
));
561 mutex_lock(&array_lock
);
563 for (i
= 0; i
< ARRAY_SIZE(mipi_dsi
) && mipi_dsi
[i
] != mipi
; i
++)
566 if (i
== ARRAY_SIZE(mipi_dsi
)) {
573 mutex_unlock(&array_lock
);
578 pm_runtime_disable(&pdev
->dev
);
579 clk_disable(mipi
->dsit_clk
);
580 clk_put(mipi
->dsit_clk
);
582 iounmap(mipi
->linkbase
);
584 release_mem_region(res2
->start
, resource_size(res2
));
587 release_mem_region(res
->start
, resource_size(res
));
588 platform_set_drvdata(pdev
, NULL
);
594 static struct platform_driver sh_mipi_driver
= {
595 .remove
= __exit_p(sh_mipi_remove
),
596 .shutdown
= sh_mipi_shutdown
,
598 .name
= "sh-mipi-dsi",
602 static int __init
sh_mipi_init(void)
604 return platform_driver_probe(&sh_mipi_driver
, sh_mipi_probe
);
606 module_init(sh_mipi_init
);
608 static void __exit
sh_mipi_exit(void)
610 platform_driver_unregister(&sh_mipi_driver
);
612 module_exit(sh_mipi_exit
);
614 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
615 MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
616 MODULE_LICENSE("GPL v2");