drivers/video/via/via-core.h

   1 /*
   2  * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
   3  * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
   4  * Copyright 2009 Jonathan Corbet <corbet@lwn.net>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public
   8  * License as published by the Free Software Foundation;
   9  * either version 2, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  13  * the implied warranty of MERCHANTABILITY or FITNESS FOR
  14  * A PARTICULAR PURPOSE.See the GNU General Public License
  15  * for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc.,
  20  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21  */
  22
  23 #ifndef __VIA_CORE_H__
  24 #define __VIA_CORE_H__
  25 #include <linux/spinlock.h>
  26 #include <linux/pci.h>
  27
  28 /*
  29  * A description of each known serial I2C/GPIO port.
  30  */
  31 enum via_port_type {
  32         VIA_PORT_NONE = 0,
  33         VIA_PORT_I2C,
  34         VIA_PORT_GPIO,
  35 };
  36
  37 enum via_port_mode {
  38         VIA_MODE_OFF = 0,
  39         VIA_MODE_I2C,           /* Used as I2C port */
  40         VIA_MODE_GPIO,  /* Two GPIO ports */
  41 };
  42
  43 enum viafb_i2c_adap {
  44         VIA_PORT_26 = 0,
  45         VIA_PORT_31,
  46         VIA_PORT_25,
  47         VIA_PORT_2C,
  48         VIA_PORT_3D,
  49 };
  50 #define VIAFB_NUM_PORTS 5
  51
  52 struct via_port_cfg {
  53         enum via_port_type      type;
  54         enum via_port_mode      mode;
  55         u16                     io_port;
  56         u8                      ioport_index;
  57 };
  58
  59 /*
  60  * This is the global viafb "device" containing stuff needed by
  61  * all subdevs.
  62  */
  63 struct viafb_dev {
  64         struct pci_dev *pdev;
  65         int chip_type;
  66         struct via_port_cfg *port_cfg;
  67         /*
  68          * Spinlock for access to device registers.  Not yet
  69          * globally used.
  70          */
  71         spinlock_t reg_lock;
  72         /*
  73          * The framebuffer MMIO region.  Little, if anything, touches
  74          * this memory directly, and certainly nothing outside of the
  75          * framebuffer device itself.  We *do* have to be able to allocate
  76          * chunks of this memory for other devices, though.
  77          */
  78         unsigned long fbmem_start;
  79         long fbmem_len;
  80         void __iomem *fbmem;
  81 #if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE)
  82         long camera_fbmem_offset;
  83         long camera_fbmem_size;
  84 #endif
  85         /*
  86          * The MMIO region for device registers.
  87          */
  88         unsigned long engine_start;
  89         unsigned long engine_len;
  90         void __iomem *engine_mmio;
  91
  92 };
  93
  94 /*
  95  * Interrupt management.
  96  */
  97
  98 void viafb_irq_enable(u32 mask);
  99 void viafb_irq_disable(u32 mask);
 100
 101 /*
 102  * The global interrupt control register and its bits.
 103  */
 104 #define VDE_INTERRUPT   0x200   /* Video interrupt flags/masks */
 105 #define   VDE_I_DVISENSE  0x00000001  /* DVI sense int status */
 106 #define   VDE_I_VBLANK    0x00000002  /* Vertical blank status */
 107 #define   VDE_I_MCCFI     0x00000004  /* MCE compl. frame int status */
 108 #define   VDE_I_VSYNC     0x00000008  /* VGA VSYNC int status */
 109 #define   VDE_I_DMA0DDONE 0x00000010  /* DMA 0 descr done */
 110 #define   VDE_I_DMA0TDONE 0x00000020  /* DMA 0 transfer done */
 111 #define   VDE_I_DMA1DDONE 0x00000040  /* DMA 1 descr done */
 112 #define   VDE_I_DMA1TDONE 0x00000080  /* DMA 1 transfer done */
 113 #define   VDE_I_C1AV      0x00000100  /* Cap Eng 1 act vid end */
 114 #define   VDE_I_HQV0      0x00000200  /* First HQV engine */
 115 #define   VDE_I_HQV1      0x00000400  /* Second HQV engine */
 116 #define   VDE_I_HQV1EN    0x00000800  /* Second HQV engine enable */
 117 #define   VDE_I_C0AV      0x00001000  /* Cap Eng 0 act vid end */
 118 #define   VDE_I_C0VBI     0x00002000  /* Cap Eng 0 VBI end */
 119 #define   VDE_I_C1VBI     0x00004000  /* Cap Eng 1 VBI end */
 120 #define   VDE_I_VSYNC2    0x00008000  /* Sec. Disp. VSYNC */
 121 #define   VDE_I_DVISNSEN  0x00010000  /* DVI sense enable */
 122 #define   VDE_I_VSYNC2EN  0x00020000  /* Sec Disp VSYNC enable */
 123 #define   VDE_I_MCCFIEN   0x00040000  /* MC comp frame int mask enable */
 124 #define   VDE_I_VSYNCEN   0x00080000  /* VSYNC enable */
 125 #define   VDE_I_DMA0DDEN  0x00100000  /* DMA 0 descr done enable */
 126 #define   VDE_I_DMA0TDEN  0x00200000  /* DMA 0 trans done enable */
 127 #define   VDE_I_DMA1DDEN  0x00400000  /* DMA 1 descr done enable */
 128 #define   VDE_I_DMA1TDEN  0x00800000  /* DMA 1 trans done enable */
 129 #define   VDE_I_C1AVEN    0x01000000  /* cap 1 act vid end enable */
 130 #define   VDE_I_HQV0EN    0x02000000  /* First hqv engine enable */
 131 #define   VDE_I_C1VBIEN   0x04000000  /* Cap 1 VBI end enable */
 132 #define   VDE_I_LVDSSI    0x08000000  /* LVDS sense interrupt */
 133 #define   VDE_I_C0AVEN    0x10000000  /* Cap 0 act vid end enable */
 134 #define   VDE_I_C0VBIEN   0x20000000  /* Cap 0 VBI end enable */
 135 #define   VDE_I_LVDSSIEN  0x40000000  /* LVDS Sense enable */
 136 #define   VDE_I_ENABLE    0x80000000  /* Global interrupt enable */
 137
 138 /*
 139  * DMA management.
 140  */
 141 int viafb_request_dma(void);
 142 void viafb_release_dma(void);
 143 /* void viafb_dma_copy_out(unsigned int offset, dma_addr_t paddr, int len); */
 144 int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg);
 145
 146 /*
 147  * DMA Controller registers.
 148  */
 149 #define VDMA_MR0        0xe00           /* Mod reg 0 */
 150 #define   VDMA_MR_CHAIN   0x01          /* Chaining mode */
 151 #define   VDMA_MR_TDIE    0x02          /* Transfer done int enable */
 152 #define VDMA_CSR0       0xe04           /* Control/status */
 153 #define   VDMA_C_ENABLE   0x01            /* DMA Enable */
 154 #define   VDMA_C_START    0x02            /* Start a transfer */
 155 #define   VDMA_C_ABORT    0x04            /* Abort a transfer */
 156 #define   VDMA_C_DONE     0x08            /* Transfer is done */
 157 #define VDMA_MARL0      0xe20           /* Mem addr low */
 158 #define VDMA_MARH0      0xe24           /* Mem addr high */
 159 #define VDMA_DAR0       0xe28           /* Device address */
 160 #define VDMA_DQWCR0     0xe2c           /* Count (16-byte) */
 161 #define VDMA_TMR0       0xe30           /* Tile mode reg */
 162 #define VDMA_DPRL0      0xe34           /* Not sure */
 163 #define   VDMA_DPR_IN     0x08          /* Inbound transfer to FB */
 164 #define VDMA_DPRH0      0xe38
 165 #define VDMA_PMR0       (0xe00 + 0x134) /* Pitch mode */
 166
 167 /*
 168  * Useful stuff that probably belongs somewhere global.
 169  */
 170 #define VGA_WIDTH       640
 171 #define VGA_HEIGHT      480
 172
 173 #endif /* __VIA_CORE_H__ */