drivers/w1/masters/ds1wm.c

   1 /*
   2  * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
   3  * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
   4  * like hx4700).
   5  *
   6  * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
   7  * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
   8  *
   9  * Use consistent with the GNU GPL is permitted,
  10  * provided that this copyright notice is
  11  * preserved in its entirety in all copies and derived works.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/err.h>
  20 #include <linux/delay.h>
  21 #include <linux/mfd/core.h>
  22 #include <linux/mfd/ds1wm.h>
  23 #include <linux/slab.h>
  24
  25 #include <asm/io.h>
  26
  27 #include "../w1.h"
  28 #include "../w1_int.h"
  29
  30
  31 #define DS1WM_CMD       0x00    /* R/W 4 bits command */
  32 #define DS1WM_DATA      0x01    /* R/W 8 bits, transmit/receive buffer */
  33 #define DS1WM_INT       0x02    /* R/W interrupt status */
  34 #define DS1WM_INT_EN    0x03    /* R/W interrupt enable */
  35 #define DS1WM_CLKDIV    0x04    /* R/W 5 bits of divisor and pre-scale */
  36 #define DS1WM_CNTRL     0x05    /* R/W master control register (not used yet) */
  37
  38 #define DS1WM_CMD_1W_RESET  (1 << 0)    /* force reset on 1-wire bus */
  39 #define DS1WM_CMD_SRA       (1 << 1)    /* enable Search ROM accelerator mode */
  40 #define DS1WM_CMD_DQ_OUTPUT (1 << 2)    /* write only - forces bus low */
  41 #define DS1WM_CMD_DQ_INPUT  (1 << 3)    /* read only - reflects state of bus */
  42 #define DS1WM_CMD_RST       (1 << 5)    /* software reset */
  43 #define DS1WM_CMD_OD        (1 << 7)    /* overdrive */
  44
  45 #define DS1WM_INT_PD        (1 << 0)    /* presence detect */
  46 #define DS1WM_INT_PDR       (1 << 1)    /* presence detect result */
  47 #define DS1WM_INT_TBE       (1 << 2)    /* tx buffer empty */
  48 #define DS1WM_INT_TSRE      (1 << 3)    /* tx shift register empty */
  49 #define DS1WM_INT_RBF       (1 << 4)    /* rx buffer full */
  50 #define DS1WM_INT_RSRF      (1 << 5)    /* rx shift register full */
  51
  52 #define DS1WM_INTEN_EPD     (1 << 0)    /* enable presence detect int */
  53 #define DS1WM_INTEN_IAS     (1 << 1)    /* INTR active state */
  54 #define DS1WM_INTEN_ETBE    (1 << 2)    /* enable tx buffer empty int */
  55 #define DS1WM_INTEN_ETMT    (1 << 3)    /* enable tx shift register empty int */
  56 #define DS1WM_INTEN_ERBF    (1 << 4)    /* enable rx buffer full int */
  57 #define DS1WM_INTEN_ERSRF   (1 << 5)    /* enable rx shift register full int */
  58 #define DS1WM_INTEN_DQO     (1 << 6)    /* enable direct bus driving ops */
  59
  60 #define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS)  /* all but INTR active state */
  61
  62 #define DS1WM_TIMEOUT (HZ * 5)
  63
  64 static struct {
  65         unsigned long freq;
  66         unsigned long divisor;
  67 } freq[] = {
  68         {   1000000, 0x80 },
  69         {   2000000, 0x84 },
  70         {   3000000, 0x81 },
  71         {   4000000, 0x88 },
  72         {   5000000, 0x82 },
  73         {   6000000, 0x85 },
  74         {   7000000, 0x83 },
  75         {   8000000, 0x8c },
  76         {  10000000, 0x86 },
  77         {  12000000, 0x89 },
  78         {  14000000, 0x87 },
  79         {  16000000, 0x90 },
  80         {  20000000, 0x8a },
  81         {  24000000, 0x8d },
  82         {  28000000, 0x8b },
  83         {  32000000, 0x94 },
  84         {  40000000, 0x8e },
  85         {  48000000, 0x91 },
  86         {  56000000, 0x8f },
  87         {  64000000, 0x98 },
  88         {  80000000, 0x92 },
  89         {  96000000, 0x95 },
  90         { 112000000, 0x93 },
  91         { 128000000, 0x9c },
  92 /* you can continue this table, consult the OPERATION - CLOCK DIVISOR
  93    section of the ds1wm spec sheet. */
  94 };
  95
  96 struct ds1wm_data {
  97         void     __iomem *map;
  98         int      bus_shift; /* # of shifts to calc register offsets */
  99         struct platform_device *pdev;
 100         const struct mfd_cell   *cell;
 101         int      irq;
 102         int      slave_present;
 103         void     *reset_complete;
 104         void     *read_complete;
 105         void     *write_complete;
 106         int      read_error;
 107         /* last byte received */
 108         u8       read_byte;
 109         /* byte to write that makes all intr disabled, */
 110         /* considering active_state (IAS) (optimization) */
 111         u8       int_en_reg_none;
 112 };
 113
 114 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 115                                         u8 val)
 116 {
 117         __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 118 }
 119
 120 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 121 {
 122         return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 123 }
 124
 125
 126 static irqreturn_t ds1wm_isr(int isr, void *data)
 127 {
 128         struct ds1wm_data *ds1wm_data = data;
 129         u8 intr;
 130         u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
 131         /* if no bits are set in int enable register (except the IAS)
 132         than go no further, reading the regs below has side effects */
 133         if (!(inten & DS1WM_INTEN_NOT_IAS))
 134                 return IRQ_NONE;
 135
 136         ds1wm_write_register(ds1wm_data,
 137                 DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
 138
 139         /* this read action clears the INTR and certain flags in ds1wm */
 140         intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
 141
 142         ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
 143
 144         if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
 145                 inten &= ~DS1WM_INTEN_ETMT;
 146                 complete(ds1wm_data->write_complete);
 147         }
 148         if (intr & DS1WM_INT_RBF) {
 149                 /* this read clears the RBF flag */
 150                 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
 151                 DS1WM_DATA);
 152                 inten &= ~DS1WM_INTEN_ERBF;
 153                 if (ds1wm_data->read_complete)
 154                         complete(ds1wm_data->read_complete);
 155         }
 156         if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
 157                 inten &= ~DS1WM_INTEN_EPD;
 158                 complete(ds1wm_data->reset_complete);
 159         }
 160
 161         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
 162         return IRQ_HANDLED;
 163 }
 164
 165 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
 166 {
 167         unsigned long timeleft;
 168         DECLARE_COMPLETION_ONSTACK(reset_done);
 169
 170         ds1wm_data->reset_complete = &reset_done;
 171
 172         /* enable Presence detect only */
 173         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
 174         ds1wm_data->int_en_reg_none);
 175
 176         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
 177
 178         timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
 179         ds1wm_data->reset_complete = NULL;
 180         if (!timeleft) {
 181                 dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
 182                 return 1;
 183         }
 184
 185         if (!ds1wm_data->slave_present) {
 186                 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
 187                 return 1;
 188         }
 189
 190         return 0;
 191 }
 192
 193 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
 194 {
 195         unsigned long timeleft;
 196         DECLARE_COMPLETION_ONSTACK(write_done);
 197         ds1wm_data->write_complete = &write_done;
 198
 199         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 200         ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
 201
 202         ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
 203
 204         timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
 205
 206         ds1wm_data->write_complete = NULL;
 207         if (!timeleft) {
 208                 dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
 209                 return -ETIMEDOUT;
 210         }
 211
 212         return 0;
 213 }
 214
 215 static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
 216 {
 217         unsigned long timeleft;
 218         u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
 219         DECLARE_COMPLETION_ONSTACK(read_done);
 220
 221         ds1wm_read_register(ds1wm_data, DS1WM_DATA);
 222
 223         ds1wm_data->read_complete = &read_done;
 224         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
 225
 226         ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
 227         timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
 228
 229         ds1wm_data->read_complete = NULL;
 230         if (!timeleft) {
 231                 dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
 232                 ds1wm_data->read_error = -ETIMEDOUT;
 233                 return 0xFF;
 234         }
 235         ds1wm_data->read_error = 0;
 236         return ds1wm_data->read_byte;
 237 }
 238
 239 static int ds1wm_find_divisor(int gclk)
 240 {
 241         int i;
 242
 243         for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
 244                 if (gclk >= freq[i].freq)
 245                         return freq[i].divisor;
 246
 247         return 0;
 248 }
 249
 250 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
 251 {
 252         int divisor;
 253         struct ds1wm_driver_data *plat = ds1wm_data->pdev->dev.platform_data;
 254
 255         if (ds1wm_data->cell->enable)
 256                 ds1wm_data->cell->enable(ds1wm_data->pdev);
 257
 258         divisor = ds1wm_find_divisor(plat->clock_rate);
 259         dev_dbg(&ds1wm_data->pdev->dev,
 260                 "found divisor 0x%x for clock %d\n", divisor, plat->clock_rate);
 261         if (divisor == 0) {
 262                 dev_err(&ds1wm_data->pdev->dev,
 263                         "no suitable divisor for %dHz clock\n",
 264                         plat->clock_rate);
 265                 return;
 266         }
 267         ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
 268
 269         /* Let the w1 clock stabilize. */
 270         msleep(1);
 271
 272         ds1wm_reset(ds1wm_data);
 273 }
 274
 275 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
 276 {
 277         ds1wm_reset(ds1wm_data);
 278
 279         /* Disable interrupts. */
 280         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 281                 ds1wm_data->int_en_reg_none);
 282
 283         if (ds1wm_data->cell->disable)
 284                 ds1wm_data->cell->disable(ds1wm_data->pdev);
 285 }
 286
 287 /* --------------------------------------------------------------------- */
 288 /* w1 methods */
 289
 290 static u8 ds1wm_read_byte(void *data)
 291 {
 292         struct ds1wm_data *ds1wm_data = data;
 293
 294         return ds1wm_read(ds1wm_data, 0xff);
 295 }
 296
 297 static void ds1wm_write_byte(void *data, u8 byte)
 298 {
 299         struct ds1wm_data *ds1wm_data = data;
 300
 301         ds1wm_write(ds1wm_data, byte);
 302 }
 303
 304 static u8 ds1wm_reset_bus(void *data)
 305 {
 306         struct ds1wm_data *ds1wm_data = data;
 307
 308         ds1wm_reset(ds1wm_data);
 309
 310         return 0;
 311 }
 312
 313 static void ds1wm_search(void *data, struct w1_master *master_dev,
 314                         u8 search_type, w1_slave_found_callback slave_found)
 315 {
 316         struct ds1wm_data *ds1wm_data = data;
 317         int i;
 318         int ms_discrep_bit = -1;
 319         u64 r = 0; /* holds the progress of the search */
 320         u64 r_prime, d;
 321         unsigned slaves_found = 0;
 322         unsigned int pass = 0;
 323
 324         dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
 325         while (true) {
 326                 ++pass;
 327                 if (pass > 100) {
 328                         dev_dbg(&ds1wm_data->pdev->dev,
 329                                 "too many attempts (100), search aborted\n");
 330                         return;
 331                 }
 332
 333                 if (ds1wm_reset(ds1wm_data)) {
 334                         dev_dbg(&ds1wm_data->pdev->dev,
 335                                 "pass: %d reset error (or no slaves)\n", pass);
 336                         break;
 337                 }
 338
 339                 dev_dbg(&ds1wm_data->pdev->dev,
 340                         "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
 341                 ds1wm_write(ds1wm_data, search_type);
 342                 dev_dbg(&ds1wm_data->pdev->dev,
 343                         "pass: %d entering ASM\n", pass);
 344                 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
 345                 dev_dbg(&ds1wm_data->pdev->dev,
 346                         "pass: %d begining nibble loop\n", pass);
 347
 348                 r_prime = 0;
 349                 d = 0;
 350                 /* we work one nibble at a time */
 351                 /* each nibble is interleaved to form a byte */
 352                 for (i = 0; i < 16; i++) {
 353
 354                         unsigned char resp, _r, _r_prime, _d;
 355
 356                         _r = (r >> (4*i)) & 0xf;
 357                         _r = ((_r & 0x1) << 1) |
 358                         ((_r & 0x2) << 2) |
 359                         ((_r & 0x4) << 3) |
 360                         ((_r & 0x8) << 4);
 361
 362                         /* writes _r, then reads back: */
 363                         resp = ds1wm_read(ds1wm_data, _r);
 364
 365                         if (ds1wm_data->read_error) {
 366                                 dev_err(&ds1wm_data->pdev->dev,
 367                                 "pass: %d nibble: %d read error\n", pass, i);
 368                                 break;
 369                         }
 370
 371                         _r_prime = ((resp & 0x02) >> 1) |
 372                         ((resp & 0x08) >> 2) |
 373                         ((resp & 0x20) >> 3) |
 374                         ((resp & 0x80) >> 4);
 375
 376                         _d = ((resp & 0x01) >> 0) |
 377                         ((resp & 0x04) >> 1) |
 378                         ((resp & 0x10) >> 2) |
 379                         ((resp & 0x40) >> 3);
 380
 381                         r_prime |= (unsigned long long) _r_prime << (i * 4);
 382                         d |= (unsigned long long) _d << (i * 4);
 383
 384                 }
 385                 if (ds1wm_data->read_error) {
 386                         dev_err(&ds1wm_data->pdev->dev,
 387                                 "pass: %d read error, retrying\n", pass);
 388                         break;
 389                 }
 390                 dev_dbg(&ds1wm_data->pdev->dev,
 391                         "pass: %d r\': %0#18llx d:%0#18llx\n",
 392                         pass, r_prime, d);
 393                 dev_dbg(&ds1wm_data->pdev->dev,
 394                         "pass: %d nibble loop complete, exiting ASM\n", pass);
 395                 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
 396                 dev_dbg(&ds1wm_data->pdev->dev,
 397                         "pass: %d resetting bus\n", pass);
 398                 ds1wm_reset(ds1wm_data);
 399                 if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
 400                         dev_err(&ds1wm_data->pdev->dev,
 401                                 "pass: %d bus error, retrying\n", pass);
 402                         continue; /* start over */
 403                 }
 404
 405
 406                 dev_dbg(&ds1wm_data->pdev->dev,
 407                         "pass: %d found %0#18llx\n", pass, r_prime);
 408                 slave_found(master_dev, r_prime);
 409                 ++slaves_found;
 410                 dev_dbg(&ds1wm_data->pdev->dev,
 411                         "pass: %d complete, preparing next pass\n", pass);
 412
 413                 /* any discrepency found which we already choose the
 414                    '1' branch is now is now irrelevant we reveal the
 415                    next branch with this: */
 416                 d &= ~r;
 417                 /* find last bit set, i.e. the most signif. bit set */
 418                 ms_discrep_bit = fls64(d) - 1;
 419                 dev_dbg(&ds1wm_data->pdev->dev,
 420                         "pass: %d new d:%0#18llx MS discrep bit:%d\n",
 421                         pass, d, ms_discrep_bit);
 422
 423                 /* prev_ms_discrep_bit = ms_discrep_bit;
 424                    prepare for next ROM search:             */
 425                 if (ms_discrep_bit == -1)
 426                         break;
 427
 428                 r = (r &  ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
 429         } /* end while true */
 430         dev_dbg(&ds1wm_data->pdev->dev,
 431                 "pass: %d total: %d search done ms d bit pos: %d\n", pass,
 432                 slaves_found, ms_discrep_bit);
 433 }
 434
 435 /* --------------------------------------------------------------------- */
 436
 437 static struct w1_bus_master ds1wm_master = {
 438         .read_byte  = ds1wm_read_byte,
 439         .write_byte = ds1wm_write_byte,
 440         .reset_bus  = ds1wm_reset_bus,
 441         .search     = ds1wm_search,
 442 };
 443
 444 static int ds1wm_probe(struct platform_device *pdev)
 445 {
 446         struct ds1wm_data *ds1wm_data;
 447         struct ds1wm_driver_data *plat;
 448         struct resource *res;
 449         int ret;
 450
 451         if (!pdev)
 452                 return -ENODEV;
 453
 454         ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
 455         if (!ds1wm_data)
 456                 return -ENOMEM;
 457
 458         platform_set_drvdata(pdev, ds1wm_data);
 459
 460         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 461         if (!res) {
 462                 ret = -ENXIO;
 463                 goto err0;
 464         }
 465         ds1wm_data->map = ioremap(res->start, resource_size(res));
 466         if (!ds1wm_data->map) {
 467                 ret = -ENOMEM;
 468                 goto err0;
 469         }
 470
 471         /* calculate bus shift from mem resource */
 472         ds1wm_data->bus_shift = resource_size(res) >> 3;
 473
 474         ds1wm_data->pdev = pdev;
 475         ds1wm_data->cell = mfd_get_cell(pdev);
 476         if (!ds1wm_data->cell) {
 477                 ret = -ENODEV;
 478                 goto err1;
 479         }
 480         plat = pdev->dev.platform_data;
 481         if (!plat) {
 482                 ret = -ENODEV;
 483                 goto err1;
 484         }
 485
 486         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 487         if (!res) {
 488                 ret = -ENXIO;
 489                 goto err1;
 490         }
 491         ds1wm_data->irq = res->start;
 492         ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
 493
 494         if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 495                 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 496         if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 497                 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
 498
 499         ret = request_irq(ds1wm_data->irq, ds1wm_isr,
 500                         IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data);
 501         if (ret)
 502                 goto err1;
 503
 504         ds1wm_up(ds1wm_data);
 505
 506         ds1wm_master.data = (void *)ds1wm_data;
 507
 508         ret = w1_add_master_device(&ds1wm_master);
 509         if (ret)
 510                 goto err2;
 511
 512         return 0;
 513
 514 err2:
 515         ds1wm_down(ds1wm_data);
 516         free_irq(ds1wm_data->irq, ds1wm_data);
 517 err1:
 518         iounmap(ds1wm_data->map);
 519 err0:
 520         kfree(ds1wm_data);
 521
 522         return ret;
 523 }
 524
 525 #ifdef CONFIG_PM
 526 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
 527 {
 528         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 529
 530         ds1wm_down(ds1wm_data);
 531
 532         return 0;
 533 }
 534
 535 static int ds1wm_resume(struct platform_device *pdev)
 536 {
 537         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 538
 539         ds1wm_up(ds1wm_data);
 540
 541         return 0;
 542 }
 543 #else
 544 #define ds1wm_suspend NULL
 545 #define ds1wm_resume NULL
 546 #endif
 547
 548 static int ds1wm_remove(struct platform_device *pdev)
 549 {
 550         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 551
 552         w1_remove_master_device(&ds1wm_master);
 553         ds1wm_down(ds1wm_data);
 554         free_irq(ds1wm_data->irq, ds1wm_data);
 555         iounmap(ds1wm_data->map);
 556         kfree(ds1wm_data);
 557
 558         return 0;
 559 }
 560
 561 static struct platform_driver ds1wm_driver = {
 562         .driver   = {
 563                 .name = "ds1wm",
 564         },
 565         .probe    = ds1wm_probe,
 566         .remove   = ds1wm_remove,
 567         .suspend  = ds1wm_suspend,
 568         .resume   = ds1wm_resume
 569 };
 570
 571 static int __init ds1wm_init(void)
 572 {
 573         printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
 574         return platform_driver_register(&ds1wm_driver);
 575 }
 576
 577 static void __exit ds1wm_exit(void)
 578 {
 579         platform_driver_unregister(&ds1wm_driver);
 580 }
 581
 582 module_init(ds1wm_init);
 583 module_exit(ds1wm_exit);
 584
 585 MODULE_LICENSE("GPL");
 586 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
 587         "Matt Reimer <mreimer@vpop.net>,"
 588         "Jean-Francois Dagenais <dagenaisj@sonatest.com>");
 589 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");