2 * Imagination Technologies PowerDown Controller Watchdog Timer.
4 * Copyright (c) 2014 Imagination Technologies Ltd.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
11 * 2012 Henrik Nordstrom
15 * The timeout value is rounded to the next power of two clock cycles.
16 * This is configured using the PDC_WDT_CONFIG register, according to this
19 * timeout = 2^(delay + 1) clock cycles
21 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
23 * Therefore, the hardware only allows to program watchdog timeouts, expressed
24 * as a power of two number of watchdog clock cycles. The current implementation
25 * guarantees that the actual watchdog timeout will be _at least_ the value
26 * programmed in the imgpdg_wdt driver.
28 * The following table shows how the user-configured timeout relates
29 * to the actual hardware timeout (watchdog clock @ 40000 Hz):
31 * input timeout | WD_DELAY | actual timeout
32 * -----------------------------------
33 * 10 | 18 | 13 seconds
34 * 20 | 19 | 26 seconds
35 * 30 | 20 | 52 seconds
36 * 60 | 21 | 104 seconds
38 * Albeit coarse, this granularity would suffice most watchdog uses.
39 * If the platform allows it, the user should be able to change the watchdog
40 * clock rate and achieve a finer timeout granularity.
43 #include <linux/clk.h>
45 #include <linux/log2.h>
46 #include <linux/module.h>
47 #include <linux/platform_device.h>
48 #include <linux/slab.h>
49 #include <linux/watchdog.h>
52 #define PDC_WDT_SOFT_RESET 0x00
53 #define PDC_WDT_CONFIG 0x04
54 #define PDC_WDT_CONFIG_ENABLE BIT(31)
55 #define PDC_WDT_CONFIG_DELAY_MASK 0x1f
57 #define PDC_WDT_TICKLE1 0x08
58 #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
59 #define PDC_WDT_TICKLE2 0x0c
60 #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
62 #define PDC_WDT_TICKLE_STATUS_MASK 0x7
63 #define PDC_WDT_TICKLE_STATUS_SHIFT 0
64 #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
65 #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */
66 #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */
67 #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
68 #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
70 /* Timeout values are in seconds */
71 #define PDC_WDT_MIN_TIMEOUT 1
72 #define PDC_WDT_DEF_TIMEOUT 64
75 module_param(heartbeat
, int, 0);
76 MODULE_PARM_DESC(heartbeat
, "Watchdog heartbeats in seconds "
77 "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT
) ")");
79 static bool nowayout
= WATCHDOG_NOWAYOUT
;
80 module_param(nowayout
, bool, 0);
81 MODULE_PARM_DESC(nowayout
, "Watchdog cannot be stopped once started "
82 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
85 struct watchdog_device wdt_dev
;
91 static int pdc_wdt_keepalive(struct watchdog_device
*wdt_dev
)
93 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
95 writel(PDC_WDT_TICKLE1_MAGIC
, wdt
->base
+ PDC_WDT_TICKLE1
);
96 writel(PDC_WDT_TICKLE2_MAGIC
, wdt
->base
+ PDC_WDT_TICKLE2
);
101 static int pdc_wdt_stop(struct watchdog_device
*wdt_dev
)
104 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
106 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
);
107 val
&= ~PDC_WDT_CONFIG_ENABLE
;
108 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
110 /* Must tickle to finish the stop */
111 pdc_wdt_keepalive(wdt_dev
);
116 static void __pdc_wdt_set_timeout(struct pdc_wdt_dev
*wdt
)
118 unsigned long clk_rate
= clk_get_rate(wdt
->wdt_clk
);
121 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
) & ~PDC_WDT_CONFIG_DELAY_MASK
;
122 val
|= order_base_2(wdt
->wdt_dev
.timeout
* clk_rate
) - 1;
123 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
126 static int pdc_wdt_set_timeout(struct watchdog_device
*wdt_dev
,
127 unsigned int new_timeout
)
129 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
131 wdt
->wdt_dev
.timeout
= new_timeout
;
133 __pdc_wdt_set_timeout(wdt
);
138 /* Start the watchdog timer (delay should already be set) */
139 static int pdc_wdt_start(struct watchdog_device
*wdt_dev
)
142 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
144 __pdc_wdt_set_timeout(wdt
);
146 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
);
147 val
|= PDC_WDT_CONFIG_ENABLE
;
148 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
153 static int pdc_wdt_restart(struct watchdog_device
*wdt_dev
)
155 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
157 /* Assert SOFT_RESET */
158 writel(0x1, wdt
->base
+ PDC_WDT_SOFT_RESET
);
163 static struct watchdog_info pdc_wdt_info
= {
164 .identity
= "IMG PDC Watchdog",
165 .options
= WDIOF_SETTIMEOUT
|
166 WDIOF_KEEPALIVEPING
|
170 static const struct watchdog_ops pdc_wdt_ops
= {
171 .owner
= THIS_MODULE
,
172 .start
= pdc_wdt_start
,
173 .stop
= pdc_wdt_stop
,
174 .ping
= pdc_wdt_keepalive
,
175 .set_timeout
= pdc_wdt_set_timeout
,
176 .restart
= pdc_wdt_restart
,
179 static int pdc_wdt_probe(struct platform_device
*pdev
)
183 unsigned long clk_rate
;
184 struct resource
*res
;
185 struct pdc_wdt_dev
*pdc_wdt
;
187 pdc_wdt
= devm_kzalloc(&pdev
->dev
, sizeof(*pdc_wdt
), GFP_KERNEL
);
191 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
192 pdc_wdt
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
193 if (IS_ERR(pdc_wdt
->base
))
194 return PTR_ERR(pdc_wdt
->base
);
196 pdc_wdt
->sys_clk
= devm_clk_get(&pdev
->dev
, "sys");
197 if (IS_ERR(pdc_wdt
->sys_clk
)) {
198 dev_err(&pdev
->dev
, "failed to get the sys clock\n");
199 return PTR_ERR(pdc_wdt
->sys_clk
);
202 pdc_wdt
->wdt_clk
= devm_clk_get(&pdev
->dev
, "wdt");
203 if (IS_ERR(pdc_wdt
->wdt_clk
)) {
204 dev_err(&pdev
->dev
, "failed to get the wdt clock\n");
205 return PTR_ERR(pdc_wdt
->wdt_clk
);
208 ret
= clk_prepare_enable(pdc_wdt
->sys_clk
);
210 dev_err(&pdev
->dev
, "could not prepare or enable sys clock\n");
214 ret
= clk_prepare_enable(pdc_wdt
->wdt_clk
);
216 dev_err(&pdev
->dev
, "could not prepare or enable wdt clock\n");
217 goto disable_sys_clk
;
220 /* We use the clock rate to calculate the max timeout */
221 clk_rate
= clk_get_rate(pdc_wdt
->wdt_clk
);
223 dev_err(&pdev
->dev
, "failed to get clock rate\n");
225 goto disable_wdt_clk
;
228 if (order_base_2(clk_rate
) > PDC_WDT_CONFIG_DELAY_MASK
+ 1) {
229 dev_err(&pdev
->dev
, "invalid clock rate\n");
231 goto disable_wdt_clk
;
234 if (order_base_2(clk_rate
) == 0)
235 pdc_wdt
->wdt_dev
.min_timeout
= PDC_WDT_MIN_TIMEOUT
+ 1;
237 pdc_wdt
->wdt_dev
.min_timeout
= PDC_WDT_MIN_TIMEOUT
;
239 pdc_wdt
->wdt_dev
.info
= &pdc_wdt_info
;
240 pdc_wdt
->wdt_dev
.ops
= &pdc_wdt_ops
;
242 div
= 1ULL << (PDC_WDT_CONFIG_DELAY_MASK
+ 1);
243 do_div(div
, clk_rate
);
244 pdc_wdt
->wdt_dev
.max_timeout
= div
;
245 pdc_wdt
->wdt_dev
.timeout
= PDC_WDT_DEF_TIMEOUT
;
246 pdc_wdt
->wdt_dev
.parent
= &pdev
->dev
;
247 watchdog_set_drvdata(&pdc_wdt
->wdt_dev
, pdc_wdt
);
249 watchdog_init_timeout(&pdc_wdt
->wdt_dev
, heartbeat
, &pdev
->dev
);
251 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
253 /* Find what caused the last reset */
254 val
= readl(pdc_wdt
->base
+ PDC_WDT_TICKLE1
);
255 val
= (val
& PDC_WDT_TICKLE_STATUS_MASK
) >> PDC_WDT_TICKLE_STATUS_SHIFT
;
257 case PDC_WDT_TICKLE_STATUS_TICKLE
:
258 case PDC_WDT_TICKLE_STATUS_TIMEOUT
:
259 pdc_wdt
->wdt_dev
.bootstatus
|= WDIOF_CARDRESET
;
261 "watchdog module last reset due to timeout\n");
263 case PDC_WDT_TICKLE_STATUS_HRESET
:
265 "watchdog module last reset due to hard reset\n");
267 case PDC_WDT_TICKLE_STATUS_SRESET
:
269 "watchdog module last reset due to soft reset\n");
271 case PDC_WDT_TICKLE_STATUS_USER
:
273 "watchdog module last reset due to user reset\n");
277 "contains an illegal status code (%08x)\n", val
);
281 watchdog_set_nowayout(&pdc_wdt
->wdt_dev
, nowayout
);
282 watchdog_set_restart_priority(&pdc_wdt
->wdt_dev
, 128);
284 platform_set_drvdata(pdev
, pdc_wdt
);
286 ret
= watchdog_register_device(&pdc_wdt
->wdt_dev
);
288 goto disable_wdt_clk
;
293 clk_disable_unprepare(pdc_wdt
->wdt_clk
);
295 clk_disable_unprepare(pdc_wdt
->sys_clk
);
299 static void pdc_wdt_shutdown(struct platform_device
*pdev
)
301 struct pdc_wdt_dev
*pdc_wdt
= platform_get_drvdata(pdev
);
303 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
306 static int pdc_wdt_remove(struct platform_device
*pdev
)
308 struct pdc_wdt_dev
*pdc_wdt
= platform_get_drvdata(pdev
);
310 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
311 watchdog_unregister_device(&pdc_wdt
->wdt_dev
);
312 clk_disable_unprepare(pdc_wdt
->wdt_clk
);
313 clk_disable_unprepare(pdc_wdt
->sys_clk
);
318 static const struct of_device_id pdc_wdt_match
[] = {
319 { .compatible
= "img,pdc-wdt" },
322 MODULE_DEVICE_TABLE(of
, pdc_wdt_match
);
324 static struct platform_driver pdc_wdt_driver
= {
326 .name
= "imgpdc-wdt",
327 .of_match_table
= pdc_wdt_match
,
329 .probe
= pdc_wdt_probe
,
330 .remove
= pdc_wdt_remove
,
331 .shutdown
= pdc_wdt_shutdown
,
333 module_platform_driver(pdc_wdt_driver
);
335 MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
336 MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
337 MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
338 MODULE_LICENSE("GPL v2");