2 * Imagination Technologies PowerDown Controller Watchdog Timer.
4 * Copyright (c) 2014 Imagination Technologies Ltd.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * Based on drivers/watchdog/sunxi_wdt.c Copyright (c) 2013 Carlo Caione
11 * 2012 Henrik Nordstrom
14 #include <linux/clk.h>
16 #include <linux/log2.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/reboot.h>
20 #include <linux/slab.h>
21 #include <linux/watchdog.h>
24 #define PDC_WDT_SOFT_RESET 0x00
25 #define PDC_WDT_CONFIG 0x04
26 #define PDC_WDT_CONFIG_ENABLE BIT(31)
27 #define PDC_WDT_CONFIG_DELAY_MASK 0x1f
29 #define PDC_WDT_TICKLE1 0x08
30 #define PDC_WDT_TICKLE1_MAGIC 0xabcd1234
31 #define PDC_WDT_TICKLE2 0x0c
32 #define PDC_WDT_TICKLE2_MAGIC 0x4321dcba
34 #define PDC_WDT_TICKLE_STATUS_MASK 0x7
35 #define PDC_WDT_TICKLE_STATUS_SHIFT 0
36 #define PDC_WDT_TICKLE_STATUS_HRESET 0x0 /* Hard reset */
37 #define PDC_WDT_TICKLE_STATUS_TIMEOUT 0x1 /* Timeout */
38 #define PDC_WDT_TICKLE_STATUS_TICKLE 0x2 /* Tickled incorrectly */
39 #define PDC_WDT_TICKLE_STATUS_SRESET 0x3 /* Soft reset */
40 #define PDC_WDT_TICKLE_STATUS_USER 0x4 /* User reset */
42 /* Timeout values are in seconds */
43 #define PDC_WDT_MIN_TIMEOUT 1
44 #define PDC_WDT_DEF_TIMEOUT 64
47 module_param(heartbeat
, int, 0);
48 MODULE_PARM_DESC(heartbeat
, "Watchdog heartbeats in seconds "
49 "(default=" __MODULE_STRING(PDC_WDT_DEF_TIMEOUT
) ")");
51 static bool nowayout
= WATCHDOG_NOWAYOUT
;
52 module_param(nowayout
, bool, 0);
53 MODULE_PARM_DESC(nowayout
, "Watchdog cannot be stopped once started "
54 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT
) ")");
57 struct watchdog_device wdt_dev
;
61 struct notifier_block restart_handler
;
64 static int pdc_wdt_keepalive(struct watchdog_device
*wdt_dev
)
66 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
68 writel(PDC_WDT_TICKLE1_MAGIC
, wdt
->base
+ PDC_WDT_TICKLE1
);
69 writel(PDC_WDT_TICKLE2_MAGIC
, wdt
->base
+ PDC_WDT_TICKLE2
);
74 static int pdc_wdt_stop(struct watchdog_device
*wdt_dev
)
77 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
79 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
);
80 val
&= ~PDC_WDT_CONFIG_ENABLE
;
81 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
83 /* Must tickle to finish the stop */
84 pdc_wdt_keepalive(wdt_dev
);
89 static void __pdc_wdt_set_timeout(struct pdc_wdt_dev
*wdt
)
91 unsigned long clk_rate
= clk_get_rate(wdt
->wdt_clk
);
94 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
) & ~PDC_WDT_CONFIG_DELAY_MASK
;
95 val
|= order_base_2(wdt
->wdt_dev
.timeout
* clk_rate
) - 1;
96 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
99 static int pdc_wdt_set_timeout(struct watchdog_device
*wdt_dev
,
100 unsigned int new_timeout
)
102 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
104 wdt
->wdt_dev
.timeout
= new_timeout
;
106 __pdc_wdt_set_timeout(wdt
);
111 /* Start the watchdog timer (delay should already be set) */
112 static int pdc_wdt_start(struct watchdog_device
*wdt_dev
)
115 struct pdc_wdt_dev
*wdt
= watchdog_get_drvdata(wdt_dev
);
117 __pdc_wdt_set_timeout(wdt
);
119 val
= readl(wdt
->base
+ PDC_WDT_CONFIG
);
120 val
|= PDC_WDT_CONFIG_ENABLE
;
121 writel(val
, wdt
->base
+ PDC_WDT_CONFIG
);
126 static struct watchdog_info pdc_wdt_info
= {
127 .identity
= "IMG PDC Watchdog",
128 .options
= WDIOF_SETTIMEOUT
|
129 WDIOF_KEEPALIVEPING
|
133 static const struct watchdog_ops pdc_wdt_ops
= {
134 .owner
= THIS_MODULE
,
135 .start
= pdc_wdt_start
,
136 .stop
= pdc_wdt_stop
,
137 .ping
= pdc_wdt_keepalive
,
138 .set_timeout
= pdc_wdt_set_timeout
,
141 static int pdc_wdt_restart(struct notifier_block
*this, unsigned long mode
,
144 struct pdc_wdt_dev
*wdt
= container_of(this, struct pdc_wdt_dev
,
147 /* Assert SOFT_RESET */
148 writel(0x1, wdt
->base
+ PDC_WDT_SOFT_RESET
);
153 static int pdc_wdt_probe(struct platform_device
*pdev
)
157 unsigned long clk_rate
;
158 struct resource
*res
;
159 struct pdc_wdt_dev
*pdc_wdt
;
161 pdc_wdt
= devm_kzalloc(&pdev
->dev
, sizeof(*pdc_wdt
), GFP_KERNEL
);
165 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
166 pdc_wdt
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
167 if (IS_ERR(pdc_wdt
->base
))
168 return PTR_ERR(pdc_wdt
->base
);
170 pdc_wdt
->sys_clk
= devm_clk_get(&pdev
->dev
, "sys");
171 if (IS_ERR(pdc_wdt
->sys_clk
)) {
172 dev_err(&pdev
->dev
, "failed to get the sys clock\n");
173 return PTR_ERR(pdc_wdt
->sys_clk
);
176 pdc_wdt
->wdt_clk
= devm_clk_get(&pdev
->dev
, "wdt");
177 if (IS_ERR(pdc_wdt
->wdt_clk
)) {
178 dev_err(&pdev
->dev
, "failed to get the wdt clock\n");
179 return PTR_ERR(pdc_wdt
->wdt_clk
);
182 ret
= clk_prepare_enable(pdc_wdt
->sys_clk
);
184 dev_err(&pdev
->dev
, "could not prepare or enable sys clock\n");
188 ret
= clk_prepare_enable(pdc_wdt
->wdt_clk
);
190 dev_err(&pdev
->dev
, "could not prepare or enable wdt clock\n");
191 goto disable_sys_clk
;
194 /* We use the clock rate to calculate the max timeout */
195 clk_rate
= clk_get_rate(pdc_wdt
->wdt_clk
);
197 dev_err(&pdev
->dev
, "failed to get clock rate\n");
199 goto disable_wdt_clk
;
202 if (order_base_2(clk_rate
) > PDC_WDT_CONFIG_DELAY_MASK
+ 1) {
203 dev_err(&pdev
->dev
, "invalid clock rate\n");
205 goto disable_wdt_clk
;
208 if (order_base_2(clk_rate
) == 0)
209 pdc_wdt
->wdt_dev
.min_timeout
= PDC_WDT_MIN_TIMEOUT
+ 1;
211 pdc_wdt
->wdt_dev
.min_timeout
= PDC_WDT_MIN_TIMEOUT
;
213 pdc_wdt
->wdt_dev
.info
= &pdc_wdt_info
;
214 pdc_wdt
->wdt_dev
.ops
= &pdc_wdt_ops
;
216 div
= 1ULL << (PDC_WDT_CONFIG_DELAY_MASK
+ 1);
217 do_div(div
, clk_rate
);
218 pdc_wdt
->wdt_dev
.max_timeout
= div
;
219 pdc_wdt
->wdt_dev
.timeout
= PDC_WDT_DEF_TIMEOUT
;
220 pdc_wdt
->wdt_dev
.parent
= &pdev
->dev
;
221 watchdog_set_drvdata(&pdc_wdt
->wdt_dev
, pdc_wdt
);
223 watchdog_init_timeout(&pdc_wdt
->wdt_dev
, heartbeat
, &pdev
->dev
);
225 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
227 /* Find what caused the last reset */
228 val
= readl(pdc_wdt
->base
+ PDC_WDT_TICKLE1
);
229 val
= (val
& PDC_WDT_TICKLE_STATUS_MASK
) >> PDC_WDT_TICKLE_STATUS_SHIFT
;
231 case PDC_WDT_TICKLE_STATUS_TICKLE
:
232 case PDC_WDT_TICKLE_STATUS_TIMEOUT
:
233 pdc_wdt
->wdt_dev
.bootstatus
|= WDIOF_CARDRESET
;
235 "watchdog module last reset due to timeout\n");
237 case PDC_WDT_TICKLE_STATUS_HRESET
:
239 "watchdog module last reset due to hard reset\n");
241 case PDC_WDT_TICKLE_STATUS_SRESET
:
243 "watchdog module last reset due to soft reset\n");
245 case PDC_WDT_TICKLE_STATUS_USER
:
247 "watchdog module last reset due to user reset\n");
251 "contains an illegal status code (%08x)\n", val
);
255 watchdog_set_nowayout(&pdc_wdt
->wdt_dev
, nowayout
);
257 platform_set_drvdata(pdev
, pdc_wdt
);
259 ret
= watchdog_register_device(&pdc_wdt
->wdt_dev
);
261 goto disable_wdt_clk
;
263 pdc_wdt
->restart_handler
.notifier_call
= pdc_wdt_restart
;
264 pdc_wdt
->restart_handler
.priority
= 128;
265 ret
= register_restart_handler(&pdc_wdt
->restart_handler
);
267 dev_warn(&pdev
->dev
, "failed to register restart handler: %d\n",
273 clk_disable_unprepare(pdc_wdt
->wdt_clk
);
275 clk_disable_unprepare(pdc_wdt
->sys_clk
);
279 static void pdc_wdt_shutdown(struct platform_device
*pdev
)
281 struct pdc_wdt_dev
*pdc_wdt
= platform_get_drvdata(pdev
);
283 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
286 static int pdc_wdt_remove(struct platform_device
*pdev
)
288 struct pdc_wdt_dev
*pdc_wdt
= platform_get_drvdata(pdev
);
290 pdc_wdt_stop(&pdc_wdt
->wdt_dev
);
291 watchdog_unregister_device(&pdc_wdt
->wdt_dev
);
292 clk_disable_unprepare(pdc_wdt
->wdt_clk
);
293 clk_disable_unprepare(pdc_wdt
->sys_clk
);
298 static const struct of_device_id pdc_wdt_match
[] = {
299 { .compatible
= "img,pdc-wdt" },
302 MODULE_DEVICE_TABLE(of
, pdc_wdt_match
);
304 static struct platform_driver pdc_wdt_driver
= {
306 .name
= "imgpdc-wdt",
307 .of_match_table
= pdc_wdt_match
,
309 .probe
= pdc_wdt_probe
,
310 .remove
= pdc_wdt_remove
,
311 .shutdown
= pdc_wdt_shutdown
,
313 module_platform_driver(pdc_wdt_driver
);
315 MODULE_AUTHOR("Jude Abraham <Jude.Abraham@imgtec.com>");
316 MODULE_AUTHOR("Naidu Tellapati <Naidu.Tellapati@imgtec.com>");
317 MODULE_DESCRIPTION("Imagination Technologies PDC Watchdog Timer Driver");
318 MODULE_LICENSE("GPL v2");