drivers/watchdog/imx2_wdt.c

   1 /*
   2  * Watchdog driver for IMX2 and later processors
   3  *
   4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
   5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   6  *
   7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
   8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  15  *
  16  *                      MX1:            MX2+:
  17  *                      ----            -----
  18  * Registers:           32-bit          16-bit
  19  * Stopable timer:      Yes             No
  20  * Need to enable clk:  No              Yes
  21  * Halt on suspend:     Manual          Can be automatic
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/io.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/of_address.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regmap.h>
  35 #include <linux/timer.h>
  36 #include <linux/watchdog.h>
  37
  38 #define DRIVER_NAME "imx2-wdt"
  39
  40 #define IMX2_WDT_WCR            0x00            /* Control Register */
  41 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  42 #define IMX2_WDT_WCR_WRE        (1 << 3)        /* -> WDOG Reset Enable */
  43 #define IMX2_WDT_WCR_WDE        (1 << 2)        /* -> Watchdog Enable */
  44 #define IMX2_WDT_WCR_WDZST      (1 << 0)        /* -> Watchdog timer Suspend */
  45
  46 #define IMX2_WDT_WSR            0x02            /* Service Register */
  47 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  48 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  49
  50 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  51 #define IMX2_WDT_WRSR_TOUT      (1 << 1)        /* -> Reset due to Timeout */
  52
  53 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
  54
  55 #define IMX2_WDT_MAX_TIME       128
  56 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  57
  58 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  59
  60 struct imx2_wdt_device {
  61         struct clk *clk;
  62         struct regmap *regmap;
  63         struct timer_list timer;        /* Pings the watchdog when closed */
  64         struct watchdog_device wdog;
  65 };
  66
  67 static bool nowayout = WATCHDOG_NOWAYOUT;
  68 module_param(nowayout, bool, 0);
  69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  70                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  71
  72
  73 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
  74 module_param(timeout, uint, 0);
  75 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  76                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  77
  78 static const struct watchdog_info imx2_wdt_info = {
  79         .identity = "imx2+ watchdog",
  80         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  81 };
  82
  83 static int imx2_wdt_restart(struct watchdog_device *wdog)
  84 {
  85         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  86         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  87
  88         /* Assert SRS signal */
  89         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  90         /*
  91          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  92          * written twice), we add another two writes to ensure there must be at
  93          * least two writes happen in the same one 32kHz clock period.  We save
  94          * the target check here, since the writes shouldn't be a huge burden
  95          * for other platforms.
  96          */
  97         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  98         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  99
 100         /* wait for reset to assert... */
 101         mdelay(500);
 102
 103         return 0;
 104 }
 105
 106 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 107 {
 108         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 109         u32 val;
 110
 111         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 112
 113         /* Suspend timer in low power mode, write once-only */
 114         val |= IMX2_WDT_WCR_WDZST;
 115         /* Strip the old watchdog Time-Out value */
 116         val &= ~IMX2_WDT_WCR_WT;
 117         /* Generate reset if WDOG times out */
 118         val &= ~IMX2_WDT_WCR_WRE;
 119         /* Keep Watchdog Disabled */
 120         val &= ~IMX2_WDT_WCR_WDE;
 121         /* Set the watchdog's Time-Out value */
 122         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 123
 124         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 125
 126         /* enable the watchdog */
 127         val |= IMX2_WDT_WCR_WDE;
 128         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 129 }
 130
 131 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 132 {
 133         u32 val;
 134
 135         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 136
 137         return val & IMX2_WDT_WCR_WDE;
 138 }
 139
 140 static int imx2_wdt_ping(struct watchdog_device *wdog)
 141 {
 142         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 143
 144         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 145         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 146         return 0;
 147 }
 148
 149 static void imx2_wdt_timer_ping(unsigned long arg)
 150 {
 151         struct watchdog_device *wdog = (struct watchdog_device *)arg;
 152         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 153
 154         /* ping it every wdog->timeout / 2 seconds to prevent reboot */
 155         imx2_wdt_ping(wdog);
 156         mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
 157 }
 158
 159 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 160                                 unsigned int new_timeout)
 161 {
 162         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 163
 164         wdog->timeout = new_timeout;
 165
 166         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 167                            WDOG_SEC_TO_COUNT(new_timeout));
 168         return 0;
 169 }
 170
 171 static int imx2_wdt_start(struct watchdog_device *wdog)
 172 {
 173         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 174
 175         if (imx2_wdt_is_running(wdev)) {
 176                 /* delete the timer that pings the watchdog after close */
 177                 del_timer_sync(&wdev->timer);
 178                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 179         } else
 180                 imx2_wdt_setup(wdog);
 181
 182         return imx2_wdt_ping(wdog);
 183 }
 184
 185 static int imx2_wdt_stop(struct watchdog_device *wdog)
 186 {
 187         /*
 188          * We don't need a clk_disable, it cannot be disabled once started.
 189          * We use a timer to ping the watchdog while /dev/watchdog is closed
 190          */
 191         imx2_wdt_timer_ping((unsigned long)wdog);
 192         return 0;
 193 }
 194
 195 static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
 196 {
 197         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 198
 199         if (imx2_wdt_is_running(wdev)) {
 200                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 201                 imx2_wdt_timer_ping((unsigned long)wdog);
 202         }
 203 }
 204
 205 static const struct watchdog_ops imx2_wdt_ops = {
 206         .owner = THIS_MODULE,
 207         .start = imx2_wdt_start,
 208         .stop = imx2_wdt_stop,
 209         .ping = imx2_wdt_ping,
 210         .set_timeout = imx2_wdt_set_timeout,
 211         .restart = imx2_wdt_restart,
 212 };
 213
 214 static const struct regmap_config imx2_wdt_regmap_config = {
 215         .reg_bits = 16,
 216         .reg_stride = 2,
 217         .val_bits = 16,
 218         .max_register = 0x8,
 219 };
 220
 221 static int __init imx2_wdt_probe(struct platform_device *pdev)
 222 {
 223         struct imx2_wdt_device *wdev;
 224         struct watchdog_device *wdog;
 225         struct resource *res;
 226         void __iomem *base;
 227         int ret;
 228         u32 val;
 229
 230         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
 231         if (!wdev)
 232                 return -ENOMEM;
 233
 234         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 235         base = devm_ioremap_resource(&pdev->dev, res);
 236         if (IS_ERR(base))
 237                 return PTR_ERR(base);
 238
 239         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 240                                                  &imx2_wdt_regmap_config);
 241         if (IS_ERR(wdev->regmap)) {
 242                 dev_err(&pdev->dev, "regmap init failed\n");
 243                 return PTR_ERR(wdev->regmap);
 244         }
 245
 246         wdev->clk = devm_clk_get(&pdev->dev, NULL);
 247         if (IS_ERR(wdev->clk)) {
 248                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
 249                 return PTR_ERR(wdev->clk);
 250         }
 251
 252         wdog                    = &wdev->wdog;
 253         wdog->info              = &imx2_wdt_info;
 254         wdog->ops               = &imx2_wdt_ops;
 255         wdog->min_timeout       = 1;
 256         wdog->max_timeout       = IMX2_WDT_MAX_TIME;
 257         wdog->parent            = &pdev->dev;
 258
 259         ret = clk_prepare_enable(wdev->clk);
 260         if (ret)
 261                 return ret;
 262
 263         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 264         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 265
 266         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
 267         if (wdog->timeout != timeout)
 268                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
 269                          timeout, wdog->timeout);
 270
 271         platform_set_drvdata(pdev, wdog);
 272         watchdog_set_drvdata(wdog, wdev);
 273         watchdog_set_nowayout(wdog, nowayout);
 274         watchdog_set_restart_priority(wdog, 128);
 275         watchdog_init_timeout(wdog, timeout, &pdev->dev);
 276
 277         setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
 278
 279         imx2_wdt_ping_if_active(wdog);
 280
 281         /*
 282          * Disable the watchdog power down counter at boot. Otherwise the power
 283          * down counter will pull down the #WDOG interrupt line for one clock
 284          * cycle.
 285          */
 286         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 287
 288         ret = watchdog_register_device(wdog);
 289         if (ret) {
 290                 dev_err(&pdev->dev, "cannot register watchdog device\n");
 291                 goto disable_clk;
 292         }
 293
 294         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
 295                  wdog->timeout, nowayout);
 296
 297         return 0;
 298
 299 disable_clk:
 300         clk_disable_unprepare(wdev->clk);
 301         return ret;
 302 }
 303
 304 static int __exit imx2_wdt_remove(struct platform_device *pdev)
 305 {
 306         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 307         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 308
 309         watchdog_unregister_device(wdog);
 310
 311         if (imx2_wdt_is_running(wdev)) {
 312                 del_timer_sync(&wdev->timer);
 313                 imx2_wdt_ping(wdog);
 314                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
 315         }
 316         return 0;
 317 }
 318
 319 static void imx2_wdt_shutdown(struct platform_device *pdev)
 320 {
 321         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 322         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 323
 324         if (imx2_wdt_is_running(wdev)) {
 325                 /*
 326                  * We are running, we need to delete the timer but will
 327                  * give max timeout before reboot will take place
 328                  */
 329                 del_timer_sync(&wdev->timer);
 330                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 331                 imx2_wdt_ping(wdog);
 332                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 333         }
 334 }
 335
 336 #ifdef CONFIG_PM_SLEEP
 337 /* Disable watchdog if it is active or non-active but still running */
 338 static int imx2_wdt_suspend(struct device *dev)
 339 {
 340         struct watchdog_device *wdog = dev_get_drvdata(dev);
 341         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 342
 343         /* The watchdog IP block is running */
 344         if (imx2_wdt_is_running(wdev)) {
 345                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 346                 imx2_wdt_ping(wdog);
 347
 348                 /* The watchdog is not active */
 349                 if (!watchdog_active(wdog))
 350                         del_timer_sync(&wdev->timer);
 351         }
 352
 353         clk_disable_unprepare(wdev->clk);
 354
 355         return 0;
 356 }
 357
 358 /* Enable watchdog and configure it if necessary */
 359 static int imx2_wdt_resume(struct device *dev)
 360 {
 361         struct watchdog_device *wdog = dev_get_drvdata(dev);
 362         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 363         int ret;
 364
 365         ret = clk_prepare_enable(wdev->clk);
 366         if (ret)
 367                 return ret;
 368
 369         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 370                 /*
 371                  * If the watchdog is still active and resumes
 372                  * from deep sleep state, need to restart the
 373                  * watchdog again.
 374                  */
 375                 imx2_wdt_setup(wdog);
 376                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 377                 imx2_wdt_ping(wdog);
 378         } else if (imx2_wdt_is_running(wdev)) {
 379                 /* Resuming from non-deep sleep state. */
 380                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 381                 imx2_wdt_ping(wdog);
 382                 /*
 383                  * But the watchdog is not active, then start
 384                  * the timer again.
 385                  */
 386                 if (!watchdog_active(wdog))
 387                         mod_timer(&wdev->timer,
 388                                   jiffies + wdog->timeout * HZ / 2);
 389         }
 390
 391         return 0;
 392 }
 393 #endif
 394
 395 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 396                          imx2_wdt_resume);
 397
 398 static const struct of_device_id imx2_wdt_dt_ids[] = {
 399         { .compatible = "fsl,imx21-wdt", },
 400         { /* sentinel */ }
 401 };
 402 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 403
 404 static struct platform_driver imx2_wdt_driver = {
 405         .remove         = __exit_p(imx2_wdt_remove),
 406         .shutdown       = imx2_wdt_shutdown,
 407         .driver         = {
 408                 .name   = DRIVER_NAME,
 409                 .pm     = &imx2_wdt_pm_ops,
 410                 .of_match_table = imx2_wdt_dt_ids,
 411         },
 412 };
 413
 414 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 415
 416 MODULE_AUTHOR("Wolfram Sang");
 417 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 418 MODULE_LICENSE("GPL v2");
 419 MODULE_ALIAS("platform:" DRIVER_NAME);