drivers/watchdog/imx2_wdt.c

   1 /*
   2  * Watchdog driver for IMX2 and later processors
   3  *
   4  *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
   5  *  Copyright (C) 2014 Freescale Semiconductor, Inc.
   6  *
   7  * some parts adapted by similar drivers from Darius Augulis and Vladimir
   8  * Zapolskiy, additional improvements by Wim Van Sebroeck.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
  15  *
  16  *                      MX1:            MX2+:
  17  *                      ----            -----
  18  * Registers:           32-bit          16-bit
  19  * Stopable timer:      Yes             No
  20  * Need to enable clk:  No              Yes
  21  * Halt on suspend:     Manual          Can be automatic
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/io.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/of_address.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regmap.h>
  35 #include <linux/timer.h>
  36 #include <linux/watchdog.h>
  37
  38 #define DRIVER_NAME "imx2-wdt"
  39
  40 #define IMX2_WDT_WCR            0x00            /* Control Register */
  41 #define IMX2_WDT_WCR_WT         (0xFF << 8)     /* -> Watchdog Timeout Field */
  42 #define IMX2_WDT_WCR_WRE        (1 << 3)        /* -> WDOG Reset Enable */
  43 #define IMX2_WDT_WCR_WDE        (1 << 2)        /* -> Watchdog Enable */
  44 #define IMX2_WDT_WCR_WDZST      (1 << 0)        /* -> Watchdog timer Suspend */
  45
  46 #define IMX2_WDT_WSR            0x02            /* Service Register */
  47 #define IMX2_WDT_SEQ1           0x5555          /* -> service sequence 1 */
  48 #define IMX2_WDT_SEQ2           0xAAAA          /* -> service sequence 2 */
  49
  50 #define IMX2_WDT_WRSR           0x04            /* Reset Status Register */
  51 #define IMX2_WDT_WRSR_TOUT      (1 << 1)        /* -> Reset due to Timeout */
  52
  53 #define IMX2_WDT_WMCR           0x08            /* Misc Register */
  54
  55 #define IMX2_WDT_MAX_TIME       128
  56 #define IMX2_WDT_DEFAULT_TIME   60              /* in seconds */
  57
  58 #define WDOG_SEC_TO_COUNT(s)    ((s * 2 - 1) << 8)
  59
  60 struct imx2_wdt_device {
  61         struct clk *clk;
  62         struct regmap *regmap;
  63         struct timer_list timer;        /* Pings the watchdog when closed */
  64         struct watchdog_device wdog;
  65 };
  66
  67 static bool nowayout = WATCHDOG_NOWAYOUT;
  68 module_param(nowayout, bool, 0);
  69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  70                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  71
  72
  73 static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
  74 module_param(timeout, uint, 0);
  75 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
  76                                 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
  77
  78 static const struct watchdog_info imx2_wdt_info = {
  79         .identity = "imx2+ watchdog",
  80         .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
  81 };
  82
  83 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
  84                             void *data)
  85 {
  86         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
  87         unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
  88
  89         /* Assert SRS signal */
  90         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  91         /*
  92          * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
  93          * written twice), we add another two writes to ensure there must be at
  94          * least two writes happen in the same one 32kHz clock period.  We save
  95          * the target check here, since the writes shouldn't be a huge burden
  96          * for other platforms.
  97          */
  98         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
  99         regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
 100
 101         /* wait for reset to assert... */
 102         mdelay(500);
 103
 104         return 0;
 105 }
 106
 107 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
 108 {
 109         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 110         u32 val;
 111
 112         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 113
 114         /* Suspend timer in low power mode, write once-only */
 115         val |= IMX2_WDT_WCR_WDZST;
 116         /* Strip the old watchdog Time-Out value */
 117         val &= ~IMX2_WDT_WCR_WT;
 118         /* Generate reset if WDOG times out */
 119         val &= ~IMX2_WDT_WCR_WRE;
 120         /* Keep Watchdog Disabled */
 121         val &= ~IMX2_WDT_WCR_WDE;
 122         /* Set the watchdog's Time-Out value */
 123         val |= WDOG_SEC_TO_COUNT(wdog->timeout);
 124
 125         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 126
 127         /* enable the watchdog */
 128         val |= IMX2_WDT_WCR_WDE;
 129         regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
 130 }
 131
 132 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
 133 {
 134         u32 val;
 135
 136         regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
 137
 138         return val & IMX2_WDT_WCR_WDE;
 139 }
 140
 141 static int imx2_wdt_ping(struct watchdog_device *wdog)
 142 {
 143         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 144
 145         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
 146         regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
 147         return 0;
 148 }
 149
 150 static void imx2_wdt_timer_ping(unsigned long arg)
 151 {
 152         struct watchdog_device *wdog = (struct watchdog_device *)arg;
 153         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 154
 155         /* ping it every wdog->timeout / 2 seconds to prevent reboot */
 156         imx2_wdt_ping(wdog);
 157         mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
 158 }
 159
 160 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
 161                                 unsigned int new_timeout)
 162 {
 163         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 164
 165         wdog->timeout = new_timeout;
 166
 167         regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
 168                            WDOG_SEC_TO_COUNT(new_timeout));
 169         return 0;
 170 }
 171
 172 static int imx2_wdt_start(struct watchdog_device *wdog)
 173 {
 174         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 175
 176         if (imx2_wdt_is_running(wdev)) {
 177                 /* delete the timer that pings the watchdog after close */
 178                 del_timer_sync(&wdev->timer);
 179                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 180         } else
 181                 imx2_wdt_setup(wdog);
 182
 183         return imx2_wdt_ping(wdog);
 184 }
 185
 186 static int imx2_wdt_stop(struct watchdog_device *wdog)
 187 {
 188         /*
 189          * We don't need a clk_disable, it cannot be disabled once started.
 190          * We use a timer to ping the watchdog while /dev/watchdog is closed
 191          */
 192         imx2_wdt_timer_ping((unsigned long)wdog);
 193         return 0;
 194 }
 195
 196 static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
 197 {
 198         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 199
 200         if (imx2_wdt_is_running(wdev)) {
 201                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 202                 imx2_wdt_timer_ping((unsigned long)wdog);
 203         }
 204 }
 205
 206 static const struct watchdog_ops imx2_wdt_ops = {
 207         .owner = THIS_MODULE,
 208         .start = imx2_wdt_start,
 209         .stop = imx2_wdt_stop,
 210         .ping = imx2_wdt_ping,
 211         .set_timeout = imx2_wdt_set_timeout,
 212         .restart = imx2_wdt_restart,
 213 };
 214
 215 static const struct regmap_config imx2_wdt_regmap_config = {
 216         .reg_bits = 16,
 217         .reg_stride = 2,
 218         .val_bits = 16,
 219         .max_register = 0x8,
 220 };
 221
 222 static int __init imx2_wdt_probe(struct platform_device *pdev)
 223 {
 224         struct imx2_wdt_device *wdev;
 225         struct watchdog_device *wdog;
 226         struct resource *res;
 227         void __iomem *base;
 228         int ret;
 229         u32 val;
 230
 231         wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
 232         if (!wdev)
 233                 return -ENOMEM;
 234
 235         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 236         base = devm_ioremap_resource(&pdev->dev, res);
 237         if (IS_ERR(base))
 238                 return PTR_ERR(base);
 239
 240         wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 241                                                  &imx2_wdt_regmap_config);
 242         if (IS_ERR(wdev->regmap)) {
 243                 dev_err(&pdev->dev, "regmap init failed\n");
 244                 return PTR_ERR(wdev->regmap);
 245         }
 246
 247         wdev->clk = devm_clk_get(&pdev->dev, NULL);
 248         if (IS_ERR(wdev->clk)) {
 249                 dev_err(&pdev->dev, "can't get Watchdog clock\n");
 250                 return PTR_ERR(wdev->clk);
 251         }
 252
 253         wdog                    = &wdev->wdog;
 254         wdog->info              = &imx2_wdt_info;
 255         wdog->ops               = &imx2_wdt_ops;
 256         wdog->min_timeout       = 1;
 257         wdog->max_timeout       = IMX2_WDT_MAX_TIME;
 258         wdog->parent            = &pdev->dev;
 259
 260         ret = clk_prepare_enable(wdev->clk);
 261         if (ret)
 262                 return ret;
 263
 264         regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
 265         wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
 266
 267         wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
 268         if (wdog->timeout != timeout)
 269                 dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
 270                          timeout, wdog->timeout);
 271
 272         platform_set_drvdata(pdev, wdog);
 273         watchdog_set_drvdata(wdog, wdev);
 274         watchdog_set_nowayout(wdog, nowayout);
 275         watchdog_set_restart_priority(wdog, 128);
 276         watchdog_init_timeout(wdog, timeout, &pdev->dev);
 277
 278         setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
 279
 280         imx2_wdt_ping_if_active(wdog);
 281
 282         /*
 283          * Disable the watchdog power down counter at boot. Otherwise the power
 284          * down counter will pull down the #WDOG interrupt line for one clock
 285          * cycle.
 286          */
 287         regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
 288
 289         ret = watchdog_register_device(wdog);
 290         if (ret) {
 291                 dev_err(&pdev->dev, "cannot register watchdog device\n");
 292                 goto disable_clk;
 293         }
 294
 295         dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
 296                  wdog->timeout, nowayout);
 297
 298         return 0;
 299
 300 disable_clk:
 301         clk_disable_unprepare(wdev->clk);
 302         return ret;
 303 }
 304
 305 static int __exit imx2_wdt_remove(struct platform_device *pdev)
 306 {
 307         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 308         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 309
 310         watchdog_unregister_device(wdog);
 311
 312         if (imx2_wdt_is_running(wdev)) {
 313                 del_timer_sync(&wdev->timer);
 314                 imx2_wdt_ping(wdog);
 315                 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
 316         }
 317         return 0;
 318 }
 319
 320 static void imx2_wdt_shutdown(struct platform_device *pdev)
 321 {
 322         struct watchdog_device *wdog = platform_get_drvdata(pdev);
 323         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 324
 325         if (imx2_wdt_is_running(wdev)) {
 326                 /*
 327                  * We are running, we need to delete the timer but will
 328                  * give max timeout before reboot will take place
 329                  */
 330                 del_timer_sync(&wdev->timer);
 331                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 332                 imx2_wdt_ping(wdog);
 333                 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
 334         }
 335 }
 336
 337 #ifdef CONFIG_PM_SLEEP
 338 /* Disable watchdog if it is active or non-active but still running */
 339 static int imx2_wdt_suspend(struct device *dev)
 340 {
 341         struct watchdog_device *wdog = dev_get_drvdata(dev);
 342         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 343
 344         /* The watchdog IP block is running */
 345         if (imx2_wdt_is_running(wdev)) {
 346                 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
 347                 imx2_wdt_ping(wdog);
 348
 349                 /* The watchdog is not active */
 350                 if (!watchdog_active(wdog))
 351                         del_timer_sync(&wdev->timer);
 352         }
 353
 354         clk_disable_unprepare(wdev->clk);
 355
 356         return 0;
 357 }
 358
 359 /* Enable watchdog and configure it if necessary */
 360 static int imx2_wdt_resume(struct device *dev)
 361 {
 362         struct watchdog_device *wdog = dev_get_drvdata(dev);
 363         struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
 364         int ret;
 365
 366         ret = clk_prepare_enable(wdev->clk);
 367         if (ret)
 368                 return ret;
 369
 370         if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
 371                 /*
 372                  * If the watchdog is still active and resumes
 373                  * from deep sleep state, need to restart the
 374                  * watchdog again.
 375                  */
 376                 imx2_wdt_setup(wdog);
 377                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 378                 imx2_wdt_ping(wdog);
 379         } else if (imx2_wdt_is_running(wdev)) {
 380                 /* Resuming from non-deep sleep state. */
 381                 imx2_wdt_set_timeout(wdog, wdog->timeout);
 382                 imx2_wdt_ping(wdog);
 383                 /*
 384                  * But the watchdog is not active, then start
 385                  * the timer again.
 386                  */
 387                 if (!watchdog_active(wdog))
 388                         mod_timer(&wdev->timer,
 389                                   jiffies + wdog->timeout * HZ / 2);
 390         }
 391
 392         return 0;
 393 }
 394 #endif
 395
 396 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
 397                          imx2_wdt_resume);
 398
 399 static const struct of_device_id imx2_wdt_dt_ids[] = {
 400         { .compatible = "fsl,imx21-wdt", },
 401         { /* sentinel */ }
 402 };
 403 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
 404
 405 static struct platform_driver imx2_wdt_driver = {
 406         .remove         = __exit_p(imx2_wdt_remove),
 407         .shutdown       = imx2_wdt_shutdown,
 408         .driver         = {
 409                 .name   = DRIVER_NAME,
 410                 .pm     = &imx2_wdt_pm_ops,
 411                 .of_match_table = imx2_wdt_dt_ids,
 412         },
 413 };
 414
 415 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
 416
 417 MODULE_AUTHOR("Wolfram Sang");
 418 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
 419 MODULE_LICENSE("GPL v2");
 420 MODULE_ALIAS("platform:" DRIVER_NAME);