drivers/watchdog/of_xilinx_wdt.c

   1 /*
   2  * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt
   3  *
   4  * (C) Copyright 2013 - 2014 Xilinx, Inc.
   5  * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>)
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/module.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ioport.h>
  18 #include <linux/watchdog.h>
  19 #include <linux/io.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_address.h>
  23
  24 /* Register offsets for the Wdt device */
  25 #define XWT_TWCSR0_OFFSET   0x0 /* Control/Status Register0 */
  26 #define XWT_TWCSR1_OFFSET   0x4 /* Control/Status Register1 */
  27 #define XWT_TBR_OFFSET      0x8 /* Timebase Register Offset */
  28
  29 /* Control/Status Register Masks  */
  30 #define XWT_CSR0_WRS_MASK   0x00000008 /* Reset status */
  31 #define XWT_CSR0_WDS_MASK   0x00000004 /* Timer state  */
  32 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */
  33
  34 /* Control/Status Register 0/1 bits  */
  35 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */
  36
  37 /* SelfTest constants */
  38 #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000
  39 #define XWT_TIMER_FAILED            0xFFFFFFFF
  40
  41 #define WATCHDOG_NAME     "Xilinx Watchdog"
  42
  43 struct xwdt_device {
  44         void __iomem *base;
  45         u32 wdt_interval;
  46         spinlock_t spinlock;
  47         struct watchdog_device xilinx_wdt_wdd;
  48 };
  49
  50 static int xilinx_wdt_start(struct watchdog_device *wdd)
  51 {
  52         u32 control_status_reg;
  53         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  54
  55         spin_lock(&xdev->spinlock);
  56
  57         /* Clean previous status and enable the watchdog timer */
  58         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  59         control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
  60
  61         iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK),
  62                   xdev->base + XWT_TWCSR0_OFFSET);
  63
  64         iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET);
  65
  66         spin_unlock(&xdev->spinlock);
  67
  68         return 0;
  69 }
  70
  71 static int xilinx_wdt_stop(struct watchdog_device *wdd)
  72 {
  73         u32 control_status_reg;
  74         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  75
  76         spin_lock(&xdev->spinlock);
  77
  78         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  79
  80         iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK),
  81                   xdev->base + XWT_TWCSR0_OFFSET);
  82
  83         iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET);
  84
  85         spin_unlock(&xdev->spinlock);
  86         pr_info("Stopped!\n");
  87
  88         return 0;
  89 }
  90
  91 static int xilinx_wdt_keepalive(struct watchdog_device *wdd)
  92 {
  93         u32 control_status_reg;
  94         struct xwdt_device *xdev = watchdog_get_drvdata(wdd);
  95
  96         spin_lock(&xdev->spinlock);
  97
  98         control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET);
  99         control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK);
 100         iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET);
 101
 102         spin_unlock(&xdev->spinlock);
 103
 104         return 0;
 105 }
 106
 107 static const struct watchdog_info xilinx_wdt_ident = {
 108         .options =  WDIOF_MAGICCLOSE |
 109                     WDIOF_KEEPALIVEPING,
 110         .firmware_version =     1,
 111         .identity =     WATCHDOG_NAME,
 112 };
 113
 114 static const struct watchdog_ops xilinx_wdt_ops = {
 115         .owner = THIS_MODULE,
 116         .start = xilinx_wdt_start,
 117         .stop = xilinx_wdt_stop,
 118         .ping = xilinx_wdt_keepalive,
 119 };
 120
 121 static u32 xwdt_selftest(struct xwdt_device *xdev)
 122 {
 123         int i;
 124         u32 timer_value1;
 125         u32 timer_value2;
 126
 127         spin_lock(&xdev->spinlock);
 128
 129         timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET);
 130         timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
 131
 132         for (i = 0;
 133                 ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) &&
 134                         (timer_value2 == timer_value1)); i++) {
 135                 timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET);
 136         }
 137
 138         spin_unlock(&xdev->spinlock);
 139
 140         if (timer_value2 != timer_value1)
 141                 return ~XWT_TIMER_FAILED;
 142         else
 143                 return XWT_TIMER_FAILED;
 144 }
 145
 146 static int xwdt_probe(struct platform_device *pdev)
 147 {
 148         int rc;
 149         u32 pfreq, enable_once = 0;
 150         struct resource *res;
 151         struct xwdt_device *xdev;
 152         bool no_timeout = false;
 153         struct watchdog_device *xilinx_wdt_wdd;
 154
 155         xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
 156         if (!xdev)
 157                 return -ENOMEM;
 158
 159         xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd;
 160         xilinx_wdt_wdd->info = &xilinx_wdt_ident;
 161         xilinx_wdt_wdd->ops = &xilinx_wdt_ops;
 162         xilinx_wdt_wdd->parent = &pdev->dev;
 163
 164         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 165         xdev->base = devm_ioremap_resource(&pdev->dev, res);
 166         if (IS_ERR(xdev->base))
 167                 return PTR_ERR(xdev->base);
 168
 169         rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq);
 170         if (rc) {
 171                 dev_warn(&pdev->dev,
 172                          "The watchdog clock frequency cannot be obtained\n");
 173                 no_timeout = true;
 174         }
 175
 176         rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval",
 177                                   &xdev->wdt_interval);
 178         if (rc) {
 179                 dev_warn(&pdev->dev,
 180                          "Parameter \"xlnx,wdt-interval\" not found\n");
 181                 no_timeout = true;
 182         }
 183
 184         rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once",
 185                                   &enable_once);
 186         if (rc)
 187                 dev_warn(&pdev->dev,
 188                          "Parameter \"xlnx,wdt-enable-once\" not found\n");
 189
 190         watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
 191
 192 /*
 193  *  Twice of the 2^wdt_interval / freq  because the first wdt overflow is
 194  *  ignored (interrupt), reset is only generated at second wdt overflow
 195  */
 196         if (!no_timeout)
 197                 xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) /
 198                                           pfreq);
 199
 200         spin_lock_init(&xdev->spinlock);
 201         watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
 202
 203         rc = xwdt_selftest(xdev);
 204         if (rc == XWT_TIMER_FAILED) {
 205                 dev_err(&pdev->dev, "SelfTest routine error\n");
 206                 return rc;
 207         }
 208
 209         rc = watchdog_register_device(xilinx_wdt_wdd);
 210         if (rc) {
 211                 dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc);
 212                 return rc;
 213         }
 214
 215         dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n",
 216                  xdev->base, xilinx_wdt_wdd->timeout);
 217
 218         platform_set_drvdata(pdev, xdev);
 219
 220         return 0;
 221 }
 222
 223 static int xwdt_remove(struct platform_device *pdev)
 224 {
 225         struct xwdt_device *xdev = platform_get_drvdata(pdev);
 226
 227         watchdog_unregister_device(&xdev->xilinx_wdt_wdd);
 228
 229         return 0;
 230 }
 231
 232 /* Match table for of_platform binding */
 233 static struct of_device_id xwdt_of_match[] = {
 234         { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
 235         { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
 236         {},
 237 };
 238 MODULE_DEVICE_TABLE(of, xwdt_of_match);
 239
 240 static struct platform_driver xwdt_driver = {
 241         .probe       = xwdt_probe,
 242         .remove      = xwdt_remove,
 243         .driver = {
 244                 .owner = THIS_MODULE,
 245                 .name  = WATCHDOG_NAME,
 246                 .of_match_table = xwdt_of_match,
 247         },
 248 };
 249
 250 module_platform_driver(xwdt_driver);
 251
 252 MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>");
 253 MODULE_DESCRIPTION("Xilinx Watchdog driver");
 254 MODULE_LICENSE("GPL v2");