drivers/watchdog/pnx4008_wdt.c

   1 /*
   2  * drivers/char/watchdog/pnx4008_wdt.c
   3  *
   4  * Watchdog driver for PNX4008 board
   5  *
   6  * Authors: Dmitry Chigirev <source@mvista.com>,
   7  *          Vitaly Wool <vitalywool@gmail.com>
   8  * Based on sa1100 driver,
   9  * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
  10  *
  11  * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
  12  * the terms of the GNU General Public License version 2. This program
  13  * is licensed "as is" without any warranty of any kind, whether express
  14  * or implied.
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/types.h>
  22 #include <linux/kernel.h>
  23 #include <linux/fs.h>
  24 #include <linux/miscdevice.h>
  25 #include <linux/watchdog.h>
  26 #include <linux/init.h>
  27 #include <linux/bitops.h>
  28 #include <linux/ioport.h>
  29 #include <linux/device.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/clk.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/uaccess.h>
  34 #include <linux/io.h>
  35 #include <linux/slab.h>
  36 #include <mach/hardware.h>
  37
  38 #define MODULE_NAME "PNX4008-WDT: "
  39
  40 /* WatchDog Timer - Chapter 23 Page 207 */
  41
  42 #define DEFAULT_HEARTBEAT 19
  43 #define MAX_HEARTBEAT     60
  44
  45 /* Watchdog timer register set definition */
  46 #define WDTIM_INT(p)     ((p) + 0x0)
  47 #define WDTIM_CTRL(p)    ((p) + 0x4)
  48 #define WDTIM_COUNTER(p) ((p) + 0x8)
  49 #define WDTIM_MCTRL(p)   ((p) + 0xC)
  50 #define WDTIM_MATCH0(p)  ((p) + 0x10)
  51 #define WDTIM_EMR(p)     ((p) + 0x14)
  52 #define WDTIM_PULSE(p)   ((p) + 0x18)
  53 #define WDTIM_RES(p)     ((p) + 0x1C)
  54
  55 /* WDTIM_INT bit definitions */
  56 #define MATCH_INT      1
  57
  58 /* WDTIM_CTRL bit definitions */
  59 #define COUNT_ENAB     1
  60 #define RESET_COUNT    (1 << 1)
  61 #define DEBUG_EN       (1 << 2)
  62
  63 /* WDTIM_MCTRL bit definitions */
  64 #define MR0_INT        1
  65 #undef  RESET_COUNT0
  66 #define RESET_COUNT0   (1 << 2)
  67 #define STOP_COUNT0    (1 << 2)
  68 #define M_RES1         (1 << 3)
  69 #define M_RES2         (1 << 4)
  70 #define RESFRC1        (1 << 5)
  71 #define RESFRC2        (1 << 6)
  72
  73 /* WDTIM_EMR bit definitions */
  74 #define EXT_MATCH0      1
  75 #define MATCH_OUTPUT_HIGH (2 << 4)      /*a MATCH_CTRL setting */
  76
  77 /* WDTIM_RES bit definitions */
  78 #define WDOG_RESET      1       /* read only */
  79
  80 #define WDOG_COUNTER_RATE 13000000      /*the counter clock is 13 MHz fixed */
  81
  82 static bool nowayout = WATCHDOG_NOWAYOUT;
  83 static int heartbeat = DEFAULT_HEARTBEAT;
  84
  85 static DEFINE_SPINLOCK(io_lock);
  86 static unsigned long wdt_status;
  87 #define WDT_IN_USE        0
  88 #define WDT_OK_TO_CLOSE   1
  89
  90 static unsigned long boot_status;
  91
  92 static void __iomem     *wdt_base;
  93 struct clk              *wdt_clk;
  94
  95 static void wdt_enable(void)
  96 {
  97         spin_lock(&io_lock);
  98
  99         /* stop counter, initiate counter reset */
 100         writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
 101         /*wait for reset to complete. 100% guarantee event */
 102         while (readl(WDTIM_COUNTER(wdt_base)))
 103                 cpu_relax();
 104         /* internal and external reset, stop after that */
 105         writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base));
 106         /* configure match output */
 107         writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
 108         /* clear interrupt, just in case */
 109         writel(MATCH_INT, WDTIM_INT(wdt_base));
 110         /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
 111         writel(0xFFFF, WDTIM_PULSE(wdt_base));
 112         writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
 113         /*enable counter, stop when debugger active */
 114         writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));
 115
 116         spin_unlock(&io_lock);
 117 }
 118
 119 static void wdt_disable(void)
 120 {
 121         spin_lock(&io_lock);
 122
 123         writel(0, WDTIM_CTRL(wdt_base));        /*stop counter */
 124
 125         spin_unlock(&io_lock);
 126 }
 127
 128 static int pnx4008_wdt_open(struct inode *inode, struct file *file)
 129 {
 130         int ret;
 131
 132         if (test_and_set_bit(WDT_IN_USE, &wdt_status))
 133                 return -EBUSY;
 134
 135         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 136
 137         ret = clk_enable(wdt_clk);
 138         if (ret) {
 139                 clear_bit(WDT_IN_USE, &wdt_status);
 140                 return ret;
 141         }
 142
 143         wdt_enable();
 144
 145         return nonseekable_open(inode, file);
 146 }
 147
 148 static ssize_t pnx4008_wdt_write(struct file *file, const char *data,
 149                                         size_t len, loff_t *ppos)
 150 {
 151         if (len) {
 152                 if (!nowayout) {
 153                         size_t i;
 154
 155                         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 156
 157                         for (i = 0; i != len; i++) {
 158                                 char c;
 159
 160                                 if (get_user(c, data + i))
 161                                         return -EFAULT;
 162                                 if (c == 'V')
 163                                         set_bit(WDT_OK_TO_CLOSE, &wdt_status);
 164                         }
 165                 }
 166                 wdt_enable();
 167         }
 168
 169         return len;
 170 }
 171
 172 static const struct watchdog_info ident = {
 173         .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
 174             WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
 175         .identity = "PNX4008 Watchdog",
 176 };
 177
 178 static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
 179                                 unsigned long arg)
 180 {
 181         int ret = -ENOTTY;
 182         int time;
 183
 184         switch (cmd) {
 185         case WDIOC_GETSUPPORT:
 186                 ret = copy_to_user((struct watchdog_info *)arg, &ident,
 187                                    sizeof(ident)) ? -EFAULT : 0;
 188                 break;
 189
 190         case WDIOC_GETSTATUS:
 191                 ret = put_user(0, (int *)arg);
 192                 break;
 193
 194         case WDIOC_GETBOOTSTATUS:
 195                 ret = put_user(boot_status, (int *)arg);
 196                 break;
 197
 198         case WDIOC_KEEPALIVE:
 199                 wdt_enable();
 200                 ret = 0;
 201                 break;
 202
 203         case WDIOC_SETTIMEOUT:
 204                 ret = get_user(time, (int *)arg);
 205                 if (ret)
 206                         break;
 207
 208                 if (time <= 0 || time > MAX_HEARTBEAT) {
 209                         ret = -EINVAL;
 210                         break;
 211                 }
 212
 213                 heartbeat = time;
 214                 wdt_enable();
 215                 /* Fall through */
 216
 217         case WDIOC_GETTIMEOUT:
 218                 ret = put_user(heartbeat, (int *)arg);
 219                 break;
 220         }
 221         return ret;
 222 }
 223
 224 static int pnx4008_wdt_release(struct inode *inode, struct file *file)
 225 {
 226         if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
 227                 pr_warn("Device closed unexpectedly\n");
 228
 229         wdt_disable();
 230         clk_disable(wdt_clk);
 231         clear_bit(WDT_IN_USE, &wdt_status);
 232         clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
 233
 234         return 0;
 235 }
 236
 237 static const struct file_operations pnx4008_wdt_fops = {
 238         .owner = THIS_MODULE,
 239         .llseek = no_llseek,
 240         .write = pnx4008_wdt_write,
 241         .unlocked_ioctl = pnx4008_wdt_ioctl,
 242         .open = pnx4008_wdt_open,
 243         .release = pnx4008_wdt_release,
 244 };
 245
 246 static struct miscdevice pnx4008_wdt_miscdev = {
 247         .minor = WATCHDOG_MINOR,
 248         .name = "watchdog",
 249         .fops = &pnx4008_wdt_fops,
 250 };
 251
 252 static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
 253 {
 254         struct resource *r;
 255         int ret = 0;
 256
 257         if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
 258                 heartbeat = DEFAULT_HEARTBEAT;
 259
 260         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 261         wdt_base = devm_request_and_ioremap(&pdev->dev, r);
 262         if (!wdt_base)
 263                 return -EADDRINUSE;
 264
 265         wdt_clk = clk_get(&pdev->dev, NULL);
 266         if (IS_ERR(wdt_clk))
 267                 return PTR_ERR(wdt_clk);
 268
 269         ret = clk_enable(wdt_clk);
 270         if (ret)
 271                 goto out;
 272
 273         boot_status = (readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
 274                         WDIOF_CARDRESET : 0;
 275         wdt_disable();          /*disable for now */
 276         clk_disable(wdt_clk);
 277
 278         ret = misc_register(&pnx4008_wdt_miscdev);
 279         if (ret < 0) {
 280                 dev_err(&pdev->dev, "cannot register misc device\n");
 281                 goto out;
 282         }
 283
 284         dev_info(&pdev->dev, "PNX4008 Watchdog Timer: heartbeat %d sec\n",
 285                         heartbeat);
 286
 287         return 0;
 288
 289 out:
 290         clk_put(wdt_clk);
 291         return ret;
 292 }
 293
 294 static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
 295 {
 296         misc_deregister(&pnx4008_wdt_miscdev);
 297
 298         clk_disable(wdt_clk);
 299         clk_put(wdt_clk);
 300
 301         return 0;
 302 }
 303
 304 static struct platform_driver platform_wdt_driver = {
 305         .driver = {
 306                 .name = "pnx4008-watchdog",
 307                 .owner  = THIS_MODULE,
 308         },
 309         .probe = pnx4008_wdt_probe,
 310         .remove = __devexit_p(pnx4008_wdt_remove),
 311 };
 312
 313 module_platform_driver(platform_wdt_driver);
 314
 315 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 316 MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
 317
 318 module_param(heartbeat, int, 0);
 319 MODULE_PARM_DESC(heartbeat,
 320                  "Watchdog heartbeat period in seconds from 1 to "
 321                  __MODULE_STRING(MAX_HEARTBEAT) ", default "
 322                  __MODULE_STRING(DEFAULT_HEARTBEAT));
 323
 324 module_param(nowayout, bool, 0);
 325 MODULE_PARM_DESC(nowayout,
 326                  "Set to 1 to keep watchdog running after device release");
 327
 328 MODULE_LICENSE("GPL");
 329 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 330 MODULE_ALIAS("platform:pnx4008-watchdog");