2 * PCI Backend - Handles the virtual fields in the configuration space headers.
4 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
12 #include "conf_space.h"
24 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
25 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
27 /* Bits guests are allowed to control in permissive mode. */
28 #define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
29 PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
30 PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)
32 static void *command_init(struct pci_dev
*dev
, int offset
)
34 struct pci_cmd_info
*cmd
= kmalloc(sizeof(*cmd
), GFP_KERNEL
);
38 return ERR_PTR(-ENOMEM
);
40 err
= pci_read_config_word(dev
, PCI_COMMAND
, &cmd
->val
);
49 static int command_read(struct pci_dev
*dev
, int offset
, u16
*value
, void *data
)
51 int ret
= pci_read_config_word(dev
, offset
, value
);
52 const struct pci_cmd_info
*cmd
= data
;
54 *value
&= PCI_COMMAND_GUEST
;
55 *value
|= cmd
->val
& ~PCI_COMMAND_GUEST
;
60 static int command_write(struct pci_dev
*dev
, int offset
, u16 value
, void *data
)
62 struct xen_pcibk_dev_data
*dev_data
;
65 struct pci_cmd_info
*cmd
= data
;
67 dev_data
= pci_get_drvdata(dev
);
68 if (!pci_is_enabled(dev
) && is_enable_cmd(value
)) {
69 if (unlikely(verbose_request
))
70 printk(KERN_DEBUG DRV_NAME
": %s: enable\n",
72 err
= pci_enable_device(dev
);
76 dev_data
->enable_intx
= 1;
77 } else if (pci_is_enabled(dev
) && !is_enable_cmd(value
)) {
78 if (unlikely(verbose_request
))
79 printk(KERN_DEBUG DRV_NAME
": %s: disable\n",
81 pci_disable_device(dev
);
83 dev_data
->enable_intx
= 0;
86 if (!dev
->is_busmaster
&& is_master_cmd(value
)) {
87 if (unlikely(verbose_request
))
88 printk(KERN_DEBUG DRV_NAME
": %s: set bus master\n",
91 } else if (dev
->is_busmaster
&& !is_master_cmd(value
)) {
92 if (unlikely(verbose_request
))
93 printk(KERN_DEBUG DRV_NAME
": %s: clear bus master\n",
95 pci_clear_master(dev
);
98 if (!(cmd
->val
& PCI_COMMAND_INVALIDATE
) &&
99 (value
& PCI_COMMAND_INVALIDATE
)) {
100 if (unlikely(verbose_request
))
102 DRV_NAME
": %s: enable memory-write-invalidate\n",
104 err
= pci_set_mwi(dev
);
106 pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
108 value
&= ~PCI_COMMAND_INVALIDATE
;
110 } else if ((cmd
->val
& PCI_COMMAND_INVALIDATE
) &&
111 !(value
& PCI_COMMAND_INVALIDATE
)) {
112 if (unlikely(verbose_request
))
114 DRV_NAME
": %s: disable memory-write-invalidate\n",
121 if (!xen_pcibk_permissive
&& (!dev_data
|| !dev_data
->permissive
))
124 /* Only allow the guest to control certain bits. */
125 err
= pci_read_config_word(dev
, offset
, &val
);
126 if (err
|| val
== value
)
129 value
&= PCI_COMMAND_GUEST
;
130 value
|= val
& ~PCI_COMMAND_GUEST
;
132 return pci_write_config_word(dev
, offset
, value
);
135 static int rom_write(struct pci_dev
*dev
, int offset
, u32 value
, void *data
)
137 struct pci_bar_info
*bar
= data
;
139 if (unlikely(!bar
)) {
140 pr_warn(DRV_NAME
": driver data not found for %s\n",
142 return XEN_PCI_ERR_op_failed
;
145 /* A write to obtain the length must happen as a 32-bit write.
146 * This does not (yet) support writing individual bytes
148 if ((value
| ~PCI_ROM_ADDRESS_MASK
) == ~0U)
152 pci_read_config_dword(dev
, offset
, &tmpval
);
153 if (tmpval
!= bar
->val
&& value
== bar
->val
) {
154 /* Allow restoration of bar value. */
155 pci_write_config_dword(dev
, offset
, bar
->val
);
160 /* Do we need to support enabling/disabling the rom address here? */
165 /* For the BARs, only allow writes which write ~0 or
166 * the correct resource information
167 * (Needed for when the driver probes the resource usage)
169 static int bar_write(struct pci_dev
*dev
, int offset
, u32 value
, void *data
)
171 struct pci_bar_info
*bar
= data
;
173 if (unlikely(!bar
)) {
174 pr_warn(DRV_NAME
": driver data not found for %s\n",
176 return XEN_PCI_ERR_op_failed
;
179 /* A write to obtain the length must happen as a 32-bit write.
180 * This does not (yet) support writing individual bytes
186 pci_read_config_dword(dev
, offset
, &tmpval
);
187 if (tmpval
!= bar
->val
&& value
== bar
->val
) {
188 /* Allow restoration of bar value. */
189 pci_write_config_dword(dev
, offset
, bar
->val
);
197 static int bar_read(struct pci_dev
*dev
, int offset
, u32
* value
, void *data
)
199 struct pci_bar_info
*bar
= data
;
201 if (unlikely(!bar
)) {
202 pr_warn(DRV_NAME
": driver data not found for %s\n",
204 return XEN_PCI_ERR_op_failed
;
207 *value
= bar
->which
? bar
->len_val
: bar
->val
;
212 static inline void read_dev_bar(struct pci_dev
*dev
,
213 struct pci_bar_info
*bar_info
, int offset
,
217 struct resource
*res
= dev
->resource
;
219 if (offset
== PCI_ROM_ADDRESS
|| offset
== PCI_ROM_ADDRESS1
)
220 pos
= PCI_ROM_RESOURCE
;
222 pos
= (offset
- PCI_BASE_ADDRESS_0
) / 4;
223 if (pos
&& ((res
[pos
- 1].flags
& (PCI_BASE_ADDRESS_SPACE
|
224 PCI_BASE_ADDRESS_MEM_TYPE_MASK
)) ==
225 (PCI_BASE_ADDRESS_SPACE_MEMORY
|
226 PCI_BASE_ADDRESS_MEM_TYPE_64
))) {
227 bar_info
->val
= res
[pos
- 1].start
>> 32;
228 bar_info
->len_val
= -resource_size(&res
[pos
- 1]) >> 32;
233 if (!res
[pos
].flags
||
234 (res
[pos
].flags
& (IORESOURCE_DISABLED
| IORESOURCE_UNSET
|
238 bar_info
->val
= res
[pos
].start
|
239 (res
[pos
].flags
& PCI_REGION_FLAG_MASK
);
240 bar_info
->len_val
= -resource_size(&res
[pos
]) |
241 (res
[pos
].flags
& PCI_REGION_FLAG_MASK
);
244 static void *bar_init(struct pci_dev
*dev
, int offset
)
246 struct pci_bar_info
*bar
= kzalloc(sizeof(*bar
), GFP_KERNEL
);
249 return ERR_PTR(-ENOMEM
);
251 read_dev_bar(dev
, bar
, offset
, ~0);
256 static void *rom_init(struct pci_dev
*dev
, int offset
)
258 struct pci_bar_info
*bar
= kzalloc(sizeof(*bar
), GFP_KERNEL
);
261 return ERR_PTR(-ENOMEM
);
263 read_dev_bar(dev
, bar
, offset
, ~PCI_ROM_ADDRESS_ENABLE
);
268 static void bar_reset(struct pci_dev
*dev
, int offset
, void *data
)
270 struct pci_bar_info
*bar
= data
;
275 static void bar_release(struct pci_dev
*dev
, int offset
, void *data
)
280 static int xen_pcibk_read_vendor(struct pci_dev
*dev
, int offset
,
281 u16
*value
, void *data
)
283 *value
= dev
->vendor
;
288 static int xen_pcibk_read_device(struct pci_dev
*dev
, int offset
,
289 u16
*value
, void *data
)
291 *value
= dev
->device
;
296 static int interrupt_read(struct pci_dev
*dev
, int offset
, u8
* value
,
299 *value
= (u8
) dev
->irq
;
304 static int bist_write(struct pci_dev
*dev
, int offset
, u8 value
, void *data
)
309 err
= pci_read_config_byte(dev
, offset
, &cur_value
);
313 if ((cur_value
& ~PCI_BIST_START
) == (value
& ~PCI_BIST_START
)
314 || value
== PCI_BIST_START
)
315 err
= pci_write_config_byte(dev
, offset
, value
);
321 static const struct config_field header_common
[] = {
323 .offset
= PCI_VENDOR_ID
,
325 .u
.w
.read
= xen_pcibk_read_vendor
,
328 .offset
= PCI_DEVICE_ID
,
330 .u
.w
.read
= xen_pcibk_read_device
,
333 .offset
= PCI_COMMAND
,
335 .init
= command_init
,
336 .release
= bar_release
,
337 .u
.w
.read
= command_read
,
338 .u
.w
.write
= command_write
,
341 .offset
= PCI_INTERRUPT_LINE
,
343 .u
.b
.read
= interrupt_read
,
346 .offset
= PCI_INTERRUPT_PIN
,
348 .u
.b
.read
= xen_pcibk_read_config_byte
,
351 /* Any side effects of letting driver domain control cache line? */
352 .offset
= PCI_CACHE_LINE_SIZE
,
354 .u
.b
.read
= xen_pcibk_read_config_byte
,
355 .u
.b
.write
= xen_pcibk_write_config_byte
,
358 .offset
= PCI_LATENCY_TIMER
,
360 .u
.b
.read
= xen_pcibk_read_config_byte
,
365 .u
.b
.read
= xen_pcibk_read_config_byte
,
366 .u
.b
.write
= bist_write
,
371 #define CFG_FIELD_BAR(reg_offset) \
373 .offset = reg_offset, \
376 .reset = bar_reset, \
377 .release = bar_release, \
378 .u.dw.read = bar_read, \
379 .u.dw.write = bar_write, \
382 #define CFG_FIELD_ROM(reg_offset) \
384 .offset = reg_offset, \
387 .reset = bar_reset, \
388 .release = bar_release, \
389 .u.dw.read = bar_read, \
390 .u.dw.write = rom_write, \
393 static const struct config_field header_0
[] = {
394 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0
),
395 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1
),
396 CFG_FIELD_BAR(PCI_BASE_ADDRESS_2
),
397 CFG_FIELD_BAR(PCI_BASE_ADDRESS_3
),
398 CFG_FIELD_BAR(PCI_BASE_ADDRESS_4
),
399 CFG_FIELD_BAR(PCI_BASE_ADDRESS_5
),
400 CFG_FIELD_ROM(PCI_ROM_ADDRESS
),
404 static const struct config_field header_1
[] = {
405 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0
),
406 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1
),
407 CFG_FIELD_ROM(PCI_ROM_ADDRESS1
),
411 int xen_pcibk_config_header_add_fields(struct pci_dev
*dev
)
415 err
= xen_pcibk_config_add_fields(dev
, header_common
);
419 switch (dev
->hdr_type
) {
420 case PCI_HEADER_TYPE_NORMAL
:
421 err
= xen_pcibk_config_add_fields(dev
, header_0
);
424 case PCI_HEADER_TYPE_BRIDGE
:
425 err
= xen_pcibk_config_add_fields(dev
, header_1
);
430 pr_err("%s: Unsupported header type %d!\n",
431 pci_name(dev
), dev
->hdr_type
);