1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" // opcode generating auxiliaries
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *format, ...);
165 char *current_inputline;
167 int yyerror (char *msg);
169 void error (char *format, ...)
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (expr);
199 if (expr->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define imm16(x) EXPR_VALUE (x)
216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
217 #define uimm16(x) EXPR_VALUE (x)
219 /* Return true if a value is inside a range. */
220 #define IN_RANGE(x, low, high) \
221 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
223 /* Auxiliary functions. */
226 neg_value (Expr_Node *expr)
228 expr->value.i_value = -expr->value.i_value;
232 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
234 if (!IS_DREG (*reg1))
236 yyerror ("Dregs expected");
240 if (reg1->regno != 1 && reg1->regno != 3)
242 yyerror ("Bad register pair");
246 if (imm7 (reg2) != reg1->regno - 1)
248 yyerror ("Bad register pair");
257 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
259 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
260 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
261 return yyerror ("Source multiplication register mismatch");
267 /* Check mac option. */
270 check_macfunc_option (Macfunc *a, Opt_mode *opt)
272 /* Default option is always valid. */
276 if ((a->op == 3 && a->w == 1 && a->P == 1
277 && opt->mod != M_FU && opt->mod != M_S2RND && opt->mod != M_ISS2)
278 || (a->op == 3 && a->w == 1 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
280 && opt->mod != M_T && opt->mod != M_S2RND && opt->mod != M_ISS2
282 || (a->w == 0 && a->P == 0
283 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)
284 || (a->w == 1 && a->P == 1
285 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_S2RND
286 && opt->mod != M_ISS2 && opt->mod != M_IU)
287 || (a->w == 1 && a->P == 0
288 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
289 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
290 && opt->mod != M_ISS2 && opt->mod != M_IH))
296 /* Check (vector) mac funcs and ops. */
299 check_macfuncs (Macfunc *aa, Opt_mode *opa,
300 Macfunc *ab, Opt_mode *opb)
302 /* Variables for swapping. */
306 /* The option mode should be put at the end of the second instruction
307 of the vector except M, which should follow MAC1 instruction. */
309 return yyerror ("Bad opt mode");
311 /* If a0macfunc comes before a1macfunc, swap them. */
315 /* (M) is not allowed here. */
317 return yyerror ("(M) not allowed with A0MAC");
319 return yyerror ("Vector AxMACs can't be same");
321 mtmp = *aa; *aa = *ab; *ab = mtmp;
322 otmp = *opa; *opa = *opb; *opb = otmp;
327 return yyerror ("(M) not allowed with A0MAC");
329 return yyerror ("Vector AxMACs can't be same");
332 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
333 assignment_or_macfuncs. */
334 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
335 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
337 if (check_multiply_halfregs (aa, ab) < 0)
342 /* Only one of the assign_macfuncs has a half reg multiply
343 Evil trick: Just 'OR' their source register codes:
344 We can do that, because we know they were initialized to 0
345 in the rules that don't use multiply_halfregs. */
346 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
347 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
350 if (aa->w == ab->w && aa->P != ab->P)
352 return yyerror ("macfuncs must differ");
353 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
354 return yyerror ("Destination Dregs must differ by one");
357 /* Make sure mod flags get ORed, too. */
358 opb->mod |= opa->mod;
361 if (check_macfunc_option (aa, opb) < 0
362 && check_macfunc_option (ab, opb) < 0)
363 return yyerror ("bad option");
365 /* Make sure first macfunc has got both P flags ORed. */
373 is_group1 (INSTR_T x)
375 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
376 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
383 is_group2 (INSTR_T x)
385 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
386 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
387 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
388 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
389 || (x->value == 0x0000))
403 struct { int r0; int s0; int x0; int aop; } modcodes;
404 struct { int r0; } r0;
411 /* Vector Specific. */
412 %token BYTEOP16P BYTEOP16M
413 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
414 %token BYTEUNPACK BYTEPACK
417 %token ALIGN8 ALIGN16 ALIGN24
419 %token EXTRACT DEPOSIT EXPADJ SEARCH
420 %token ONES SIGN SIGNBITS
428 %token CCREG BYTE_DREG
429 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
430 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
435 %token RTI RTS RTX RTN RTE
446 %token JUMP JUMP_DOT_S JUMP_DOT_L
453 %token NOT TILDA BANG
459 %token MINUS PLUS STAR SLASH
463 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
464 %token _MINUS_MINUS _PLUS_PLUS
466 /* Shift/rotate ops. */
467 %token SHIFT LSHIFT ASHIFT BXORSHIFT
468 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
470 %token LESS_LESS GREATER_GREATER
471 %token _GREATER_GREATER_GREATER
472 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
475 /* In place operators. */
476 %token ASSIGN _STAR_ASSIGN
477 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
478 %token _MINUS_ASSIGN _PLUS_ASSIGN
480 /* Assignments, comparisons. */
481 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
486 %token FLUSHINV FLUSH
487 %token IFLUSH PREFETCH
504 %token R RND RNDL RNDH RND12 RND20
509 %token BITTGL BITCLR BITSET BITTST BITMUX
512 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
514 /* Semantic auxiliaries. */
517 %token COLON SEMICOLON
518 %token RPAREN LPAREN LBRACK RBRACK
522 %token GOT GOT17M4 FUNCDESC_GOT17M4
532 %type <modcodes> byteop_mod
534 %type <reg> a_plusassign
535 %type <reg> a_minusassign
536 %type <macfunc> multiply_halfregs
537 %type <macfunc> assign_macfunc
538 %type <macfunc> a_macfunc
542 %type <modcodes> vsmod
543 %type <modcodes> ccstat
546 %type <reg> reg_with_postinc
547 %type <reg> reg_with_predec
551 %type <symbol> SYMBOL
554 %type <reg> BYTE_DREG
555 %type <reg> REG_A_DOUBLE_ZERO
556 %type <reg> REG_A_DOUBLE_ONE
558 %type <reg> STATUS_REG
562 %type <modcodes> smod
563 %type <modcodes> b3_op
564 %type <modcodes> rnd_op
565 %type <modcodes> post_op
567 %type <r0> iu_or_nothing
568 %type <r0> plus_minus
572 %type <modcodes> amod0
573 %type <modcodes> amod1
574 %type <modcodes> amod2
576 %type <r0> w32_or_nothing
580 %type <expr> got_or_expr
582 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
584 /* Precedence rules. */
588 %left LESS_LESS GREATER_GREATER
590 %left STAR SLASH PERCENT
601 if (insn == (INSTR_T) 0)
602 return NO_INSN_GENERATED;
603 else if (insn == (INSTR_T) - 1)
604 return SEMANTIC_ERROR;
606 return INSN_GENERATED;
611 /* Parallel instructions. */
612 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
614 if (($1->value & 0xf800) == 0xc000)
616 if (is_group1 ($3) && is_group2 ($5))
617 $$ = bfin_gen_multi_instr ($1, $3, $5);
618 else if (is_group2 ($3) && is_group1 ($5))
619 $$ = bfin_gen_multi_instr ($1, $5, $3);
621 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
623 else if (($3->value & 0xf800) == 0xc000)
625 if (is_group1 ($1) && is_group2 ($5))
626 $$ = bfin_gen_multi_instr ($3, $1, $5);
627 else if (is_group2 ($1) && is_group1 ($5))
628 $$ = bfin_gen_multi_instr ($3, $5, $1);
630 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
632 else if (($5->value & 0xf800) == 0xc000)
634 if (is_group1 ($1) && is_group2 ($3))
635 $$ = bfin_gen_multi_instr ($5, $1, $3);
636 else if (is_group2 ($1) && is_group1 ($3))
637 $$ = bfin_gen_multi_instr ($5, $3, $1);
639 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
642 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
645 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
647 if (($1->value & 0xf800) == 0xc000)
650 $$ = bfin_gen_multi_instr ($1, $3, 0);
651 else if (is_group2 ($3))
652 $$ = bfin_gen_multi_instr ($1, 0, $3);
654 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
656 else if (($3->value & 0xf800) == 0xc000)
659 $$ = bfin_gen_multi_instr ($3, $1, 0);
660 else if (is_group2 ($1))
661 $$ = bfin_gen_multi_instr ($3, 0, $1);
663 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
665 else if (is_group1 ($1) && is_group2 ($3))
666 $$ = bfin_gen_multi_instr (0, $1, $3);
667 else if (is_group2 ($1) && is_group1 ($3))
668 $$ = bfin_gen_multi_instr (0, $3, $1);
670 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
685 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
687 | assign_macfunc opt_mode
691 int h00, h10, h01, h11;
693 if (check_macfunc_option (&$1, &$2) < 0)
694 return yyerror ("bad option");
699 return yyerror ("(m) not allowed with a0 unit");
718 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
719 &$1.dst, op0, &$1.s0, &$1.s1, w0);
725 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
729 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
731 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
738 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
739 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
740 dst, $4.op, &$1.s0, &$1.s1, $4.w);
747 notethat ("dsp32alu: DISALGNEXCPT\n");
748 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
750 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
752 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
754 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
755 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
758 return yyerror ("Register mismatch");
760 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
762 if (!IS_A1 ($4) && IS_A1 ($5))
764 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
765 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
768 return yyerror ("Register mismatch");
770 | A_ZERO_DOT_H ASSIGN HALF_REG
772 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
773 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
775 | A_ONE_DOT_H ASSIGN HALF_REG
777 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
778 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
780 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
781 COLON expr COMMA REG COLON expr RPAREN aligndir
783 if (!IS_DREG ($2) || !IS_DREG ($4))
784 return yyerror ("Dregs expected");
785 else if (!valid_dreg_pair (&$9, $11))
786 return yyerror ("Bad dreg pair");
787 else if (!valid_dreg_pair (&$13, $15))
788 return yyerror ("Bad dreg pair");
791 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
792 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
796 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
797 REG COLON expr RPAREN aligndir
799 if (!IS_DREG ($2) || !IS_DREG($4))
800 return yyerror ("Dregs expected");
801 else if (!valid_dreg_pair (&$9, $11))
802 return yyerror ("Bad dreg pair");
803 else if (!valid_dreg_pair (&$13, $15))
804 return yyerror ("Bad dreg pair");
807 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
808 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
812 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
814 if (!IS_DREG ($2) || !IS_DREG ($4))
815 return yyerror ("Dregs expected");
816 else if (!valid_dreg_pair (&$8, $10))
817 return yyerror ("Bad dreg pair");
820 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
821 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
824 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
826 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
828 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
829 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
832 return yyerror ("Register mismatch");
834 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
835 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
837 if (IS_DREG ($1) && IS_DREG ($7))
839 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
840 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
843 return yyerror ("Register mismatch");
847 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
849 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
850 && IS_A1 ($9) && !IS_A1 ($11))
852 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
853 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
856 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
857 && !IS_A1 ($9) && IS_A1 ($11))
859 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
860 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
863 return yyerror ("Register mismatch");
866 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
869 return yyerror ("Operators must differ");
871 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
872 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
874 notethat ("dsp32alu: dregs = dregs + dregs,"
875 "dregs = dregs - dregs (amod1)\n");
876 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
879 return yyerror ("Register mismatch");
882 /* Bar Operations. */
884 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
886 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
887 return yyerror ("Differing source registers");
889 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
890 return yyerror ("Dregs expected");
893 if ($4.r0 == 1 && $10.r0 == 2)
895 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
896 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
898 else if ($4.r0 == 0 && $10.r0 == 3)
900 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
901 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
904 return yyerror ("Bar operand mismatch");
907 | REG ASSIGN ABS REG vmod
911 if (IS_DREG ($1) && IS_DREG ($4))
915 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
920 /* Vector version of ABS. */
921 notethat ("dsp32alu: dregs = ABS dregs\n");
924 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
927 return yyerror ("Dregs expected");
931 notethat ("dsp32alu: Ax = ABS Ax\n");
932 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
934 | A_ZERO_DOT_L ASSIGN HALF_REG
938 notethat ("dsp32alu: A0.l = reg_half\n");
939 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
942 return yyerror ("A0.l = Rx.l expected");
944 | A_ONE_DOT_L ASSIGN HALF_REG
948 notethat ("dsp32alu: A1.l = reg_half\n");
949 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
952 return yyerror ("A1.l = Rx.l expected");
955 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
957 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
959 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
960 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
963 return yyerror ("Dregs expected");
966 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
969 return yyerror ("Dregs expected");
970 else if (!valid_dreg_pair (&$5, $7))
971 return yyerror ("Bad dreg pair");
972 else if (!valid_dreg_pair (&$9, $11))
973 return yyerror ("Bad dreg pair");
976 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
977 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
980 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
983 return yyerror ("Dregs expected");
984 else if (!valid_dreg_pair (&$5, $7))
985 return yyerror ("Bad dreg pair");
986 else if (!valid_dreg_pair (&$9, $11))
987 return yyerror ("Bad dreg pair");
990 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
991 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
995 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
999 return yyerror ("Dregs expected");
1000 else if (!valid_dreg_pair (&$5, $7))
1001 return yyerror ("Bad dreg pair");
1002 else if (!valid_dreg_pair (&$9, $11))
1003 return yyerror ("Bad dreg pair");
1006 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1007 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1011 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1015 return yyerror ("Dregs expected");
1016 else if (!valid_dreg_pair (&$5, $7))
1017 return yyerror ("Bad dreg pair");
1018 else if (!valid_dreg_pair (&$9, $11))
1019 return yyerror ("Bad dreg pair");
1022 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1023 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1027 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1031 return yyerror ("Dregs expected");
1032 else if (!valid_dreg_pair (&$5, $7))
1033 return yyerror ("Bad dreg pair");
1034 else if (!valid_dreg_pair (&$9, $11))
1035 return yyerror ("Bad dreg pair");
1038 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1039 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1043 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1045 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1047 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1048 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1051 return yyerror ("Dregs expected");
1054 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1055 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1057 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1059 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1060 "SIGN (dregs_hi) * dregs_hi + "
1061 "SIGN (dregs_lo) * dregs_lo \n");
1063 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1066 return yyerror ("Dregs expected");
1068 | REG ASSIGN REG plus_minus REG amod1
1070 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1074 /* No saturation flag specified, generate the 16 bit variant. */
1075 notethat ("COMP3op: dregs = dregs +- dregs\n");
1076 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1080 /* Saturation flag specified, generate the 32 bit variant. */
1081 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1082 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1086 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1088 notethat ("COMP3op: pregs = pregs + pregs\n");
1089 $$ = COMP3OP (&$1, &$3, &$5, 5);
1092 return yyerror ("Dregs expected");
1094 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1098 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1105 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1106 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1109 return yyerror ("Dregs expected");
1112 | a_assign MINUS REG_A
1114 notethat ("dsp32alu: Ax = - Ax\n");
1115 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1117 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1119 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1120 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1121 $6.s0, $6.x0, HL2 ($3, $5));
1123 | a_assign a_assign expr
1125 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1127 notethat ("dsp32alu: A1 = A0 = 0\n");
1128 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1131 return yyerror ("Bad value, 0 expected");
1135 | a_assign REG_A LPAREN S RPAREN
1137 if (REG_SAME ($1, $2))
1139 notethat ("dsp32alu: Ax = Ax (S)\n");
1140 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1143 return yyerror ("Registers must be equal");
1146 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1150 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1151 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1154 return yyerror ("Dregs expected");
1157 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1159 if (IS_DREG ($3) && IS_DREG ($5))
1161 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1162 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1165 return yyerror ("Dregs expected");
1168 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1170 if (IS_DREG ($3) && IS_DREG ($5))
1172 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1173 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1176 return yyerror ("Dregs expected");
1181 if (!REG_SAME ($1, $2))
1183 notethat ("dsp32alu: An = Am\n");
1184 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1187 return yyerror ("Accu reg arguments must differ");
1194 notethat ("dsp32alu: An = dregs\n");
1195 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1198 return yyerror ("Dregs expected");
1201 | REG ASSIGN HALF_REG xpmod
1205 if ($1.regno == REG_A0x && IS_DREG ($3))
1207 notethat ("dsp32alu: A0.x = dregs_lo\n");
1208 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1210 else if ($1.regno == REG_A1x && IS_DREG ($3))
1212 notethat ("dsp32alu: A1.x = dregs_lo\n");
1213 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1215 else if (IS_DREG ($1) && IS_DREG ($3))
1217 notethat ("ALU2op: dregs = dregs_lo\n");
1218 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1221 return yyerror ("Register mismatch");
1224 return yyerror ("Low reg expected");
1227 | HALF_REG ASSIGN expr
1229 notethat ("LDIMMhalf: pregs_half = imm16\n");
1231 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1232 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1233 return yyerror ("Wrong register for load immediate");
1235 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1236 return yyerror ("Constant out of range");
1238 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1243 notethat ("dsp32alu: An = 0\n");
1246 return yyerror ("0 expected");
1248 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1251 | REG ASSIGN expr xpmod1
1253 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1254 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1255 return yyerror ("Wrong register for load immediate");
1259 /* 7 bit immediate value if possible.
1260 We will check for that constant value for efficiency
1261 If it goes to reloc, it will be 16 bit. */
1262 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1264 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1265 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1267 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1269 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1270 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1274 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1275 return yyerror ("Immediate value out of range");
1277 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1279 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1284 /* (z) There is no 7 bit zero extended instruction.
1285 If the expr is a relocation, generate it. */
1287 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1288 return yyerror ("Immediate value out of range");
1290 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1292 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1296 | HALF_REG ASSIGN REG
1299 return yyerror ("Low reg expected");
1301 if (IS_DREG ($1) && $3.regno == REG_A0x)
1303 notethat ("dsp32alu: dregs_lo = A0.x\n");
1304 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1306 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1308 notethat ("dsp32alu: dregs_lo = A1.x\n");
1309 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1312 return yyerror ("Register mismatch");
1315 | REG ASSIGN REG op_bar_op REG amod0
1317 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1319 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1320 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1323 return yyerror ("Register mismatch");
1326 | REG ASSIGN BYTE_DREG xpmod
1328 if (IS_DREG ($1) && IS_DREG ($3))
1330 notethat ("ALU2op: dregs = dregs_byte\n");
1331 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1334 return yyerror ("Register mismatch");
1337 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1339 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1341 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1342 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1345 return yyerror ("Register mismatch");
1348 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1350 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1352 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1353 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1356 return yyerror ("Register mismatch");
1359 | a_minusassign REG_A w32_or_nothing
1361 if (!IS_A1 ($1) && IS_A1 ($2))
1363 notethat ("dsp32alu: A0 -= A1\n");
1364 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1367 return yyerror ("Register mismatch");
1370 | REG _MINUS_ASSIGN expr
1372 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1374 notethat ("dagMODik: iregs -= 4\n");
1375 $$ = DAGMODIK (&$1, 3);
1377 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1379 notethat ("dagMODik: iregs -= 2\n");
1380 $$ = DAGMODIK (&$1, 1);
1383 return yyerror ("Register or value mismatch");
1386 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1388 if (IS_IREG ($1) && IS_MREG ($3))
1390 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1392 $$ = DAGMODIM (&$1, &$3, 0, 1);
1394 else if (IS_PREG ($1) && IS_PREG ($3))
1396 notethat ("PTR2op: pregs += pregs (BREV )\n");
1397 $$ = PTR2OP (&$1, &$3, 5);
1400 return yyerror ("Register mismatch");
1403 | REG _MINUS_ASSIGN REG
1405 if (IS_IREG ($1) && IS_MREG ($3))
1407 notethat ("dagMODim: iregs -= mregs\n");
1408 $$ = DAGMODIM (&$1, &$3, 1, 0);
1410 else if (IS_PREG ($1) && IS_PREG ($3))
1412 notethat ("PTR2op: pregs -= pregs\n");
1413 $$ = PTR2OP (&$1, &$3, 0);
1416 return yyerror ("Register mismatch");
1419 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1421 if (!IS_A1 ($1) && IS_A1 ($3))
1423 notethat ("dsp32alu: A0 += A1 (W32)\n");
1424 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1427 return yyerror ("Register mismatch");
1430 | REG _PLUS_ASSIGN REG
1432 if (IS_IREG ($1) && IS_MREG ($3))
1434 notethat ("dagMODim: iregs += mregs\n");
1435 $$ = DAGMODIM (&$1, &$3, 0, 0);
1438 return yyerror ("iregs += mregs expected");
1441 | REG _PLUS_ASSIGN expr
1445 if (EXPR_VALUE ($3) == 4)
1447 notethat ("dagMODik: iregs += 4\n");
1448 $$ = DAGMODIK (&$1, 2);
1450 else if (EXPR_VALUE ($3) == 2)
1452 notethat ("dagMODik: iregs += 2\n");
1453 $$ = DAGMODIK (&$1, 0);
1456 return yyerror ("iregs += [ 2 | 4 ");
1458 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1460 notethat ("COMPI2opP: pregs += imm7\n");
1461 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1463 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1465 notethat ("COMPI2opD: dregs += imm7\n");
1466 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1468 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1469 return yyerror ("Immediate value out of range");
1471 return yyerror ("Register mismatch");
1474 | REG _STAR_ASSIGN REG
1476 if (IS_DREG ($1) && IS_DREG ($3))
1478 notethat ("ALU2op: dregs *= dregs\n");
1479 $$ = ALU2OP (&$1, &$3, 3);
1482 return yyerror ("Register mismatch");
1485 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1487 if (!valid_dreg_pair (&$3, $5))
1488 return yyerror ("Bad dreg pair");
1489 else if (!valid_dreg_pair (&$7, $9))
1490 return yyerror ("Bad dreg pair");
1493 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1494 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1498 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1500 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1502 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1503 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1506 return yyerror ("Register mismatch");
1509 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1511 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1512 && REG_SAME ($1, $4))
1514 if (EXPR_VALUE ($9) == 1)
1516 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1517 $$ = ALU2OP (&$1, &$6, 4);
1519 else if (EXPR_VALUE ($9) == 2)
1521 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1522 $$ = ALU2OP (&$1, &$6, 5);
1525 return yyerror ("Bad shift value");
1527 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1528 && REG_SAME ($1, $4))
1530 if (EXPR_VALUE ($9) == 1)
1532 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1533 $$ = PTR2OP (&$1, &$6, 6);
1535 else if (EXPR_VALUE ($9) == 2)
1537 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1538 $$ = PTR2OP (&$1, &$6, 7);
1541 return yyerror ("Bad shift value");
1544 return yyerror ("Register mismatch");
1548 | REG ASSIGN REG BAR REG
1550 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1552 notethat ("COMP3op: dregs = dregs | dregs\n");
1553 $$ = COMP3OP (&$1, &$3, &$5, 3);
1556 return yyerror ("Dregs expected");
1558 | REG ASSIGN REG CARET REG
1560 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1562 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1563 $$ = COMP3OP (&$1, &$3, &$5, 4);
1566 return yyerror ("Dregs expected");
1568 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1570 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1572 if (EXPR_VALUE ($8) == 1)
1574 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1575 $$ = COMP3OP (&$1, &$3, &$6, 6);
1577 else if (EXPR_VALUE ($8) == 2)
1579 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1580 $$ = COMP3OP (&$1, &$3, &$6, 7);
1583 return yyerror ("Bad shift value");
1586 return yyerror ("Dregs expected");
1588 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1590 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1592 notethat ("CCflag: CC = A0 == A1\n");
1593 $$ = CCFLAG (0, 0, 5, 0, 0);
1596 return yyerror ("AREGs are in bad order or same");
1598 | CCREG ASSIGN REG_A LESS_THAN REG_A
1600 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1602 notethat ("CCflag: CC = A0 < A1\n");
1603 $$ = CCFLAG (0, 0, 6, 0, 0);
1606 return yyerror ("AREGs are in bad order or same");
1608 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1610 if (REG_CLASS($3) == REG_CLASS($5))
1612 notethat ("CCflag: CC = dpregs < dpregs\n");
1613 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1616 return yyerror ("Compare only of same register class");
1618 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1620 if (($6.r0 == 1 && IS_IMM ($5, 3))
1621 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1623 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1624 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1627 return yyerror ("Bad constant value");
1629 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1631 if (REG_CLASS($3) == REG_CLASS($5))
1633 notethat ("CCflag: CC = dpregs == dpregs\n");
1634 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1637 return yyerror ("Compare only of same register class");
1639 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1643 notethat ("CCflag: CC = dpregs == imm3\n");
1644 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1647 return yyerror ("Bad constant range");
1649 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1651 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1653 notethat ("CCflag: CC = A0 <= A1\n");
1654 $$ = CCFLAG (0, 0, 7, 0, 0);
1657 return yyerror ("AREGs are in bad order or same");
1659 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1661 if (REG_CLASS($3) == REG_CLASS($5))
1663 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1664 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1665 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1668 return yyerror ("Compare only of same register class");
1670 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1672 if (($6.r0 == 1 && IS_IMM ($5, 3))
1673 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1677 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1679 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1681 else if (IS_PREG ($3))
1683 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1685 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1688 return yyerror ("Dreg or Preg expected");
1691 return yyerror ("Bad constant value");
1694 | REG ASSIGN REG AMPERSAND REG
1696 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1698 notethat ("COMP3op: dregs = dregs & dregs\n");
1699 $$ = COMP3OP (&$1, &$3, &$5, 2);
1702 return yyerror ("Dregs expected");
1707 notethat ("CC2stat operation\n");
1708 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1713 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1715 notethat ("REGMV: allregs = allregs\n");
1716 $$ = bfin_gen_regmv (&$3, &$1);
1719 return yyerror ("Register mismatch");
1726 notethat ("CC2dreg: CC = dregs\n");
1727 $$ = bfin_gen_cc2dreg (1, &$3);
1730 return yyerror ("Register mismatch");
1737 notethat ("CC2dreg: dregs = CC\n");
1738 $$ = bfin_gen_cc2dreg (0, &$1);
1741 return yyerror ("Register mismatch");
1744 | CCREG _ASSIGN_BANG CCREG
1746 notethat ("CC2dreg: CC =! CC\n");
1747 $$ = bfin_gen_cc2dreg (3, 0);
1752 | HALF_REG ASSIGN multiply_halfregs opt_mode
1754 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1756 if (!IS_H ($1) && $4.MM)
1757 return yyerror ("(M) not allowed with MAC0");
1761 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1762 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1763 &$1, 0, &$3.s0, &$3.s1, 0);
1767 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1768 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1769 &$1, 0, &$3.s0, &$3.s1, 1);
1773 | REG ASSIGN multiply_halfregs opt_mode
1775 /* Odd registers can use (M). */
1777 return yyerror ("Dreg expected");
1779 if (IS_EVEN ($1) && $4.MM)
1780 return yyerror ("(M) not allowed with MAC0");
1784 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1786 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1787 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1788 &$1, 0, &$3.s0, &$3.s1, 0);
1792 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1793 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1794 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1795 &$1, 0, &$3.s0, &$3.s1, 1);
1799 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1800 HALF_REG ASSIGN multiply_halfregs opt_mode
1802 if (!IS_DREG ($1) || !IS_DREG ($6))
1803 return yyerror ("Dregs expected");
1805 if (!IS_HCOMPL($1, $6))
1806 return yyerror ("Dest registers mismatch");
1808 if (check_multiply_halfregs (&$3, &$8) < 0)
1811 if ((!IS_H ($1) && $4.MM)
1812 || (!IS_H ($6) && $9.MM))
1813 return yyerror ("(M) not allowed with MAC0");
1815 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1816 "dregs_lo = multiply_halfregs opt_mode\n");
1819 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1820 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1821 &$1, 0, &$3.s0, &$3.s1, 1);
1823 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1824 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1825 &$1, 0, &$3.s0, &$3.s1, 1);
1828 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1830 if (!IS_DREG ($1) || !IS_DREG ($6))
1831 return yyerror ("Dregs expected");
1833 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1834 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1835 return yyerror ("Dest registers mismatch");
1837 if (check_multiply_halfregs (&$3, &$8) < 0)
1840 if ((IS_EVEN ($1) && $4.MM)
1841 || (IS_EVEN ($6) && $9.MM))
1842 return yyerror ("(M) not allowed with MAC0");
1844 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1845 "dregs = multiply_halfregs opt_mode\n");
1848 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1849 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1850 &$1, 0, &$3.s0, &$3.s1, 1);
1852 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1853 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1854 &$1, 0, &$3.s0, &$3.s1, 1);
1859 | a_assign ASHIFT REG_A BY HALF_REG
1861 if (!REG_SAME ($1, $3))
1862 return yyerror ("Aregs must be same");
1864 if (IS_DREG ($5) && !IS_H ($5))
1866 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1867 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1870 return yyerror ("Dregs expected");
1873 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1875 if (IS_DREG ($6) && !IS_H ($6))
1877 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1878 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1881 return yyerror ("Dregs expected");
1884 | a_assign REG_A LESS_LESS expr
1886 if (!REG_SAME ($1, $2))
1887 return yyerror ("Aregs must be same");
1889 if (IS_UIMM ($4, 5))
1891 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1892 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1895 return yyerror ("Bad shift value");
1898 | REG ASSIGN REG LESS_LESS expr vsmod
1900 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1905 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1906 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1910 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1911 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1914 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1916 if (EXPR_VALUE ($5) == 2)
1918 notethat ("PTR2op: pregs = pregs << 2\n");
1919 $$ = PTR2OP (&$1, &$3, 1);
1921 else if (EXPR_VALUE ($5) == 1)
1923 notethat ("COMP3op: pregs = pregs << 1\n");
1924 $$ = COMP3OP (&$1, &$3, &$3, 5);
1927 return yyerror ("Bad shift value");
1930 return yyerror ("Bad shift value or register");
1932 | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1934 if (IS_UIMM ($5, 4))
1936 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1937 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1940 return yyerror ("Bad shift value");
1942 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1944 if (IS_UIMM ($5, 4))
1946 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1947 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1950 return yyerror ("Bad shift value");
1952 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1956 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1961 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1962 "dregs_lo (V, .)\n");
1968 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1970 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1973 return yyerror ("Dregs expected");
1977 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1979 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1981 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1982 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1985 return yyerror ("Bad shift value or register");
1989 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1991 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1993 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
1994 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
1996 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
1998 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
1999 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2002 return yyerror ("Bad shift value or register");
2007 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2009 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2011 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2012 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2015 return yyerror ("Register mismatch");
2018 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2020 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2022 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2023 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2026 return yyerror ("Register mismatch");
2029 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2031 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2033 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2034 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2037 return yyerror ("Register mismatch");
2040 | a_assign REG_A _GREATER_GREATER_GREATER expr
2042 if (!REG_SAME ($1, $2))
2043 return yyerror ("Aregs must be same");
2045 if (IS_UIMM ($4, 5))
2047 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2048 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2051 return yyerror ("Shift value range error");
2053 | a_assign LSHIFT REG_A BY HALF_REG
2055 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2057 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2058 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2061 return yyerror ("Register mismatch");
2064 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2066 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2068 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2069 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2072 return yyerror ("Register mismatch");
2075 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2077 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2079 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2080 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2083 return yyerror ("Register mismatch");
2086 | REG ASSIGN SHIFT REG BY HALF_REG
2088 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2090 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2091 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2094 return yyerror ("Register mismatch");
2097 | a_assign REG_A GREATER_GREATER expr
2099 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2101 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2102 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2105 return yyerror ("Accu register expected");
2108 | REG ASSIGN REG GREATER_GREATER expr vmod
2112 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2114 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2115 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2118 return yyerror ("Register mismatch");
2122 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2124 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2125 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2127 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2129 notethat ("PTR2op: pregs = pregs >> 2\n");
2130 $$ = PTR2OP (&$1, &$3, 3);
2132 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2134 notethat ("PTR2op: pregs = pregs >> 1\n");
2135 $$ = PTR2OP (&$1, &$3, 4);
2138 return yyerror ("Register mismatch");
2141 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2143 if (IS_UIMM ($5, 5))
2145 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2146 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2149 return yyerror ("Register mismatch");
2151 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2153 if (IS_UIMM ($5, 5))
2155 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2156 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2157 $6.s0, HL2 ($1, $3));
2160 return yyerror ("Register or modifier mismatch");
2164 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2166 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2171 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2172 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2176 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2177 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2181 return yyerror ("Register mismatch");
2184 | HALF_REG ASSIGN ONES REG
2186 if (IS_DREG_L ($1) && IS_DREG ($4))
2188 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2189 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2192 return yyerror ("Register mismatch");
2195 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2197 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2199 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2200 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2203 return yyerror ("Register mismatch");
2206 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2209 && $7.regno == REG_A0
2210 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2212 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2213 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2216 return yyerror ("Register mismatch");
2219 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2222 && $7.regno == REG_A0
2223 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2225 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2226 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2229 return yyerror ("Register mismatch");
2232 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2234 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2236 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2237 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2240 return yyerror ("Register mismatch");
2243 | a_assign ROT REG_A BY HALF_REG
2245 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2247 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2248 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2251 return yyerror ("Register mismatch");
2254 | REG ASSIGN ROT REG BY HALF_REG
2256 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2258 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2259 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2262 return yyerror ("Register mismatch");
2265 | a_assign ROT REG_A BY expr
2269 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2270 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2273 return yyerror ("Register mismatch");
2276 | REG ASSIGN ROT REG BY expr
2278 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2280 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2283 return yyerror ("Register mismatch");
2286 | HALF_REG ASSIGN SIGNBITS REG_A
2290 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2291 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2294 return yyerror ("Register mismatch");
2297 | HALF_REG ASSIGN SIGNBITS REG
2299 if (IS_DREG_L ($1) && IS_DREG ($4))
2301 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2302 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2305 return yyerror ("Register mismatch");
2308 | HALF_REG ASSIGN SIGNBITS HALF_REG
2312 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2313 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2316 return yyerror ("Register mismatch");
2319 /* The ASR bit is just inverted here. */
2320 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2322 if (IS_DREG_L ($1) && IS_DREG ($5))
2324 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2325 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2328 return yyerror ("Register mismatch");
2331 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2333 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2335 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2336 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2339 return yyerror ("Register mismatch");
2342 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2344 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2346 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2347 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2350 return yyerror ("Register mismatch");
2353 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2355 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2357 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2358 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2361 return yyerror ("Dregs expected");
2365 /* LOGI2op: BITCLR (dregs, uimm5). */
2366 | BITCLR LPAREN REG COMMA expr RPAREN
2368 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2370 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2371 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2374 return yyerror ("Register mismatch");
2377 /* LOGI2op: BITSET (dregs, uimm5). */
2378 | BITSET LPAREN REG COMMA expr RPAREN
2380 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2382 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2383 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2386 return yyerror ("Register mismatch");
2389 /* LOGI2op: BITTGL (dregs, uimm5). */
2390 | BITTGL LPAREN REG COMMA expr RPAREN
2392 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2394 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2395 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2398 return yyerror ("Register mismatch");
2401 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2403 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2405 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2406 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2409 return yyerror ("Register mismatch or value error");
2412 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2414 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2416 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2417 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2420 return yyerror ("Register mismatch or value error");
2423 | IF BANG CCREG REG ASSIGN REG
2425 if ((IS_DREG ($4) || IS_PREG ($4))
2426 && (IS_DREG ($6) || IS_PREG ($6)))
2428 notethat ("ccMV: IF ! CC gregs = gregs\n");
2429 $$ = CCMV (&$6, &$4, 0);
2432 return yyerror ("Register mismatch");
2435 | IF CCREG REG ASSIGN REG
2437 if ((IS_DREG ($5) || IS_PREG ($5))
2438 && (IS_DREG ($3) || IS_PREG ($3)))
2440 notethat ("ccMV: IF CC gregs = gregs\n");
2441 $$ = CCMV (&$5, &$3, 1);
2444 return yyerror ("Register mismatch");
2447 | IF BANG CCREG JUMP expr
2449 if (IS_PCREL10 ($5))
2451 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2452 $$ = BRCC (0, 0, $5);
2455 return yyerror ("Bad jump offset");
2458 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2460 if (IS_PCREL10 ($5))
2462 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2463 $$ = BRCC (0, 1, $5);
2466 return yyerror ("Bad jump offset");
2469 | IF CCREG JUMP expr
2471 if (IS_PCREL10 ($4))
2473 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2474 $$ = BRCC (1, 0, $4);
2477 return yyerror ("Bad jump offset");
2480 | IF CCREG JUMP expr LPAREN BP RPAREN
2482 if (IS_PCREL10 ($4))
2484 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2485 $$ = BRCC (1, 1, $4);
2488 return yyerror ("Bad jump offset");
2492 notethat ("ProgCtrl: NOP\n");
2493 $$ = PROGCTRL (0, 0);
2498 notethat ("ProgCtrl: RTS\n");
2499 $$ = PROGCTRL (1, 0);
2504 notethat ("ProgCtrl: RTI\n");
2505 $$ = PROGCTRL (1, 1);
2510 notethat ("ProgCtrl: RTX\n");
2511 $$ = PROGCTRL (1, 2);
2516 notethat ("ProgCtrl: RTN\n");
2517 $$ = PROGCTRL (1, 3);
2522 notethat ("ProgCtrl: RTE\n");
2523 $$ = PROGCTRL (1, 4);
2528 notethat ("ProgCtrl: IDLE\n");
2529 $$ = PROGCTRL (2, 0);
2534 notethat ("ProgCtrl: CSYNC\n");
2535 $$ = PROGCTRL (2, 3);
2540 notethat ("ProgCtrl: SSYNC\n");
2541 $$ = PROGCTRL (2, 4);
2546 notethat ("ProgCtrl: EMUEXCPT\n");
2547 $$ = PROGCTRL (2, 5);
2554 notethat ("ProgCtrl: CLI dregs\n");
2555 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2558 return yyerror ("Dreg expected for CLI");
2565 notethat ("ProgCtrl: STI dregs\n");
2566 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2569 return yyerror ("Dreg expected for STI");
2572 | JUMP LPAREN REG RPAREN
2576 notethat ("ProgCtrl: JUMP (pregs )\n");
2577 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2580 return yyerror ("Bad register for indirect jump");
2583 | CALL LPAREN REG RPAREN
2587 notethat ("ProgCtrl: CALL (pregs )\n");
2588 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2591 return yyerror ("Bad register for indirect call");
2594 | CALL LPAREN PC PLUS REG RPAREN
2598 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2599 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2602 return yyerror ("Bad register for indirect call");
2605 | JUMP LPAREN PC PLUS REG RPAREN
2609 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2610 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2613 return yyerror ("Bad register for indirect jump");
2618 if (IS_UIMM ($2, 4))
2620 notethat ("ProgCtrl: RAISE uimm4\n");
2621 $$ = PROGCTRL (9, uimm4 ($2));
2624 return yyerror ("Bad value for RAISE");
2629 notethat ("ProgCtrl: EMUEXCPT\n");
2630 $$ = PROGCTRL (10, uimm4 ($2));
2633 | TESTSET LPAREN REG RPAREN
2637 notethat ("ProgCtrl: TESTSET (pregs )\n");
2638 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2641 return yyerror ("Preg expected");
2646 if (IS_PCREL12 ($2))
2648 notethat ("UJUMP: JUMP pcrel12\n");
2652 return yyerror ("Bad value for relative jump");
2657 if (IS_PCREL12 ($2))
2659 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2663 return yyerror ("Bad value for relative jump");
2668 if (IS_PCREL24 ($2))
2670 notethat ("CALLa: jump.l pcrel24\n");
2674 return yyerror ("Bad value for long jump");
2679 if (IS_PCREL24 ($2))
2681 notethat ("CALLa: jump.l pcrel24\n");
2685 return yyerror ("Bad value for long jump");
2690 if (IS_PCREL24 ($2))
2692 notethat ("CALLa: CALL pcrel25m2\n");
2696 return yyerror ("Bad call address");
2700 if (IS_PCREL24 ($2))
2702 notethat ("CALLa: CALL pcrel25m2\n");
2706 return yyerror ("Bad call address");
2710 /* ALU2op: DIVQ (dregs, dregs). */
2711 | DIVQ LPAREN REG COMMA REG RPAREN
2713 if (IS_DREG ($3) && IS_DREG ($5))
2714 $$ = ALU2OP (&$3, &$5, 8);
2716 return yyerror ("Bad registers for DIVQ");
2719 | DIVS LPAREN REG COMMA REG RPAREN
2721 if (IS_DREG ($3) && IS_DREG ($5))
2722 $$ = ALU2OP (&$3, &$5, 9);
2724 return yyerror ("Bad registers for DIVS");
2727 | REG ASSIGN MINUS REG vsmod
2729 if (IS_DREG ($1) && IS_DREG ($4))
2731 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2733 notethat ("ALU2op: dregs = - dregs\n");
2734 $$ = ALU2OP (&$1, &$4, 14);
2736 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2738 notethat ("dsp32alu: dregs = - dregs (.)\n");
2739 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2743 notethat ("dsp32alu: dregs = - dregs (.)\n");
2744 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2748 return yyerror ("Dregs expected");
2751 | REG ASSIGN TILDA REG
2753 if (IS_DREG ($1) && IS_DREG ($4))
2755 notethat ("ALU2op: dregs = ~dregs\n");
2756 $$ = ALU2OP (&$1, &$4, 15);
2759 return yyerror ("Dregs expected");
2762 | REG _GREATER_GREATER_ASSIGN REG
2764 if (IS_DREG ($1) && IS_DREG ($3))
2766 notethat ("ALU2op: dregs >>= dregs\n");
2767 $$ = ALU2OP (&$1, &$3, 1);
2770 return yyerror ("Dregs expected");
2773 | REG _GREATER_GREATER_ASSIGN expr
2775 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2777 notethat ("LOGI2op: dregs >>= uimm5\n");
2778 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2781 return yyerror ("Dregs expected or value error");
2784 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2786 if (IS_DREG ($1) && IS_DREG ($3))
2788 notethat ("ALU2op: dregs >>>= dregs\n");
2789 $$ = ALU2OP (&$1, &$3, 0);
2792 return yyerror ("Dregs expected");
2795 | REG _LESS_LESS_ASSIGN REG
2797 if (IS_DREG ($1) && IS_DREG ($3))
2799 notethat ("ALU2op: dregs <<= dregs\n");
2800 $$ = ALU2OP (&$1, &$3, 2);
2803 return yyerror ("Dregs expected");
2806 | REG _LESS_LESS_ASSIGN expr
2808 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2810 notethat ("LOGI2op: dregs <<= uimm5\n");
2811 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2814 return yyerror ("Dregs expected or const value error");
2818 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2820 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2822 notethat ("LOGI2op: dregs >>>= uimm5\n");
2823 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2826 return yyerror ("Dregs expected");
2829 /* Cache Control. */
2831 | FLUSH LBRACK REG RBRACK
2833 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2835 $$ = CACTRL (&$3, 0, 2);
2837 return yyerror ("Bad register(s) for FLUSH");
2840 | FLUSH reg_with_postinc
2844 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2845 $$ = CACTRL (&$2, 1, 2);
2848 return yyerror ("Bad register(s) for FLUSH");
2851 | FLUSHINV LBRACK REG RBRACK
2855 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2856 $$ = CACTRL (&$3, 0, 1);
2859 return yyerror ("Bad register(s) for FLUSH");
2862 | FLUSHINV reg_with_postinc
2866 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2867 $$ = CACTRL (&$2, 1, 1);
2870 return yyerror ("Bad register(s) for FLUSH");
2873 /* CaCTRL: IFLUSH [pregs]. */
2874 | IFLUSH LBRACK REG RBRACK
2878 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2879 $$ = CACTRL (&$3, 0, 3);
2882 return yyerror ("Bad register(s) for FLUSH");
2885 | IFLUSH reg_with_postinc
2889 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2890 $$ = CACTRL (&$2, 1, 3);
2893 return yyerror ("Bad register(s) for FLUSH");
2896 | PREFETCH LBRACK REG RBRACK
2900 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2901 $$ = CACTRL (&$3, 0, 0);
2904 return yyerror ("Bad register(s) for PREFETCH");
2907 | PREFETCH reg_with_postinc
2911 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2912 $$ = CACTRL (&$2, 1, 0);
2915 return yyerror ("Bad register(s) for PREFETCH");
2919 /* LDST: B [ pregs <post_op> ] = dregs. */
2921 | B LBRACK REG post_op RBRACK ASSIGN REG
2923 if (IS_PREG ($3) && IS_DREG ($7))
2925 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2926 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2929 return yyerror ("Register mismatch");
2932 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2933 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2935 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2937 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2940 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2943 return yyerror ("Register mismatch or const size wrong");
2947 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2948 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2950 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2952 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2953 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2955 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2957 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2960 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2963 return yyerror ("Bad register(s) or wrong constant size");
2966 /* LDST: W [ pregs <post_op> ] = dregs. */
2967 | W LBRACK REG post_op RBRACK ASSIGN REG
2969 if (IS_PREG ($3) && IS_DREG ($7))
2971 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2972 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2975 return yyerror ("Bad register(s) for STORE");
2978 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2982 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2983 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2985 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2987 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2988 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
2992 return yyerror ("Bad register(s) for STORE");
2995 /* LDSTiiFP: [ FP - const ] = dpregs. */
2996 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
2998 Expr_Node *tmp = $4;
2999 int ispreg = IS_PREG ($7);
3002 return yyerror ("Preg expected for indirect");
3004 if (!IS_DREG ($7) && !ispreg)
3005 return yyerror ("Bad source register for STORE");
3008 tmp = unary (Expr_Op_Type_NEG, tmp);
3010 if (in_range_p (tmp, 0, 63, 3))
3012 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3013 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3015 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3017 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3018 tmp = unary (Expr_Op_Type_NEG, tmp);
3019 $$ = LDSTIIFP (tmp, &$7, 1);
3021 else if (in_range_p (tmp, -131072, 131071, 3))
3023 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3024 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
3027 return yyerror ("Displacement out of range for store");
3030 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3032 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
3034 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
3035 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
3037 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
3039 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3042 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3045 return yyerror ("Bad register or constant for LOAD");
3048 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3052 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3053 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3055 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3057 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3058 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3061 return yyerror ("Bad register or post_op for LOAD");
3065 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3067 if (IS_DREG ($1) && IS_PREG ($5))
3069 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3070 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3073 return yyerror ("Bad register for LOAD");
3076 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3078 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3080 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3081 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3084 return yyerror ("Bad register for LOAD");
3087 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3089 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3091 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3092 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3095 return yyerror ("Bad register for LOAD");
3098 | LBRACK REG post_op RBRACK ASSIGN REG
3100 if (IS_IREG ($2) && IS_DREG ($6))
3102 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3103 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3105 else if (IS_PREG ($2) && IS_DREG ($6))
3107 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3108 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3110 else if (IS_PREG ($2) && IS_PREG ($6))
3112 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3113 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3116 return yyerror ("Bad register for STORE");
3119 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3122 return yyerror ("Expected Dreg for last argument");
3124 if (IS_IREG ($2) && IS_MREG ($4))
3126 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3127 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3129 else if (IS_PREG ($2) && IS_PREG ($4))
3131 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3132 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3135 return yyerror ("Bad register for STORE");
3138 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3141 return yyerror ("Expect Dreg as last argument");
3142 if (IS_PREG ($3) && IS_PREG ($5))
3144 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3145 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3148 return yyerror ("Bad register for STORE");
3151 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3153 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3155 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3159 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3162 return yyerror ("Bad register or value for LOAD");
3165 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3167 if (IS_DREG ($1) && IS_PREG ($5))
3169 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3171 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3174 return yyerror ("Bad register for LOAD");
3177 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3179 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3181 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3182 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3184 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3186 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3187 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3190 return yyerror ("Bad register for LOAD");
3193 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3195 Expr_Node *tmp = $6;
3196 int ispreg = IS_PREG ($1);
3197 int isgot = IS_RELOC($6);
3200 return yyerror ("Preg expected for indirect");
3202 if (!IS_DREG ($1) && !ispreg)
3203 return yyerror ("Bad destination register for LOAD");
3206 tmp = unary (Expr_Op_Type_NEG, tmp);
3209 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3210 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3212 else if (in_range_p (tmp, 0, 63, 3))
3214 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3215 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3217 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3219 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3220 tmp = unary (Expr_Op_Type_NEG, tmp);
3221 $$ = LDSTIIFP (tmp, &$1, 0);
3223 else if (in_range_p (tmp, -131072, 131071, 3))
3225 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3226 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3230 return yyerror ("Displacement out of range for load");
3233 | REG ASSIGN LBRACK REG post_op RBRACK
3235 if (IS_DREG ($1) && IS_IREG ($4))
3237 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3238 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3240 else if (IS_DREG ($1) && IS_PREG ($4))
3242 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3243 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3245 else if (IS_PREG ($1) && IS_PREG ($4))
3247 if (REG_SAME ($1, $4) && $5.x0 != 2)
3248 return yyerror ("Pregs can't be same");
3250 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3251 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3253 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3255 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3256 $$ = PUSHPOPREG (&$1, 0);
3259 return yyerror ("Bad register or value");
3263 /* PushPopMultiple. */
3264 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3266 if ($1.regno != REG_SP)
3267 yyerror ("Stack Pointer expected");
3268 if ($4.regno == REG_R7
3269 && IN_RANGE ($6, 0, 7)
3270 && $8.regno == REG_P5
3271 && IN_RANGE ($10, 0, 5))
3273 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3274 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3277 return yyerror ("Bad register for PushPopMultiple");
3280 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3282 if ($1.regno != REG_SP)
3283 yyerror ("Stack Pointer expected");
3285 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3287 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3288 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3290 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3292 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3293 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3296 return yyerror ("Bad register for PushPopMultiple");
3299 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3301 if ($11.regno != REG_SP)
3302 yyerror ("Stack Pointer expected");
3303 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3304 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3306 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3307 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3310 return yyerror ("Bad register range for PushPopMultiple");
3313 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3315 if ($7.regno != REG_SP)
3316 yyerror ("Stack Pointer expected");
3318 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3320 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3321 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3323 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3325 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3326 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3329 return yyerror ("Bad register range for PushPopMultiple");
3332 | reg_with_predec ASSIGN REG
3334 if ($1.regno != REG_SP)
3335 yyerror ("Stack Pointer expected");
3339 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3340 $$ = PUSHPOPREG (&$3, 1);
3343 return yyerror ("Bad register for PushPopReg");
3350 if (IS_URANGE (16, $2, 0, 4))
3351 $$ = LINKAGE (0, uimm16s4 ($2));
3353 return yyerror ("Bad constant for LINK");
3358 notethat ("linkage: UNLINK\n");
3359 $$ = LINKAGE (1, 0);
3365 | LSETUP LPAREN expr COMMA expr RPAREN REG
3367 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3369 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3370 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3373 return yyerror ("Bad register or values for LSETUP");
3376 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3378 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3379 && IS_PREG ($9) && IS_CREG ($7))
3381 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3382 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3385 return yyerror ("Bad register or values for LSETUP");
3388 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3390 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3391 && IS_PREG ($9) && IS_CREG ($7)
3392 && EXPR_VALUE ($11) == 1)
3394 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3395 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3398 return yyerror ("Bad register or values for LSETUP");
3405 return yyerror ("Invalid expression in loop statement");
3407 return yyerror ("Invalid loop counter register");
3408 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3410 | LOOP expr REG ASSIGN REG
3412 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3414 notethat ("Loop: LOOP expr counters = pregs\n");
3415 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3418 return yyerror ("Bad register or values for LOOP");
3420 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3422 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3424 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3425 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3428 return yyerror ("Bad register or values for LOOP");
3434 notethat ("pseudoDEBUG: DBG\n");
3435 $$ = bfin_gen_pseudodbg (3, 7, 0);
3439 notethat ("pseudoDEBUG: DBG REG_A\n");
3440 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3444 notethat ("pseudoDEBUG: DBG allregs\n");
3445 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3448 | DBGCMPLX LPAREN REG RPAREN
3451 return yyerror ("Dregs expected");
3452 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3453 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3458 notethat ("psedoDEBUG: DBGHALT\n");
3459 $$ = bfin_gen_pseudodbg (3, 5, 0);
3462 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3464 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3465 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3468 | DBGAH LPAREN REG COMMA expr RPAREN
3470 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3471 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3474 | DBGAL LPAREN REG COMMA expr RPAREN
3476 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3477 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3485 /* Register rules. */
3487 REG_A: REG_A_DOUBLE_ZERO
3505 | LPAREN M COMMA MMOD RPAREN
3510 | LPAREN MMOD COMMA M RPAREN
3515 | LPAREN MMOD RPAREN
3527 asr_asl: LPAREN ASL RPAREN
3608 | LPAREN asr_asl_0 RPAREN
3620 | LPAREN asr_asl_0 COMMA sco RPAREN
3626 | LPAREN sco COMMA asr_asl_0 RPAREN
3686 | LPAREN V COMMA S RPAREN
3691 | LPAREN S COMMA V RPAREN
3753 | LPAREN MMOD RPAREN
3756 return yyerror ("Bad modifier");
3760 | LPAREN MMOD COMMA R RPAREN
3763 return yyerror ("Bad modifier");
3767 | LPAREN R COMMA MMOD RPAREN
3770 return yyerror ("Bad modifier");
3797 | LPAREN MMOD RPAREN
3802 return yyerror ("Only (W32) allowed");
3810 | LPAREN MMOD RPAREN
3815 return yyerror ("(IU) expected");
3819 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3825 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3877 $$.r0 = 1; /* HL. */
3880 $$.aop = 0; /* aop. */
3885 $$.r0 = 1; /* HL. */
3888 $$.aop = 1; /* aop. */
3891 | LPAREN RNDL RPAREN
3893 $$.r0 = 0; /* HL. */
3896 $$.aop = 0; /* aop. */
3901 $$.r0 = 0; /* HL. */
3907 | LPAREN RNDH COMMA R RPAREN
3909 $$.r0 = 1; /* HL. */
3912 $$.aop = 0; /* aop. */
3914 | LPAREN TH COMMA R RPAREN
3916 $$.r0 = 1; /* HL. */
3919 $$.aop = 1; /* aop. */
3921 | LPAREN RNDL COMMA R RPAREN
3923 $$.r0 = 0; /* HL. */
3926 $$.aop = 0; /* aop. */
3929 | LPAREN TL COMMA R RPAREN
3931 $$.r0 = 0; /* HL. */
3934 $$.aop = 1; /* aop. */
3942 $$.x0 = 0; /* HL. */
3947 $$.x0 = 1; /* HL. */
3949 | LPAREN LO COMMA R RPAREN
3952 $$.x0 = 0; /* HL. */
3954 | LPAREN HI COMMA R RPAREN
3957 $$.x0 = 1; /* HL. */
3975 /* Assignments, Macfuncs. */
4001 if (IS_A1 ($3) && IS_EVEN ($1))
4002 return yyerror ("Cannot move A1 to even register");
4003 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4004 return yyerror ("Cannot move A0 to odd register");
4020 | REG ASSIGN LPAREN a_macfunc RPAREN
4022 if ($4.n && IS_EVEN ($1))
4023 return yyerror ("Cannot move A1 to even register");
4024 else if (!$4.n && !IS_EVEN ($1))
4025 return yyerror ("Cannot move A0 to odd register");
4033 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4035 if ($4.n && !IS_H ($1))
4036 return yyerror ("Cannot move A1 to low half of register");
4037 else if (!$4.n && IS_H ($1))
4038 return yyerror ("Cannot move A0 to high half of register");
4046 | HALF_REG ASSIGN REG_A
4048 if (IS_A1 ($3) && !IS_H ($1))
4049 return yyerror ("Cannot move A1 to low half of register");
4050 else if (!IS_A1 ($3) && IS_H ($1))
4051 return yyerror ("Cannot move A0 to high half of register");
4064 a_assign multiply_halfregs
4071 | a_plusassign multiply_halfregs
4078 | a_minusassign multiply_halfregs
4088 HALF_REG STAR HALF_REG
4090 if (IS_DREG ($1) && IS_DREG ($3))
4096 return yyerror ("Dregs expected");
4120 CCREG cc_op STATUS_REG
4132 | STATUS_REG cc_op CCREG
4146 /* Expressions and Symbols. */
4150 Expr_Node_Value val;
4151 val.s_value = S_GET_NAME($1);
4152 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4158 { $$ = BFD_RELOC_BFIN_GOT; }
4160 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4162 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4165 got: symbol AT any_gotrel
4167 Expr_Node_Value val;
4169 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4192 Expr_Node_Value val;
4194 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4200 | LPAREN expr_1 RPAREN
4206 $$ = unary (Expr_Op_Type_COMP, $2);
4208 | MINUS expr_1 %prec TILDA
4210 $$ = unary (Expr_Op_Type_NEG, $2);
4220 expr_1: expr_1 STAR expr_1
4222 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4224 | expr_1 SLASH expr_1
4226 $$ = binary (Expr_Op_Type_Div, $1, $3);
4228 | expr_1 PERCENT expr_1
4230 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4232 | expr_1 PLUS expr_1
4234 $$ = binary (Expr_Op_Type_Add, $1, $3);
4236 | expr_1 MINUS expr_1
4238 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4240 | expr_1 LESS_LESS expr_1
4242 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4244 | expr_1 GREATER_GREATER expr_1
4246 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4248 | expr_1 AMPERSAND expr_1
4250 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4252 | expr_1 CARET expr_1
4254 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4258 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4270 mkexpr (int x, SYMBOL_T s)
4272 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4279 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4281 long umax = (1L << sz) - 1;
4282 long min = -1L << (sz - 1);
4283 long max = (1L << (sz - 1)) - 1;
4285 long v = EXPR_VALUE (expr);
4289 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4300 if (v >= min && v <= max) return 1;
4303 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4307 if (v <= umax && v >= 0)
4310 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4315 /* Return the expression structure that allows symbol operations.
4316 If the left and right children are constants, do the operation. */
4318 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4320 Expr_Node_Value val;
4322 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4326 case Expr_Op_Type_Add:
4327 x->value.i_value += y->value.i_value;
4329 case Expr_Op_Type_Sub:
4330 x->value.i_value -= y->value.i_value;
4332 case Expr_Op_Type_Mult:
4333 x->value.i_value *= y->value.i_value;
4335 case Expr_Op_Type_Div:
4336 if (y->value.i_value == 0)
4337 error ("Illegal Expression: Division by zero.");
4339 x->value.i_value /= y->value.i_value;
4341 case Expr_Op_Type_Mod:
4342 x->value.i_value %= y->value.i_value;
4344 case Expr_Op_Type_Lshift:
4345 x->value.i_value <<= y->value.i_value;
4347 case Expr_Op_Type_Rshift:
4348 x->value.i_value >>= y->value.i_value;
4350 case Expr_Op_Type_BAND:
4351 x->value.i_value &= y->value.i_value;
4353 case Expr_Op_Type_BOR:
4354 x->value.i_value |= y->value.i_value;
4356 case Expr_Op_Type_BXOR:
4357 x->value.i_value ^= y->value.i_value;
4359 case Expr_Op_Type_LAND:
4360 x->value.i_value = x->value.i_value && y->value.i_value;
4362 case Expr_Op_Type_LOR:
4363 x->value.i_value = x->value.i_value || y->value.i_value;
4367 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4371 /* Canonicalize order to EXPR OP CONSTANT. */
4372 if (x->type == Expr_Node_Constant)
4378 /* Canonicalize subtraction of const to addition of negated const. */
4379 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4381 op = Expr_Op_Type_Add;
4382 y->value.i_value = -y->value.i_value;
4384 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4385 && x->Right_Child->type == Expr_Node_Constant)
4387 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4389 x->Right_Child->value.i_value += y->value.i_value;
4394 /* Create a new expression structure. */
4396 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4400 unary (Expr_Op_Type op, Expr_Node *x)
4402 if (x->type == Expr_Node_Constant)
4406 case Expr_Op_Type_NEG:
4407 x->value.i_value = -x->value.i_value;
4409 case Expr_Op_Type_COMP:
4410 x->value.i_value = ~x->value.i_value;
4413 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4419 /* Create a new expression structure. */
4420 Expr_Node_Value val;
4422 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4426 int debug_codeselection = 0;
4428 notethat (char *format, ...)
4431 va_start (ap, format);
4432 if (debug_codeselection)
4434 vfprintf (errorf, format, ap);
4440 main (int argc, char **argv)