gas/config/bfin-parse.y

   1 /* bfin-parse.y  ADI Blackfin parser
   2    Copyright 2005, 2006, 2007, 2008, 2009
   3    Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21 %{
  22
  23 #include "as.h"
  24 #include <obstack.h>
  25
  26 #include "bfin-aux.h"  /* Opcode generating auxiliaries.  */
  27 #include "libbfd.h"
  28 #include "elf/common.h"
  29 #include "elf/bfin.h"
  30
  31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
  32         bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
  33
  34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  35         bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  36                            dst, src0, src1, w0)
  37
  38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
  39         bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
  40                             dst, src0, src1, w0)
  41
  42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
  43         bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
  44
  45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
  46         bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
  47
  48 #define LDIMMHALF_R(reg, h, s, z, hword) \
  49         bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
  50
  51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
  52         bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
  53
  54 #define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
  55         bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
  56
  57 #define LDST(ptr, reg, aop, sz, z, w)  \
  58         bfin_gen_ldst (ptr, reg, aop, sz, z, w)
  59
  60 #define LDSTII(ptr, reg, offset, w, op)  \
  61         bfin_gen_ldstii (ptr, reg, offset, w, op)
  62
  63 #define DSPLDST(i, m, reg, aop, w) \
  64         bfin_gen_dspldst (i, reg, aop, w, m)
  65
  66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
  67         bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
  68
  69 #define LDSTIIFP(offset, reg, w)  \
  70         bfin_gen_ldstiifp (reg, offset, w)
  71
  72 #define LOGI2OP(dst, src, opc) \
  73         bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
  74
  75 #define ALU2OP(dst, src, opc)  \
  76         bfin_gen_alu2op (dst, src, opc)
  77
  78 #define BRCC(t, b, offset) \
  79         bfin_gen_brcc (t, b, offset)
  80
  81 #define UJUMP(offset) \
  82         bfin_gen_ujump (offset)
  83
  84 #define PROGCTRL(prgfunc, poprnd) \
  85         bfin_gen_progctrl (prgfunc, poprnd)
  86
  87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
  88         bfin_gen_pushpopmultiple (dr, pr, d, p, w)
  89
  90 #define PUSHPOPREG(reg, w) \
  91         bfin_gen_pushpopreg (reg, w)
  92
  93 #define CALLA(addr, s)  \
  94         bfin_gen_calla (addr, s)
  95
  96 #define LINKAGE(r, framesize) \
  97         bfin_gen_linkage (r, framesize)
  98
  99 #define COMPI2OPD(dst, src, op)  \
 100         bfin_gen_compi2opd (dst, src, op)
 101
 102 #define COMPI2OPP(dst, src, op)  \
 103         bfin_gen_compi2opp (dst, src, op)
 104
 105 #define DAGMODIK(i, op)  \
 106         bfin_gen_dagmodik (i, op)
 107
 108 #define DAGMODIM(i, m, op, br)  \
 109         bfin_gen_dagmodim (i, m, op, br)
 110
 111 #define COMP3OP(dst, src0, src1, opc)   \
 112         bfin_gen_comp3op (src0, src1, dst, opc)
 113
 114 #define PTR2OP(dst, src, opc)   \
 115         bfin_gen_ptr2op (dst, src, opc)
 116
 117 #define CCFLAG(x, y, opc, i, g)  \
 118         bfin_gen_ccflag (x, y, opc, i, g)
 119
 120 #define CCMV(src, dst, t) \
 121         bfin_gen_ccmv (src, dst, t)
 122
 123 #define CACTRL(reg, a, op) \
 124         bfin_gen_cactrl (reg, a, op)
 125
 126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
 127         bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
 128
 129 #define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
 130 #define IS_RANGE(bits, expr, sign, mul)    \
 131         value_match(expr, bits, sign, mul, 1)
 132 #define IS_URANGE(bits, expr, sign, mul)    \
 133         value_match(expr, bits, sign, mul, 0)
 134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
 135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
 136 #define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
 137 #define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
 138
 139 #define IS_PCREL4(expr) \
 140         (value_match (expr, 4, 0, 2, 0))
 141
 142 #define IS_LPPCREL10(expr) \
 143         (value_match (expr, 10, 0, 2, 0))
 144
 145 #define IS_PCREL10(expr) \
 146         (value_match (expr, 10, 0, 2, 1))
 147
 148 #define IS_PCREL12(expr) \
 149         (value_match (expr, 12, 0, 2, 1))
 150
 151 #define IS_PCREL24(expr) \
 152         (value_match (expr, 24, 0, 2, 1))
 153
 154
 155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
 156
 157 extern FILE *errorf;
 158 extern INSTR_T insn;
 159
 160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
 161 static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
 162
 163 static void notethat (char *format, ...);
 164
 165 char *current_inputline;
 166 extern char *yytext;
 167 int yyerror (char *msg);
 168
 169 void error (char *format, ...)
 170 {
 171     va_list ap;
 172     static char buffer[2000];
 173
 174     va_start (ap, format);
 175     vsprintf (buffer, format, ap);
 176     va_end (ap);
 177
 178     as_bad ("%s", buffer);
 179 }
 180
 181 int
 182 yyerror (char *msg)
 183 {
 184   if (msg[0] == '\0')
 185     error ("%s", msg);
 186
 187   else if (yytext[0] != ';')
 188     error ("%s. Input text was %s.", msg, yytext);
 189   else
 190     error ("%s.", msg);
 191
 192   return -1;
 193 }
 194
 195 static int
 196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
 197 {
 198   int val = EXPR_VALUE (expr);
 199   if (expr->type != Expr_Node_Constant)
 200     return 0;
 201   if (val < from || val > to)
 202     return 0;
 203   return (val & mask) == 0;
 204 }
 205
 206 extern int yylex (void);
 207
 208 #define imm3(x) EXPR_VALUE (x)
 209 #define imm4(x) EXPR_VALUE (x)
 210 #define uimm4(x) EXPR_VALUE (x)
 211 #define imm5(x) EXPR_VALUE (x)
 212 #define uimm5(x) EXPR_VALUE (x)
 213 #define imm6(x) EXPR_VALUE (x)
 214 #define imm7(x) EXPR_VALUE (x)
 215 #define imm16(x) EXPR_VALUE (x)
 216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
 217 #define uimm16(x) EXPR_VALUE (x)
 218
 219 /* Return true if a value is inside a range.  */
 220 #define IN_RANGE(x, low, high) \
 221   (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
 222
 223 /* Auxiliary functions.  */
 224
 225 static int
 226 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
 227 {
 228   if (!IS_DREG (*reg1))
 229     {
 230       yyerror ("Dregs expected");
 231       return 0;
 232     }
 233
 234   if (reg1->regno != 1 && reg1->regno != 3)
 235     {
 236       yyerror ("Bad register pair");
 237       return 0;
 238     }
 239
 240   if (imm7 (reg2) != reg1->regno - 1)
 241     {
 242       yyerror ("Bad register pair");
 243       return 0;
 244     }
 245
 246   reg1->regno--;
 247   return 1;
 248 }
 249
 250 static int
 251 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
 252 {
 253   if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
 254       || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
 255     return yyerror ("Source multiplication register mismatch");
 256
 257   return 0;
 258 }
 259
 260
 261 /* Check mac option.  */
 262
 263 static int
 264 check_macfunc_option (Macfunc *a, Opt_mode *opt)
 265 {
 266   /* Default option is always valid.  */
 267   if (opt->mod == 0)
 268     return 0;
 269
 270   if ((a->w == 1 && a->P == 1
 271        && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 272        && opt->mod != M_S2RND && opt->mod != M_ISS2)
 273       || (a->w == 1 && a->P == 0
 274           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
 275           && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
 276           && opt->mod != M_ISS2 && opt->mod != M_IH)
 277       || (a->w == 0 && a->P == 0
 278           && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
 279     return -1;
 280
 281   return 0;
 282 }
 283
 284 /* Check (vector) mac funcs and ops.  */
 285
 286 static int
 287 check_macfuncs (Macfunc *aa, Opt_mode *opa,
 288                 Macfunc *ab, Opt_mode *opb)
 289 {
 290   /* Variables for swapping.  */
 291   Macfunc mtmp;
 292   Opt_mode otmp;
 293
 294   /* The option mode should be put at the end of the second instruction
 295      of the vector except M, which should follow MAC1 instruction.  */
 296   if (opa->mod != 0)
 297     return yyerror ("Bad opt mode");
 298
 299   /* If a0macfunc comes before a1macfunc, swap them.  */
 300
 301   if (aa->n == 0)
 302     {
 303       /*  (M) is not allowed here.  */
 304       if (opa->MM != 0)
 305         return yyerror ("(M) not allowed with A0MAC");
 306       if (ab->n != 1)
 307         return yyerror ("Vector AxMACs can't be same");
 308
 309       mtmp = *aa; *aa = *ab; *ab = mtmp;
 310       otmp = *opa; *opa = *opb; *opb = otmp;
 311     }
 312   else
 313     {
 314       if (opb->MM != 0)
 315         return yyerror ("(M) not allowed with A0MAC");
 316       if (ab->n != 0)
 317         return yyerror ("Vector AxMACs can't be same");
 318     }
 319
 320   /*  If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
 321   assignment_or_macfuncs.  */
 322   if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
 323       && (ab->op == 0 || ab->op == 1 || ab->op == 2))
 324     {
 325       if (check_multiply_halfregs (aa, ab) < 0)
 326         return -1;
 327     }
 328   else
 329     {
 330       /*  Only one of the assign_macfuncs has a half reg multiply
 331       Evil trick: Just 'OR' their source register codes:
 332       We can do that, because we know they were initialized to 0
 333       in the rules that don't use multiply_halfregs.  */
 334       aa->s0.regno |= (ab->s0.regno & CODE_MASK);
 335       aa->s1.regno |= (ab->s1.regno & CODE_MASK);
 336     }
 337
 338   if (aa->w == ab->w  && aa->P != ab->P)
 339     {
 340       return yyerror ("macfuncs must differ");
 341       if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
 342         return yyerror ("Destination Dregs must differ by one");
 343     }
 344
 345   /* Make sure mod flags get ORed, too.  */
 346   opb->mod |= opa->mod;
 347
 348   /* Check option.  */
 349   if (check_macfunc_option (aa, opb) < 0
 350       && check_macfunc_option (ab, opb) < 0)
 351     return yyerror ("bad option");
 352
 353   /* Make sure first macfunc has got both P flags ORed.  */
 354   aa->P |= ab->P;
 355
 356   return 0;
 357 }
 358
 359
 360 static int
 361 is_group1 (INSTR_T x)
 362 {
 363   /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
 364   if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
 365     return 1;
 366
 367   return 0;
 368 }
 369
 370 static int
 371 is_group2 (INSTR_T x)
 372 {
 373   if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
 374        && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
 375        && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
 376        && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
 377       || (x->value == 0x0000))
 378     return 1;
 379   return 0;
 380 }
 381
 382 static INSTR_T
 383 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
 384 {
 385   int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
 386   int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
 387   int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
 388
 389   if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
 390     yyerror ("resource conflict in multi-issue instruction");
 391
 392   /* Anomaly 05000074 */
 393   if (ENABLE_AC_05000074
 394       && (dsp32->value & 0xf780) == 0xc680
 395       && ((dsp16_grp1->value & 0xfe40) == 0x9240
 396           || (dsp16_grp1->value & 0xfe08) == 0xba08
 397           || (dsp16_grp1->value & 0xfc00) == 0xbc00))
 398     yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
 399 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
 400
 401   return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
 402 }
 403
 404 %}
 405
 406 %union {
 407   INSTR_T instr;
 408   Expr_Node *expr;
 409   SYMBOL_T symbol;
 410   long value;
 411   Register reg;
 412   Macfunc macfunc;
 413   struct { int r0; int s0; int x0; int aop; } modcodes;
 414   struct { int r0; } r0;
 415   Opt_mode mod;
 416 }
 417
 418
 419 /* Tokens.  */
 420
 421 /* Vector Specific.  */
 422 %token BYTEOP16P BYTEOP16M
 423 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
 424 %token BYTEUNPACK BYTEPACK
 425 %token PACK
 426 %token SAA
 427 %token ALIGN8 ALIGN16 ALIGN24
 428 %token VIT_MAX
 429 %token EXTRACT DEPOSIT EXPADJ SEARCH
 430 %token ONES SIGN SIGNBITS
 431
 432 /* Stack.  */
 433 %token LINK UNLINK
 434
 435 /* Registers.  */
 436 %token REG
 437 %token PC
 438 %token CCREG BYTE_DREG
 439 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
 440 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
 441 %token HALF_REG
 442
 443 /* Progctrl.  */
 444 %token NOP
 445 %token RTI RTS RTX RTN RTE
 446 %token HLT IDLE
 447 %token STI CLI
 448 %token CSYNC SSYNC
 449 %token EMUEXCPT
 450 %token RAISE EXCPT
 451 %token LSETUP
 452 %token LOOP
 453 %token LOOP_BEGIN
 454 %token LOOP_END
 455 %token DISALGNEXCPT
 456 %token JUMP JUMP_DOT_S JUMP_DOT_L
 457 %token CALL
 458
 459 /* Emulator only.  */
 460 %token ABORT
 461
 462 /* Operators.  */
 463 %token NOT TILDA BANG
 464 %token AMPERSAND BAR
 465 %token PERCENT
 466 %token CARET
 467 %token BXOR
 468
 469 %token MINUS PLUS STAR SLASH
 470 %token NEG
 471 %token MIN MAX ABS
 472 %token DOUBLE_BAR
 473 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
 474 %token _MINUS_MINUS _PLUS_PLUS
 475
 476 /* Shift/rotate ops.  */
 477 %token SHIFT LSHIFT ASHIFT BXORSHIFT
 478 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
 479 %token ROT
 480 %token LESS_LESS GREATER_GREATER
 481 %token _GREATER_GREATER_GREATER
 482 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
 483 %token DIVS DIVQ
 484
 485 /* In place operators.  */
 486 %token ASSIGN _STAR_ASSIGN
 487 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
 488 %token _MINUS_ASSIGN _PLUS_ASSIGN
 489
 490 /* Assignments, comparisons.  */
 491 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
 492 %token GE LT LE GT
 493 %token LESS_THAN
 494
 495 /* Cache.  */
 496 %token FLUSHINV FLUSH
 497 %token IFLUSH PREFETCH
 498
 499 /* Misc.  */
 500 %token PRNT
 501 %token OUTC
 502 %token WHATREG
 503 %token TESTSET
 504
 505 /* Modifiers.  */
 506 %token ASL ASR
 507 %token B W
 508 %token NS S CO SCO
 509 %token TH TL
 510 %token BP
 511 %token BREV
 512 %token X Z
 513 %token M MMOD
 514 %token R RND RNDL RNDH RND12 RND20
 515 %token V
 516 %token LO HI
 517
 518 /* Bit ops.  */
 519 %token BITTGL BITCLR BITSET BITTST BITMUX
 520
 521 /* Debug.  */
 522 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
 523
 524 /* Semantic auxiliaries.  */
 525
 526 %token IF COMMA BY
 527 %token COLON SEMICOLON
 528 %token RPAREN LPAREN LBRACK RBRACK
 529 %token STATUS_REG
 530 %token MNOP
 531 %token SYMBOL NUMBER
 532 %token GOT GOT17M4 FUNCDESC_GOT17M4
 533 %token AT PLTPC
 534
 535 /* Types.  */
 536 %type <instr> asm
 537 %type <value> MMOD
 538 %type <mod> opt_mode
 539
 540 %type <value> NUMBER
 541 %type <r0> aligndir
 542 %type <modcodes> byteop_mod
 543 %type <reg> a_assign
 544 %type <reg> a_plusassign
 545 %type <reg> a_minusassign
 546 %type <macfunc> multiply_halfregs
 547 %type <macfunc> assign_macfunc
 548 %type <macfunc> a_macfunc
 549 %type <expr> expr_1
 550 %type <instr> asm_1
 551 %type <r0> vmod
 552 %type <modcodes> vsmod
 553 %type <modcodes> ccstat
 554 %type <r0> cc_op
 555 %type <reg> CCREG
 556 %type <reg> reg_with_postinc
 557 %type <reg> reg_with_predec
 558
 559 %type <r0> searchmod
 560 %type <expr> symbol
 561 %type <symbol> SYMBOL
 562 %type <expr> eterm
 563 %type <reg> REG
 564 %type <reg> BYTE_DREG
 565 %type <reg> REG_A_DOUBLE_ZERO
 566 %type <reg> REG_A_DOUBLE_ONE
 567 %type <reg> REG_A
 568 %type <reg> STATUS_REG
 569 %type <expr> expr
 570 %type <r0> xpmod
 571 %type <r0> xpmod1
 572 %type <modcodes> smod
 573 %type <modcodes> b3_op
 574 %type <modcodes> rnd_op
 575 %type <modcodes> post_op
 576 %type <reg> HALF_REG
 577 %type <r0> iu_or_nothing
 578 %type <r0> plus_minus
 579 %type <r0> asr_asl
 580 %type <r0> asr_asl_0
 581 %type <modcodes> sco
 582 %type <modcodes> amod0
 583 %type <modcodes> amod1
 584 %type <modcodes> amod2
 585 %type <r0> op_bar_op
 586 %type <r0> w32_or_nothing
 587 %type <r0> c_align
 588 %type <r0> min_max
 589 %type <expr> got
 590 %type <expr> got_or_expr
 591 %type <expr> pltpc
 592 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
 593
 594 /* Precedence rules.  */
 595 %left BAR
 596 %left CARET
 597 %left AMPERSAND
 598 %left LESS_LESS GREATER_GREATER
 599 %left PLUS MINUS
 600 %left STAR SLASH PERCENT
 601
 602 %right ASSIGN
 603
 604 %right TILDA BANG
 605 %start statement
 606 %%
 607 statement:
 608         | asm
 609         {
 610           insn = $1;
 611           if (insn == (INSTR_T) 0)
 612             return NO_INSN_GENERATED;
 613           else if (insn == (INSTR_T) - 1)
 614             return SEMANTIC_ERROR;
 615           else
 616             return INSN_GENERATED;
 617         }
 618         ;
 619
 620 asm: asm_1 SEMICOLON
 621         /* Parallel instructions.  */
 622         | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
 623         {
 624           if (($1->value & 0xf800) == 0xc000)
 625             {
 626               if (is_group1 ($3) && is_group2 ($5))
 627                 $$ = gen_multi_instr_1 ($1, $3, $5);
 628               else if (is_group2 ($3) && is_group1 ($5))
 629                 $$ = gen_multi_instr_1 ($1, $5, $3);
 630               else
 631                 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
 632             }
 633           else if (($3->value & 0xf800) == 0xc000)
 634             {
 635               if (is_group1 ($1) && is_group2 ($5))
 636                 $$ = gen_multi_instr_1 ($3, $1, $5);
 637               else if (is_group2 ($1) && is_group1 ($5))
 638                 $$ = gen_multi_instr_1 ($3, $5, $1);
 639               else
 640                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
 641             }
 642           else if (($5->value & 0xf800) == 0xc000)
 643             {
 644               if (is_group1 ($1) && is_group2 ($3))
 645                 $$ = gen_multi_instr_1 ($5, $1, $3);
 646               else if (is_group2 ($1) && is_group1 ($3))
 647                 $$ = gen_multi_instr_1 ($5, $3, $1);
 648               else
 649                 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
 650             }
 651           else
 652             error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
 653         }
 654
 655         | asm_1 DOUBLE_BAR asm_1 SEMICOLON
 656         {
 657           if (($1->value & 0xf800) == 0xc000)
 658             {
 659               if (is_group1 ($3))
 660                 $$ = gen_multi_instr_1 ($1, $3, 0);
 661               else if (is_group2 ($3))
 662                 $$ = gen_multi_instr_1 ($1, 0, $3);
 663               else
 664                 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
 665             }
 666           else if (($3->value & 0xf800) == 0xc000)
 667             {
 668               if (is_group1 ($1))
 669                 $$ = gen_multi_instr_1 ($3, $1, 0);
 670               else if (is_group2 ($1))
 671                 $$ = gen_multi_instr_1 ($3, 0, $1);
 672               else
 673                 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
 674             }
 675           else if (is_group1 ($1) && is_group2 ($3))
 676               $$ = gen_multi_instr_1 (0, $1, $3);
 677           else if (is_group2 ($1) && is_group1 ($3))
 678             $$ = gen_multi_instr_1 (0, $3, $1);
 679           else
 680             return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
 681         }
 682         | error
 683         {
 684         $$ = 0;
 685         yyerror ("");
 686         yyerrok;
 687         }
 688         ;
 689
 690 /* DSPMAC.  */
 691
 692 asm_1:
 693         MNOP
 694         {
 695           $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
 696         }
 697         | assign_macfunc opt_mode
 698         {
 699           int op0, op1;
 700           int w0 = 0, w1 = 0;
 701           int h00, h10, h01, h11;
 702
 703           if (check_macfunc_option (&$1, &$2) < 0)
 704             return yyerror ("bad option");
 705
 706           if ($1.n == 0)
 707             {
 708               if ($2.MM)
 709                 return yyerror ("(m) not allowed with a0 unit");
 710               op1 = 3;
 711               op0 = $1.op;
 712               w1 = 0;
 713               w0 = $1.w;
 714               h00 = IS_H ($1.s0);
 715               h10 = IS_H ($1.s1);
 716               h01 = h11 = 0;
 717             }
 718           else
 719             {
 720               op1 = $1.op;
 721               op0 = 3;
 722               w1 = $1.w;
 723               w0 = 0;
 724               h00 = h10 = 0;
 725               h01 = IS_H ($1.s0);
 726               h11 = IS_H ($1.s1);
 727             }
 728           $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
 729                          &$1.dst, op0, &$1.s0, &$1.s1, w0);
 730         }
 731
 732
 733 /* VECTOR MACs.  */
 734
 735         | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
 736         {
 737           Register *dst;
 738
 739           if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
 740             return -1;
 741           notethat ("assign_macfunc (.), assign_macfunc (.)\n");
 742
 743           if ($1.w)
 744             dst = &$1.dst;
 745           else
 746             dst = &$4.dst;
 747
 748           $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
 749                          IS_H ($1.s0),  IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
 750                          dst, $4.op, &$1.s0, &$1.s1, $4.w);
 751         }
 752
 753 /* DSPALU.  */
 754
 755         | DISALGNEXCPT
 756         {
 757           notethat ("dsp32alu: DISALGNEXCPT\n");
 758           $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
 759         }
 760         | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 761         {
 762           if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
 763             {
 764               notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
 765               $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
 766             }
 767           else
 768             return yyerror ("Register mismatch");
 769         }
 770         | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
 771         {
 772           if (!IS_A1 ($4) && IS_A1 ($5))
 773             {
 774               notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
 775               $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
 776             }
 777           else
 778             return yyerror ("Register mismatch");
 779         }
 780         | A_ZERO_DOT_H ASSIGN HALF_REG
 781         {
 782           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 783           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 784         }
 785         | A_ONE_DOT_H ASSIGN HALF_REG
 786         {
 787           notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
 788           $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 789         }
 790         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
 791           COLON expr COMMA REG COLON expr RPAREN aligndir
 792         {
 793           if (!IS_DREG ($2) || !IS_DREG ($4))
 794             return yyerror ("Dregs expected");
 795           else if (!valid_dreg_pair (&$9, $11))
 796             return yyerror ("Bad dreg pair");
 797           else if (!valid_dreg_pair (&$13, $15))
 798             return yyerror ("Bad dreg pair");
 799           else
 800             {
 801               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
 802               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
 803             }
 804         }
 805
 806         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
 807           REG COLON expr RPAREN aligndir
 808         {
 809           if (!IS_DREG ($2) || !IS_DREG ($4))
 810             return yyerror ("Dregs expected");
 811           else if (!valid_dreg_pair (&$9, $11))
 812             return yyerror ("Bad dreg pair");
 813           else if (!valid_dreg_pair (&$13, $15))
 814             return yyerror ("Bad dreg pair");
 815           else
 816             {
 817               notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
 818               $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
 819             }
 820         }
 821
 822         | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
 823         {
 824           if (!IS_DREG ($2) || !IS_DREG ($4))
 825             return yyerror ("Dregs expected");
 826           else if (!valid_dreg_pair (&$8, $10))
 827             return yyerror ("Bad dreg pair");
 828           else
 829             {
 830               notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
 831               $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
 832             }
 833         }
 834         | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
 835         {
 836           if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
 837             {
 838               notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
 839               $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
 840             }
 841           else
 842             return yyerror ("Register mismatch");
 843         }
 844         | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
 845           REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
 846         {
 847           if (IS_DREG ($1) && IS_DREG ($7))
 848             {
 849               notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
 850               $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
 851             }
 852           else
 853             return yyerror ("Register mismatch");
 854         }
 855
 856
 857         | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
 858         {
 859           if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 860               && IS_A1 ($9) && !IS_A1 ($11))
 861             {
 862               notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
 863               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
 864
 865             }
 866           else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
 867                    && !IS_A1 ($9) && IS_A1 ($11))
 868             {
 869               notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
 870               $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
 871             }
 872           else
 873             return yyerror ("Register mismatch");
 874         }
 875
 876         | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
 877         {
 878           if ($4.r0 == $10.r0)
 879             return yyerror ("Operators must differ");
 880
 881           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
 882               && REG_SAME ($3, $9) && REG_SAME ($5, $11))
 883             {
 884               notethat ("dsp32alu: dregs = dregs + dregs,"
 885                        "dregs = dregs - dregs (amod1)\n");
 886               $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
 887             }
 888           else
 889             return yyerror ("Register mismatch");
 890         }
 891
 892 /*  Bar Operations.  */
 893
 894         | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
 895         {
 896           if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
 897             return yyerror ("Differing source registers");
 898
 899           if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
 900             return yyerror ("Dregs expected");
 901
 902
 903           if ($4.r0 == 1 && $10.r0 == 2)
 904             {
 905               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 906               $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 907             }
 908           else if ($4.r0 == 0 && $10.r0 == 3)
 909             {
 910               notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
 911               $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
 912             }
 913           else
 914             return yyerror ("Bar operand mismatch");
 915         }
 916
 917         | REG ASSIGN ABS REG vmod
 918         {
 919           int op;
 920
 921           if (IS_DREG ($1) && IS_DREG ($4))
 922             {
 923               if ($5.r0)
 924                 {
 925                   notethat ("dsp32alu: dregs = ABS dregs (v)\n");
 926                   op = 6;
 927                 }
 928               else
 929                 {
 930                   /* Vector version of ABS.  */
 931                   notethat ("dsp32alu: dregs = ABS dregs\n");
 932                   op = 7;
 933                 }
 934               $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
 935             }
 936           else
 937             return yyerror ("Dregs expected");
 938         }
 939         | a_assign ABS REG_A
 940         {
 941           notethat ("dsp32alu: Ax = ABS Ax\n");
 942           $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
 943         }
 944         | A_ZERO_DOT_L ASSIGN HALF_REG
 945         {
 946           if (IS_DREG_L ($3))
 947             {
 948               notethat ("dsp32alu: A0.l = reg_half\n");
 949               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
 950             }
 951           else
 952             return yyerror ("A0.l = Rx.l expected");
 953         }
 954         | A_ONE_DOT_L ASSIGN HALF_REG
 955         {
 956           if (IS_DREG_L ($3))
 957             {
 958               notethat ("dsp32alu: A1.l = reg_half\n");
 959               $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
 960             }
 961           else
 962             return yyerror ("A1.l = Rx.l expected");
 963         }
 964
 965         | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
 966         {
 967           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
 968             {
 969               notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
 970               $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
 971             }
 972           else
 973             return yyerror ("Dregs expected");
 974         }
 975
 976         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
 977         {
 978           if (!IS_DREG ($1))
 979             return yyerror ("Dregs expected");
 980           else if (!valid_dreg_pair (&$5, $7))
 981             return yyerror ("Bad dreg pair");
 982           else if (!valid_dreg_pair (&$9, $11))
 983             return yyerror ("Bad dreg pair");
 984           else
 985             {
 986               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
 987               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
 988             }
 989         }
 990         | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
 991         {
 992           if (!IS_DREG ($1))
 993             return yyerror ("Dregs expected");
 994           else if (!valid_dreg_pair (&$5, $7))
 995             return yyerror ("Bad dreg pair");
 996           else if (!valid_dreg_pair (&$9, $11))
 997             return yyerror ("Bad dreg pair");
 998           else
 999             {
1000               notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1001               $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1002             }
1003         }
1004
1005         | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1006           rnd_op
1007         {
1008           if (!IS_DREG ($1))
1009             return yyerror ("Dregs expected");
1010           else if (!valid_dreg_pair (&$5, $7))
1011             return yyerror ("Bad dreg pair");
1012           else if (!valid_dreg_pair (&$9, $11))
1013             return yyerror ("Bad dreg pair");
1014           else
1015             {
1016               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1017               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1018             }
1019         }
1020
1021         | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1022           rnd_op
1023         {
1024           if (!IS_DREG ($1))
1025             return yyerror ("Dregs expected");
1026           else if (!valid_dreg_pair (&$5, $7))
1027             return yyerror ("Bad dreg pair");
1028           else if (!valid_dreg_pair (&$9, $11))
1029             return yyerror ("Bad dreg pair");
1030           else
1031             {
1032               notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1033               $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1034             }
1035         }
1036
1037         | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1038           b3_op
1039         {
1040           if (!IS_DREG ($1))
1041             return yyerror ("Dregs expected");
1042           else if (!valid_dreg_pair (&$5, $7))
1043             return yyerror ("Bad dreg pair");
1044           else if (!valid_dreg_pair (&$9, $11))
1045             return yyerror ("Bad dreg pair");
1046           else
1047             {
1048               notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1049               $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1050             }
1051         }
1052
1053         | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1054         {
1055           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1056             {
1057               notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1058               $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1059             }
1060           else
1061             return yyerror ("Dregs expected");
1062         }
1063
1064         | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1065           HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1066         {
1067           if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1068             {
1069               notethat ("dsp32alu:      dregs_hi = dregs_lo ="
1070                        "SIGN (dregs_hi) * dregs_hi + "
1071                        "SIGN (dregs_lo) * dregs_lo \n");
1072
1073                 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1074             }
1075           else
1076             return yyerror ("Dregs expected");
1077         }
1078         | REG ASSIGN REG plus_minus REG amod1
1079         {
1080           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1081             {
1082               if ($6.aop == 0)
1083                 {
1084                   /* No saturation flag specified, generate the 16 bit variant.  */
1085                   notethat ("COMP3op: dregs = dregs +- dregs\n");
1086                   $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1087                 }
1088               else
1089                 {
1090                  /* Saturation flag specified, generate the 32 bit variant.  */
1091                  notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1092                  $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1093                 }
1094             }
1095           else
1096             if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1097               {
1098                 notethat ("COMP3op: pregs = pregs + pregs\n");
1099                 $$ = COMP3OP (&$1, &$3, &$5, 5);
1100               }
1101             else
1102               return yyerror ("Dregs expected");
1103         }
1104         | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1105         {
1106           int op;
1107
1108           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1109             {
1110               if ($9.r0)
1111                 op = 6;
1112               else
1113                 op = 7;
1114
1115               notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1116               $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1117             }
1118           else
1119             return yyerror ("Dregs expected");
1120         }
1121
1122         | a_assign MINUS REG_A
1123         {
1124           notethat ("dsp32alu: Ax = - Ax\n");
1125           $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1126         }
1127         | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1128         {
1129           notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1130           $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1131                          $6.s0, $6.x0, HL2 ($3, $5));
1132         }
1133         | a_assign a_assign expr
1134         {
1135           if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1136             {
1137               notethat ("dsp32alu: A1 = A0 = 0\n");
1138               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1139             }
1140           else
1141             return yyerror ("Bad value, 0 expected");
1142         }
1143
1144         /* Saturating.  */
1145         | a_assign REG_A LPAREN S RPAREN
1146         {
1147           if (REG_SAME ($1, $2))
1148             {
1149               notethat ("dsp32alu: Ax = Ax (S)\n");
1150               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1151             }
1152           else
1153             return yyerror ("Registers must be equal");
1154         }
1155
1156         | HALF_REG ASSIGN REG LPAREN RND RPAREN
1157         {
1158           if (IS_DREG ($3))
1159             {
1160               notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1161               $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1162             }
1163           else
1164             return yyerror ("Dregs expected");
1165         }
1166
1167         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1168         {
1169           if (IS_DREG ($3) && IS_DREG ($5))
1170             {
1171               notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1172               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1173             }
1174           else
1175             return yyerror ("Dregs expected");
1176         }
1177
1178         | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1179         {
1180           if (IS_DREG ($3) && IS_DREG ($5))
1181             {
1182               notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1183               $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1184             }
1185           else
1186             return yyerror ("Dregs expected");
1187         }
1188
1189         | a_assign REG_A
1190         {
1191           if (!REG_SAME ($1, $2))
1192             {
1193               notethat ("dsp32alu: An = Am\n");
1194               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1195             }
1196           else
1197             return yyerror ("Accu reg arguments must differ");
1198         }
1199
1200         | a_assign REG
1201         {
1202           if (IS_DREG ($2))
1203             {
1204               notethat ("dsp32alu: An = dregs\n");
1205               $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1206             }
1207           else
1208             return yyerror ("Dregs expected");
1209         }
1210
1211         | REG ASSIGN HALF_REG xpmod
1212         {
1213           if (!IS_H ($3))
1214             {
1215               if ($1.regno == REG_A0x && IS_DREG ($3))
1216                 {
1217                   notethat ("dsp32alu: A0.x = dregs_lo\n");
1218                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1219                 }
1220               else if ($1.regno == REG_A1x && IS_DREG ($3))
1221                 {
1222                   notethat ("dsp32alu: A1.x = dregs_lo\n");
1223                   $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1224                 }
1225               else if (IS_DREG ($1) && IS_DREG ($3))
1226                 {
1227                   notethat ("ALU2op: dregs = dregs_lo\n");
1228                   $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1229                 }
1230               else
1231                 return yyerror ("Register mismatch");
1232             }
1233           else
1234             return yyerror ("Low reg expected");
1235         }
1236
1237         | HALF_REG ASSIGN expr
1238         {
1239           notethat ("LDIMMhalf: pregs_half = imm16\n");
1240
1241           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1242               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1243             return yyerror ("Wrong register for load immediate");
1244
1245           if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1246             return yyerror ("Constant out of range");
1247
1248           $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1249         }
1250
1251         | a_assign expr
1252         {
1253           notethat ("dsp32alu: An = 0\n");
1254
1255           if (imm7 ($2) != 0)
1256             return yyerror ("0 expected");
1257
1258           $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1259         }
1260
1261         | REG ASSIGN expr xpmod1
1262         {
1263           if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1264               && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1265             return yyerror ("Wrong register for load immediate");
1266
1267           if ($4.r0 == 0)
1268             {
1269               /* 7 bit immediate value if possible.
1270                  We will check for that constant value for efficiency
1271                  If it goes to reloc, it will be 16 bit.  */
1272               if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1273                 {
1274                   notethat ("COMPI2opD: dregs = imm7 (x) \n");
1275                   $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1276                 }
1277               else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1278                 {
1279                   notethat ("COMPI2opP: pregs = imm7 (x)\n");
1280                   $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1281                 }
1282               else
1283                 {
1284                   if (IS_CONST ($3) && !IS_IMM ($3, 16))
1285                     return yyerror ("Immediate value out of range");
1286
1287                   notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1288                   /* reg, H, S, Z.   */
1289                   $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1290                 }
1291             }
1292           else
1293             {
1294               /* (z) There is no 7 bit zero extended instruction.
1295               If the expr is a relocation, generate it.   */
1296
1297               if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1298                 return yyerror ("Immediate value out of range");
1299
1300               notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1301               /* reg, H, S, Z.  */
1302               $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1303             }
1304         }
1305
1306         | HALF_REG ASSIGN REG
1307         {
1308           if (IS_H ($1))
1309             return yyerror ("Low reg expected");
1310
1311           if (IS_DREG ($1) && $3.regno == REG_A0x)
1312             {
1313               notethat ("dsp32alu: dregs_lo = A0.x\n");
1314               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1315             }
1316           else if (IS_DREG ($1) && $3.regno == REG_A1x)
1317             {
1318               notethat ("dsp32alu: dregs_lo = A1.x\n");
1319               $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1320             }
1321           else
1322             return yyerror ("Register mismatch");
1323         }
1324
1325         | REG ASSIGN REG op_bar_op REG amod0
1326         {
1327           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1328             {
1329               notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1330               $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1331             }
1332           else
1333             return yyerror ("Register mismatch");
1334         }
1335
1336         | REG ASSIGN BYTE_DREG xpmod
1337         {
1338           if (IS_DREG ($1) && IS_DREG ($3))
1339             {
1340               notethat ("ALU2op: dregs = dregs_byte\n");
1341               $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1342             }
1343           else
1344             return yyerror ("Register mismatch");
1345         }
1346
1347         | a_assign ABS REG_A COMMA a_assign ABS REG_A
1348         {
1349           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1350             {
1351               notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1352               $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1353             }
1354           else
1355             return yyerror ("Register mismatch");
1356         }
1357
1358         | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1359         {
1360           if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1361             {
1362               notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1363               $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1364             }
1365           else
1366             return yyerror ("Register mismatch");
1367         }
1368
1369         | a_minusassign REG_A w32_or_nothing
1370         {
1371           if (!IS_A1 ($1) && IS_A1 ($2))
1372             {
1373               notethat ("dsp32alu: A0 -= A1\n");
1374               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1375             }
1376           else
1377             return yyerror ("Register mismatch");
1378         }
1379
1380         | REG _MINUS_ASSIGN expr
1381         {
1382           if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1383             {
1384               notethat ("dagMODik: iregs -= 4\n");
1385               $$ = DAGMODIK (&$1, 3);
1386             }
1387           else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1388             {
1389               notethat ("dagMODik: iregs -= 2\n");
1390               $$ = DAGMODIK (&$1, 1);
1391             }
1392           else
1393             return yyerror ("Register or value mismatch");
1394         }
1395
1396         | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1397         {
1398           if (IS_IREG ($1) && IS_MREG ($3))
1399             {
1400               notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1401               /* i, m, op, br.  */
1402               $$ = DAGMODIM (&$1, &$3, 0, 1);
1403             }
1404           else if (IS_PREG ($1) && IS_PREG ($3))
1405             {
1406               notethat ("PTR2op: pregs += pregs (BREV )\n");
1407               $$ = PTR2OP (&$1, &$3, 5);
1408             }
1409           else
1410             return yyerror ("Register mismatch");
1411         }
1412
1413         | REG _MINUS_ASSIGN REG
1414         {
1415           if (IS_IREG ($1) && IS_MREG ($3))
1416             {
1417               notethat ("dagMODim: iregs -= mregs\n");
1418               $$ = DAGMODIM (&$1, &$3, 1, 0);
1419             }
1420           else if (IS_PREG ($1) && IS_PREG ($3))
1421             {
1422               notethat ("PTR2op: pregs -= pregs\n");
1423               $$ = PTR2OP (&$1, &$3, 0);
1424             }
1425           else
1426             return yyerror ("Register mismatch");
1427         }
1428
1429         | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1430         {
1431           if (!IS_A1 ($1) && IS_A1 ($3))
1432             {
1433               notethat ("dsp32alu: A0 += A1 (W32)\n");
1434               $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1435             }
1436           else
1437             return yyerror ("Register mismatch");
1438         }
1439
1440         | REG _PLUS_ASSIGN REG
1441         {
1442           if (IS_IREG ($1) && IS_MREG ($3))
1443             {
1444               notethat ("dagMODim: iregs += mregs\n");
1445               $$ = DAGMODIM (&$1, &$3, 0, 0);
1446             }
1447           else
1448             return yyerror ("iregs += mregs expected");
1449         }
1450
1451         | REG _PLUS_ASSIGN expr
1452         {
1453           if (IS_IREG ($1))
1454             {
1455               if (EXPR_VALUE ($3) == 4)
1456                 {
1457                   notethat ("dagMODik: iregs += 4\n");
1458                   $$ = DAGMODIK (&$1, 2);
1459                 }
1460               else if (EXPR_VALUE ($3) == 2)
1461                 {
1462                   notethat ("dagMODik: iregs += 2\n");
1463                   $$ = DAGMODIK (&$1, 0);
1464                 }
1465               else
1466                 return yyerror ("iregs += [ 2 | 4 ");
1467             }
1468           else if (IS_PREG ($1) && IS_IMM ($3, 7))
1469             {
1470               notethat ("COMPI2opP: pregs += imm7\n");
1471               $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1472             }
1473           else if (IS_DREG ($1) && IS_IMM ($3, 7))
1474             {
1475               notethat ("COMPI2opD: dregs += imm7\n");
1476               $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1477             }
1478           else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1479             return yyerror ("Immediate value out of range");
1480           else
1481             return yyerror ("Register mismatch");
1482         }
1483
1484         | REG _STAR_ASSIGN REG
1485         {
1486           if (IS_DREG ($1) && IS_DREG ($3))
1487             {
1488               notethat ("ALU2op: dregs *= dregs\n");
1489               $$ = ALU2OP (&$1, &$3, 3);
1490             }
1491           else
1492             return yyerror ("Register mismatch");
1493         }
1494
1495         | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1496         {
1497           if (!valid_dreg_pair (&$3, $5))
1498             return yyerror ("Bad dreg pair");
1499           else if (!valid_dreg_pair (&$7, $9))
1500             return yyerror ("Bad dreg pair");
1501           else
1502             {
1503               notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1504               $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1505             }
1506         }
1507
1508         | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1509         {
1510           if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1511             {
1512               notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1513               $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1514             }
1515           else
1516             return yyerror ("Register mismatch");
1517         }
1518
1519         | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1520         {
1521           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1522               && REG_SAME ($1, $4))
1523             {
1524               if (EXPR_VALUE ($9) == 1)
1525                 {
1526                   notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1527                   $$ = ALU2OP (&$1, &$6, 4);
1528                 }
1529               else if (EXPR_VALUE ($9) == 2)
1530                 {
1531                   notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1532                   $$ = ALU2OP (&$1, &$6, 5);
1533                 }
1534               else
1535                 return yyerror ("Bad shift value");
1536             }
1537           else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1538                    && REG_SAME ($1, $4))
1539             {
1540               if (EXPR_VALUE ($9) == 1)
1541                 {
1542                   notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1543                   $$ = PTR2OP (&$1, &$6, 6);
1544                 }
1545               else if (EXPR_VALUE ($9) == 2)
1546                 {
1547                   notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1548                   $$ = PTR2OP (&$1, &$6, 7);
1549                 }
1550               else
1551                 return yyerror ("Bad shift value");
1552             }
1553           else
1554             return yyerror ("Register mismatch");
1555         }
1556
1557 /*  COMP3 CCFLAG.  */
1558         | REG ASSIGN REG BAR REG
1559         {
1560           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1561             {
1562               notethat ("COMP3op: dregs = dregs | dregs\n");
1563               $$ = COMP3OP (&$1, &$3, &$5, 3);
1564             }
1565           else
1566             return yyerror ("Dregs expected");
1567         }
1568         | REG ASSIGN REG CARET REG
1569         {
1570           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1571             {
1572               notethat ("COMP3op: dregs = dregs ^ dregs\n");
1573               $$ = COMP3OP (&$1, &$3, &$5, 4);
1574             }
1575           else
1576             return yyerror ("Dregs expected");
1577         }
1578         | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1579         {
1580           if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1581             {
1582               if (EXPR_VALUE ($8) == 1)
1583                 {
1584                   notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1585                   $$ = COMP3OP (&$1, &$3, &$6, 6);
1586                 }
1587               else if (EXPR_VALUE ($8) == 2)
1588                 {
1589                   notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1590                   $$ = COMP3OP (&$1, &$3, &$6, 7);
1591                 }
1592               else
1593                   return yyerror ("Bad shift value");
1594             }
1595           else
1596             return yyerror ("Dregs expected");
1597         }
1598         | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1599         {
1600           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1601             {
1602               notethat ("CCflag: CC = A0 == A1\n");
1603               $$ = CCFLAG (0, 0, 5, 0, 0);
1604             }
1605           else
1606             return yyerror ("AREGs are in bad order or same");
1607         }
1608         | CCREG ASSIGN REG_A LESS_THAN REG_A
1609         {
1610           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1611             {
1612               notethat ("CCflag: CC = A0 < A1\n");
1613               $$ = CCFLAG (0, 0, 6, 0, 0);
1614             }
1615           else
1616             return yyerror ("AREGs are in bad order or same");
1617         }
1618         | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1619         {
1620           if ((IS_DREG ($3) && IS_DREG ($5))
1621               || (IS_PREG ($3) && IS_PREG ($5)))
1622             {
1623               notethat ("CCflag: CC = dpregs < dpregs\n");
1624               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1625             }
1626           else
1627             return yyerror ("Bad register in comparison");
1628         }
1629         | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1630         {
1631           if (!IS_DREG ($3) && !IS_PREG ($3))
1632             return yyerror ("Bad register in comparison");
1633
1634           if (($6.r0 == 1 && IS_IMM ($5, 3))
1635               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1636             {
1637               notethat ("CCflag: CC = dpregs < (u)imm3\n");
1638               $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1639             }
1640           else
1641             return yyerror ("Bad constant value");
1642         }
1643         | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1644         {
1645           if ((IS_DREG ($3) && IS_DREG ($5))
1646               || (IS_PREG ($3) && IS_PREG ($5)))
1647             {
1648               notethat ("CCflag: CC = dpregs == dpregs\n");
1649               $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1650             }
1651           else
1652             return yyerror ("Bad register in comparison");
1653         }
1654         | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1655         {
1656           if (!IS_DREG ($3) && !IS_PREG ($3))
1657             return yyerror ("Bad register in comparison");
1658
1659           if (IS_IMM ($5, 3))
1660             {
1661               notethat ("CCflag: CC = dpregs == imm3\n");
1662               $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1663             }
1664           else
1665             return yyerror ("Bad constant range");
1666         }
1667         | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1668         {
1669           if ($3.regno == REG_A0 && $5.regno == REG_A1)
1670             {
1671               notethat ("CCflag: CC = A0 <= A1\n");
1672               $$ = CCFLAG (0, 0, 7, 0, 0);
1673             }
1674           else
1675             return yyerror ("AREGs are in bad order or same");
1676         }
1677         | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1678         {
1679           if ((IS_DREG ($3) && IS_DREG ($5))
1680               || (IS_PREG ($3) && IS_PREG ($5)))
1681             {
1682               notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1683               $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1684                            1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1685             }
1686           else
1687             return yyerror ("Bad register in comparison");
1688         }
1689         | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1690         {
1691           if (!IS_DREG ($3) && !IS_PREG ($3))
1692             return yyerror ("Bad register in comparison");
1693
1694           if (($6.r0 == 1 && IS_IMM ($5, 3))
1695               || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1696             {
1697               notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1698               $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1699             }
1700           else
1701             return yyerror ("Bad constant value");
1702         }
1703
1704         | REG ASSIGN REG AMPERSAND REG
1705         {
1706           if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1707             {
1708               notethat ("COMP3op: dregs = dregs & dregs\n");
1709               $$ = COMP3OP (&$1, &$3, &$5, 2);
1710             }
1711           else
1712             return yyerror ("Dregs expected");
1713         }
1714
1715         | ccstat
1716         {
1717           notethat ("CC2stat operation\n");
1718           $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1719         }
1720
1721         | REG ASSIGN REG
1722         {
1723           if ((IS_GENREG ($1) && IS_GENREG ($3))
1724               || (IS_GENREG ($1) && IS_DAGREG ($3))
1725               || (IS_DAGREG ($1) && IS_GENREG ($3))
1726               || (IS_DAGREG ($1) && IS_DAGREG ($3))
1727               || (IS_GENREG ($1) && $3.regno == REG_USP)
1728               || ($1.regno == REG_USP && IS_GENREG ($3))
1729               || (IS_DREG ($1) && IS_SYSREG ($3))
1730               || (IS_PREG ($1) && IS_SYSREG ($3))
1731               || (IS_SYSREG ($1) && IS_DREG ($3))
1732               || (IS_SYSREG ($1) && IS_PREG ($3))
1733               || (IS_SYSREG ($1) && $3.regno == REG_USP))
1734             {
1735               $$ = bfin_gen_regmv (&$3, &$1);
1736             }
1737           else
1738             return yyerror ("Register mismatch");
1739         }
1740
1741         | CCREG ASSIGN REG
1742         {
1743           if (IS_DREG ($3))
1744             {
1745               notethat ("CC2dreg: CC = dregs\n");
1746               $$ = bfin_gen_cc2dreg (1, &$3);
1747             }
1748           else
1749             return yyerror ("Register mismatch");
1750         }
1751
1752         | REG ASSIGN CCREG
1753         {
1754           if (IS_DREG ($1))
1755             {
1756               notethat ("CC2dreg: dregs = CC\n");
1757               $$ = bfin_gen_cc2dreg (0, &$1);
1758             }
1759           else
1760             return yyerror ("Register mismatch");
1761         }
1762
1763         | CCREG _ASSIGN_BANG CCREG
1764         {
1765           notethat ("CC2dreg: CC =! CC\n");
1766           $$ = bfin_gen_cc2dreg (3, 0);
1767         }
1768
1769 /* DSPMULT.  */
1770
1771         | HALF_REG ASSIGN multiply_halfregs opt_mode
1772         {
1773           notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1774
1775           if (!IS_H ($1) && $4.MM)
1776             return yyerror ("(M) not allowed with MAC0");
1777
1778           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1779               && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1780               && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1781             return yyerror ("bad option.");
1782
1783           if (IS_H ($1))
1784             {
1785               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1786                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1787                               &$1, 0, &$3.s0, &$3.s1, 0);
1788             }
1789           else
1790             {
1791               $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1792                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1793                               &$1, 0, &$3.s0, &$3.s1, 1);
1794             }
1795         }
1796
1797         | REG ASSIGN multiply_halfregs opt_mode
1798         {
1799           /* Odd registers can use (M).  */
1800           if (!IS_DREG ($1))
1801             return yyerror ("Dreg expected");
1802
1803           if (IS_EVEN ($1) && $4.MM)
1804             return yyerror ("(M) not allowed with MAC0");
1805
1806           if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1807               && $4.mod != M_S2RND && $4.mod != M_ISS2)
1808             return yyerror ("bad option");
1809
1810           if (!IS_EVEN ($1))
1811             {
1812               notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1813
1814               $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1815                               IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1816                               &$1, 0, &$3.s0, &$3.s1, 0);
1817             }
1818           else
1819             {
1820               notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1821               $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1822                               0, 0, IS_H ($3.s0), IS_H ($3.s1),
1823                               &$1,  0, &$3.s0, &$3.s1, 1);
1824             }
1825         }
1826
1827         | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1828           HALF_REG ASSIGN multiply_halfregs opt_mode
1829         {
1830           if (!IS_DREG ($1) || !IS_DREG ($6))
1831             return yyerror ("Dregs expected");
1832
1833           if (!IS_HCOMPL($1, $6))
1834             return yyerror ("Dest registers mismatch");
1835
1836           if (check_multiply_halfregs (&$3, &$8) < 0)
1837             return -1;
1838
1839           if ((!IS_H ($1) && $4.MM)
1840               || (!IS_H ($6) && $9.MM))
1841             return yyerror ("(M) not allowed with MAC0");
1842
1843           notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1844                     "dregs_lo = multiply_halfregs opt_mode\n");
1845
1846           if (IS_H ($1))
1847             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1848                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1849                             &$1, 0, &$3.s0, &$3.s1, 1);
1850           else
1851             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1852                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1853                             &$1, 0, &$3.s0, &$3.s1, 1);
1854         }
1855
1856         | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1857         {
1858           if (!IS_DREG ($1) || !IS_DREG ($6))
1859             return yyerror ("Dregs expected");
1860
1861           if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1862               || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1863             return yyerror ("Dest registers mismatch");
1864
1865           if (check_multiply_halfregs (&$3, &$8) < 0)
1866             return -1;
1867
1868           if ((IS_EVEN ($1) && $4.MM)
1869               || (IS_EVEN ($6) && $9.MM))
1870             return yyerror ("(M) not allowed with MAC0");
1871
1872           notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1873                    "dregs = multiply_halfregs opt_mode\n");
1874
1875           if (IS_EVEN ($1))
1876             $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1877                             IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1878                             &$1, 0, &$3.s0, &$3.s1, 1);
1879           else
1880             $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1881                             IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1882                             &$1, 0, &$3.s0, &$3.s1, 1);
1883         }
1884
1885 \f
1886 /* SHIFTs.  */
1887         | a_assign ASHIFT REG_A BY HALF_REG
1888         {
1889           if (!REG_SAME ($1, $3))
1890             return yyerror ("Aregs must be same");
1891
1892           if (IS_DREG ($5) && !IS_H ($5))
1893             {
1894               notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1895               $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1896             }
1897           else
1898             return yyerror ("Dregs expected");
1899         }
1900
1901         | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1902         {
1903           if (IS_DREG ($6) && !IS_H ($6))
1904             {
1905               notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1906               $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1907             }
1908           else
1909             return yyerror ("Dregs expected");
1910         }
1911
1912         | a_assign REG_A LESS_LESS expr
1913         {
1914           if (!REG_SAME ($1, $2))
1915             return yyerror ("Aregs must be same");
1916
1917           if (IS_UIMM ($4, 5))
1918             {
1919               notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1920               $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1921             }
1922           else
1923             return yyerror ("Bad shift value");
1924         }
1925
1926         | REG ASSIGN REG LESS_LESS expr vsmod
1927         {
1928           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1929             {
1930               if ($6.r0)
1931                 {
1932                   /*  Vector?  */
1933                   notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1934                   $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1935                 }
1936               else
1937                 {
1938                   notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
1939                   $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1940                 }
1941             }
1942           else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1943             {
1944               if (EXPR_VALUE ($5) == 2)
1945                 {
1946                   notethat ("PTR2op: pregs = pregs << 2\n");
1947                   $$ = PTR2OP (&$1, &$3, 1);
1948                 }
1949               else if (EXPR_VALUE ($5) == 1)
1950                 {
1951                   notethat ("COMP3op: pregs = pregs << 1\n");
1952                   $$ = COMP3OP (&$1, &$3, &$3, 5);
1953                 }
1954               else
1955                 return yyerror ("Bad shift value");
1956             }
1957           else
1958             return yyerror ("Bad shift value or register");
1959         }
1960         | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1961         {
1962           if (IS_UIMM ($5, 4))
1963             {
1964               if ($6.s0)
1965                 {
1966                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1967                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1968                 }
1969               else
1970                 {
1971                   notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1972                   $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1973                 }
1974             }
1975           else
1976             return yyerror ("Bad shift value");
1977         }
1978         | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1979         {
1980           int op;
1981
1982           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1983             {
1984               if ($7.r0)
1985                 {
1986                   op = 1;
1987                   notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1988                            "dregs_lo (V, .)\n");
1989                 }
1990               else
1991                 {
1992
1993                   op = 2;
1994                   notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1995                 }
1996               $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1997             }
1998           else
1999             return yyerror ("Dregs expected");
2000         }
2001
2002 /*  EXPADJ.  */
2003         | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2004         {
2005           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2006             {
2007               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2008               $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2009             }
2010           else
2011             return yyerror ("Bad shift value or register");
2012         }
2013
2014
2015         | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2016         {
2017           if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2018             {
2019               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2020               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2021             }
2022           else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2023             {
2024               notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2025               $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2026             }
2027           else
2028             return yyerror ("Bad shift value or register");
2029         }
2030
2031 /* DEPOSIT.  */
2032
2033         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2034         {
2035           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2036             {
2037               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2038               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2039             }
2040           else
2041             return yyerror ("Register mismatch");
2042         }
2043
2044         | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2045         {
2046           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2047             {
2048               notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2049               $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2050             }
2051           else
2052             return yyerror ("Register mismatch");
2053         }
2054
2055         | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2056         {
2057           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2058             {
2059               notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2060               $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2061             }
2062           else
2063             return yyerror ("Register mismatch");
2064         }
2065
2066         | a_assign REG_A _GREATER_GREATER_GREATER expr
2067         {
2068           if (!REG_SAME ($1, $2))
2069             return yyerror ("Aregs must be same");
2070
2071           if (IS_UIMM ($4, 5))
2072             {
2073               notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2074               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2075             }
2076           else
2077             return yyerror ("Shift value range error");
2078         }
2079         | a_assign LSHIFT REG_A BY HALF_REG
2080         {
2081           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2082             {
2083               notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2084               $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2085             }
2086           else
2087             return yyerror ("Register mismatch");
2088         }
2089
2090         | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2091         {
2092           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2093             {
2094               notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2095               $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2096             }
2097           else
2098             return yyerror ("Register mismatch");
2099         }
2100
2101         | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2102         {
2103           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2104             {
2105               notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2106               $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2107             }
2108           else
2109             return yyerror ("Register mismatch");
2110         }
2111
2112         | REG ASSIGN SHIFT REG BY HALF_REG
2113         {
2114           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2115             {
2116               notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2117               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2118             }
2119           else
2120             return yyerror ("Register mismatch");
2121         }
2122
2123         | a_assign REG_A GREATER_GREATER expr
2124         {
2125           if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2126             {
2127               notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2128               $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2129             }
2130           else
2131             return yyerror ("Accu register expected");
2132         }
2133
2134         | REG ASSIGN REG GREATER_GREATER expr vmod
2135         {
2136           if ($6.r0 == 1)
2137             {
2138               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2139                 {
2140                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2141                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2142                 }
2143               else
2144                 return yyerror ("Register mismatch");
2145             }
2146           else
2147             {
2148               if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2149                 {
2150                   notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2151                   $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2152                 }
2153               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2154                 {
2155                   notethat ("PTR2op: pregs = pregs >> 2\n");
2156                   $$ = PTR2OP (&$1, &$3, 3);
2157                 }
2158               else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2159                 {
2160                   notethat ("PTR2op: pregs = pregs >> 1\n");
2161                   $$ = PTR2OP (&$1, &$3, 4);
2162                 }
2163               else
2164                 return yyerror ("Register mismatch");
2165             }
2166         }
2167         | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2168         {
2169           if (IS_UIMM ($5, 5))
2170             {
2171               notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
2172               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2173             }
2174           else
2175             return yyerror ("Register mismatch");
2176         }
2177         | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2178         {
2179           if (IS_UIMM ($5, 5))
2180             {
2181               notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2182               $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2183                                   $6.s0, HL2 ($1, $3));
2184             }
2185           else
2186             return yyerror ("Register or modifier mismatch");
2187         }
2188
2189
2190         | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2191         {
2192           if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2193             {
2194               if ($6.r0)
2195                 {
2196                   /* Vector?  */
2197                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
2198                   $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2199                 }
2200               else
2201                 {
2202                   notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
2203                   $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2204                 }
2205             }
2206           else
2207             return yyerror ("Register mismatch");
2208         }
2209
2210         | HALF_REG ASSIGN ONES REG
2211         {
2212           if (IS_DREG_L ($1) && IS_DREG ($4))
2213             {
2214               notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2215               $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2216             }
2217           else
2218             return yyerror ("Register mismatch");
2219         }
2220
2221         | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2222         {
2223           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2224             {
2225               notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2226               $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2227             }
2228           else
2229             return yyerror ("Register mismatch");
2230         }
2231
2232         | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2233         {
2234           if (IS_DREG ($1)
2235               && $7.regno == REG_A0
2236               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2237             {
2238               notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2239               $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2240             }
2241           else
2242             return yyerror ("Register mismatch");
2243         }
2244
2245         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2246         {
2247           if (IS_DREG ($1)
2248               && $7.regno == REG_A0
2249               && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2250             {
2251               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2252               $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2253             }
2254           else
2255             return yyerror ("Register mismatch");
2256         }
2257
2258         | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2259         {
2260           if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2261             {
2262               notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2263               $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2264             }
2265           else
2266             return yyerror ("Register mismatch");
2267         }
2268
2269         | a_assign ROT REG_A BY HALF_REG
2270         {
2271           if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2272             {
2273               notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2274               $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2275             }
2276           else
2277             return yyerror ("Register mismatch");
2278         }
2279
2280         | REG ASSIGN ROT REG BY HALF_REG
2281         {
2282           if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2283             {
2284               notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2285               $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2286             }
2287           else
2288             return yyerror ("Register mismatch");
2289         }
2290
2291         | a_assign ROT REG_A BY expr
2292         {
2293           if (IS_IMM ($5, 6))
2294             {
2295               notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2296               $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2297             }
2298           else
2299             return yyerror ("Register mismatch");
2300         }
2301
2302         | REG ASSIGN ROT REG BY expr
2303         {
2304           if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2305             {
2306               $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2307             }
2308           else
2309             return yyerror ("Register mismatch");
2310         }
2311
2312         | HALF_REG ASSIGN SIGNBITS REG_A
2313         {
2314           if (IS_DREG_L ($1))
2315             {
2316               notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2317               $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2318             }
2319           else
2320             return yyerror ("Register mismatch");
2321         }
2322
2323         | HALF_REG ASSIGN SIGNBITS REG
2324         {
2325           if (IS_DREG_L ($1) && IS_DREG ($4))
2326             {
2327               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2328               $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2329             }
2330           else
2331             return yyerror ("Register mismatch");
2332         }
2333
2334         | HALF_REG ASSIGN SIGNBITS HALF_REG
2335         {
2336           if (IS_DREG_L ($1))
2337             {
2338               notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2339               $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2340             }
2341           else
2342             return yyerror ("Register mismatch");
2343         }
2344
2345         /* The ASR bit is just inverted here. */
2346         | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2347         {
2348           if (IS_DREG_L ($1) && IS_DREG ($5))
2349             {
2350               notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2351               $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2352             }
2353           else
2354             return yyerror ("Register mismatch");
2355         }
2356
2357         | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2358         {
2359           if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2360             {
2361               notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2362               $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2363             }
2364           else
2365             return yyerror ("Register mismatch");
2366         }
2367
2368         | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2369         {
2370           if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2371             {
2372               notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2373               $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2374             }
2375           else
2376             return yyerror ("Register mismatch");
2377         }
2378
2379         | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2380         {
2381           if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2382             {
2383               notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2384               $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2385             }
2386           else
2387             return yyerror ("Dregs expected");
2388         }
2389
2390
2391 /* LOGI2op:     BITCLR (dregs, uimm5).  */
2392         | BITCLR LPAREN REG COMMA expr RPAREN
2393         {
2394           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2395             {
2396               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2397               $$ = LOGI2OP ($3, uimm5 ($5), 4);
2398             }
2399           else
2400             return yyerror ("Register mismatch");
2401         }
2402
2403 /* LOGI2op:     BITSET (dregs, uimm5).  */
2404         | BITSET LPAREN REG COMMA expr RPAREN
2405         {
2406           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2407             {
2408               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2409               $$ = LOGI2OP ($3, uimm5 ($5), 2);
2410             }
2411           else
2412             return yyerror ("Register mismatch");
2413         }
2414
2415 /* LOGI2op:     BITTGL (dregs, uimm5).  */
2416         | BITTGL LPAREN REG COMMA expr RPAREN
2417         {
2418           if (IS_DREG ($3) && IS_UIMM ($5, 5))
2419             {
2420               notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2421               $$ = LOGI2OP ($3, uimm5 ($5), 3);
2422             }
2423           else
2424             return yyerror ("Register mismatch");
2425         }
2426
2427         | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2428         {
2429           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2430             {
2431               notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2432               $$ = LOGI2OP ($5, uimm5 ($7), 0);
2433             }
2434           else
2435             return yyerror ("Register mismatch or value error");
2436         }
2437
2438         | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2439         {
2440           if (IS_DREG ($5) && IS_UIMM ($7, 5))
2441             {
2442               notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2443               $$ = LOGI2OP ($5, uimm5 ($7), 1);
2444             }
2445           else
2446             return yyerror ("Register mismatch or value error");
2447         }
2448
2449         | IF BANG CCREG REG ASSIGN REG
2450         {
2451           if ((IS_DREG ($4) || IS_PREG ($4))
2452               && (IS_DREG ($6) || IS_PREG ($6)))
2453             {
2454               notethat ("ccMV: IF ! CC gregs = gregs\n");
2455               $$ = CCMV (&$6, &$4, 0);
2456             }
2457           else
2458             return yyerror ("Register mismatch");
2459         }
2460
2461         | IF CCREG REG ASSIGN REG
2462         {
2463           if ((IS_DREG ($5) || IS_PREG ($5))
2464               && (IS_DREG ($3) || IS_PREG ($3)))
2465             {
2466               notethat ("ccMV: IF CC gregs = gregs\n");
2467               $$ = CCMV (&$5, &$3, 1);
2468             }
2469           else
2470             return yyerror ("Register mismatch");
2471         }
2472
2473         | IF BANG CCREG JUMP expr
2474         {
2475           if (IS_PCREL10 ($5))
2476             {
2477               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2478               $$ = BRCC (0, 0, $5);
2479             }
2480           else
2481             return yyerror ("Bad jump offset");
2482         }
2483
2484         | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2485         {
2486           if (IS_PCREL10 ($5))
2487             {
2488               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2489               $$ = BRCC (0, 1, $5);
2490             }
2491           else
2492             return yyerror ("Bad jump offset");
2493         }
2494
2495         | IF CCREG JUMP expr
2496         {
2497           if (IS_PCREL10 ($4))
2498             {
2499               notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
2500               $$ = BRCC (1, 0, $4);
2501             }
2502           else
2503             return yyerror ("Bad jump offset");
2504         }
2505
2506         | IF CCREG JUMP expr LPAREN BP RPAREN
2507         {
2508           if (IS_PCREL10 ($4))
2509             {
2510               notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
2511               $$ = BRCC (1, 1, $4);
2512             }
2513           else
2514             return yyerror ("Bad jump offset");
2515         }
2516         | NOP
2517         {
2518           notethat ("ProgCtrl: NOP\n");
2519           $$ = PROGCTRL (0, 0);
2520         }
2521
2522         | RTS
2523         {
2524           notethat ("ProgCtrl: RTS\n");
2525           $$ = PROGCTRL (1, 0);
2526         }
2527
2528         | RTI
2529         {
2530           notethat ("ProgCtrl: RTI\n");
2531           $$ = PROGCTRL (1, 1);
2532         }
2533
2534         | RTX
2535         {
2536           notethat ("ProgCtrl: RTX\n");
2537           $$ = PROGCTRL (1, 2);
2538         }
2539
2540         | RTN
2541         {
2542           notethat ("ProgCtrl: RTN\n");
2543           $$ = PROGCTRL (1, 3);
2544         }
2545
2546         | RTE
2547         {
2548           notethat ("ProgCtrl: RTE\n");
2549           $$ = PROGCTRL (1, 4);
2550         }
2551
2552         | IDLE
2553         {
2554           notethat ("ProgCtrl: IDLE\n");
2555           $$ = PROGCTRL (2, 0);
2556         }
2557
2558         | CSYNC
2559         {
2560           notethat ("ProgCtrl: CSYNC\n");
2561           $$ = PROGCTRL (2, 3);
2562         }
2563
2564         | SSYNC
2565         {
2566           notethat ("ProgCtrl: SSYNC\n");
2567           $$ = PROGCTRL (2, 4);
2568         }
2569
2570         | EMUEXCPT
2571         {
2572           notethat ("ProgCtrl: EMUEXCPT\n");
2573           $$ = PROGCTRL (2, 5);
2574         }
2575
2576         | CLI REG
2577         {
2578           if (IS_DREG ($2))
2579             {
2580               notethat ("ProgCtrl: CLI dregs\n");
2581               $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2582             }
2583           else
2584             return yyerror ("Dreg expected for CLI");
2585         }
2586
2587         | STI REG
2588         {
2589           if (IS_DREG ($2))
2590             {
2591               notethat ("ProgCtrl: STI dregs\n");
2592               $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2593             }
2594           else
2595             return yyerror ("Dreg expected for STI");
2596         }
2597
2598         | JUMP LPAREN REG RPAREN
2599         {
2600           if (IS_PREG ($3))
2601             {
2602               notethat ("ProgCtrl: JUMP (pregs )\n");
2603               $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2604             }
2605           else
2606             return yyerror ("Bad register for indirect jump");
2607         }
2608
2609         | CALL LPAREN REG RPAREN
2610         {
2611           if (IS_PREG ($3))
2612             {
2613               notethat ("ProgCtrl: CALL (pregs )\n");
2614               $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2615             }
2616           else
2617             return yyerror ("Bad register for indirect call");
2618         }
2619
2620         | CALL LPAREN PC PLUS REG RPAREN
2621         {
2622           if (IS_PREG ($5))
2623             {
2624               notethat ("ProgCtrl: CALL (PC + pregs )\n");
2625               $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2626             }
2627           else
2628             return yyerror ("Bad register for indirect call");
2629         }
2630
2631         | JUMP LPAREN PC PLUS REG RPAREN
2632         {
2633           if (IS_PREG ($5))
2634             {
2635               notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2636               $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2637             }
2638           else
2639             return yyerror ("Bad register for indirect jump");
2640         }
2641
2642         | RAISE expr
2643         {
2644           if (IS_UIMM ($2, 4))
2645             {
2646               notethat ("ProgCtrl: RAISE uimm4\n");
2647               $$ = PROGCTRL (9, uimm4 ($2));
2648             }
2649           else
2650             return yyerror ("Bad value for RAISE");
2651         }
2652
2653         | EXCPT expr
2654         {
2655                 notethat ("ProgCtrl: EMUEXCPT\n");
2656                 $$ = PROGCTRL (10, uimm4 ($2));
2657         }
2658
2659         | TESTSET LPAREN REG RPAREN
2660         {
2661           if (IS_PREG ($3))
2662             {
2663               notethat ("ProgCtrl: TESTSET (pregs )\n");
2664               $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2665             }
2666           else
2667             return yyerror ("Preg expected");
2668         }
2669
2670         | JUMP expr
2671         {
2672           if (IS_PCREL12 ($2))
2673             {
2674               notethat ("UJUMP: JUMP pcrel12\n");
2675               $$ = UJUMP ($2);
2676             }
2677           else
2678             return yyerror ("Bad value for relative jump");
2679         }
2680
2681         | JUMP_DOT_S expr
2682         {
2683           if (IS_PCREL12 ($2))
2684             {
2685               notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2686               $$ = UJUMP($2);
2687             }
2688           else
2689             return yyerror ("Bad value for relative jump");
2690         }
2691
2692         | JUMP_DOT_L expr
2693         {
2694           if (IS_PCREL24 ($2))
2695             {
2696               notethat ("CALLa: jump.l pcrel24\n");
2697               $$ = CALLA ($2, 0);
2698             }
2699           else
2700             return yyerror ("Bad value for long jump");
2701         }
2702
2703         | JUMP_DOT_L pltpc
2704         {
2705           if (IS_PCREL24 ($2))
2706             {
2707               notethat ("CALLa: jump.l pcrel24\n");
2708               $$ = CALLA ($2, 2);
2709             }
2710           else
2711             return yyerror ("Bad value for long jump");
2712         }
2713
2714         | CALL expr
2715         {
2716           if (IS_PCREL24 ($2))
2717             {
2718               notethat ("CALLa: CALL pcrel25m2\n");
2719               $$ = CALLA ($2, 1);
2720             }
2721           else
2722             return yyerror ("Bad call address");
2723         }
2724         | CALL pltpc
2725         {
2726           if (IS_PCREL24 ($2))
2727             {
2728               notethat ("CALLa: CALL pcrel25m2\n");
2729               $$ = CALLA ($2, 2);
2730             }
2731           else
2732             return yyerror ("Bad call address");
2733         }
2734
2735 /* ALU2ops.  */
2736 /* ALU2op:      DIVQ (dregs, dregs).  */
2737         | DIVQ LPAREN REG COMMA REG RPAREN
2738         {
2739           if (IS_DREG ($3) && IS_DREG ($5))
2740             $$ = ALU2OP (&$3, &$5, 8);
2741           else
2742             return yyerror ("Bad registers for DIVQ");
2743         }
2744
2745         | DIVS LPAREN REG COMMA REG RPAREN
2746         {
2747           if (IS_DREG ($3) && IS_DREG ($5))
2748             $$ = ALU2OP (&$3, &$5, 9);
2749           else
2750             return yyerror ("Bad registers for DIVS");
2751         }
2752
2753         | REG ASSIGN MINUS REG vsmod
2754         {
2755           if (IS_DREG ($1) && IS_DREG ($4))
2756             {
2757               if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2758                 {
2759                   notethat ("ALU2op: dregs = - dregs\n");
2760                   $$ = ALU2OP (&$1, &$4, 14);
2761                 }
2762               else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2763                 {
2764                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2765                   $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2766                 }
2767               else
2768                 {
2769                   notethat ("dsp32alu: dregs = - dregs (.)\n");
2770                   $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2771                 }
2772             }
2773           else
2774             return yyerror ("Dregs expected");
2775         }
2776
2777         | REG ASSIGN TILDA REG
2778         {
2779           if (IS_DREG ($1) && IS_DREG ($4))
2780             {
2781               notethat ("ALU2op: dregs = ~dregs\n");
2782               $$ = ALU2OP (&$1, &$4, 15);
2783             }
2784           else
2785             return yyerror ("Dregs expected");
2786         }
2787
2788         | REG _GREATER_GREATER_ASSIGN REG
2789         {
2790           if (IS_DREG ($1) && IS_DREG ($3))
2791             {
2792               notethat ("ALU2op: dregs >>= dregs\n");
2793               $$ = ALU2OP (&$1, &$3, 1);
2794             }
2795           else
2796             return yyerror ("Dregs expected");
2797         }
2798
2799         | REG _GREATER_GREATER_ASSIGN expr
2800         {
2801           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2802             {
2803               notethat ("LOGI2op: dregs >>= uimm5\n");
2804               $$ = LOGI2OP ($1, uimm5 ($3), 6);
2805             }
2806           else
2807             return yyerror ("Dregs expected or value error");
2808         }
2809
2810         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2811         {
2812           if (IS_DREG ($1) && IS_DREG ($3))
2813             {
2814               notethat ("ALU2op: dregs >>>= dregs\n");
2815               $$ = ALU2OP (&$1, &$3, 0);
2816             }
2817           else
2818             return yyerror ("Dregs expected");
2819         }
2820
2821         | REG _LESS_LESS_ASSIGN REG
2822         {
2823           if (IS_DREG ($1) && IS_DREG ($3))
2824             {
2825               notethat ("ALU2op: dregs <<= dregs\n");
2826               $$ = ALU2OP (&$1, &$3, 2);
2827             }
2828           else
2829             return yyerror ("Dregs expected");
2830         }
2831
2832         | REG _LESS_LESS_ASSIGN expr
2833         {
2834           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2835             {
2836               notethat ("LOGI2op: dregs <<= uimm5\n");
2837               $$ = LOGI2OP ($1, uimm5 ($3), 7);
2838             }
2839           else
2840             return yyerror ("Dregs expected or const value error");
2841         }
2842
2843
2844         | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2845         {
2846           if (IS_DREG ($1) && IS_UIMM ($3, 5))
2847             {
2848               notethat ("LOGI2op: dregs >>>= uimm5\n");
2849               $$ = LOGI2OP ($1, uimm5 ($3), 5);
2850             }
2851           else
2852             return yyerror ("Dregs expected");
2853         }
2854
2855 /* Cache Control.  */
2856
2857         | FLUSH LBRACK REG RBRACK
2858         {
2859           notethat ("CaCTRL: FLUSH [ pregs ]\n");
2860           if (IS_PREG ($3))
2861             $$ = CACTRL (&$3, 0, 2);
2862           else
2863             return yyerror ("Bad register(s) for FLUSH");
2864         }
2865
2866         | FLUSH reg_with_postinc
2867         {
2868           if (IS_PREG ($2))
2869             {
2870               notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2871               $$ = CACTRL (&$2, 1, 2);
2872             }
2873           else
2874             return yyerror ("Bad register(s) for FLUSH");
2875         }
2876
2877         | FLUSHINV LBRACK REG RBRACK
2878         {
2879           if (IS_PREG ($3))
2880             {
2881               notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2882               $$ = CACTRL (&$3, 0, 1);
2883             }
2884           else
2885             return yyerror ("Bad register(s) for FLUSH");
2886         }
2887
2888         | FLUSHINV reg_with_postinc
2889         {
2890           if (IS_PREG ($2))
2891             {
2892               notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2893               $$ = CACTRL (&$2, 1, 1);
2894             }
2895           else
2896             return yyerror ("Bad register(s) for FLUSH");
2897         }
2898
2899 /* CaCTRL:      IFLUSH [pregs].  */
2900         | IFLUSH LBRACK REG RBRACK
2901         {
2902           if (IS_PREG ($3))
2903             {
2904               notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2905               $$ = CACTRL (&$3, 0, 3);
2906             }
2907           else
2908             return yyerror ("Bad register(s) for FLUSH");
2909         }
2910
2911         | IFLUSH reg_with_postinc
2912         {
2913           if (IS_PREG ($2))
2914             {
2915               notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2916               $$ = CACTRL (&$2, 1, 3);
2917             }
2918           else
2919             return yyerror ("Bad register(s) for FLUSH");
2920         }
2921
2922         | PREFETCH LBRACK REG RBRACK
2923         {
2924           if (IS_PREG ($3))
2925             {
2926               notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2927               $$ = CACTRL (&$3, 0, 0);
2928             }
2929           else
2930             return yyerror ("Bad register(s) for PREFETCH");
2931         }
2932
2933         | PREFETCH reg_with_postinc
2934         {
2935           if (IS_PREG ($2))
2936             {
2937               notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2938               $$ = CACTRL (&$2, 1, 0);
2939             }
2940           else
2941             return yyerror ("Bad register(s) for PREFETCH");
2942         }
2943
2944 /* LOAD/STORE.  */
2945 /* LDST:        B [ pregs <post_op> ] = dregs.  */
2946
2947         | B LBRACK REG post_op RBRACK ASSIGN REG
2948         {
2949           if (!IS_DREG ($7))
2950             return yyerror ("Dreg expected for source operand");
2951           if (!IS_PREG ($3))
2952             return yyerror ("Preg expected in address");
2953
2954           notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2955           $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2956         }
2957
2958 /* LDSTidxI:    B [ pregs + imm16 ] = dregs.  */
2959         | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2960         {
2961           Expr_Node *tmp = $5;
2962
2963           if (!IS_DREG ($8))
2964             return yyerror ("Dreg expected for source operand");
2965           if (!IS_PREG ($3))
2966             return yyerror ("Preg expected in address");
2967
2968           if (IS_RELOC ($5))
2969             return yyerror ("Plain symbol used as offset");
2970
2971           if ($4.r0)
2972             tmp = unary (Expr_Op_Type_NEG, tmp);
2973
2974           if (in_range_p (tmp, -32768, 32767, 0))
2975             {
2976               notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2977               $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2978             }
2979           else
2980             return yyerror ("Displacement out of range");
2981         }
2982
2983
2984 /* LDSTii:      W [ pregs + uimm4s2 ] = dregs.  */
2985         | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2986         {
2987           Expr_Node *tmp = $5;
2988
2989           if (!IS_DREG ($8))
2990             return yyerror ("Dreg expected for source operand");
2991           if (!IS_PREG ($3))
2992             return yyerror ("Preg expected in address");
2993
2994           if ($4.r0)
2995             tmp = unary (Expr_Op_Type_NEG, tmp);
2996
2997           if (IS_RELOC ($5))
2998             return yyerror ("Plain symbol used as offset");
2999
3000           if (in_range_p (tmp, 0, 30, 1))
3001             {
3002               notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3003               $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3004             }
3005           else if (in_range_p (tmp, -65536, 65535, 1))
3006             {
3007               notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3008               $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3009             }
3010           else
3011             return yyerror ("Displacement out of range");
3012         }
3013
3014 /* LDST:        W [ pregs <post_op> ] = dregs.  */
3015         | W LBRACK REG post_op RBRACK ASSIGN REG
3016         {
3017           if (!IS_DREG ($7))
3018             return yyerror ("Dreg expected for source operand");
3019           if (!IS_PREG ($3))
3020             return yyerror ("Preg expected in address");
3021
3022           notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3023           $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3024         }
3025
3026         | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3027         {
3028           if (!IS_DREG ($7))
3029             return yyerror ("Dreg expected for source operand");
3030           if ($4.x0 == 2)
3031             {
3032               if (!IS_IREG ($3) && !IS_PREG ($3))
3033                 return yyerror ("Ireg or Preg expected in address");
3034             }
3035           else if (!IS_IREG ($3))
3036             return yyerror ("Ireg expected in address");
3037
3038           if (IS_IREG ($3))
3039             {
3040               notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3041               $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3042             }
3043           else
3044             {
3045               notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3046               $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3047             }
3048         }
3049
3050 /* LDSTiiFP:    [ FP - const ] = dpregs.  */
3051         | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3052         {
3053           Expr_Node *tmp = $4;
3054           int ispreg = IS_PREG ($7);
3055
3056           if (!IS_PREG ($2))
3057             return yyerror ("Preg expected in address");
3058
3059           if (!IS_DREG ($7) && !ispreg)
3060             return yyerror ("Preg expected for source operand");
3061
3062           if ($3.r0)
3063             tmp = unary (Expr_Op_Type_NEG, tmp);
3064
3065           if (IS_RELOC ($4))
3066             return yyerror ("Plain symbol used as offset");
3067
3068           if (in_range_p (tmp, 0, 63, 3))
3069             {
3070               notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3071               $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3072             }
3073           else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3074             {
3075               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3076               tmp = unary (Expr_Op_Type_NEG, tmp);
3077               $$ = LDSTIIFP (tmp, &$7, 1);
3078             }
3079           else if (in_range_p (tmp, -131072, 131071, 3))
3080             {
3081               notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3082               $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3083             }
3084           else
3085             return yyerror ("Displacement out of range");
3086         }
3087
3088         | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3089         {
3090           Expr_Node *tmp = $7;
3091           if (!IS_DREG ($1))
3092             return yyerror ("Dreg expected for destination operand");
3093           if (!IS_PREG ($5))
3094             return yyerror ("Preg expected in address");
3095
3096           if ($6.r0)
3097             tmp = unary (Expr_Op_Type_NEG, tmp);
3098
3099           if (IS_RELOC ($7))
3100             return yyerror ("Plain symbol used as offset");
3101
3102           if (in_range_p (tmp, 0, 30, 1))
3103             {
3104               notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3105               $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3106             }
3107           else if (in_range_p (tmp, -65536, 65535, 1))
3108             {
3109               notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3110               $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3111             }
3112           else
3113             return yyerror ("Displacement out of range");
3114         }
3115
3116         | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3117         {
3118           if (!IS_DREG ($1))
3119             return yyerror ("Dreg expected for source operand");
3120           if ($6.x0 == 2)
3121             {
3122               if (!IS_IREG ($5) && !IS_PREG ($5))
3123                 return yyerror ("Ireg or Preg expected in address");
3124             }
3125           else if (!IS_IREG ($5))
3126             return yyerror ("Ireg expected in address");
3127
3128           if (IS_IREG ($5))
3129             {
3130               notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3131               $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3132             }
3133           else
3134             {
3135               notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3136               $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3137             }
3138         }
3139
3140
3141         | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3142         {
3143           if (!IS_DREG ($1))
3144             return yyerror ("Dreg expected for destination operand");
3145           if (!IS_PREG ($5))
3146             return yyerror ("Preg expected in address");
3147
3148           notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3149           $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3150         }
3151
3152         | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3153         {
3154           if (!IS_DREG ($1))
3155             return yyerror ("Dreg expected for destination operand");
3156           if (!IS_PREG ($5) || !IS_PREG ($7))
3157             return yyerror ("Preg expected in address");
3158
3159           notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3160           $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3161         }
3162
3163         | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3164         {
3165           if (!IS_DREG ($1))
3166             return yyerror ("Dreg expected for destination operand");
3167           if (!IS_PREG ($5) || !IS_PREG ($7))
3168             return yyerror ("Preg expected in address");
3169
3170           notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3171           $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3172         }
3173
3174         | LBRACK REG post_op RBRACK ASSIGN REG
3175         {
3176           if (!IS_IREG ($2) && !IS_PREG ($2))
3177             return yyerror ("Ireg or Preg expected in address");
3178           else if (IS_IREG ($2) && !IS_DREG ($6))
3179             return yyerror ("Dreg expected for source operand");
3180           else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3181             return yyerror ("Dreg or Preg expected for source operand");
3182
3183           if (IS_IREG ($2))
3184             {
3185               notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3186               $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3187             }
3188           else if (IS_DREG ($6))
3189             {
3190               notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3191               $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3192             }
3193           else
3194             {
3195               notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3196               $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3197             }
3198         }
3199
3200         | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3201         {
3202           if (!IS_DREG ($7))
3203             return yyerror ("Dreg expected for source operand");
3204
3205           if (IS_IREG ($2) && IS_MREG ($4))
3206             {
3207               notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3208               $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3209             }
3210           else if (IS_PREG ($2) && IS_PREG ($4))
3211             {
3212               notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3213               $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3214             }
3215           else
3216             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3217         }
3218
3219         | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3220         {
3221           if (!IS_DREG ($8))
3222             return yyerror ("Dreg expected for source operand");
3223
3224           if (IS_PREG ($3) && IS_PREG ($5))
3225             {
3226               notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3227               $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3228             }
3229           else
3230             return yyerror ("Preg ++ Preg expected in address");
3231         }
3232
3233         | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3234         {
3235           Expr_Node *tmp = $7;
3236           if (!IS_DREG ($1))
3237             return yyerror ("Dreg expected for destination operand");
3238           if (!IS_PREG ($5))
3239             return yyerror ("Preg expected in address");
3240
3241           if ($6.r0)
3242             tmp = unary (Expr_Op_Type_NEG, tmp);
3243
3244           if (IS_RELOC ($7))
3245             return yyerror ("Plain symbol used as offset");
3246
3247           if (in_range_p (tmp, -32768, 32767, 0))
3248             {
3249               notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3250                        $9.r0 ? 'X' : 'Z');
3251               $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3252             }
3253           else
3254             return yyerror ("Displacement out of range");
3255         }
3256
3257         | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3258         {
3259           if (!IS_DREG ($1))
3260             return yyerror ("Dreg expected for destination operand");
3261           if (!IS_PREG ($5))
3262             return yyerror ("Preg expected in address");
3263
3264           notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3265                     $8.r0 ? 'X' : 'Z');
3266           $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3267         }
3268
3269         | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3270         {
3271           if (!IS_DREG ($1))
3272             return yyerror ("Dreg expected for destination operand");
3273
3274           if (IS_IREG ($4) && IS_MREG ($6))
3275             {
3276               notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3277               $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3278             }
3279           else if (IS_PREG ($4) && IS_PREG ($6))
3280             {
3281               notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3282               $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3283             }
3284           else
3285             return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3286         }
3287
3288         | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3289         {
3290           Expr_Node *tmp = $6;
3291           int ispreg = IS_PREG ($1);
3292           int isgot = IS_RELOC($6);
3293
3294           if (!IS_PREG ($4))
3295             return yyerror ("Preg expected in address");
3296
3297           if (!IS_DREG ($1) && !ispreg)
3298             return yyerror ("Dreg or Preg expected for destination operand");
3299
3300           if (tmp->type == Expr_Node_Reloc
3301               && strcmp (tmp->value.s_value,
3302                          "_current_shared_library_p5_offset_") != 0)
3303             return yyerror ("Plain symbol used as offset");
3304
3305           if ($5.r0)
3306             tmp = unary (Expr_Op_Type_NEG, tmp);
3307
3308           if (isgot)
3309             {
3310               notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3311               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3312             }
3313           else if (in_range_p (tmp, 0, 63, 3))
3314             {
3315               notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3316               $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3317             }
3318           else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3319             {
3320               notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3321               tmp = unary (Expr_Op_Type_NEG, tmp);
3322               $$ = LDSTIIFP (tmp, &$1, 0);
3323             }
3324           else if (in_range_p (tmp, -131072, 131071, 3))
3325             {
3326               notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3327               $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3328
3329             }
3330           else
3331             return yyerror ("Displacement out of range");
3332         }
3333
3334         | REG ASSIGN LBRACK REG post_op RBRACK
3335         {
3336           if (!IS_IREG ($4) && !IS_PREG ($4))
3337             return yyerror ("Ireg or Preg expected in address");
3338           else if (IS_IREG ($4) && !IS_DREG ($1))
3339             return yyerror ("Dreg expected in destination operand");
3340           else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3341                    && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3342             return yyerror ("Dreg or Preg expected in destination operand");
3343
3344           if (IS_IREG ($4))
3345             {
3346               notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3347               $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3348             }
3349           else if (IS_DREG ($1))
3350             {
3351               notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3352               $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3353             }
3354           else if (IS_PREG ($1))
3355             {
3356               if (REG_SAME ($1, $4) && $5.x0 != 2)
3357                 return yyerror ("Pregs can't be same");
3358
3359               notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3360               $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3361             }
3362           else
3363             {
3364               notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3365               $$ = PUSHPOPREG (&$1, 0);
3366             }
3367         }
3368
3369
3370 /*  PushPopMultiple.  */
3371         | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3372         {
3373           if ($1.regno != REG_SP)
3374             yyerror ("Stack Pointer expected");
3375           if ($4.regno == REG_R7
3376               && IN_RANGE ($6, 0, 7)
3377               && $8.regno == REG_P5
3378               && IN_RANGE ($10, 0, 5))
3379             {
3380               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3381               $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3382             }
3383           else
3384             return yyerror ("Bad register for PushPopMultiple");
3385         }
3386
3387         | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3388         {
3389           if ($1.regno != REG_SP)
3390             yyerror ("Stack Pointer expected");
3391
3392           if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3393             {
3394               notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3395               $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3396             }
3397           else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3398             {
3399               notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3400               $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3401             }
3402           else
3403             return yyerror ("Bad register for PushPopMultiple");
3404         }
3405
3406         | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3407         {
3408           if ($11.regno != REG_SP)
3409             yyerror ("Stack Pointer expected");
3410           if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3411               && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3412             {
3413               notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3414               $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3415             }
3416           else
3417             return yyerror ("Bad register range for PushPopMultiple");
3418         }
3419
3420         | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3421         {
3422           if ($7.regno != REG_SP)
3423             yyerror ("Stack Pointer expected");
3424
3425           if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3426             {
3427               notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3428               $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3429             }
3430           else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3431             {
3432               notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3433               $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3434             }
3435           else
3436             return yyerror ("Bad register range for PushPopMultiple");
3437         }
3438
3439         | reg_with_predec ASSIGN REG
3440         {
3441           if ($1.regno != REG_SP)
3442             yyerror ("Stack Pointer expected");
3443
3444           if (IS_ALLREG ($3))
3445             {
3446               notethat ("PushPopReg: [ -- SP ] = allregs\n");
3447               $$ = PUSHPOPREG (&$3, 1);
3448             }
3449           else
3450             return yyerror ("Bad register for PushPopReg");
3451         }
3452
3453 /* Linkage.  */
3454
3455         | LINK expr
3456         {
3457           if (IS_URANGE (16, $2, 0, 4))
3458             $$ = LINKAGE (0, uimm16s4 ($2));
3459           else
3460             return yyerror ("Bad constant for LINK");
3461         }
3462
3463         | UNLINK
3464         {
3465                 notethat ("linkage: UNLINK\n");
3466                 $$ = LINKAGE (1, 0);
3467         }
3468
3469
3470 /* LSETUP.  */
3471
3472         | LSETUP LPAREN expr COMMA expr RPAREN REG
3473         {
3474           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3475             {
3476               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3477               $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3478             }
3479           else
3480             return yyerror ("Bad register or values for LSETUP");
3481
3482         }
3483         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3484         {
3485           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3486               && IS_PREG ($9) && IS_CREG ($7))
3487             {
3488               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3489               $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3490             }
3491           else
3492             return yyerror ("Bad register or values for LSETUP");
3493         }
3494
3495         | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3496         {
3497           if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3498               && IS_PREG ($9) && IS_CREG ($7)
3499               && EXPR_VALUE ($11) == 1)
3500             {
3501               notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3502               $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3503             }
3504           else
3505             return yyerror ("Bad register or values for LSETUP");
3506         }
3507
3508 /* LOOP.  */
3509         | LOOP expr REG
3510         {
3511           if (!IS_RELOC ($2))
3512             return yyerror ("Invalid expression in loop statement");
3513           if (!IS_CREG ($3))
3514             return yyerror ("Invalid loop counter register");
3515         $$ = bfin_gen_loop ($2, &$3, 0, 0);
3516         }
3517         | LOOP expr REG ASSIGN REG
3518         {
3519           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3520             {
3521               notethat ("Loop: LOOP expr counters = pregs\n");
3522               $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3523             }
3524           else
3525             return yyerror ("Bad register or values for LOOP");
3526         }
3527         | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3528         {
3529           if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3530             {
3531               notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3532               $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3533             }
3534           else
3535             return yyerror ("Bad register or values for LOOP");
3536         }
3537
3538 /* LOOP_BEGIN.  */
3539         | LOOP_BEGIN expr
3540         {
3541           if (!IS_RELOC ($2))
3542             return yyerror ("Invalid expression in LOOP_BEGIN statement");
3543
3544           bfin_loop_beginend ($2, 1);
3545           $$ = 0;
3546         }
3547
3548 /* LOOP_END.  */
3549         | LOOP_END expr
3550         {
3551           if (!IS_RELOC ($2))
3552             return yyerror ("Invalid expression in LOOP_END statement");
3553
3554           bfin_loop_beginend ($2, 0);
3555           $$ = 0;
3556         }
3557
3558 /* pseudoDEBUG.  */
3559
3560         | DBG
3561         {
3562           notethat ("pseudoDEBUG: DBG\n");
3563           $$ = bfin_gen_pseudodbg (3, 7, 0);
3564         }
3565         | DBG REG_A
3566         {
3567           notethat ("pseudoDEBUG: DBG REG_A\n");
3568           $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3569         }
3570         | DBG REG
3571         {
3572           notethat ("pseudoDEBUG: DBG allregs\n");
3573           $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3574         }
3575
3576         | DBGCMPLX LPAREN REG RPAREN
3577         {
3578           if (!IS_DREG ($3))
3579             return yyerror ("Dregs expected");
3580           notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3581           $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3582         }
3583
3584         | DBGHALT
3585         {
3586           notethat ("psedoDEBUG: DBGHALT\n");
3587           $$ = bfin_gen_pseudodbg (3, 5, 0);
3588         }
3589
3590         | DBGA LPAREN HALF_REG COMMA expr RPAREN
3591         {
3592           notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3593           $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3594         }
3595
3596         | DBGAH LPAREN REG COMMA expr RPAREN
3597         {
3598           notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3599           $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3600         }
3601
3602         | DBGAL LPAREN REG COMMA expr RPAREN
3603         {
3604           notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3605           $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3606         }
3607
3608
3609 ;
3610
3611 /*  AUX RULES.  */
3612
3613 /*  Register rules.  */
3614
3615 REG_A:  REG_A_DOUBLE_ZERO
3616         {
3617         $$ = $1;
3618         }
3619         | REG_A_DOUBLE_ONE
3620         {
3621         $$ = $1;
3622         }
3623         ;
3624
3625
3626 /*  Modifiers. */
3627
3628 opt_mode:
3629         {
3630         $$.MM = 0;
3631         $$.mod = 0;
3632         }
3633         | LPAREN M COMMA MMOD RPAREN
3634         {
3635         $$.MM = 1;
3636         $$.mod = $4;
3637         }
3638         | LPAREN MMOD COMMA M RPAREN
3639         {
3640         $$.MM = 1;
3641         $$.mod = $2;
3642         }
3643         | LPAREN MMOD RPAREN
3644         {
3645         $$.MM = 0;
3646         $$.mod = $2;
3647         }
3648         | LPAREN M RPAREN
3649         {
3650         $$.MM = 1;
3651         $$.mod = 0;
3652         }
3653         ;
3654
3655 asr_asl: LPAREN ASL RPAREN
3656         {
3657         $$.r0 = 1;
3658         }
3659         | LPAREN ASR RPAREN
3660         {
3661         $$.r0 = 0;
3662         }
3663         ;
3664
3665 sco:
3666         {
3667         $$.s0 = 0;
3668         $$.x0 = 0;
3669         }
3670         | S
3671         {
3672         $$.s0 = 1;
3673         $$.x0 = 0;
3674         }
3675         | CO
3676         {
3677         $$.s0 = 0;
3678         $$.x0 = 1;
3679         }
3680         | SCO
3681         {
3682         $$.s0 = 1;
3683         $$.x0 = 1;
3684         }
3685         ;
3686
3687 asr_asl_0:
3688         ASL
3689         {
3690         $$.r0 = 1;
3691         }
3692         | ASR
3693         {
3694         $$.r0 = 0;
3695         }
3696         ;
3697
3698 amod0:
3699         {
3700         $$.s0 = 0;
3701         $$.x0 = 0;
3702         }
3703         | LPAREN sco RPAREN
3704         {
3705         $$.s0 = $2.s0;
3706         $$.x0 = $2.x0;
3707         }
3708         ;
3709
3710 amod1:
3711         {
3712         $$.s0 = 0;
3713         $$.x0 = 0;
3714         $$.aop = 0;
3715         }
3716         | LPAREN NS RPAREN
3717         {
3718         $$.s0 = 0;
3719         $$.x0 = 0;
3720         $$.aop = 1;
3721         }
3722         | LPAREN S RPAREN
3723         {
3724         $$.s0 = 1;
3725         $$.x0 = 0;
3726         $$.aop = 1;
3727         }
3728         ;
3729
3730 amod2:
3731         {
3732         $$.r0 = 0;
3733         $$.s0 = 0;
3734         $$.x0 = 0;
3735         }
3736         | LPAREN asr_asl_0 RPAREN
3737         {
3738         $$.r0 = 2 + $2.r0;
3739         $$.s0 = 0;
3740         $$.x0 = 0;
3741         }
3742         | LPAREN sco RPAREN
3743         {
3744         $$.r0 = 0;
3745         $$.s0 = $2.s0;
3746         $$.x0 = $2.x0;
3747         }
3748         | LPAREN asr_asl_0 COMMA sco RPAREN
3749         {
3750         $$.r0 = 2 + $2.r0;
3751         $$.s0 = $4.s0;
3752         $$.x0 = $4.x0;
3753         }
3754         | LPAREN sco COMMA asr_asl_0 RPAREN
3755         {
3756         $$.r0 = 2 + $4.r0;
3757         $$.s0 = $2.s0;
3758         $$.x0 = $2.x0;
3759         }
3760         ;
3761
3762 xpmod:
3763         {
3764         $$.r0 = 0;
3765         }
3766         | LPAREN Z RPAREN
3767         {
3768         $$.r0 = 0;
3769         }
3770         | LPAREN X RPAREN
3771         {
3772         $$.r0 = 1;
3773         }
3774         ;
3775
3776 xpmod1:
3777         {
3778         $$.r0 = 0;
3779         }
3780         | LPAREN X RPAREN
3781         {
3782         $$.r0 = 0;
3783         }
3784         | LPAREN Z RPAREN
3785         {
3786         $$.r0 = 1;
3787         }
3788         ;
3789
3790 vsmod:
3791         {
3792         $$.r0 = 0;
3793         $$.s0 = 0;
3794         $$.aop = 0;
3795         }
3796         | LPAREN NS RPAREN
3797         {
3798         $$.r0 = 0;
3799         $$.s0 = 0;
3800         $$.aop = 3;
3801         }
3802         | LPAREN S RPAREN
3803         {
3804         $$.r0 = 0;
3805         $$.s0 = 1;
3806         $$.aop = 3;
3807         }
3808         | LPAREN V RPAREN
3809         {
3810         $$.r0 = 1;
3811         $$.s0 = 0;
3812         $$.aop = 3;
3813         }
3814         | LPAREN V COMMA S RPAREN
3815         {
3816         $$.r0 = 1;
3817         $$.s0 = 1;
3818         }
3819         | LPAREN S COMMA V RPAREN
3820         {
3821         $$.r0 = 1;
3822         $$.s0 = 1;
3823         }
3824         ;
3825
3826 vmod:
3827         {
3828         $$.r0 = 0;
3829         }
3830         | LPAREN V RPAREN
3831         {
3832         $$.r0 = 1;
3833         }
3834         ;
3835
3836 smod:
3837         {
3838         $$.s0 = 0;
3839         }
3840         | LPAREN S RPAREN
3841         {
3842         $$.s0 = 1;
3843         }
3844         ;
3845
3846 searchmod:
3847           GE
3848         {
3849         $$.r0 = 1;
3850         }
3851         | GT
3852         {
3853         $$.r0 = 0;
3854         }
3855         | LE
3856         {
3857         $$.r0 = 3;
3858         }
3859         | LT
3860         {
3861         $$.r0 = 2;
3862         }
3863         ;
3864
3865 aligndir:
3866         {
3867         $$.r0 = 0;
3868         }
3869         | LPAREN R RPAREN
3870         {
3871         $$.r0 = 1;
3872         }
3873         ;
3874
3875 byteop_mod:
3876         LPAREN R RPAREN
3877         {
3878         $$.r0 = 0;
3879         $$.s0 = 1;
3880         }
3881         | LPAREN MMOD RPAREN
3882         {
3883         if ($2 != M_T)
3884           return yyerror ("Bad modifier");
3885         $$.r0 = 1;
3886         $$.s0 = 0;
3887         }
3888         | LPAREN MMOD COMMA R RPAREN
3889         {
3890         if ($2 != M_T)
3891           return yyerror ("Bad modifier");
3892         $$.r0 = 1;
3893         $$.s0 = 1;
3894         }
3895         | LPAREN R COMMA MMOD RPAREN
3896         {
3897         if ($4 != M_T)
3898           return yyerror ("Bad modifier");
3899         $$.r0 = 1;
3900         $$.s0 = 1;
3901         }
3902         ;
3903
3904
3905
3906 c_align:
3907         ALIGN8
3908         {
3909         $$.r0 = 0;
3910         }
3911         | ALIGN16
3912         {
3913         $$.r0 = 1;
3914         }
3915         | ALIGN24
3916         {
3917         $$.r0 = 2;
3918         }
3919         ;
3920
3921 w32_or_nothing:
3922         {
3923         $$.r0 = 0;
3924         }
3925         | LPAREN MMOD RPAREN
3926         {
3927           if ($2 == M_W32)
3928             $$.r0 = 1;
3929           else
3930             return yyerror ("Only (W32) allowed");
3931         }
3932         ;
3933
3934 iu_or_nothing:
3935         {
3936         $$.r0 = 1;
3937         }
3938         | LPAREN MMOD RPAREN
3939         {
3940           if ($2 == M_IU)
3941             $$.r0 = 3;
3942           else
3943             return yyerror ("(IU) expected");
3944         }
3945         ;
3946
3947 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3948         {
3949         $$ = $3;
3950         }
3951         ;
3952
3953 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3954         {
3955         $$ = $2;
3956         }
3957         ;
3958
3959 /* Operators.  */
3960
3961 min_max:
3962         MIN
3963         {
3964         $$.r0 = 1;
3965         }
3966         | MAX
3967         {
3968         $$.r0 = 0;
3969         }
3970         ;
3971
3972 op_bar_op:
3973         _PLUS_BAR_PLUS
3974         {
3975         $$.r0 = 0;
3976         }
3977         | _PLUS_BAR_MINUS
3978         {
3979         $$.r0 = 1;
3980         }
3981         | _MINUS_BAR_PLUS
3982         {
3983         $$.r0 = 2;
3984         }
3985         | _MINUS_BAR_MINUS
3986         {
3987         $$.r0 = 3;
3988         }
3989         ;
3990
3991 plus_minus:
3992         PLUS
3993         {
3994         $$.r0 = 0;
3995         }
3996         | MINUS
3997         {
3998         $$.r0 = 1;
3999         }
4000         ;
4001
4002 rnd_op:
4003         LPAREN RNDH RPAREN
4004         {
4005           $$.r0 = 1;    /* HL.  */
4006           $$.s0 = 0;    /* s.  */
4007           $$.x0 = 0;    /* x.  */
4008           $$.aop = 0;   /* aop.  */
4009         }
4010
4011         | LPAREN TH RPAREN
4012         {
4013           $$.r0 = 1;    /* HL.  */
4014           $$.s0 = 0;    /* s.  */
4015           $$.x0 = 0;    /* x.  */
4016           $$.aop = 1;   /* aop.  */
4017         }
4018
4019         | LPAREN RNDL RPAREN
4020         {
4021           $$.r0 = 0;    /* HL.  */
4022           $$.s0 = 0;    /* s.  */
4023           $$.x0 = 0;    /* x.  */
4024           $$.aop = 0;   /* aop.  */
4025         }
4026
4027         | LPAREN TL RPAREN
4028         {
4029           $$.r0 = 0;    /* HL.  */
4030           $$.s0 = 0;    /* s.  */
4031           $$.x0 = 0;    /* x.  */
4032           $$.aop = 1;
4033         }
4034
4035         | LPAREN RNDH COMMA R RPAREN
4036         {
4037           $$.r0 = 1;    /* HL.  */
4038           $$.s0 = 1;    /* s.  */
4039           $$.x0 = 0;    /* x.  */
4040           $$.aop = 0;   /* aop.  */
4041         }
4042         | LPAREN TH COMMA R RPAREN
4043         {
4044           $$.r0 = 1;    /* HL.  */
4045           $$.s0 = 1;    /* s.  */
4046           $$.x0 = 0;    /* x.  */
4047           $$.aop = 1;   /* aop.  */
4048         }
4049         | LPAREN RNDL COMMA R RPAREN
4050         {
4051           $$.r0 = 0;    /* HL.  */
4052           $$.s0 = 1;    /* s.  */
4053           $$.x0 = 0;    /* x.  */
4054           $$.aop = 0;   /* aop.  */
4055         }
4056
4057         | LPAREN TL COMMA R RPAREN
4058         {
4059           $$.r0 = 0;    /* HL.  */
4060           $$.s0 = 1;    /* s.  */
4061           $$.x0 = 0;    /* x.  */
4062           $$.aop = 1;   /* aop.  */
4063         }
4064         ;
4065
4066 b3_op:
4067         LPAREN LO RPAREN
4068         {
4069           $$.s0 = 0;    /* s.  */
4070           $$.x0 = 0;    /* HL.  */
4071         }
4072         | LPAREN HI RPAREN
4073         {
4074           $$.s0 = 0;    /* s.  */
4075           $$.x0 = 1;    /* HL.  */
4076         }
4077         | LPAREN LO COMMA R RPAREN
4078         {
4079           $$.s0 = 1;    /* s.  */
4080           $$.x0 = 0;    /* HL.  */
4081         }
4082         | LPAREN HI COMMA R RPAREN
4083         {
4084           $$.s0 = 1;    /* s.  */
4085           $$.x0 = 1;    /* HL.  */
4086         }
4087         ;
4088
4089 post_op:
4090         {
4091         $$.x0 = 2;
4092         }
4093         | _PLUS_PLUS
4094         {
4095         $$.x0 = 0;
4096         }
4097         | _MINUS_MINUS
4098         {
4099         $$.x0 = 1;
4100         }
4101         ;
4102
4103 /* Assignments, Macfuncs.  */
4104
4105 a_assign:
4106         REG_A ASSIGN
4107         {
4108         $$ = $1;
4109         }
4110         ;
4111
4112 a_minusassign:
4113         REG_A _MINUS_ASSIGN
4114         {
4115         $$ = $1;
4116         }
4117         ;
4118
4119 a_plusassign:
4120         REG_A _PLUS_ASSIGN
4121         {
4122         $$ = $1;
4123         }
4124         ;
4125
4126 assign_macfunc:
4127         REG ASSIGN REG_A
4128         {
4129           if (IS_A1 ($3) && IS_EVEN ($1))
4130             return yyerror ("Cannot move A1 to even register");
4131           else if (!IS_A1 ($3) && !IS_EVEN ($1))
4132             return yyerror ("Cannot move A0 to odd register");
4133
4134           $$.w = 1;
4135           $$.P = 1;
4136           $$.n = IS_A1 ($3);
4137           $$.op = 3;
4138           $$.dst = $1;
4139           $$.s0.regno = 0;
4140           $$.s1.regno = 0;
4141         }
4142         | a_macfunc
4143         {
4144           $$ = $1;
4145           $$.w = 0; $$.P = 0;
4146           $$.dst.regno = 0;
4147         }
4148         | REG ASSIGN LPAREN a_macfunc RPAREN
4149         {
4150           if ($4.n && IS_EVEN ($1))
4151             return yyerror ("Cannot move A1 to even register");
4152           else if (!$4.n && !IS_EVEN ($1))
4153             return yyerror ("Cannot move A0 to odd register");
4154
4155           $$ = $4;
4156           $$.w = 1;
4157           $$.P = 1;
4158           $$.dst = $1;
4159         }
4160
4161         | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4162         {
4163           if ($4.n && !IS_H ($1))
4164             return yyerror ("Cannot move A1 to low half of register");
4165           else if (!$4.n && IS_H ($1))
4166             return yyerror ("Cannot move A0 to high half of register");
4167
4168           $$ = $4;
4169           $$.w = 1;
4170           $$.P = 0;
4171           $$.dst = $1;
4172         }
4173
4174         | HALF_REG ASSIGN REG_A
4175         {
4176           if (IS_A1 ($3) && !IS_H ($1))
4177             return yyerror ("Cannot move A1 to low half of register");
4178           else if (!IS_A1 ($3) && IS_H ($1))
4179             return yyerror ("Cannot move A0 to high half of register");
4180
4181           $$.w = 1;
4182           $$.P = 0;
4183           $$.n = IS_A1 ($3);
4184           $$.op = 3;
4185           $$.dst = $1;
4186           $$.s0.regno = 0;
4187           $$.s1.regno = 0;
4188         }
4189         ;
4190
4191 a_macfunc:
4192         a_assign multiply_halfregs
4193         {
4194           $$.n = IS_A1 ($1);
4195           $$.op = 0;
4196           $$.s0 = $2.s0;
4197           $$.s1 = $2.s1;
4198         }
4199         | a_plusassign multiply_halfregs
4200         {
4201           $$.n = IS_A1 ($1);
4202           $$.op = 1;
4203           $$.s0 = $2.s0;
4204           $$.s1 = $2.s1;
4205         }
4206         | a_minusassign multiply_halfregs
4207         {
4208           $$.n = IS_A1 ($1);
4209           $$.op = 2;
4210           $$.s0 = $2.s0;
4211           $$.s1 = $2.s1;
4212         }
4213         ;
4214
4215 multiply_halfregs:
4216         HALF_REG STAR HALF_REG
4217         {
4218           if (IS_DREG ($1) && IS_DREG ($3))
4219             {
4220               $$.s0 = $1;
4221               $$.s1 = $3;
4222             }
4223           else
4224             return yyerror ("Dregs expected");
4225         }
4226         ;
4227
4228 cc_op:
4229         ASSIGN
4230         {
4231         $$.r0 = 0;
4232         }
4233         | _BAR_ASSIGN
4234         {
4235         $$.r0 = 1;
4236         }
4237         | _AMPERSAND_ASSIGN
4238         {
4239         $$.r0 = 2;
4240         }
4241         | _CARET_ASSIGN
4242         {
4243         $$.r0 = 3;
4244         }
4245         ;
4246
4247 ccstat:
4248         CCREG cc_op STATUS_REG
4249         {
4250         $$.r0 = $3.regno;
4251         $$.x0 = $2.r0;
4252         $$.s0 = 0;
4253         }
4254         | CCREG cc_op V
4255         {
4256         $$.r0 = 0x18;
4257         $$.x0 = $2.r0;
4258         $$.s0 = 0;
4259         }
4260         | STATUS_REG cc_op CCREG
4261         {
4262         $$.r0 = $1.regno;
4263         $$.x0 = $2.r0;
4264         $$.s0 = 1;
4265         }
4266         | V cc_op CCREG
4267         {
4268         $$.r0 = 0x18;
4269         $$.x0 = $2.r0;
4270         $$.s0 = 1;
4271         }
4272         ;
4273
4274 /* Expressions and Symbols.  */
4275
4276 symbol: SYMBOL
4277         {
4278         Expr_Node_Value val;
4279         val.s_value = S_GET_NAME($1);
4280         $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4281         }
4282         ;
4283
4284 any_gotrel:
4285         GOT
4286         { $$ = BFD_RELOC_BFIN_GOT; }
4287         | GOT17M4
4288         { $$ = BFD_RELOC_BFIN_GOT17M4; }
4289         | FUNCDESC_GOT17M4
4290         { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4291         ;
4292
4293 got:    symbol AT any_gotrel
4294         {
4295         Expr_Node_Value val;
4296         val.i_value = $3;
4297         $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4298         }
4299         ;
4300
4301 got_or_expr:    got
4302         {
4303         $$ = $1;
4304         }
4305         | expr
4306         {
4307         $$ = $1;
4308         }
4309         ;
4310
4311 pltpc :
4312         symbol AT PLTPC
4313         {
4314         $$ = $1;
4315         }
4316         ;
4317
4318 eterm: NUMBER
4319         {
4320         Expr_Node_Value val;
4321         val.i_value = $1;
4322         $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4323         }
4324         | symbol
4325         {
4326         $$ = $1;
4327         }
4328         | LPAREN expr_1 RPAREN
4329         {
4330         $$ = $2;
4331         }
4332         | TILDA expr_1
4333         {
4334         $$ = unary (Expr_Op_Type_COMP, $2);
4335         }
4336         | MINUS expr_1 %prec TILDA
4337         {
4338         $$ = unary (Expr_Op_Type_NEG, $2);
4339         }
4340         ;
4341
4342 expr: expr_1
4343         {
4344         $$ = $1;
4345         }
4346         ;
4347
4348 expr_1: expr_1 STAR expr_1
4349         {
4350         $$ = binary (Expr_Op_Type_Mult, $1, $3);
4351         }
4352         | expr_1 SLASH expr_1
4353         {
4354         $$ = binary (Expr_Op_Type_Div, $1, $3);
4355         }
4356         | expr_1 PERCENT expr_1
4357         {
4358         $$ = binary (Expr_Op_Type_Mod, $1, $3);
4359         }
4360         | expr_1 PLUS expr_1
4361         {
4362         $$ = binary (Expr_Op_Type_Add, $1, $3);
4363         }
4364         | expr_1 MINUS expr_1
4365         {
4366         $$ = binary (Expr_Op_Type_Sub, $1, $3);
4367         }
4368         | expr_1 LESS_LESS expr_1
4369         {
4370         $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4371         }
4372         | expr_1 GREATER_GREATER expr_1
4373         {
4374         $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4375         }
4376         | expr_1 AMPERSAND expr_1
4377         {
4378         $$ = binary (Expr_Op_Type_BAND, $1, $3);
4379         }
4380         | expr_1 CARET expr_1
4381         {
4382         $$ = binary (Expr_Op_Type_LOR, $1, $3);
4383         }
4384         | expr_1 BAR expr_1
4385         {
4386         $$ = binary (Expr_Op_Type_BOR, $1, $3);
4387         }
4388         | eterm
4389         {
4390         $$ = $1;
4391         }
4392         ;
4393
4394
4395 %%
4396
4397 EXPR_T
4398 mkexpr (int x, SYMBOL_T s)
4399 {
4400   EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4401   e->value = x;
4402   EXPR_SYMBOL(e) = s;
4403   return e;
4404 }
4405
4406 static int
4407 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4408 {
4409   int umax = (1 << sz) - 1;
4410   int min = -1 << (sz - 1);
4411   int max = (1 << (sz - 1)) - 1;
4412
4413   int v = (EXPR_VALUE (expr)) & 0xffffffff;
4414
4415   if ((v % mul) != 0)
4416     {
4417       error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4418       return 0;
4419     }
4420
4421   v /= mul;
4422
4423   if (sign)
4424     v = -v;
4425
4426   if (issigned)
4427     {
4428       if (v >= min && v <= max) return 1;
4429
4430 #ifdef DEBUG
4431       fprintf(stderr, "signed value %lx out of range\n", v * mul);
4432 #endif
4433       return 0;
4434     }
4435   if (v <= umax && v >= 0)
4436     return 1;
4437 #ifdef DEBUG
4438   fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4439 #endif
4440   return 0;
4441 }
4442
4443 /* Return the expression structure that allows symbol operations.
4444    If the left and right children are constants, do the operation.  */
4445 static Expr_Node *
4446 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4447 {
4448   Expr_Node_Value val;
4449
4450   if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4451     {
4452       switch (op)
4453         {
4454         case Expr_Op_Type_Add:
4455           x->value.i_value += y->value.i_value;
4456           break;
4457         case Expr_Op_Type_Sub:
4458           x->value.i_value -= y->value.i_value;
4459           break;
4460         case Expr_Op_Type_Mult:
4461           x->value.i_value *= y->value.i_value;
4462           break;
4463         case Expr_Op_Type_Div:
4464           if (y->value.i_value == 0)
4465             error ("Illegal Expression:  Division by zero.");
4466           else
4467             x->value.i_value /= y->value.i_value;
4468           break;
4469         case Expr_Op_Type_Mod:
4470           x->value.i_value %= y->value.i_value;
4471           break;
4472         case Expr_Op_Type_Lshift:
4473           x->value.i_value <<= y->value.i_value;
4474           break;
4475         case Expr_Op_Type_Rshift:
4476           x->value.i_value >>= y->value.i_value;
4477           break;
4478         case Expr_Op_Type_BAND:
4479           x->value.i_value &= y->value.i_value;
4480           break;
4481         case Expr_Op_Type_BOR:
4482           x->value.i_value |= y->value.i_value;
4483           break;
4484         case Expr_Op_Type_BXOR:
4485           x->value.i_value ^= y->value.i_value;
4486           break;
4487         case Expr_Op_Type_LAND:
4488           x->value.i_value = x->value.i_value && y->value.i_value;
4489           break;
4490         case Expr_Op_Type_LOR:
4491           x->value.i_value = x->value.i_value || y->value.i_value;
4492           break;
4493
4494         default:
4495           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4496         }
4497       return x;
4498     }
4499   /* Canonicalize order to EXPR OP CONSTANT.  */
4500   if (x->type == Expr_Node_Constant)
4501     {
4502       Expr_Node *t = x;
4503       x = y;
4504       y = t;
4505     }
4506   /* Canonicalize subtraction of const to addition of negated const.  */
4507   if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4508     {
4509       op = Expr_Op_Type_Add;
4510       y->value.i_value = -y->value.i_value;
4511     }
4512   if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4513       && x->Right_Child->type == Expr_Node_Constant)
4514     {
4515       if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4516         {
4517           x->Right_Child->value.i_value += y->value.i_value;
4518           return x;
4519         }
4520     }
4521
4522   /* Create a new expression structure.  */
4523   val.op_value = op;
4524   return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4525 }
4526
4527 static Expr_Node *
4528 unary (Expr_Op_Type op, Expr_Node *x)
4529 {
4530   if (x->type == Expr_Node_Constant)
4531     {
4532       switch (op)
4533         {
4534         case Expr_Op_Type_NEG:
4535           x->value.i_value = -x->value.i_value;
4536           break;
4537         case Expr_Op_Type_COMP:
4538           x->value.i_value = ~x->value.i_value;
4539           break;
4540         default:
4541           error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4542         }
4543       return x;
4544     }
4545   else
4546     {
4547       /* Create a new expression structure.  */
4548       Expr_Node_Value val;
4549       val.op_value = op;
4550       return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4551     }
4552 }
4553
4554 int debug_codeselection = 0;
4555 static void
4556 notethat (char *format, ...)
4557 {
4558   va_list ap;
4559   va_start (ap, format);
4560   if (debug_codeselection)
4561     {
4562       vfprintf (errorf, format, ap);
4563     }
4564   va_end (ap);
4565 }
4566
4567 #ifdef TEST
4568 main (int argc, char **argv)
4569 {
4570   yyparse();
4571 }
4572 #endif
4573