1 /* bfin-parse.y ADI Blackfin parser
2 Copyright (C) 2005-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
26 #include "elf/common.h"
29 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
30 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
33 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
37 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
40 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
41 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
43 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
44 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
46 #define LDIMMHALF_R(reg, h, s, z, hword) \
47 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
49 #define LDIMMHALF_R5(reg, h, s, z, hword) \
50 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
52 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
53 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
55 #define LDST(ptr, reg, aop, sz, z, w) \
56 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
58 #define LDSTII(ptr, reg, offset, w, op) \
59 bfin_gen_ldstii (ptr, reg, offset, w, op)
61 #define DSPLDST(i, m, reg, aop, w) \
62 bfin_gen_dspldst (i, reg, aop, w, m)
64 #define LDSTPMOD(ptr, reg, idx, aop, w) \
65 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
67 #define LDSTIIFP(offset, reg, w) \
68 bfin_gen_ldstiifp (reg, offset, w)
70 #define LOGI2OP(dst, src, opc) \
71 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
73 #define ALU2OP(dst, src, opc) \
74 bfin_gen_alu2op (dst, src, opc)
76 #define BRCC(t, b, offset) \
77 bfin_gen_brcc (t, b, offset)
79 #define UJUMP(offset) \
80 bfin_gen_ujump (offset)
82 #define PROGCTRL(prgfunc, poprnd) \
83 bfin_gen_progctrl (prgfunc, poprnd)
85 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
86 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
88 #define PUSHPOPREG(reg, w) \
89 bfin_gen_pushpopreg (reg, w)
91 #define CALLA(addr, s) \
92 bfin_gen_calla (addr, s)
94 #define LINKAGE(r, framesize) \
95 bfin_gen_linkage (r, framesize)
97 #define COMPI2OPD(dst, src, op) \
98 bfin_gen_compi2opd (dst, src, op)
100 #define COMPI2OPP(dst, src, op) \
101 bfin_gen_compi2opp (dst, src, op)
103 #define DAGMODIK(i, op) \
104 bfin_gen_dagmodik (i, op)
106 #define DAGMODIM(i, m, op, br) \
107 bfin_gen_dagmodim (i, m, op, br)
109 #define COMP3OP(dst, src0, src1, opc) \
110 bfin_gen_comp3op (src0, src1, dst, opc)
112 #define PTR2OP(dst, src, opc) \
113 bfin_gen_ptr2op (dst, src, opc)
115 #define CCFLAG(x, y, opc, i, g) \
116 bfin_gen_ccflag (x, y, opc, i, g)
118 #define CCMV(src, dst, t) \
119 bfin_gen_ccmv (src, dst, t)
121 #define CACTRL(reg, a, op) \
122 bfin_gen_cactrl (reg, a, op)
124 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
125 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
127 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
128 #define IS_RANGE(bits, expr, sign, mul) \
129 value_match(expr, bits, sign, mul, 1)
130 #define IS_URANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 0)
132 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
133 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
134 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
135 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
137 #define IS_PCREL4(expr) \
138 (value_match (expr, 4, 0, 2, 0))
140 #define IS_LPPCREL10(expr) \
141 (value_match (expr, 10, 0, 2, 0))
143 #define IS_PCREL10(expr) \
144 (value_match (expr, 10, 0, 2, 1))
146 #define IS_PCREL12(expr) \
147 (value_match (expr, 12, 0, 2, 1))
149 #define IS_PCREL24(expr) \
150 (value_match (expr, 24, 0, 2, 1))
153 static int value_match (Expr_Node *, int, int, int, int);
158 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
159 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
161 static void notethat (char *, ...);
163 char *current_inputline;
165 int yyerror (char *);
167 /* Used to set SRCx fields to all 1s as described in the PRM. */
168 static Register reg7 = {REG_R7, 0};
170 void error (char *format, ...)
173 static char buffer[2000];
175 va_start (ap, format);
176 vsprintf (buffer, format, ap);
179 as_bad ("%s", buffer);
188 else if (yytext[0] != ';')
189 error ("%s. Input text was %s.", msg, yytext);
197 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
199 int val = EXPR_VALUE (exp);
200 if (exp->type != Expr_Node_Constant)
202 if (val < from || val > to)
204 return (val & mask) == 0;
207 extern int yylex (void);
209 #define imm3(x) EXPR_VALUE (x)
210 #define imm4(x) EXPR_VALUE (x)
211 #define uimm4(x) EXPR_VALUE (x)
212 #define imm5(x) EXPR_VALUE (x)
213 #define uimm5(x) EXPR_VALUE (x)
214 #define imm6(x) EXPR_VALUE (x)
215 #define imm7(x) EXPR_VALUE (x)
216 #define uimm8(x) EXPR_VALUE (x)
217 #define imm16(x) EXPR_VALUE (x)
218 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
219 #define uimm16(x) EXPR_VALUE (x)
221 /* Return true if a value is inside a range. */
222 #define IN_RANGE(x, low, high) \
223 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
225 /* Auxiliary functions. */
228 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
230 if (!IS_DREG (*reg1))
232 yyerror ("Dregs expected");
236 if (reg1->regno != 1 && reg1->regno != 3)
238 yyerror ("Bad register pair");
242 if (imm7 (reg2) != reg1->regno - 1)
244 yyerror ("Bad register pair");
253 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
255 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
256 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
257 return yyerror ("Source multiplication register mismatch");
263 /* Check mac option. */
266 check_macfunc_option (Macfunc *a, Opt_mode *opt)
268 /* Default option is always valid. */
272 if ((a->w == 1 && a->P == 1
273 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
274 && opt->mod != M_S2RND && opt->mod != M_ISS2)
275 || (a->w == 1 && a->P == 0
276 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
277 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
278 && opt->mod != M_ISS2 && opt->mod != M_IH)
279 || (a->w == 0 && a->P == 0
280 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
286 /* Check (vector) mac funcs and ops. */
289 check_macfuncs (Macfunc *aa, Opt_mode *opa,
290 Macfunc *ab, Opt_mode *opb)
292 /* Variables for swapping. */
296 /* The option mode should be put at the end of the second instruction
297 of the vector except M, which should follow MAC1 instruction. */
299 return yyerror ("Bad opt mode");
301 /* If a0macfunc comes before a1macfunc, swap them. */
305 /* (M) is not allowed here. */
307 return yyerror ("(M) not allowed with A0MAC");
309 return yyerror ("Vector AxMACs can't be same");
311 mtmp = *aa; *aa = *ab; *ab = mtmp;
312 otmp = *opa; *opa = *opb; *opb = otmp;
317 return yyerror ("(M) not allowed with A0MAC");
319 return yyerror ("Vector AxMACs can't be same");
322 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
323 assignment_or_macfuncs. */
324 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
325 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
327 if (check_multiply_halfregs (aa, ab) < 0)
332 /* Only one of the assign_macfuncs has a half reg multiply
333 Evil trick: Just 'OR' their source register codes:
334 We can do that, because we know they were initialized to 0
335 in the rules that don't use multiply_halfregs. */
336 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
337 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
340 if (aa->w == ab->w && aa->P != ab->P)
341 return yyerror ("Destination Dreg sizes (full or half) must match");
345 if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
346 return yyerror ("Destination Dregs (full) must differ by one");
347 if (!aa->P && aa->dst.regno != ab->dst.regno)
348 return yyerror ("Destination Dregs (half) must match");
351 /* Make sure mod flags get ORed, too. */
352 opb->mod |= opa->mod;
355 if (check_macfunc_option (aa, opb) < 0
356 && check_macfunc_option (ab, opb) < 0)
357 return yyerror ("bad option");
359 /* Make sure first macfunc has got both P flags ORed. */
367 is_group1 (INSTR_T x)
369 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
370 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
377 is_group2 (INSTR_T x)
379 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
380 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
381 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
382 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
383 || (x->value == 0x0000))
394 if ((x->value & 0xf000) == 0x8000)
396 int aop = ((x->value >> 9) & 0x3);
397 int w = ((x->value >> 11) & 0x1);
403 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
404 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
407 /* decode_dspLDST_0 */
408 if ((x->value & 0xFC00) == 0x9C00)
410 int w = ((x->value >> 9) & 0x1);
419 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
421 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
422 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
423 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
425 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
426 yyerror ("resource conflict in multi-issue instruction");
428 /* Anomaly 05000074 */
429 if (ENABLE_AC_05000074
430 && dsp32 != NULL && dsp16_grp1 != NULL
431 && (dsp32->value & 0xf780) == 0xc680
432 && ((dsp16_grp1->value & 0xfe40) == 0x9240
433 || (dsp16_grp1->value & 0xfe08) == 0xba08
434 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
435 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
436 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
438 if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
439 yyerror ("Only one instruction in multi-issue instruction can be a store");
441 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
453 struct { int r0; int s0; int x0; int aop; } modcodes;
454 struct { int r0; } r0;
461 /* Vector Specific. */
462 %token BYTEOP16P BYTEOP16M
463 %token BYTEOP1P BYTEOP2P BYTEOP3P
464 %token BYTEUNPACK BYTEPACK
467 %token ALIGN8 ALIGN16 ALIGN24
469 %token EXTRACT DEPOSIT EXPADJ SEARCH
470 %token ONES SIGN SIGNBITS
478 %token CCREG BYTE_DREG
479 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
480 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
485 %token RTI RTS RTX RTN RTE
496 %token JUMP JUMP_DOT_S JUMP_DOT_L
503 %token NOT TILDA BANG
509 %token MINUS PLUS STAR SLASH
513 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
514 %token _MINUS_MINUS _PLUS_PLUS
516 /* Shift/rotate ops. */
517 %token SHIFT LSHIFT ASHIFT BXORSHIFT
518 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
520 %token LESS_LESS GREATER_GREATER
521 %token _GREATER_GREATER_GREATER
522 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
525 /* In place operators. */
526 %token ASSIGN _STAR_ASSIGN
527 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
528 %token _MINUS_ASSIGN _PLUS_ASSIGN
530 /* Assignments, comparisons. */
531 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
536 %token FLUSHINV FLUSH
537 %token IFLUSH PREFETCH
554 %token R RND RNDL RNDH RND12 RND20
559 %token BITTGL BITCLR BITSET BITTST BITMUX
562 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
564 /* Semantic auxiliaries. */
567 %token COLON SEMICOLON
568 %token RPAREN LPAREN LBRACK RBRACK
572 %token GOT GOT17M4 FUNCDESC_GOT17M4
582 %type <modcodes> byteop_mod
584 %type <reg> a_plusassign
585 %type <reg> a_minusassign
586 %type <macfunc> multiply_halfregs
587 %type <macfunc> assign_macfunc
588 %type <macfunc> a_macfunc
592 %type <modcodes> vsmod
593 %type <modcodes> ccstat
596 %type <reg> reg_with_postinc
597 %type <reg> reg_with_predec
601 %type <symbol> SYMBOL
604 %type <reg> BYTE_DREG
605 %type <reg> REG_A_DOUBLE_ZERO
606 %type <reg> REG_A_DOUBLE_ONE
608 %type <reg> STATUS_REG
612 %type <modcodes> smod
613 %type <modcodes> b3_op
614 %type <modcodes> rnd_op
615 %type <modcodes> post_op
617 %type <r0> iu_or_nothing
618 %type <r0> plus_minus
622 %type <modcodes> amod0
623 %type <modcodes> amod1
624 %type <modcodes> amod2
626 %type <r0> w32_or_nothing
630 %type <expr> got_or_expr
632 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
634 /* Precedence rules. */
638 %left LESS_LESS GREATER_GREATER
640 %left STAR SLASH PERCENT
651 if (insn == (INSTR_T) 0)
652 return NO_INSN_GENERATED;
653 else if (insn == (INSTR_T) - 1)
654 return SEMANTIC_ERROR;
656 return INSN_GENERATED;
661 /* Parallel instructions. */
662 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
664 if (($1->value & 0xf800) == 0xc000)
666 if (is_group1 ($3) && is_group2 ($5))
667 $$ = gen_multi_instr_1 ($1, $3, $5);
668 else if (is_group2 ($3) && is_group1 ($5))
669 $$ = gen_multi_instr_1 ($1, $5, $3);
671 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
673 else if (($3->value & 0xf800) == 0xc000)
675 if (is_group1 ($1) && is_group2 ($5))
676 $$ = gen_multi_instr_1 ($3, $1, $5);
677 else if (is_group2 ($1) && is_group1 ($5))
678 $$ = gen_multi_instr_1 ($3, $5, $1);
680 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
682 else if (($5->value & 0xf800) == 0xc000)
684 if (is_group1 ($1) && is_group2 ($3))
685 $$ = gen_multi_instr_1 ($5, $1, $3);
686 else if (is_group2 ($1) && is_group1 ($3))
687 $$ = gen_multi_instr_1 ($5, $3, $1);
689 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
692 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
695 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
697 if (($1->value & 0xf800) == 0xc000)
700 $$ = gen_multi_instr_1 ($1, $3, 0);
701 else if (is_group2 ($3))
702 $$ = gen_multi_instr_1 ($1, 0, $3);
704 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
706 else if (($3->value & 0xf800) == 0xc000)
709 $$ = gen_multi_instr_1 ($3, $1, 0);
710 else if (is_group2 ($1))
711 $$ = gen_multi_instr_1 ($3, 0, $1);
713 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
715 else if (is_group1 ($1) && is_group2 ($3))
716 $$ = gen_multi_instr_1 (0, $1, $3);
717 else if (is_group2 ($1) && is_group1 ($3))
718 $$ = gen_multi_instr_1 (0, $3, $1);
720 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
735 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
737 | assign_macfunc opt_mode
741 int h00, h10, h01, h11;
743 if (check_macfunc_option (&$1, &$2) < 0)
744 return yyerror ("bad option");
749 return yyerror ("(m) not allowed with a0 unit");
768 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
769 &$1.dst, op0, &$1.s0, &$1.s1, w0);
775 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
779 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
781 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
788 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
789 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
790 dst, $4.op, &$1.s0, &$1.s1, $4.w);
797 notethat ("dsp32alu: DISALGNEXCPT\n");
798 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
800 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
802 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
804 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
805 $$ = DSP32ALU (11, 0, 0, &$1, ®7, ®7, 0, 0, 0);
808 return yyerror ("Register mismatch");
810 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
812 if (!IS_A1 ($4) && IS_A1 ($5))
814 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
815 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, ®7, ®7, 0, 0, 1);
818 return yyerror ("Register mismatch");
820 | A_ZERO_DOT_H ASSIGN HALF_REG
822 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
823 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
825 | A_ONE_DOT_H ASSIGN HALF_REG
827 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
828 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
830 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
831 COLON expr COMMA REG COLON expr RPAREN aligndir
833 if (!IS_DREG ($2) || !IS_DREG ($4))
834 return yyerror ("Dregs expected");
835 else if (REG_SAME ($2, $4))
836 return yyerror ("Illegal dest register combination");
837 else if (!valid_dreg_pair (&$9, $11))
838 return yyerror ("Bad dreg pair");
839 else if (!valid_dreg_pair (&$13, $15))
840 return yyerror ("Bad dreg pair");
843 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
844 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
848 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
849 REG COLON expr RPAREN aligndir
851 if (!IS_DREG ($2) || !IS_DREG ($4))
852 return yyerror ("Dregs expected");
853 else if (REG_SAME ($2, $4))
854 return yyerror ("Illegal dest register combination");
855 else if (!valid_dreg_pair (&$9, $11))
856 return yyerror ("Bad dreg pair");
857 else if (!valid_dreg_pair (&$13, $15))
858 return yyerror ("Bad dreg pair");
861 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
862 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
866 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
868 if (!IS_DREG ($2) || !IS_DREG ($4))
869 return yyerror ("Dregs expected");
870 else if (REG_SAME ($2, $4))
871 return yyerror ("Illegal dest register combination");
872 else if (!valid_dreg_pair (&$8, $10))
873 return yyerror ("Bad dreg pair");
876 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
877 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
880 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
882 if (REG_SAME ($2, $4))
883 return yyerror ("Illegal dest register combination");
885 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
887 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
888 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
891 return yyerror ("Register mismatch");
893 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
894 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
896 if (REG_SAME ($1, $7))
897 return yyerror ("Illegal dest register combination");
899 if (IS_DREG ($1) && IS_DREG ($7))
901 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
902 $$ = DSP32ALU (12, 0, &$1, &$7, ®7, ®7, 0, 0, 1);
905 return yyerror ("Register mismatch");
909 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
911 if (REG_SAME ($1, $7))
912 return yyerror ("Resource conflict in dest reg");
914 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
915 && IS_A1 ($9) && !IS_A1 ($11))
917 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
918 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 0);
921 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
922 && !IS_A1 ($9) && IS_A1 ($11))
924 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
925 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 1);
928 return yyerror ("Register mismatch");
931 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
934 return yyerror ("Operators must differ");
936 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
937 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
939 notethat ("dsp32alu: dregs = dregs + dregs,"
940 "dregs = dregs - dregs (amod1)\n");
941 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
944 return yyerror ("Register mismatch");
947 /* Bar Operations. */
949 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
951 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
952 return yyerror ("Differing source registers");
954 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
955 return yyerror ("Dregs expected");
957 if (REG_SAME ($1, $7))
958 return yyerror ("Resource conflict in dest reg");
960 if ($4.r0 == 1 && $10.r0 == 2)
962 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
963 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
965 else if ($4.r0 == 0 && $10.r0 == 3)
967 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
968 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
971 return yyerror ("Bar operand mismatch");
974 | REG ASSIGN ABS REG vmod
978 if (IS_DREG ($1) && IS_DREG ($4))
982 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
987 /* Vector version of ABS. */
988 notethat ("dsp32alu: dregs = ABS dregs\n");
991 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
994 return yyerror ("Dregs expected");
998 notethat ("dsp32alu: Ax = ABS Ax\n");
999 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3));
1001 | A_ZERO_DOT_L ASSIGN HALF_REG
1005 notethat ("dsp32alu: A0.l = reg_half\n");
1006 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
1009 return yyerror ("A0.l = Rx.l expected");
1011 | A_ONE_DOT_L ASSIGN HALF_REG
1015 notethat ("dsp32alu: A1.l = reg_half\n");
1016 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
1019 return yyerror ("A1.l = Rx.l expected");
1022 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1024 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1026 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1027 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1030 return yyerror ("Dregs expected");
1033 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1036 return yyerror ("Dregs expected");
1037 else if (!valid_dreg_pair (&$5, $7))
1038 return yyerror ("Bad dreg pair");
1039 else if (!valid_dreg_pair (&$9, $11))
1040 return yyerror ("Bad dreg pair");
1043 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1044 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1047 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1050 return yyerror ("Dregs expected");
1051 else if (!valid_dreg_pair (&$5, $7))
1052 return yyerror ("Bad dreg pair");
1053 else if (!valid_dreg_pair (&$9, $11))
1054 return yyerror ("Bad dreg pair");
1057 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1058 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1062 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1066 return yyerror ("Dregs expected");
1067 else if (!valid_dreg_pair (&$5, $7))
1068 return yyerror ("Bad dreg pair");
1069 else if (!valid_dreg_pair (&$9, $11))
1070 return yyerror ("Bad dreg pair");
1073 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1074 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1078 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1082 return yyerror ("Dregs expected");
1083 else if (!valid_dreg_pair (&$5, $7))
1084 return yyerror ("Bad dreg pair");
1085 else if (!valid_dreg_pair (&$9, $11))
1086 return yyerror ("Bad dreg pair");
1089 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1090 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1094 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1096 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1098 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1099 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1102 return yyerror ("Dregs expected");
1105 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1106 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1108 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1110 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1111 "SIGN (dregs_hi) * dregs_hi + "
1112 "SIGN (dregs_lo) * dregs_lo \n");
1114 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1117 return yyerror ("Dregs expected");
1119 | REG ASSIGN REG plus_minus REG amod1
1121 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1125 /* No saturation flag specified, generate the 16 bit variant. */
1126 notethat ("COMP3op: dregs = dregs +- dregs\n");
1127 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1131 /* Saturation flag specified, generate the 32 bit variant. */
1132 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1133 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1137 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1139 notethat ("COMP3op: pregs = pregs + pregs\n");
1140 $$ = COMP3OP (&$1, &$3, &$5, 5);
1143 return yyerror ("Dregs expected");
1145 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1149 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1156 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1157 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1160 return yyerror ("Dregs expected");
1163 | a_assign MINUS REG_A
1165 notethat ("dsp32alu: Ax = - Ax\n");
1166 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3));
1168 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1170 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1171 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1172 $6.s0, $6.x0, HL2 ($3, $5));
1174 | a_assign a_assign expr
1176 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1178 notethat ("dsp32alu: A1 = A0 = 0\n");
1179 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 0, 0, 2);
1182 return yyerror ("Bad value, 0 expected");
1186 | a_assign REG_A LPAREN S RPAREN
1188 if (REG_SAME ($1, $2))
1190 notethat ("dsp32alu: Ax = Ax (S)\n");
1191 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, IS_A1 ($1));
1194 return yyerror ("Registers must be equal");
1197 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1201 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1202 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1205 return yyerror ("Dregs expected");
1208 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1210 if (IS_DREG ($3) && IS_DREG ($5))
1212 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1213 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1216 return yyerror ("Dregs expected");
1219 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1221 if (IS_DREG ($3) && IS_DREG ($5))
1223 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1224 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1227 return yyerror ("Dregs expected");
1232 if (!REG_SAME ($1, $2))
1234 notethat ("dsp32alu: An = Am\n");
1235 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, IS_A1 ($1), 0, 3);
1238 return yyerror ("Accu reg arguments must differ");
1245 notethat ("dsp32alu: An = dregs\n");
1246 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1249 return yyerror ("Dregs expected");
1252 | REG ASSIGN HALF_REG xpmod
1256 if ($1.regno == REG_A0x && IS_DREG ($3))
1258 notethat ("dsp32alu: A0.x = dregs_lo\n");
1259 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1261 else if ($1.regno == REG_A1x && IS_DREG ($3))
1263 notethat ("dsp32alu: A1.x = dregs_lo\n");
1264 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1266 else if (IS_DREG ($1) && IS_DREG ($3))
1268 notethat ("ALU2op: dregs = dregs_lo\n");
1269 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1272 return yyerror ("Register mismatch");
1275 return yyerror ("Low reg expected");
1278 | HALF_REG ASSIGN expr
1280 notethat ("LDIMMhalf: pregs_half = imm16\n");
1282 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1283 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1284 return yyerror ("Wrong register for load immediate");
1286 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1287 return yyerror ("Constant out of range");
1289 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1294 notethat ("dsp32alu: An = 0\n");
1297 return yyerror ("0 expected");
1299 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1302 | REG ASSIGN expr xpmod1
1304 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1305 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1306 return yyerror ("Wrong register for load immediate");
1310 /* 7 bit immediate value if possible.
1311 We will check for that constant value for efficiency
1312 If it goes to reloc, it will be 16 bit. */
1313 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1315 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1316 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1318 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1320 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1321 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1325 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1326 return yyerror ("Immediate value out of range");
1328 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1330 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1335 /* (z) There is no 7 bit zero extended instruction.
1336 If the expr is a relocation, generate it. */
1338 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1339 return yyerror ("Immediate value out of range");
1341 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1343 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1347 | HALF_REG ASSIGN REG
1350 return yyerror ("Low reg expected");
1352 if (IS_DREG ($1) && $3.regno == REG_A0x)
1354 notethat ("dsp32alu: dregs_lo = A0.x\n");
1355 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 0);
1357 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1359 notethat ("dsp32alu: dregs_lo = A1.x\n");
1360 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 1);
1363 return yyerror ("Register mismatch");
1366 | REG ASSIGN REG op_bar_op REG amod0
1368 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1370 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1371 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1374 return yyerror ("Register mismatch");
1377 | REG ASSIGN BYTE_DREG xpmod
1379 if (IS_DREG ($1) && IS_DREG ($3))
1381 notethat ("ALU2op: dregs = dregs_byte\n");
1382 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1385 return yyerror ("Register mismatch");
1388 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1390 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1392 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1393 $$ = DSP32ALU (16, 0, 0, 0, ®7, ®7, 0, 0, 3);
1396 return yyerror ("Register mismatch");
1399 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1401 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1403 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1404 $$ = DSP32ALU (14, 0, 0, 0, ®7, ®7, 0, 0, 3);
1407 return yyerror ("Register mismatch");
1410 | a_minusassign REG_A w32_or_nothing
1412 if (!IS_A1 ($1) && IS_A1 ($2))
1414 notethat ("dsp32alu: A0 -= A1\n");
1415 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $3.r0, 0, 3);
1418 return yyerror ("Register mismatch");
1421 | REG _MINUS_ASSIGN expr
1423 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1425 notethat ("dagMODik: iregs -= 4\n");
1426 $$ = DAGMODIK (&$1, 3);
1428 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1430 notethat ("dagMODik: iregs -= 2\n");
1431 $$ = DAGMODIK (&$1, 1);
1434 return yyerror ("Register or value mismatch");
1437 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1439 if (IS_IREG ($1) && IS_MREG ($3))
1441 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1443 $$ = DAGMODIM (&$1, &$3, 0, 1);
1445 else if (IS_PREG ($1) && IS_PREG ($3))
1447 notethat ("PTR2op: pregs += pregs (BREV )\n");
1448 $$ = PTR2OP (&$1, &$3, 5);
1451 return yyerror ("Register mismatch");
1454 | REG _MINUS_ASSIGN REG
1456 if (IS_IREG ($1) && IS_MREG ($3))
1458 notethat ("dagMODim: iregs -= mregs\n");
1459 $$ = DAGMODIM (&$1, &$3, 1, 0);
1461 else if (IS_PREG ($1) && IS_PREG ($3))
1463 notethat ("PTR2op: pregs -= pregs\n");
1464 $$ = PTR2OP (&$1, &$3, 0);
1467 return yyerror ("Register mismatch");
1470 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1472 if (!IS_A1 ($1) && IS_A1 ($3))
1474 notethat ("dsp32alu: A0 += A1 (W32)\n");
1475 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $4.r0, 0, 2);
1478 return yyerror ("Register mismatch");
1481 | REG _PLUS_ASSIGN REG
1483 if (IS_IREG ($1) && IS_MREG ($3))
1485 notethat ("dagMODim: iregs += mregs\n");
1486 $$ = DAGMODIM (&$1, &$3, 0, 0);
1489 return yyerror ("iregs += mregs expected");
1492 | REG _PLUS_ASSIGN expr
1496 if (EXPR_VALUE ($3) == 4)
1498 notethat ("dagMODik: iregs += 4\n");
1499 $$ = DAGMODIK (&$1, 2);
1501 else if (EXPR_VALUE ($3) == 2)
1503 notethat ("dagMODik: iregs += 2\n");
1504 $$ = DAGMODIK (&$1, 0);
1507 return yyerror ("iregs += [ 2 | 4 ");
1509 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1511 notethat ("COMPI2opP: pregs += imm7\n");
1512 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1514 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1516 notethat ("COMPI2opD: dregs += imm7\n");
1517 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1519 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1520 return yyerror ("Immediate value out of range");
1522 return yyerror ("Register mismatch");
1525 | REG _STAR_ASSIGN REG
1527 if (IS_DREG ($1) && IS_DREG ($3))
1529 notethat ("ALU2op: dregs *= dregs\n");
1530 $$ = ALU2OP (&$1, &$3, 3);
1533 return yyerror ("Register mismatch");
1536 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1538 if (!valid_dreg_pair (&$3, $5))
1539 return yyerror ("Bad dreg pair");
1540 else if (!valid_dreg_pair (&$7, $9))
1541 return yyerror ("Bad dreg pair");
1544 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1545 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1549 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1551 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1553 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1554 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, 2);
1557 return yyerror ("Register mismatch");
1560 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1562 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1563 && REG_SAME ($1, $4))
1565 if (EXPR_VALUE ($9) == 1)
1567 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1568 $$ = ALU2OP (&$1, &$6, 4);
1570 else if (EXPR_VALUE ($9) == 2)
1572 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1573 $$ = ALU2OP (&$1, &$6, 5);
1576 return yyerror ("Bad shift value");
1578 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1579 && REG_SAME ($1, $4))
1581 if (EXPR_VALUE ($9) == 1)
1583 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1584 $$ = PTR2OP (&$1, &$6, 6);
1586 else if (EXPR_VALUE ($9) == 2)
1588 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1589 $$ = PTR2OP (&$1, &$6, 7);
1592 return yyerror ("Bad shift value");
1595 return yyerror ("Register mismatch");
1599 | REG ASSIGN REG BAR REG
1601 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1603 notethat ("COMP3op: dregs = dregs | dregs\n");
1604 $$ = COMP3OP (&$1, &$3, &$5, 3);
1607 return yyerror ("Dregs expected");
1609 | REG ASSIGN REG CARET REG
1611 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1613 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1614 $$ = COMP3OP (&$1, &$3, &$5, 4);
1617 return yyerror ("Dregs expected");
1619 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1621 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1623 if (EXPR_VALUE ($8) == 1)
1625 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1626 $$ = COMP3OP (&$1, &$3, &$6, 6);
1628 else if (EXPR_VALUE ($8) == 2)
1630 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1631 $$ = COMP3OP (&$1, &$3, &$6, 7);
1634 return yyerror ("Bad shift value");
1637 return yyerror ("Dregs expected");
1639 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1641 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1643 notethat ("CCflag: CC = A0 == A1\n");
1644 $$ = CCFLAG (0, 0, 5, 0, 0);
1647 return yyerror ("AREGs are in bad order or same");
1649 | CCREG ASSIGN REG_A LESS_THAN REG_A
1651 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1653 notethat ("CCflag: CC = A0 < A1\n");
1654 $$ = CCFLAG (0, 0, 6, 0, 0);
1657 return yyerror ("AREGs are in bad order or same");
1659 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1661 if ((IS_DREG ($3) && IS_DREG ($5))
1662 || (IS_PREG ($3) && IS_PREG ($5)))
1664 notethat ("CCflag: CC = dpregs < dpregs\n");
1665 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1668 return yyerror ("Bad register in comparison");
1670 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1672 if (!IS_DREG ($3) && !IS_PREG ($3))
1673 return yyerror ("Bad register in comparison");
1675 if (($6.r0 == 1 && IS_IMM ($5, 3))
1676 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1678 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1679 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1682 return yyerror ("Bad constant value");
1684 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1686 if ((IS_DREG ($3) && IS_DREG ($5))
1687 || (IS_PREG ($3) && IS_PREG ($5)))
1689 notethat ("CCflag: CC = dpregs == dpregs\n");
1690 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1693 return yyerror ("Bad register in comparison");
1695 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1697 if (!IS_DREG ($3) && !IS_PREG ($3))
1698 return yyerror ("Bad register in comparison");
1702 notethat ("CCflag: CC = dpregs == imm3\n");
1703 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1706 return yyerror ("Bad constant range");
1708 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1710 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1712 notethat ("CCflag: CC = A0 <= A1\n");
1713 $$ = CCFLAG (0, 0, 7, 0, 0);
1716 return yyerror ("AREGs are in bad order or same");
1718 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1720 if ((IS_DREG ($3) && IS_DREG ($5))
1721 || (IS_PREG ($3) && IS_PREG ($5)))
1723 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1724 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1725 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1728 return yyerror ("Bad register in comparison");
1730 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1732 if (!IS_DREG ($3) && !IS_PREG ($3))
1733 return yyerror ("Bad register in comparison");
1735 if (($6.r0 == 1 && IS_IMM ($5, 3))
1736 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1738 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1739 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1742 return yyerror ("Bad constant value");
1745 | REG ASSIGN REG AMPERSAND REG
1747 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1749 notethat ("COMP3op: dregs = dregs & dregs\n");
1750 $$ = COMP3OP (&$1, &$3, &$5, 2);
1753 return yyerror ("Dregs expected");
1758 notethat ("CC2stat operation\n");
1759 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1764 if ((IS_GENREG ($1) && IS_GENREG ($3))
1765 || (IS_GENREG ($1) && IS_DAGREG ($3))
1766 || (IS_DAGREG ($1) && IS_GENREG ($3))
1767 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1768 || (IS_GENREG ($1) && $3.regno == REG_USP)
1769 || ($1.regno == REG_USP && IS_GENREG ($3))
1770 || ($1.regno == REG_USP && $3.regno == REG_USP)
1771 || (IS_DREG ($1) && IS_SYSREG ($3))
1772 || (IS_PREG ($1) && IS_SYSREG ($3))
1773 || (IS_SYSREG ($1) && IS_GENREG ($3))
1774 || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1775 || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1776 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1778 $$ = bfin_gen_regmv (&$3, &$1);
1781 return yyerror ("Unsupported register move");
1788 notethat ("CC2dreg: CC = dregs\n");
1789 $$ = bfin_gen_cc2dreg (1, &$3);
1792 return yyerror ("Only 'CC = Dreg' supported");
1799 notethat ("CC2dreg: dregs = CC\n");
1800 $$ = bfin_gen_cc2dreg (0, &$1);
1803 return yyerror ("Only 'Dreg = CC' supported");
1806 | CCREG _ASSIGN_BANG CCREG
1808 notethat ("CC2dreg: CC =! CC\n");
1809 $$ = bfin_gen_cc2dreg (3, 0);
1814 | HALF_REG ASSIGN multiply_halfregs opt_mode
1816 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1818 if (!IS_H ($1) && $4.MM)
1819 return yyerror ("(M) not allowed with MAC0");
1821 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1822 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1823 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1824 return yyerror ("bad option.");
1828 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1829 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1830 &$1, 0, &$3.s0, &$3.s1, 0);
1834 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1835 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1836 &$1, 0, &$3.s0, &$3.s1, 1);
1840 | REG ASSIGN multiply_halfregs opt_mode
1842 /* Odd registers can use (M). */
1844 return yyerror ("Dreg expected");
1846 if (IS_EVEN ($1) && $4.MM)
1847 return yyerror ("(M) not allowed with MAC0");
1849 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1850 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1851 return yyerror ("bad option");
1855 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1857 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1858 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1859 &$1, 0, &$3.s0, &$3.s1, 0);
1863 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1864 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1865 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1866 &$1, 0, &$3.s0, &$3.s1, 1);
1870 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1871 HALF_REG ASSIGN multiply_halfregs opt_mode
1873 if (!IS_DREG ($1) || !IS_DREG ($6))
1874 return yyerror ("Dregs expected");
1876 if (!IS_HCOMPL($1, $6))
1877 return yyerror ("Dest registers mismatch");
1879 if (check_multiply_halfregs (&$3, &$8) < 0)
1882 if ((!IS_H ($1) && $4.MM)
1883 || (!IS_H ($6) && $9.MM))
1884 return yyerror ("(M) not allowed with MAC0");
1886 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1887 "dregs_lo = multiply_halfregs opt_mode\n");
1890 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1891 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1892 &$1, 0, &$3.s0, &$3.s1, 1);
1894 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1895 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1896 &$1, 0, &$3.s0, &$3.s1, 1);
1899 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1901 if (!IS_DREG ($1) || !IS_DREG ($6))
1902 return yyerror ("Dregs expected");
1904 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1905 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1906 return yyerror ("Dest registers mismatch");
1908 if (check_multiply_halfregs (&$3, &$8) < 0)
1911 if ((IS_EVEN ($1) && $4.MM)
1912 || (IS_EVEN ($6) && $9.MM))
1913 return yyerror ("(M) not allowed with MAC0");
1915 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1916 "dregs = multiply_halfregs opt_mode\n");
1919 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1920 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1921 &$1, 0, &$3.s0, &$3.s1, 1);
1923 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1924 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1925 &$1, 0, &$3.s0, &$3.s1, 1);
1930 | a_assign ASHIFT REG_A BY HALF_REG
1932 if (!REG_SAME ($1, $3))
1933 return yyerror ("Aregs must be same");
1935 if (IS_DREG ($5) && !IS_H ($5))
1937 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1938 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1941 return yyerror ("Dregs expected");
1944 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1946 if (IS_DREG ($6) && !IS_H ($6))
1948 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1949 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1952 return yyerror ("Dregs expected");
1955 | a_assign REG_A LESS_LESS expr
1957 if (!REG_SAME ($1, $2))
1958 return yyerror ("Aregs must be same");
1960 if (IS_UIMM ($4, 5))
1962 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1963 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1966 return yyerror ("Bad shift value");
1969 | REG ASSIGN REG LESS_LESS expr vsmod
1971 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1976 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1977 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1981 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1982 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1985 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1987 if (EXPR_VALUE ($5) == 2)
1989 notethat ("PTR2op: pregs = pregs << 2\n");
1990 $$ = PTR2OP (&$1, &$3, 1);
1992 else if (EXPR_VALUE ($5) == 1)
1994 notethat ("COMP3op: pregs = pregs << 1\n");
1995 $$ = COMP3OP (&$1, &$3, &$3, 5);
1998 return yyerror ("Bad shift value");
2001 return yyerror ("Bad shift value or register");
2003 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
2005 if (IS_UIMM ($5, 4))
2009 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
2010 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2014 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2015 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2019 return yyerror ("Bad shift value");
2021 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2025 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2030 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2031 "dregs_lo (V, .)\n");
2037 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2039 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2042 return yyerror ("Dregs expected");
2046 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2048 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2050 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2051 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2054 return yyerror ("Bad shift value or register");
2058 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2060 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2062 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2063 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2065 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2067 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2068 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2071 return yyerror ("Bad shift value or register");
2076 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2078 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2080 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2081 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2084 return yyerror ("Register mismatch");
2087 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2089 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2091 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2092 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2095 return yyerror ("Register mismatch");
2098 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2100 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2102 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2103 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2106 return yyerror ("Register mismatch");
2109 | a_assign REG_A _GREATER_GREATER_GREATER expr
2111 if (!REG_SAME ($1, $2))
2112 return yyerror ("Aregs must be same");
2114 if (IS_UIMM ($4, 5))
2116 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2117 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2120 return yyerror ("Shift value range error");
2122 | a_assign LSHIFT REG_A BY HALF_REG
2124 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2126 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2127 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2130 return yyerror ("Register mismatch");
2133 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2135 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2137 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2138 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2141 return yyerror ("Register mismatch");
2144 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2146 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2148 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2149 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2152 return yyerror ("Register mismatch");
2155 | REG ASSIGN SHIFT REG BY HALF_REG
2157 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2159 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2160 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2163 return yyerror ("Register mismatch");
2166 | a_assign REG_A GREATER_GREATER expr
2168 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2170 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2171 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2174 return yyerror ("Accu register expected");
2177 | REG ASSIGN REG GREATER_GREATER expr vmod
2181 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2183 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2184 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2187 return yyerror ("Register mismatch");
2191 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2193 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2194 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2196 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2198 notethat ("PTR2op: pregs = pregs >> 2\n");
2199 $$ = PTR2OP (&$1, &$3, 3);
2201 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2203 notethat ("PTR2op: pregs = pregs >> 1\n");
2204 $$ = PTR2OP (&$1, &$3, 4);
2207 return yyerror ("Register mismatch");
2210 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2212 if (IS_UIMM ($5, 5))
2214 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2215 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2218 return yyerror ("Register mismatch");
2220 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2222 if (IS_UIMM ($5, 5))
2224 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2225 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2226 $6.s0, HL2 ($1, $3));
2229 return yyerror ("Register or modifier mismatch");
2233 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2235 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2240 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2241 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2245 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2246 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2250 return yyerror ("Register mismatch");
2253 | HALF_REG ASSIGN ONES REG
2255 if (IS_DREG_L ($1) && IS_DREG ($4))
2257 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2258 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2261 return yyerror ("Register mismatch");
2264 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2266 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2268 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2269 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2272 return yyerror ("Register mismatch");
2275 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2278 && $7.regno == REG_A0
2279 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2281 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2282 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2285 return yyerror ("Register mismatch");
2288 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2291 && $7.regno == REG_A0
2292 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2294 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2295 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2298 return yyerror ("Register mismatch");
2301 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2303 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2305 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2306 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2309 return yyerror ("Register mismatch");
2312 | a_assign ROT REG_A BY HALF_REG
2314 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2316 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2317 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2320 return yyerror ("Register mismatch");
2323 | REG ASSIGN ROT REG BY HALF_REG
2325 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2327 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2328 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2331 return yyerror ("Register mismatch");
2334 | a_assign ROT REG_A BY expr
2338 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2339 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2342 return yyerror ("Register mismatch");
2345 | REG ASSIGN ROT REG BY expr
2347 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2349 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2352 return yyerror ("Register mismatch");
2355 | HALF_REG ASSIGN SIGNBITS REG_A
2359 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2360 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2363 return yyerror ("Register mismatch");
2366 | HALF_REG ASSIGN SIGNBITS REG
2368 if (IS_DREG_L ($1) && IS_DREG ($4))
2370 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2371 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2374 return yyerror ("Register mismatch");
2377 | HALF_REG ASSIGN SIGNBITS HALF_REG
2381 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2382 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2385 return yyerror ("Register mismatch");
2388 /* The ASR bit is just inverted here. */
2389 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2391 if (IS_DREG_L ($1) && IS_DREG ($5))
2393 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2394 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2397 return yyerror ("Register mismatch");
2400 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2402 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2404 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2405 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2408 return yyerror ("Register mismatch");
2411 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2413 if (REG_SAME ($3, $5))
2414 return yyerror ("Illegal source register combination");
2416 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2418 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2419 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2422 return yyerror ("Register mismatch");
2425 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2427 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2429 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2430 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2433 return yyerror ("Dregs expected");
2437 /* LOGI2op: BITCLR (dregs, uimm5). */
2438 | BITCLR LPAREN REG COMMA expr RPAREN
2440 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2442 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2443 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2446 return yyerror ("Register mismatch");
2449 /* LOGI2op: BITSET (dregs, uimm5). */
2450 | BITSET LPAREN REG COMMA expr RPAREN
2452 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2454 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2455 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2458 return yyerror ("Register mismatch");
2461 /* LOGI2op: BITTGL (dregs, uimm5). */
2462 | BITTGL LPAREN REG COMMA expr RPAREN
2464 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2466 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2467 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2470 return yyerror ("Register mismatch");
2473 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2475 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2477 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2478 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2481 return yyerror ("Register mismatch or value error");
2484 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2486 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2488 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2489 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2492 return yyerror ("Register mismatch or value error");
2495 | IF BANG CCREG REG ASSIGN REG
2497 if ((IS_DREG ($4) || IS_PREG ($4))
2498 && (IS_DREG ($6) || IS_PREG ($6)))
2500 notethat ("ccMV: IF ! CC gregs = gregs\n");
2501 $$ = CCMV (&$6, &$4, 0);
2504 return yyerror ("Register mismatch");
2507 | IF CCREG REG ASSIGN REG
2509 if ((IS_DREG ($5) || IS_PREG ($5))
2510 && (IS_DREG ($3) || IS_PREG ($3)))
2512 notethat ("ccMV: IF CC gregs = gregs\n");
2513 $$ = CCMV (&$5, &$3, 1);
2516 return yyerror ("Register mismatch");
2519 | IF BANG CCREG JUMP expr
2521 if (IS_PCREL10 ($5))
2523 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2524 $$ = BRCC (0, 0, $5);
2527 return yyerror ("Bad jump offset");
2530 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2532 if (IS_PCREL10 ($5))
2534 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2535 $$ = BRCC (0, 1, $5);
2538 return yyerror ("Bad jump offset");
2541 | IF CCREG JUMP expr
2543 if (IS_PCREL10 ($4))
2545 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2546 $$ = BRCC (1, 0, $4);
2549 return yyerror ("Bad jump offset");
2552 | IF CCREG JUMP expr LPAREN BP RPAREN
2554 if (IS_PCREL10 ($4))
2556 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2557 $$ = BRCC (1, 1, $4);
2560 return yyerror ("Bad jump offset");
2564 notethat ("ProgCtrl: NOP\n");
2565 $$ = PROGCTRL (0, 0);
2570 notethat ("ProgCtrl: RTS\n");
2571 $$ = PROGCTRL (1, 0);
2576 notethat ("ProgCtrl: RTI\n");
2577 $$ = PROGCTRL (1, 1);
2582 notethat ("ProgCtrl: RTX\n");
2583 $$ = PROGCTRL (1, 2);
2588 notethat ("ProgCtrl: RTN\n");
2589 $$ = PROGCTRL (1, 3);
2594 notethat ("ProgCtrl: RTE\n");
2595 $$ = PROGCTRL (1, 4);
2600 notethat ("ProgCtrl: IDLE\n");
2601 $$ = PROGCTRL (2, 0);
2606 notethat ("ProgCtrl: CSYNC\n");
2607 $$ = PROGCTRL (2, 3);
2612 notethat ("ProgCtrl: SSYNC\n");
2613 $$ = PROGCTRL (2, 4);
2618 notethat ("ProgCtrl: EMUEXCPT\n");
2619 $$ = PROGCTRL (2, 5);
2626 notethat ("ProgCtrl: CLI dregs\n");
2627 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2630 return yyerror ("Dreg expected for CLI");
2637 notethat ("ProgCtrl: STI dregs\n");
2638 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2641 return yyerror ("Dreg expected for STI");
2644 | JUMP LPAREN REG RPAREN
2648 notethat ("ProgCtrl: JUMP (pregs )\n");
2649 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2652 return yyerror ("Bad register for indirect jump");
2655 | CALL LPAREN REG RPAREN
2659 notethat ("ProgCtrl: CALL (pregs )\n");
2660 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2663 return yyerror ("Bad register for indirect call");
2666 | CALL LPAREN PC PLUS REG RPAREN
2670 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2671 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2674 return yyerror ("Bad register for indirect call");
2677 | JUMP LPAREN PC PLUS REG RPAREN
2681 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2682 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2685 return yyerror ("Bad register for indirect jump");
2690 if (IS_UIMM ($2, 4))
2692 notethat ("ProgCtrl: RAISE uimm4\n");
2693 $$ = PROGCTRL (9, uimm4 ($2));
2696 return yyerror ("Bad value for RAISE");
2701 notethat ("ProgCtrl: EMUEXCPT\n");
2702 $$ = PROGCTRL (10, uimm4 ($2));
2705 | TESTSET LPAREN REG RPAREN
2709 if ($3.regno == REG_SP || $3.regno == REG_FP)
2710 return yyerror ("Bad register for TESTSET");
2712 notethat ("ProgCtrl: TESTSET (pregs )\n");
2713 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2716 return yyerror ("Preg expected");
2721 if (IS_PCREL12 ($2))
2723 notethat ("UJUMP: JUMP pcrel12\n");
2727 return yyerror ("Bad value for relative jump");
2732 if (IS_PCREL12 ($2))
2734 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2738 return yyerror ("Bad value for relative jump");
2743 if (IS_PCREL24 ($2))
2745 notethat ("CALLa: jump.l pcrel24\n");
2749 return yyerror ("Bad value for long jump");
2754 if (IS_PCREL24 ($2))
2756 notethat ("CALLa: jump.l pcrel24\n");
2760 return yyerror ("Bad value for long jump");
2765 if (IS_PCREL24 ($2))
2767 notethat ("CALLa: CALL pcrel25m2\n");
2771 return yyerror ("Bad call address");
2775 if (IS_PCREL24 ($2))
2777 notethat ("CALLa: CALL pcrel25m2\n");
2781 return yyerror ("Bad call address");
2785 /* ALU2op: DIVQ (dregs, dregs). */
2786 | DIVQ LPAREN REG COMMA REG RPAREN
2788 if (IS_DREG ($3) && IS_DREG ($5))
2789 $$ = ALU2OP (&$3, &$5, 8);
2791 return yyerror ("Bad registers for DIVQ");
2794 | DIVS LPAREN REG COMMA REG RPAREN
2796 if (IS_DREG ($3) && IS_DREG ($5))
2797 $$ = ALU2OP (&$3, &$5, 9);
2799 return yyerror ("Bad registers for DIVS");
2802 | REG ASSIGN MINUS REG vsmod
2804 if (IS_DREG ($1) && IS_DREG ($4))
2806 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2808 notethat ("ALU2op: dregs = - dregs\n");
2809 $$ = ALU2OP (&$1, &$4, 14);
2811 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2813 notethat ("dsp32alu: dregs = - dregs (.)\n");
2814 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2818 notethat ("dsp32alu: dregs = - dregs (.)\n");
2819 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2823 return yyerror ("Dregs expected");
2826 | REG ASSIGN TILDA REG
2828 if (IS_DREG ($1) && IS_DREG ($4))
2830 notethat ("ALU2op: dregs = ~dregs\n");
2831 $$ = ALU2OP (&$1, &$4, 15);
2834 return yyerror ("Dregs expected");
2837 | REG _GREATER_GREATER_ASSIGN REG
2839 if (IS_DREG ($1) && IS_DREG ($3))
2841 notethat ("ALU2op: dregs >>= dregs\n");
2842 $$ = ALU2OP (&$1, &$3, 1);
2845 return yyerror ("Dregs expected");
2848 | REG _GREATER_GREATER_ASSIGN expr
2850 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2852 notethat ("LOGI2op: dregs >>= uimm5\n");
2853 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2856 return yyerror ("Dregs expected or value error");
2859 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2861 if (IS_DREG ($1) && IS_DREG ($3))
2863 notethat ("ALU2op: dregs >>>= dregs\n");
2864 $$ = ALU2OP (&$1, &$3, 0);
2867 return yyerror ("Dregs expected");
2870 | REG _LESS_LESS_ASSIGN REG
2872 if (IS_DREG ($1) && IS_DREG ($3))
2874 notethat ("ALU2op: dregs <<= dregs\n");
2875 $$ = ALU2OP (&$1, &$3, 2);
2878 return yyerror ("Dregs expected");
2881 | REG _LESS_LESS_ASSIGN expr
2883 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2885 notethat ("LOGI2op: dregs <<= uimm5\n");
2886 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2889 return yyerror ("Dregs expected or const value error");
2893 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2895 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2897 notethat ("LOGI2op: dregs >>>= uimm5\n");
2898 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2901 return yyerror ("Dregs expected");
2904 /* Cache Control. */
2906 | FLUSH LBRACK REG RBRACK
2908 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2910 $$ = CACTRL (&$3, 0, 2);
2912 return yyerror ("Bad register(s) for FLUSH");
2915 | FLUSH reg_with_postinc
2919 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2920 $$ = CACTRL (&$2, 1, 2);
2923 return yyerror ("Bad register(s) for FLUSH");
2926 | FLUSHINV LBRACK REG RBRACK
2930 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2931 $$ = CACTRL (&$3, 0, 1);
2934 return yyerror ("Bad register(s) for FLUSH");
2937 | FLUSHINV reg_with_postinc
2941 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2942 $$ = CACTRL (&$2, 1, 1);
2945 return yyerror ("Bad register(s) for FLUSH");
2948 /* CaCTRL: IFLUSH [pregs]. */
2949 | IFLUSH LBRACK REG RBRACK
2953 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2954 $$ = CACTRL (&$3, 0, 3);
2957 return yyerror ("Bad register(s) for FLUSH");
2960 | IFLUSH reg_with_postinc
2964 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2965 $$ = CACTRL (&$2, 1, 3);
2968 return yyerror ("Bad register(s) for FLUSH");
2971 | PREFETCH LBRACK REG RBRACK
2975 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2976 $$ = CACTRL (&$3, 0, 0);
2979 return yyerror ("Bad register(s) for PREFETCH");
2982 | PREFETCH reg_with_postinc
2986 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2987 $$ = CACTRL (&$2, 1, 0);
2990 return yyerror ("Bad register(s) for PREFETCH");
2994 /* LDST: B [ pregs <post_op> ] = dregs. */
2996 | B LBRACK REG post_op RBRACK ASSIGN REG
2999 return yyerror ("Dreg expected for source operand");
3001 return yyerror ("Preg expected in address");
3003 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
3004 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
3007 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
3008 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
3010 Expr_Node *tmp = $5;
3013 return yyerror ("Dreg expected for source operand");
3015 return yyerror ("Preg expected in address");
3018 return yyerror ("Plain symbol used as offset");
3021 tmp = unary (Expr_Op_Type_NEG, tmp);
3023 if (in_range_p (tmp, -32768, 32767, 0))
3025 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3026 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3029 return yyerror ("Displacement out of range");
3033 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3034 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3036 Expr_Node *tmp = $5;
3039 return yyerror ("Dreg expected for source operand");
3041 return yyerror ("Preg expected in address");
3044 tmp = unary (Expr_Op_Type_NEG, tmp);
3047 return yyerror ("Plain symbol used as offset");
3049 if (in_range_p (tmp, 0, 30, 1))
3051 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3052 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3054 else if (in_range_p (tmp, -65536, 65535, 1))
3056 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3057 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3060 return yyerror ("Displacement out of range");
3063 /* LDST: W [ pregs <post_op> ] = dregs. */
3064 | W LBRACK REG post_op RBRACK ASSIGN REG
3067 return yyerror ("Dreg expected for source operand");
3069 return yyerror ("Preg expected in address");
3071 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3072 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3075 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3078 return yyerror ("Dreg expected for source operand");
3081 if (!IS_IREG ($3) && !IS_PREG ($3))
3082 return yyerror ("Ireg or Preg expected in address");
3084 else if (!IS_IREG ($3))
3085 return yyerror ("Ireg expected in address");
3089 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3090 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3094 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3095 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3099 /* LDSTiiFP: [ FP - const ] = dpregs. */
3100 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3102 Expr_Node *tmp = $4;
3103 int ispreg = IS_PREG ($7);
3106 return yyerror ("Preg expected in address");
3108 if (!IS_DREG ($7) && !ispreg)
3109 return yyerror ("Preg expected for source operand");
3112 tmp = unary (Expr_Op_Type_NEG, tmp);
3115 return yyerror ("Plain symbol used as offset");
3117 if (in_range_p (tmp, 0, 63, 3))
3119 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3120 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3122 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3124 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3125 tmp = unary (Expr_Op_Type_NEG, tmp);
3126 $$ = LDSTIIFP (tmp, &$7, 1);
3128 else if (in_range_p (tmp, -131072, 131071, 3))
3130 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3131 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3134 return yyerror ("Displacement out of range");
3137 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3139 Expr_Node *tmp = $7;
3141 return yyerror ("Dreg expected for destination operand");
3143 return yyerror ("Preg expected in address");
3146 tmp = unary (Expr_Op_Type_NEG, tmp);
3149 return yyerror ("Plain symbol used as offset");
3151 if (in_range_p (tmp, 0, 30, 1))
3153 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3154 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3156 else if (in_range_p (tmp, -65536, 65535, 1))
3158 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3159 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3162 return yyerror ("Displacement out of range");
3165 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3168 return yyerror ("Dreg expected for source operand");
3171 if (!IS_IREG ($5) && !IS_PREG ($5))
3172 return yyerror ("Ireg or Preg expected in address");
3174 else if (!IS_IREG ($5))
3175 return yyerror ("Ireg expected in address");
3179 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3180 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3184 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3185 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3190 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3193 return yyerror ("Dreg expected for destination operand");
3195 return yyerror ("Preg expected in address");
3197 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3198 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3201 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3204 return yyerror ("Dreg expected for destination operand");
3205 if (!IS_PREG ($5) || !IS_PREG ($7))
3206 return yyerror ("Preg expected in address");
3208 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3209 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3212 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3215 return yyerror ("Dreg expected for destination operand");
3216 if (!IS_PREG ($5) || !IS_PREG ($7))
3217 return yyerror ("Preg expected in address");
3219 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3220 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3223 | LBRACK REG post_op RBRACK ASSIGN REG
3225 if (!IS_IREG ($2) && !IS_PREG ($2))
3226 return yyerror ("Ireg or Preg expected in address");
3227 else if (IS_IREG ($2) && !IS_DREG ($6))
3228 return yyerror ("Dreg expected for source operand");
3229 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3230 return yyerror ("Dreg or Preg expected for source operand");
3234 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3235 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3237 else if (IS_DREG ($6))
3239 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3240 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3244 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3245 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3249 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3252 return yyerror ("Dreg expected for source operand");
3254 if (IS_IREG ($2) && IS_MREG ($4))
3256 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3257 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3259 else if (IS_PREG ($2) && IS_PREG ($4))
3261 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3262 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3265 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3268 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3271 return yyerror ("Dreg expected for source operand");
3273 if (IS_PREG ($3) && IS_PREG ($5))
3275 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3276 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3279 return yyerror ("Preg ++ Preg expected in address");
3282 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3284 Expr_Node *tmp = $7;
3286 return yyerror ("Dreg expected for destination operand");
3288 return yyerror ("Preg expected in address");
3291 tmp = unary (Expr_Op_Type_NEG, tmp);
3294 return yyerror ("Plain symbol used as offset");
3296 if (in_range_p (tmp, -32768, 32767, 0))
3298 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3300 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3303 return yyerror ("Displacement out of range");
3306 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3309 return yyerror ("Dreg expected for destination operand");
3311 return yyerror ("Preg expected in address");
3313 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3315 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3318 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3321 return yyerror ("Dreg expected for destination operand");
3323 if (IS_IREG ($4) && IS_MREG ($6))
3325 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3326 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3328 else if (IS_PREG ($4) && IS_PREG ($6))
3330 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3331 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3334 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3337 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3339 Expr_Node *tmp = $6;
3340 int ispreg = IS_PREG ($1);
3341 int isgot = IS_RELOC($6);
3344 return yyerror ("Preg expected in address");
3346 if (!IS_DREG ($1) && !ispreg)
3347 return yyerror ("Dreg or Preg expected for destination operand");
3349 if (tmp->type == Expr_Node_Reloc
3350 && strcmp (tmp->value.s_value,
3351 "_current_shared_library_p5_offset_") != 0)
3352 return yyerror ("Plain symbol used as offset");
3355 tmp = unary (Expr_Op_Type_NEG, tmp);
3359 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3360 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3362 else if (in_range_p (tmp, 0, 63, 3))
3364 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3365 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3367 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3369 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3370 tmp = unary (Expr_Op_Type_NEG, tmp);
3371 $$ = LDSTIIFP (tmp, &$1, 0);
3373 else if (in_range_p (tmp, -131072, 131071, 3))
3375 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3376 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3380 return yyerror ("Displacement out of range");
3383 | REG ASSIGN LBRACK REG post_op RBRACK
3385 if (!IS_IREG ($4) && !IS_PREG ($4))
3386 return yyerror ("Ireg or Preg expected in address");
3387 else if (IS_IREG ($4) && !IS_DREG ($1))
3388 return yyerror ("Dreg expected in destination operand");
3389 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3390 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3391 return yyerror ("Dreg or Preg expected in destination operand");
3395 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3396 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3398 else if (IS_DREG ($1))
3400 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3401 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3403 else if (IS_PREG ($1))
3405 if (REG_SAME ($1, $4) && $5.x0 != 2)
3406 return yyerror ("Pregs can't be same");
3408 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3409 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3413 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3414 $$ = PUSHPOPREG (&$1, 0);
3419 /* PushPopMultiple. */
3420 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3422 if ($1.regno != REG_SP)
3423 yyerror ("Stack Pointer expected");
3424 if ($4.regno == REG_R7
3425 && IN_RANGE ($6, 0, 7)
3426 && $8.regno == REG_P5
3427 && IN_RANGE ($10, 0, 5))
3429 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3430 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3433 return yyerror ("Bad register for PushPopMultiple");
3436 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3438 if ($1.regno != REG_SP)
3439 yyerror ("Stack Pointer expected");
3441 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3443 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3444 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3446 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3448 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3449 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3452 return yyerror ("Bad register for PushPopMultiple");
3455 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3457 if ($11.regno != REG_SP)
3458 yyerror ("Stack Pointer expected");
3459 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3460 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3462 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3463 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3466 return yyerror ("Bad register range for PushPopMultiple");
3469 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3471 if ($7.regno != REG_SP)
3472 yyerror ("Stack Pointer expected");
3474 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3476 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3477 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3479 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3481 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3482 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3485 return yyerror ("Bad register range for PushPopMultiple");
3488 | reg_with_predec ASSIGN REG
3490 if ($1.regno != REG_SP)
3491 yyerror ("Stack Pointer expected");
3495 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3496 $$ = PUSHPOPREG (&$3, 1);
3499 return yyerror ("Bad register for PushPopReg");
3506 if (IS_URANGE (16, $2, 0, 4))
3507 $$ = LINKAGE (0, uimm16s4 ($2));
3509 return yyerror ("Bad constant for LINK");
3514 notethat ("linkage: UNLINK\n");
3515 $$ = LINKAGE (1, 0);
3521 | LSETUP LPAREN expr COMMA expr RPAREN REG
3523 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3525 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3526 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3529 return yyerror ("Bad register or values for LSETUP");
3532 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3534 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3535 && IS_PREG ($9) && IS_CREG ($7))
3537 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3538 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3541 return yyerror ("Bad register or values for LSETUP");
3544 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3546 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3547 && IS_PREG ($9) && IS_CREG ($7)
3548 && EXPR_VALUE ($11) == 1)
3550 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3551 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3554 return yyerror ("Bad register or values for LSETUP");
3561 return yyerror ("Invalid expression in loop statement");
3563 return yyerror ("Invalid loop counter register");
3564 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3566 | LOOP expr REG ASSIGN REG
3568 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3570 notethat ("Loop: LOOP expr counters = pregs\n");
3571 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3574 return yyerror ("Bad register or values for LOOP");
3576 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3578 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3580 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3581 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3584 return yyerror ("Bad register or values for LOOP");
3590 Expr_Node_Value val;
3592 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3593 bfin_loop_attempt_create_label (tmp, 1);
3594 if (!IS_RELOC (tmp))
3595 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3596 bfin_loop_beginend (tmp, 1);
3602 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3604 bfin_loop_beginend ($2, 1);
3611 Expr_Node_Value val;
3613 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3614 bfin_loop_attempt_create_label (tmp, 1);
3615 if (!IS_RELOC (tmp))
3616 return yyerror ("Invalid expression in LOOP_END statement");
3617 bfin_loop_beginend (tmp, 0);
3623 return yyerror ("Invalid expression in LOOP_END statement");
3625 bfin_loop_beginend ($2, 0);
3633 notethat ("psedoDEBUG: ABORT\n");
3634 $$ = bfin_gen_pseudodbg (3, 3, 0);
3639 notethat ("pseudoDEBUG: DBG\n");
3640 $$ = bfin_gen_pseudodbg (3, 7, 0);
3644 notethat ("pseudoDEBUG: DBG REG_A\n");
3645 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3649 notethat ("pseudoDEBUG: DBG allregs\n");
3650 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3653 | DBGCMPLX LPAREN REG RPAREN
3656 return yyerror ("Dregs expected");
3657 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3658 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3663 notethat ("psedoDEBUG: DBGHALT\n");
3664 $$ = bfin_gen_pseudodbg (3, 5, 0);
3669 notethat ("psedoDEBUG: HLT\n");
3670 $$ = bfin_gen_pseudodbg (3, 4, 0);
3673 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3675 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3676 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3679 | DBGAH LPAREN REG COMMA expr RPAREN
3681 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3682 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3685 | DBGAL LPAREN REG COMMA expr RPAREN
3687 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3688 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3693 if (!IS_UIMM ($2, 8))
3694 return yyerror ("Constant out of range");
3695 notethat ("psedodbg_assert: OUTC uimm8\n");
3696 $$ = bfin_gen_pseudochr (uimm8 ($2));
3702 return yyerror ("Dregs expected");
3703 notethat ("psedodbg_assert: OUTC dreg\n");
3704 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3711 /* Register rules. */
3713 REG_A: REG_A_DOUBLE_ZERO
3731 | LPAREN M COMMA MMOD RPAREN
3736 | LPAREN MMOD COMMA M RPAREN
3741 | LPAREN MMOD RPAREN
3753 asr_asl: LPAREN ASL RPAREN
3834 | LPAREN asr_asl_0 RPAREN
3846 | LPAREN asr_asl_0 COMMA sco RPAREN
3852 | LPAREN sco COMMA asr_asl_0 RPAREN
3912 | LPAREN V COMMA S RPAREN
3917 | LPAREN S COMMA V RPAREN
3979 | LPAREN MMOD RPAREN
3982 return yyerror ("Bad modifier");
3986 | LPAREN MMOD COMMA R RPAREN
3989 return yyerror ("Bad modifier");
3993 | LPAREN R COMMA MMOD RPAREN
3996 return yyerror ("Bad modifier");
4023 | LPAREN MMOD RPAREN
4028 return yyerror ("Only (W32) allowed");
4036 | LPAREN MMOD RPAREN
4041 return yyerror ("(IU) expected");
4045 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4051 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4103 $$.r0 = 1; /* HL. */
4106 $$.aop = 0; /* aop. */
4111 $$.r0 = 1; /* HL. */
4114 $$.aop = 1; /* aop. */
4117 | LPAREN RNDL RPAREN
4119 $$.r0 = 0; /* HL. */
4122 $$.aop = 0; /* aop. */
4127 $$.r0 = 0; /* HL. */
4133 | LPAREN RNDH COMMA R RPAREN
4135 $$.r0 = 1; /* HL. */
4138 $$.aop = 0; /* aop. */
4140 | LPAREN TH COMMA R RPAREN
4142 $$.r0 = 1; /* HL. */
4145 $$.aop = 1; /* aop. */
4147 | LPAREN RNDL COMMA R RPAREN
4149 $$.r0 = 0; /* HL. */
4152 $$.aop = 0; /* aop. */
4155 | LPAREN TL COMMA R RPAREN
4157 $$.r0 = 0; /* HL. */
4160 $$.aop = 1; /* aop. */
4168 $$.x0 = 0; /* HL. */
4173 $$.x0 = 1; /* HL. */
4175 | LPAREN LO COMMA R RPAREN
4178 $$.x0 = 0; /* HL. */
4180 | LPAREN HI COMMA R RPAREN
4183 $$.x0 = 1; /* HL. */
4201 /* Assignments, Macfuncs. */
4227 if (IS_A1 ($3) && IS_EVEN ($1))
4228 return yyerror ("Cannot move A1 to even register");
4229 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4230 return yyerror ("Cannot move A0 to odd register");
4246 | REG ASSIGN LPAREN a_macfunc RPAREN
4248 if ($4.n && IS_EVEN ($1))
4249 return yyerror ("Cannot move A1 to even register");
4250 else if (!$4.n && !IS_EVEN ($1))
4251 return yyerror ("Cannot move A0 to odd register");
4259 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4261 if ($4.n && !IS_H ($1))
4262 return yyerror ("Cannot move A1 to low half of register");
4263 else if (!$4.n && IS_H ($1))
4264 return yyerror ("Cannot move A0 to high half of register");
4272 | HALF_REG ASSIGN REG_A
4274 if (IS_A1 ($3) && !IS_H ($1))
4275 return yyerror ("Cannot move A1 to low half of register");
4276 else if (!IS_A1 ($3) && IS_H ($1))
4277 return yyerror ("Cannot move A0 to high half of register");
4290 a_assign multiply_halfregs
4297 | a_plusassign multiply_halfregs
4304 | a_minusassign multiply_halfregs
4314 HALF_REG STAR HALF_REG
4316 if (IS_DREG ($1) && IS_DREG ($3))
4322 return yyerror ("Dregs expected");
4346 CCREG cc_op STATUS_REG
4358 | STATUS_REG cc_op CCREG
4372 /* Expressions and Symbols. */
4376 Expr_Node_Value val;
4377 val.s_value = S_GET_NAME($1);
4378 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4384 { $$ = BFD_RELOC_BFIN_GOT; }
4386 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4388 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4391 got: symbol AT any_gotrel
4393 Expr_Node_Value val;
4395 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4418 Expr_Node_Value val;
4420 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4426 | LPAREN expr_1 RPAREN
4432 $$ = unary (Expr_Op_Type_COMP, $2);
4434 | MINUS expr_1 %prec TILDA
4436 $$ = unary (Expr_Op_Type_NEG, $2);
4446 expr_1: expr_1 STAR expr_1
4448 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4450 | expr_1 SLASH expr_1
4452 $$ = binary (Expr_Op_Type_Div, $1, $3);
4454 | expr_1 PERCENT expr_1
4456 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4458 | expr_1 PLUS expr_1
4460 $$ = binary (Expr_Op_Type_Add, $1, $3);
4462 | expr_1 MINUS expr_1
4464 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4466 | expr_1 LESS_LESS expr_1
4468 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4470 | expr_1 GREATER_GREATER expr_1
4472 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4474 | expr_1 AMPERSAND expr_1
4476 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4478 | expr_1 CARET expr_1
4480 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4484 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4496 mkexpr (int x, SYMBOL_T s)
4498 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4505 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4507 int umax = (1 << sz) - 1;
4508 int min = -1 << (sz - 1);
4509 int max = (1 << (sz - 1)) - 1;
4511 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4515 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4526 if (v >= min && v <= max) return 1;
4529 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4533 if (v <= umax && v >= 0)
4536 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4541 /* Return the expression structure that allows symbol operations.
4542 If the left and right children are constants, do the operation. */
4544 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4546 Expr_Node_Value val;
4548 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4552 case Expr_Op_Type_Add:
4553 x->value.i_value += y->value.i_value;
4555 case Expr_Op_Type_Sub:
4556 x->value.i_value -= y->value.i_value;
4558 case Expr_Op_Type_Mult:
4559 x->value.i_value *= y->value.i_value;
4561 case Expr_Op_Type_Div:
4562 if (y->value.i_value == 0)
4563 error ("Illegal Expression: Division by zero.");
4565 x->value.i_value /= y->value.i_value;
4567 case Expr_Op_Type_Mod:
4568 x->value.i_value %= y->value.i_value;
4570 case Expr_Op_Type_Lshift:
4571 x->value.i_value <<= y->value.i_value;
4573 case Expr_Op_Type_Rshift:
4574 x->value.i_value >>= y->value.i_value;
4576 case Expr_Op_Type_BAND:
4577 x->value.i_value &= y->value.i_value;
4579 case Expr_Op_Type_BOR:
4580 x->value.i_value |= y->value.i_value;
4582 case Expr_Op_Type_BXOR:
4583 x->value.i_value ^= y->value.i_value;
4585 case Expr_Op_Type_LAND:
4586 x->value.i_value = x->value.i_value && y->value.i_value;
4588 case Expr_Op_Type_LOR:
4589 x->value.i_value = x->value.i_value || y->value.i_value;
4593 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4597 /* Canonicalize order to EXPR OP CONSTANT. */
4598 if (x->type == Expr_Node_Constant)
4604 /* Canonicalize subtraction of const to addition of negated const. */
4605 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4607 op = Expr_Op_Type_Add;
4608 y->value.i_value = -y->value.i_value;
4610 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4611 && x->Right_Child->type == Expr_Node_Constant)
4613 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4615 x->Right_Child->value.i_value += y->value.i_value;
4620 /* Create a new expression structure. */
4622 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4626 unary (Expr_Op_Type op, Expr_Node *x)
4628 if (x->type == Expr_Node_Constant)
4632 case Expr_Op_Type_NEG:
4633 x->value.i_value = -x->value.i_value;
4635 case Expr_Op_Type_COMP:
4636 x->value.i_value = ~x->value.i_value;
4639 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4645 /* Create a new expression structure. */
4646 Expr_Node_Value val;
4648 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4652 int debug_codeselection = 0;
4654 notethat (char *format, ...)
4657 va_start (ap, format);
4658 if (debug_codeselection)
4660 vfprintf (errorf, format, ap);
4666 main (int argc, char **argv)