1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *, int, int, int, int);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *, ...);
165 char *current_inputline;
167 int yyerror (char *);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (exp);
199 if (exp->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define uimm8(x) EXPR_VALUE (x)
216 #define imm16(x) EXPR_VALUE (x)
217 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
218 #define uimm16(x) EXPR_VALUE (x)
220 /* Return true if a value is inside a range. */
221 #define IN_RANGE(x, low, high) \
222 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
224 /* Auxiliary functions. */
227 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
229 if (!IS_DREG (*reg1))
231 yyerror ("Dregs expected");
235 if (reg1->regno != 1 && reg1->regno != 3)
237 yyerror ("Bad register pair");
241 if (imm7 (reg2) != reg1->regno - 1)
243 yyerror ("Bad register pair");
252 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
254 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
255 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
256 return yyerror ("Source multiplication register mismatch");
262 /* Check mac option. */
265 check_macfunc_option (Macfunc *a, Opt_mode *opt)
267 /* Default option is always valid. */
271 if ((a->w == 1 && a->P == 1
272 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
273 && opt->mod != M_S2RND && opt->mod != M_ISS2)
274 || (a->w == 1 && a->P == 0
275 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
276 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
277 && opt->mod != M_ISS2 && opt->mod != M_IH)
278 || (a->w == 0 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
285 /* Check (vector) mac funcs and ops. */
288 check_macfuncs (Macfunc *aa, Opt_mode *opa,
289 Macfunc *ab, Opt_mode *opb)
291 /* Variables for swapping. */
295 /* The option mode should be put at the end of the second instruction
296 of the vector except M, which should follow MAC1 instruction. */
298 return yyerror ("Bad opt mode");
300 /* If a0macfunc comes before a1macfunc, swap them. */
304 /* (M) is not allowed here. */
306 return yyerror ("(M) not allowed with A0MAC");
308 return yyerror ("Vector AxMACs can't be same");
310 mtmp = *aa; *aa = *ab; *ab = mtmp;
311 otmp = *opa; *opa = *opb; *opb = otmp;
316 return yyerror ("(M) not allowed with A0MAC");
318 return yyerror ("Vector AxMACs can't be same");
321 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
322 assignment_or_macfuncs. */
323 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
324 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
326 if (check_multiply_halfregs (aa, ab) < 0)
331 /* Only one of the assign_macfuncs has a half reg multiply
332 Evil trick: Just 'OR' their source register codes:
333 We can do that, because we know they were initialized to 0
334 in the rules that don't use multiply_halfregs. */
335 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
336 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
339 if (aa->w == ab->w && aa->P != ab->P)
340 return yyerror ("Destination Dreg sizes (full or half) must match");
344 if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
345 return yyerror ("Destination Dregs (full) must differ by one");
346 if (!aa->P && aa->dst.regno != ab->dst.regno)
347 return yyerror ("Destination Dregs (half) must match");
350 /* Make sure mod flags get ORed, too. */
351 opb->mod |= opa->mod;
354 if (check_macfunc_option (aa, opb) < 0
355 && check_macfunc_option (ab, opb) < 0)
356 return yyerror ("bad option");
358 /* Make sure first macfunc has got both P flags ORed. */
366 is_group1 (INSTR_T x)
368 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
369 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
376 is_group2 (INSTR_T x)
378 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
379 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
380 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
381 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
382 || (x->value == 0x0000))
393 if ((x->value & 0xf000) == 0x8000)
395 int aop = ((x->value >> 9) & 0x3);
396 int w = ((x->value >> 11) & 0x1);
402 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
403 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
406 /* decode_dspLDST_0 */
407 if ((x->value & 0xFC00) == 0x9C00)
409 int w = ((x->value >> 9) & 0x1);
418 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
420 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
421 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
422 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
424 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
425 yyerror ("resource conflict in multi-issue instruction");
427 /* Anomaly 05000074 */
428 if (ENABLE_AC_05000074
429 && dsp32 != NULL && dsp16_grp1 != NULL
430 && (dsp32->value & 0xf780) == 0xc680
431 && ((dsp16_grp1->value & 0xfe40) == 0x9240
432 || (dsp16_grp1->value & 0xfe08) == 0xba08
433 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
434 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
435 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
437 if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
438 yyerror ("Only one instruction in multi-issue instruction can be a store");
440 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
452 struct { int r0; int s0; int x0; int aop; } modcodes;
453 struct { int r0; } r0;
460 /* Vector Specific. */
461 %token BYTEOP16P BYTEOP16M
462 %token BYTEOP1P BYTEOP2P BYTEOP3P
463 %token BYTEUNPACK BYTEPACK
466 %token ALIGN8 ALIGN16 ALIGN24
468 %token EXTRACT DEPOSIT EXPADJ SEARCH
469 %token ONES SIGN SIGNBITS
477 %token CCREG BYTE_DREG
478 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
479 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
484 %token RTI RTS RTX RTN RTE
495 %token JUMP JUMP_DOT_S JUMP_DOT_L
502 %token NOT TILDA BANG
508 %token MINUS PLUS STAR SLASH
512 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
513 %token _MINUS_MINUS _PLUS_PLUS
515 /* Shift/rotate ops. */
516 %token SHIFT LSHIFT ASHIFT BXORSHIFT
517 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
519 %token LESS_LESS GREATER_GREATER
520 %token _GREATER_GREATER_GREATER
521 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
524 /* In place operators. */
525 %token ASSIGN _STAR_ASSIGN
526 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
527 %token _MINUS_ASSIGN _PLUS_ASSIGN
529 /* Assignments, comparisons. */
530 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
535 %token FLUSHINV FLUSH
536 %token IFLUSH PREFETCH
553 %token R RND RNDL RNDH RND12 RND20
558 %token BITTGL BITCLR BITSET BITTST BITMUX
561 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
563 /* Semantic auxiliaries. */
566 %token COLON SEMICOLON
567 %token RPAREN LPAREN LBRACK RBRACK
571 %token GOT GOT17M4 FUNCDESC_GOT17M4
581 %type <modcodes> byteop_mod
583 %type <reg> a_plusassign
584 %type <reg> a_minusassign
585 %type <macfunc> multiply_halfregs
586 %type <macfunc> assign_macfunc
587 %type <macfunc> a_macfunc
591 %type <modcodes> vsmod
592 %type <modcodes> ccstat
595 %type <reg> reg_with_postinc
596 %type <reg> reg_with_predec
600 %type <symbol> SYMBOL
603 %type <reg> BYTE_DREG
604 %type <reg> REG_A_DOUBLE_ZERO
605 %type <reg> REG_A_DOUBLE_ONE
607 %type <reg> STATUS_REG
611 %type <modcodes> smod
612 %type <modcodes> b3_op
613 %type <modcodes> rnd_op
614 %type <modcodes> post_op
616 %type <r0> iu_or_nothing
617 %type <r0> plus_minus
621 %type <modcodes> amod0
622 %type <modcodes> amod1
623 %type <modcodes> amod2
625 %type <r0> w32_or_nothing
629 %type <expr> got_or_expr
631 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
633 /* Precedence rules. */
637 %left LESS_LESS GREATER_GREATER
639 %left STAR SLASH PERCENT
650 if (insn == (INSTR_T) 0)
651 return NO_INSN_GENERATED;
652 else if (insn == (INSTR_T) - 1)
653 return SEMANTIC_ERROR;
655 return INSN_GENERATED;
660 /* Parallel instructions. */
661 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
663 if (($1->value & 0xf800) == 0xc000)
665 if (is_group1 ($3) && is_group2 ($5))
666 $$ = gen_multi_instr_1 ($1, $3, $5);
667 else if (is_group2 ($3) && is_group1 ($5))
668 $$ = gen_multi_instr_1 ($1, $5, $3);
670 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
672 else if (($3->value & 0xf800) == 0xc000)
674 if (is_group1 ($1) && is_group2 ($5))
675 $$ = gen_multi_instr_1 ($3, $1, $5);
676 else if (is_group2 ($1) && is_group1 ($5))
677 $$ = gen_multi_instr_1 ($3, $5, $1);
679 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
681 else if (($5->value & 0xf800) == 0xc000)
683 if (is_group1 ($1) && is_group2 ($3))
684 $$ = gen_multi_instr_1 ($5, $1, $3);
685 else if (is_group2 ($1) && is_group1 ($3))
686 $$ = gen_multi_instr_1 ($5, $3, $1);
688 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
691 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
694 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
696 if (($1->value & 0xf800) == 0xc000)
699 $$ = gen_multi_instr_1 ($1, $3, 0);
700 else if (is_group2 ($3))
701 $$ = gen_multi_instr_1 ($1, 0, $3);
703 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
705 else if (($3->value & 0xf800) == 0xc000)
708 $$ = gen_multi_instr_1 ($3, $1, 0);
709 else if (is_group2 ($1))
710 $$ = gen_multi_instr_1 ($3, 0, $1);
712 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
714 else if (is_group1 ($1) && is_group2 ($3))
715 $$ = gen_multi_instr_1 (0, $1, $3);
716 else if (is_group2 ($1) && is_group1 ($3))
717 $$ = gen_multi_instr_1 (0, $3, $1);
719 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
734 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
736 | assign_macfunc opt_mode
740 int h00, h10, h01, h11;
742 if (check_macfunc_option (&$1, &$2) < 0)
743 return yyerror ("bad option");
748 return yyerror ("(m) not allowed with a0 unit");
767 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
768 &$1.dst, op0, &$1.s0, &$1.s1, w0);
774 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
778 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
780 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
787 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
788 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
789 dst, $4.op, &$1.s0, &$1.s1, $4.w);
796 notethat ("dsp32alu: DISALGNEXCPT\n");
797 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
799 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
801 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
803 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
804 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
807 return yyerror ("Register mismatch");
809 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
811 if (!IS_A1 ($4) && IS_A1 ($5))
813 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
814 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
817 return yyerror ("Register mismatch");
819 | A_ZERO_DOT_H ASSIGN HALF_REG
821 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
822 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
824 | A_ONE_DOT_H ASSIGN HALF_REG
826 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
827 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
829 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
830 COLON expr COMMA REG COLON expr RPAREN aligndir
832 if (!IS_DREG ($2) || !IS_DREG ($4))
833 return yyerror ("Dregs expected");
834 else if (!valid_dreg_pair (&$9, $11))
835 return yyerror ("Bad dreg pair");
836 else if (!valid_dreg_pair (&$13, $15))
837 return yyerror ("Bad dreg pair");
840 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
841 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
845 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
846 REG COLON expr RPAREN aligndir
848 if (!IS_DREG ($2) || !IS_DREG ($4))
849 return yyerror ("Dregs expected");
850 else if (!valid_dreg_pair (&$9, $11))
851 return yyerror ("Bad dreg pair");
852 else if (!valid_dreg_pair (&$13, $15))
853 return yyerror ("Bad dreg pair");
856 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
857 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
861 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
863 if (!IS_DREG ($2) || !IS_DREG ($4))
864 return yyerror ("Dregs expected");
865 else if (!valid_dreg_pair (&$8, $10))
866 return yyerror ("Bad dreg pair");
869 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
870 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
873 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
875 if (REG_SAME ($2, $4))
876 return yyerror ("Illegal dest register combination");
878 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
880 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
881 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
884 return yyerror ("Register mismatch");
886 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
887 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
889 if (IS_DREG ($1) && IS_DREG ($7))
891 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
892 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
895 return yyerror ("Register mismatch");
899 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
901 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
902 && IS_A1 ($9) && !IS_A1 ($11))
904 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
905 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
908 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
909 && !IS_A1 ($9) && IS_A1 ($11))
911 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
912 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
915 return yyerror ("Register mismatch");
918 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
921 return yyerror ("Operators must differ");
923 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
924 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
926 notethat ("dsp32alu: dregs = dregs + dregs,"
927 "dregs = dregs - dregs (amod1)\n");
928 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
931 return yyerror ("Register mismatch");
934 /* Bar Operations. */
936 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
938 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
939 return yyerror ("Differing source registers");
941 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
942 return yyerror ("Dregs expected");
945 if ($4.r0 == 1 && $10.r0 == 2)
947 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
948 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
950 else if ($4.r0 == 0 && $10.r0 == 3)
952 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
953 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
956 return yyerror ("Bar operand mismatch");
959 | REG ASSIGN ABS REG vmod
963 if (IS_DREG ($1) && IS_DREG ($4))
967 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
972 /* Vector version of ABS. */
973 notethat ("dsp32alu: dregs = ABS dregs\n");
976 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
979 return yyerror ("Dregs expected");
983 notethat ("dsp32alu: Ax = ABS Ax\n");
984 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
986 | A_ZERO_DOT_L ASSIGN HALF_REG
990 notethat ("dsp32alu: A0.l = reg_half\n");
991 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
994 return yyerror ("A0.l = Rx.l expected");
996 | A_ONE_DOT_L ASSIGN HALF_REG
1000 notethat ("dsp32alu: A1.l = reg_half\n");
1001 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
1004 return yyerror ("A1.l = Rx.l expected");
1007 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1009 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1011 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1012 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1015 return yyerror ("Dregs expected");
1018 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1021 return yyerror ("Dregs expected");
1022 else if (!valid_dreg_pair (&$5, $7))
1023 return yyerror ("Bad dreg pair");
1024 else if (!valid_dreg_pair (&$9, $11))
1025 return yyerror ("Bad dreg pair");
1028 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1029 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1032 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1035 return yyerror ("Dregs expected");
1036 else if (!valid_dreg_pair (&$5, $7))
1037 return yyerror ("Bad dreg pair");
1038 else if (!valid_dreg_pair (&$9, $11))
1039 return yyerror ("Bad dreg pair");
1042 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1043 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1047 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1051 return yyerror ("Dregs expected");
1052 else if (!valid_dreg_pair (&$5, $7))
1053 return yyerror ("Bad dreg pair");
1054 else if (!valid_dreg_pair (&$9, $11))
1055 return yyerror ("Bad dreg pair");
1058 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1059 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1063 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1067 return yyerror ("Dregs expected");
1068 else if (!valid_dreg_pair (&$5, $7))
1069 return yyerror ("Bad dreg pair");
1070 else if (!valid_dreg_pair (&$9, $11))
1071 return yyerror ("Bad dreg pair");
1074 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1075 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1079 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1081 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1083 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1084 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1087 return yyerror ("Dregs expected");
1090 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1091 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1093 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1095 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1096 "SIGN (dregs_hi) * dregs_hi + "
1097 "SIGN (dregs_lo) * dregs_lo \n");
1099 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1102 return yyerror ("Dregs expected");
1104 | REG ASSIGN REG plus_minus REG amod1
1106 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1110 /* No saturation flag specified, generate the 16 bit variant. */
1111 notethat ("COMP3op: dregs = dregs +- dregs\n");
1112 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1116 /* Saturation flag specified, generate the 32 bit variant. */
1117 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1118 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1122 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1124 notethat ("COMP3op: pregs = pregs + pregs\n");
1125 $$ = COMP3OP (&$1, &$3, &$5, 5);
1128 return yyerror ("Dregs expected");
1130 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1134 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1141 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1142 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1145 return yyerror ("Dregs expected");
1148 | a_assign MINUS REG_A
1150 notethat ("dsp32alu: Ax = - Ax\n");
1151 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1153 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1155 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1156 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1157 $6.s0, $6.x0, HL2 ($3, $5));
1159 | a_assign a_assign expr
1161 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1163 notethat ("dsp32alu: A1 = A0 = 0\n");
1164 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1167 return yyerror ("Bad value, 0 expected");
1171 | a_assign REG_A LPAREN S RPAREN
1173 if (REG_SAME ($1, $2))
1175 notethat ("dsp32alu: Ax = Ax (S)\n");
1176 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1179 return yyerror ("Registers must be equal");
1182 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1186 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1187 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1190 return yyerror ("Dregs expected");
1193 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1195 if (IS_DREG ($3) && IS_DREG ($5))
1197 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1198 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1201 return yyerror ("Dregs expected");
1204 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1206 if (IS_DREG ($3) && IS_DREG ($5))
1208 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1209 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1212 return yyerror ("Dregs expected");
1217 if (!REG_SAME ($1, $2))
1219 notethat ("dsp32alu: An = Am\n");
1220 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1223 return yyerror ("Accu reg arguments must differ");
1230 notethat ("dsp32alu: An = dregs\n");
1231 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1234 return yyerror ("Dregs expected");
1237 | REG ASSIGN HALF_REG xpmod
1241 if ($1.regno == REG_A0x && IS_DREG ($3))
1243 notethat ("dsp32alu: A0.x = dregs_lo\n");
1244 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1246 else if ($1.regno == REG_A1x && IS_DREG ($3))
1248 notethat ("dsp32alu: A1.x = dregs_lo\n");
1249 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1251 else if (IS_DREG ($1) && IS_DREG ($3))
1253 notethat ("ALU2op: dregs = dregs_lo\n");
1254 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1257 return yyerror ("Register mismatch");
1260 return yyerror ("Low reg expected");
1263 | HALF_REG ASSIGN expr
1265 notethat ("LDIMMhalf: pregs_half = imm16\n");
1267 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1268 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1269 return yyerror ("Wrong register for load immediate");
1271 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1272 return yyerror ("Constant out of range");
1274 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1279 notethat ("dsp32alu: An = 0\n");
1282 return yyerror ("0 expected");
1284 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1287 | REG ASSIGN expr xpmod1
1289 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1290 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1291 return yyerror ("Wrong register for load immediate");
1295 /* 7 bit immediate value if possible.
1296 We will check for that constant value for efficiency
1297 If it goes to reloc, it will be 16 bit. */
1298 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1300 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1301 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1303 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1305 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1306 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1310 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1311 return yyerror ("Immediate value out of range");
1313 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1315 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1320 /* (z) There is no 7 bit zero extended instruction.
1321 If the expr is a relocation, generate it. */
1323 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1324 return yyerror ("Immediate value out of range");
1326 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1328 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1332 | HALF_REG ASSIGN REG
1335 return yyerror ("Low reg expected");
1337 if (IS_DREG ($1) && $3.regno == REG_A0x)
1339 notethat ("dsp32alu: dregs_lo = A0.x\n");
1340 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1342 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1344 notethat ("dsp32alu: dregs_lo = A1.x\n");
1345 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1348 return yyerror ("Register mismatch");
1351 | REG ASSIGN REG op_bar_op REG amod0
1353 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1355 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1356 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1359 return yyerror ("Register mismatch");
1362 | REG ASSIGN BYTE_DREG xpmod
1364 if (IS_DREG ($1) && IS_DREG ($3))
1366 notethat ("ALU2op: dregs = dregs_byte\n");
1367 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1370 return yyerror ("Register mismatch");
1373 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1375 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1377 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1378 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1381 return yyerror ("Register mismatch");
1384 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1386 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1388 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1389 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1392 return yyerror ("Register mismatch");
1395 | a_minusassign REG_A w32_or_nothing
1397 if (!IS_A1 ($1) && IS_A1 ($2))
1399 notethat ("dsp32alu: A0 -= A1\n");
1400 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1403 return yyerror ("Register mismatch");
1406 | REG _MINUS_ASSIGN expr
1408 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1410 notethat ("dagMODik: iregs -= 4\n");
1411 $$ = DAGMODIK (&$1, 3);
1413 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1415 notethat ("dagMODik: iregs -= 2\n");
1416 $$ = DAGMODIK (&$1, 1);
1419 return yyerror ("Register or value mismatch");
1422 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1424 if (IS_IREG ($1) && IS_MREG ($3))
1426 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1428 $$ = DAGMODIM (&$1, &$3, 0, 1);
1430 else if (IS_PREG ($1) && IS_PREG ($3))
1432 notethat ("PTR2op: pregs += pregs (BREV )\n");
1433 $$ = PTR2OP (&$1, &$3, 5);
1436 return yyerror ("Register mismatch");
1439 | REG _MINUS_ASSIGN REG
1441 if (IS_IREG ($1) && IS_MREG ($3))
1443 notethat ("dagMODim: iregs -= mregs\n");
1444 $$ = DAGMODIM (&$1, &$3, 1, 0);
1446 else if (IS_PREG ($1) && IS_PREG ($3))
1448 notethat ("PTR2op: pregs -= pregs\n");
1449 $$ = PTR2OP (&$1, &$3, 0);
1452 return yyerror ("Register mismatch");
1455 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1457 if (!IS_A1 ($1) && IS_A1 ($3))
1459 notethat ("dsp32alu: A0 += A1 (W32)\n");
1460 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1463 return yyerror ("Register mismatch");
1466 | REG _PLUS_ASSIGN REG
1468 if (IS_IREG ($1) && IS_MREG ($3))
1470 notethat ("dagMODim: iregs += mregs\n");
1471 $$ = DAGMODIM (&$1, &$3, 0, 0);
1474 return yyerror ("iregs += mregs expected");
1477 | REG _PLUS_ASSIGN expr
1481 if (EXPR_VALUE ($3) == 4)
1483 notethat ("dagMODik: iregs += 4\n");
1484 $$ = DAGMODIK (&$1, 2);
1486 else if (EXPR_VALUE ($3) == 2)
1488 notethat ("dagMODik: iregs += 2\n");
1489 $$ = DAGMODIK (&$1, 0);
1492 return yyerror ("iregs += [ 2 | 4 ");
1494 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1496 notethat ("COMPI2opP: pregs += imm7\n");
1497 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1499 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1501 notethat ("COMPI2opD: dregs += imm7\n");
1502 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1504 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1505 return yyerror ("Immediate value out of range");
1507 return yyerror ("Register mismatch");
1510 | REG _STAR_ASSIGN REG
1512 if (IS_DREG ($1) && IS_DREG ($3))
1514 notethat ("ALU2op: dregs *= dregs\n");
1515 $$ = ALU2OP (&$1, &$3, 3);
1518 return yyerror ("Register mismatch");
1521 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1523 if (!valid_dreg_pair (&$3, $5))
1524 return yyerror ("Bad dreg pair");
1525 else if (!valid_dreg_pair (&$7, $9))
1526 return yyerror ("Bad dreg pair");
1529 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1530 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1534 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1536 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1538 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1539 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1542 return yyerror ("Register mismatch");
1545 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1547 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1548 && REG_SAME ($1, $4))
1550 if (EXPR_VALUE ($9) == 1)
1552 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1553 $$ = ALU2OP (&$1, &$6, 4);
1555 else if (EXPR_VALUE ($9) == 2)
1557 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1558 $$ = ALU2OP (&$1, &$6, 5);
1561 return yyerror ("Bad shift value");
1563 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1564 && REG_SAME ($1, $4))
1566 if (EXPR_VALUE ($9) == 1)
1568 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1569 $$ = PTR2OP (&$1, &$6, 6);
1571 else if (EXPR_VALUE ($9) == 2)
1573 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1574 $$ = PTR2OP (&$1, &$6, 7);
1577 return yyerror ("Bad shift value");
1580 return yyerror ("Register mismatch");
1584 | REG ASSIGN REG BAR REG
1586 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1588 notethat ("COMP3op: dregs = dregs | dregs\n");
1589 $$ = COMP3OP (&$1, &$3, &$5, 3);
1592 return yyerror ("Dregs expected");
1594 | REG ASSIGN REG CARET REG
1596 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1598 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1599 $$ = COMP3OP (&$1, &$3, &$5, 4);
1602 return yyerror ("Dregs expected");
1604 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1606 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1608 if (EXPR_VALUE ($8) == 1)
1610 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1611 $$ = COMP3OP (&$1, &$3, &$6, 6);
1613 else if (EXPR_VALUE ($8) == 2)
1615 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1616 $$ = COMP3OP (&$1, &$3, &$6, 7);
1619 return yyerror ("Bad shift value");
1622 return yyerror ("Dregs expected");
1624 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1626 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1628 notethat ("CCflag: CC = A0 == A1\n");
1629 $$ = CCFLAG (0, 0, 5, 0, 0);
1632 return yyerror ("AREGs are in bad order or same");
1634 | CCREG ASSIGN REG_A LESS_THAN REG_A
1636 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1638 notethat ("CCflag: CC = A0 < A1\n");
1639 $$ = CCFLAG (0, 0, 6, 0, 0);
1642 return yyerror ("AREGs are in bad order or same");
1644 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1646 if ((IS_DREG ($3) && IS_DREG ($5))
1647 || (IS_PREG ($3) && IS_PREG ($5)))
1649 notethat ("CCflag: CC = dpregs < dpregs\n");
1650 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1653 return yyerror ("Bad register in comparison");
1655 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1657 if (!IS_DREG ($3) && !IS_PREG ($3))
1658 return yyerror ("Bad register in comparison");
1660 if (($6.r0 == 1 && IS_IMM ($5, 3))
1661 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1663 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1664 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1667 return yyerror ("Bad constant value");
1669 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1671 if ((IS_DREG ($3) && IS_DREG ($5))
1672 || (IS_PREG ($3) && IS_PREG ($5)))
1674 notethat ("CCflag: CC = dpregs == dpregs\n");
1675 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1678 return yyerror ("Bad register in comparison");
1680 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1682 if (!IS_DREG ($3) && !IS_PREG ($3))
1683 return yyerror ("Bad register in comparison");
1687 notethat ("CCflag: CC = dpregs == imm3\n");
1688 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1691 return yyerror ("Bad constant range");
1693 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1695 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1697 notethat ("CCflag: CC = A0 <= A1\n");
1698 $$ = CCFLAG (0, 0, 7, 0, 0);
1701 return yyerror ("AREGs are in bad order or same");
1703 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1705 if ((IS_DREG ($3) && IS_DREG ($5))
1706 || (IS_PREG ($3) && IS_PREG ($5)))
1708 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1709 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1710 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1713 return yyerror ("Bad register in comparison");
1715 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1717 if (!IS_DREG ($3) && !IS_PREG ($3))
1718 return yyerror ("Bad register in comparison");
1720 if (($6.r0 == 1 && IS_IMM ($5, 3))
1721 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1723 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1724 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1727 return yyerror ("Bad constant value");
1730 | REG ASSIGN REG AMPERSAND REG
1732 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1734 notethat ("COMP3op: dregs = dregs & dregs\n");
1735 $$ = COMP3OP (&$1, &$3, &$5, 2);
1738 return yyerror ("Dregs expected");
1743 notethat ("CC2stat operation\n");
1744 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1749 if ((IS_GENREG ($1) && IS_GENREG ($3))
1750 || (IS_GENREG ($1) && IS_DAGREG ($3))
1751 || (IS_DAGREG ($1) && IS_GENREG ($3))
1752 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1753 || (IS_GENREG ($1) && $3.regno == REG_USP)
1754 || ($1.regno == REG_USP && IS_GENREG ($3))
1755 || ($1.regno == REG_USP && $3.regno == REG_USP)
1756 || (IS_DREG ($1) && IS_SYSREG ($3))
1757 || (IS_PREG ($1) && IS_SYSREG ($3))
1758 || (IS_SYSREG ($1) && IS_GENREG ($3))
1759 || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1760 || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1761 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1763 $$ = bfin_gen_regmv (&$3, &$1);
1766 return yyerror ("Unsupported register move");
1773 notethat ("CC2dreg: CC = dregs\n");
1774 $$ = bfin_gen_cc2dreg (1, &$3);
1777 return yyerror ("Only 'CC = Dreg' supported");
1784 notethat ("CC2dreg: dregs = CC\n");
1785 $$ = bfin_gen_cc2dreg (0, &$1);
1788 return yyerror ("Only 'Dreg = CC' supported");
1791 | CCREG _ASSIGN_BANG CCREG
1793 notethat ("CC2dreg: CC =! CC\n");
1794 $$ = bfin_gen_cc2dreg (3, 0);
1799 | HALF_REG ASSIGN multiply_halfregs opt_mode
1801 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1803 if (!IS_H ($1) && $4.MM)
1804 return yyerror ("(M) not allowed with MAC0");
1806 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1807 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1808 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1809 return yyerror ("bad option.");
1813 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1814 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1815 &$1, 0, &$3.s0, &$3.s1, 0);
1819 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1820 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1821 &$1, 0, &$3.s0, &$3.s1, 1);
1825 | REG ASSIGN multiply_halfregs opt_mode
1827 /* Odd registers can use (M). */
1829 return yyerror ("Dreg expected");
1831 if (IS_EVEN ($1) && $4.MM)
1832 return yyerror ("(M) not allowed with MAC0");
1834 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1835 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1836 return yyerror ("bad option");
1840 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1842 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1843 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1844 &$1, 0, &$3.s0, &$3.s1, 0);
1848 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1849 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1850 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1851 &$1, 0, &$3.s0, &$3.s1, 1);
1855 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1856 HALF_REG ASSIGN multiply_halfregs opt_mode
1858 if (!IS_DREG ($1) || !IS_DREG ($6))
1859 return yyerror ("Dregs expected");
1861 if (!IS_HCOMPL($1, $6))
1862 return yyerror ("Dest registers mismatch");
1864 if (check_multiply_halfregs (&$3, &$8) < 0)
1867 if ((!IS_H ($1) && $4.MM)
1868 || (!IS_H ($6) && $9.MM))
1869 return yyerror ("(M) not allowed with MAC0");
1871 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1872 "dregs_lo = multiply_halfregs opt_mode\n");
1875 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1876 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1877 &$1, 0, &$3.s0, &$3.s1, 1);
1879 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1880 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1881 &$1, 0, &$3.s0, &$3.s1, 1);
1884 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1886 if (!IS_DREG ($1) || !IS_DREG ($6))
1887 return yyerror ("Dregs expected");
1889 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1890 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1891 return yyerror ("Dest registers mismatch");
1893 if (check_multiply_halfregs (&$3, &$8) < 0)
1896 if ((IS_EVEN ($1) && $4.MM)
1897 || (IS_EVEN ($6) && $9.MM))
1898 return yyerror ("(M) not allowed with MAC0");
1900 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1901 "dregs = multiply_halfregs opt_mode\n");
1904 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1905 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1906 &$1, 0, &$3.s0, &$3.s1, 1);
1908 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1909 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1910 &$1, 0, &$3.s0, &$3.s1, 1);
1915 | a_assign ASHIFT REG_A BY HALF_REG
1917 if (!REG_SAME ($1, $3))
1918 return yyerror ("Aregs must be same");
1920 if (IS_DREG ($5) && !IS_H ($5))
1922 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1923 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1926 return yyerror ("Dregs expected");
1929 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1931 if (IS_DREG ($6) && !IS_H ($6))
1933 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1934 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1937 return yyerror ("Dregs expected");
1940 | a_assign REG_A LESS_LESS expr
1942 if (!REG_SAME ($1, $2))
1943 return yyerror ("Aregs must be same");
1945 if (IS_UIMM ($4, 5))
1947 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1948 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1951 return yyerror ("Bad shift value");
1954 | REG ASSIGN REG LESS_LESS expr vsmod
1956 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1961 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1962 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1966 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1967 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1970 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1972 if (EXPR_VALUE ($5) == 2)
1974 notethat ("PTR2op: pregs = pregs << 2\n");
1975 $$ = PTR2OP (&$1, &$3, 1);
1977 else if (EXPR_VALUE ($5) == 1)
1979 notethat ("COMP3op: pregs = pregs << 1\n");
1980 $$ = COMP3OP (&$1, &$3, &$3, 5);
1983 return yyerror ("Bad shift value");
1986 return yyerror ("Bad shift value or register");
1988 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1990 if (IS_UIMM ($5, 4))
1994 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1995 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1999 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2000 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2004 return yyerror ("Bad shift value");
2006 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2010 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2015 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2016 "dregs_lo (V, .)\n");
2022 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2024 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2027 return yyerror ("Dregs expected");
2031 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2033 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2035 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2036 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2039 return yyerror ("Bad shift value or register");
2043 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2045 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2047 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2048 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2050 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2052 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2053 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2056 return yyerror ("Bad shift value or register");
2061 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2063 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2065 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2066 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2069 return yyerror ("Register mismatch");
2072 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2074 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2076 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2077 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2080 return yyerror ("Register mismatch");
2083 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2085 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2087 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2088 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2091 return yyerror ("Register mismatch");
2094 | a_assign REG_A _GREATER_GREATER_GREATER expr
2096 if (!REG_SAME ($1, $2))
2097 return yyerror ("Aregs must be same");
2099 if (IS_UIMM ($4, 5))
2101 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2102 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2105 return yyerror ("Shift value range error");
2107 | a_assign LSHIFT REG_A BY HALF_REG
2109 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2111 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2112 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2115 return yyerror ("Register mismatch");
2118 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2120 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2122 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2123 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2126 return yyerror ("Register mismatch");
2129 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2131 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2133 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2134 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2137 return yyerror ("Register mismatch");
2140 | REG ASSIGN SHIFT REG BY HALF_REG
2142 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2144 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2145 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2148 return yyerror ("Register mismatch");
2151 | a_assign REG_A GREATER_GREATER expr
2153 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2155 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2156 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2159 return yyerror ("Accu register expected");
2162 | REG ASSIGN REG GREATER_GREATER expr vmod
2166 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2168 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2169 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2172 return yyerror ("Register mismatch");
2176 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2178 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2179 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2181 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2183 notethat ("PTR2op: pregs = pregs >> 2\n");
2184 $$ = PTR2OP (&$1, &$3, 3);
2186 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2188 notethat ("PTR2op: pregs = pregs >> 1\n");
2189 $$ = PTR2OP (&$1, &$3, 4);
2192 return yyerror ("Register mismatch");
2195 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2197 if (IS_UIMM ($5, 5))
2199 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2200 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2203 return yyerror ("Register mismatch");
2205 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2207 if (IS_UIMM ($5, 5))
2209 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2210 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2211 $6.s0, HL2 ($1, $3));
2214 return yyerror ("Register or modifier mismatch");
2218 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2220 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2225 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2226 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2230 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2231 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2235 return yyerror ("Register mismatch");
2238 | HALF_REG ASSIGN ONES REG
2240 if (IS_DREG_L ($1) && IS_DREG ($4))
2242 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2243 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2246 return yyerror ("Register mismatch");
2249 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2251 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2253 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2254 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2257 return yyerror ("Register mismatch");
2260 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2263 && $7.regno == REG_A0
2264 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2266 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2267 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2270 return yyerror ("Register mismatch");
2273 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2276 && $7.regno == REG_A0
2277 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2279 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2280 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2283 return yyerror ("Register mismatch");
2286 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2288 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2290 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2291 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2294 return yyerror ("Register mismatch");
2297 | a_assign ROT REG_A BY HALF_REG
2299 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2301 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2302 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2305 return yyerror ("Register mismatch");
2308 | REG ASSIGN ROT REG BY HALF_REG
2310 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2312 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2313 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2316 return yyerror ("Register mismatch");
2319 | a_assign ROT REG_A BY expr
2323 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2324 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2327 return yyerror ("Register mismatch");
2330 | REG ASSIGN ROT REG BY expr
2332 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2334 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2337 return yyerror ("Register mismatch");
2340 | HALF_REG ASSIGN SIGNBITS REG_A
2344 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2345 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2348 return yyerror ("Register mismatch");
2351 | HALF_REG ASSIGN SIGNBITS REG
2353 if (IS_DREG_L ($1) && IS_DREG ($4))
2355 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2356 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2359 return yyerror ("Register mismatch");
2362 | HALF_REG ASSIGN SIGNBITS HALF_REG
2366 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2367 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2370 return yyerror ("Register mismatch");
2373 /* The ASR bit is just inverted here. */
2374 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2376 if (IS_DREG_L ($1) && IS_DREG ($5))
2378 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2379 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2382 return yyerror ("Register mismatch");
2385 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2387 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2389 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2390 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2393 return yyerror ("Register mismatch");
2396 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2398 if (REG_SAME ($3, $5))
2399 return yyerror ("Illegal source register combination");
2401 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2403 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2404 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2407 return yyerror ("Register mismatch");
2410 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2412 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2414 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2415 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2418 return yyerror ("Dregs expected");
2422 /* LOGI2op: BITCLR (dregs, uimm5). */
2423 | BITCLR LPAREN REG COMMA expr RPAREN
2425 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2427 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2428 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2431 return yyerror ("Register mismatch");
2434 /* LOGI2op: BITSET (dregs, uimm5). */
2435 | BITSET LPAREN REG COMMA expr RPAREN
2437 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2439 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2440 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2443 return yyerror ("Register mismatch");
2446 /* LOGI2op: BITTGL (dregs, uimm5). */
2447 | BITTGL LPAREN REG COMMA expr RPAREN
2449 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2451 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2452 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2455 return yyerror ("Register mismatch");
2458 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2460 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2462 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2463 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2466 return yyerror ("Register mismatch or value error");
2469 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2471 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2473 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2474 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2477 return yyerror ("Register mismatch or value error");
2480 | IF BANG CCREG REG ASSIGN REG
2482 if ((IS_DREG ($4) || IS_PREG ($4))
2483 && (IS_DREG ($6) || IS_PREG ($6)))
2485 notethat ("ccMV: IF ! CC gregs = gregs\n");
2486 $$ = CCMV (&$6, &$4, 0);
2489 return yyerror ("Register mismatch");
2492 | IF CCREG REG ASSIGN REG
2494 if ((IS_DREG ($5) || IS_PREG ($5))
2495 && (IS_DREG ($3) || IS_PREG ($3)))
2497 notethat ("ccMV: IF CC gregs = gregs\n");
2498 $$ = CCMV (&$5, &$3, 1);
2501 return yyerror ("Register mismatch");
2504 | IF BANG CCREG JUMP expr
2506 if (IS_PCREL10 ($5))
2508 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2509 $$ = BRCC (0, 0, $5);
2512 return yyerror ("Bad jump offset");
2515 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2517 if (IS_PCREL10 ($5))
2519 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2520 $$ = BRCC (0, 1, $5);
2523 return yyerror ("Bad jump offset");
2526 | IF CCREG JUMP expr
2528 if (IS_PCREL10 ($4))
2530 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2531 $$ = BRCC (1, 0, $4);
2534 return yyerror ("Bad jump offset");
2537 | IF CCREG JUMP expr LPAREN BP RPAREN
2539 if (IS_PCREL10 ($4))
2541 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2542 $$ = BRCC (1, 1, $4);
2545 return yyerror ("Bad jump offset");
2549 notethat ("ProgCtrl: NOP\n");
2550 $$ = PROGCTRL (0, 0);
2555 notethat ("ProgCtrl: RTS\n");
2556 $$ = PROGCTRL (1, 0);
2561 notethat ("ProgCtrl: RTI\n");
2562 $$ = PROGCTRL (1, 1);
2567 notethat ("ProgCtrl: RTX\n");
2568 $$ = PROGCTRL (1, 2);
2573 notethat ("ProgCtrl: RTN\n");
2574 $$ = PROGCTRL (1, 3);
2579 notethat ("ProgCtrl: RTE\n");
2580 $$ = PROGCTRL (1, 4);
2585 notethat ("ProgCtrl: IDLE\n");
2586 $$ = PROGCTRL (2, 0);
2591 notethat ("ProgCtrl: CSYNC\n");
2592 $$ = PROGCTRL (2, 3);
2597 notethat ("ProgCtrl: SSYNC\n");
2598 $$ = PROGCTRL (2, 4);
2603 notethat ("ProgCtrl: EMUEXCPT\n");
2604 $$ = PROGCTRL (2, 5);
2611 notethat ("ProgCtrl: CLI dregs\n");
2612 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2615 return yyerror ("Dreg expected for CLI");
2622 notethat ("ProgCtrl: STI dregs\n");
2623 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2626 return yyerror ("Dreg expected for STI");
2629 | JUMP LPAREN REG RPAREN
2633 notethat ("ProgCtrl: JUMP (pregs )\n");
2634 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2637 return yyerror ("Bad register for indirect jump");
2640 | CALL LPAREN REG RPAREN
2644 notethat ("ProgCtrl: CALL (pregs )\n");
2645 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2648 return yyerror ("Bad register for indirect call");
2651 | CALL LPAREN PC PLUS REG RPAREN
2655 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2656 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2659 return yyerror ("Bad register for indirect call");
2662 | JUMP LPAREN PC PLUS REG RPAREN
2666 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2667 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2670 return yyerror ("Bad register for indirect jump");
2675 if (IS_UIMM ($2, 4))
2677 notethat ("ProgCtrl: RAISE uimm4\n");
2678 $$ = PROGCTRL (9, uimm4 ($2));
2681 return yyerror ("Bad value for RAISE");
2686 notethat ("ProgCtrl: EMUEXCPT\n");
2687 $$ = PROGCTRL (10, uimm4 ($2));
2690 | TESTSET LPAREN REG RPAREN
2694 if ($3.regno == REG_SP || $3.regno == REG_FP)
2695 return yyerror ("Bad register for TESTSET");
2697 notethat ("ProgCtrl: TESTSET (pregs )\n");
2698 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2701 return yyerror ("Preg expected");
2706 if (IS_PCREL12 ($2))
2708 notethat ("UJUMP: JUMP pcrel12\n");
2712 return yyerror ("Bad value for relative jump");
2717 if (IS_PCREL12 ($2))
2719 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2723 return yyerror ("Bad value for relative jump");
2728 if (IS_PCREL24 ($2))
2730 notethat ("CALLa: jump.l pcrel24\n");
2734 return yyerror ("Bad value for long jump");
2739 if (IS_PCREL24 ($2))
2741 notethat ("CALLa: jump.l pcrel24\n");
2745 return yyerror ("Bad value for long jump");
2750 if (IS_PCREL24 ($2))
2752 notethat ("CALLa: CALL pcrel25m2\n");
2756 return yyerror ("Bad call address");
2760 if (IS_PCREL24 ($2))
2762 notethat ("CALLa: CALL pcrel25m2\n");
2766 return yyerror ("Bad call address");
2770 /* ALU2op: DIVQ (dregs, dregs). */
2771 | DIVQ LPAREN REG COMMA REG RPAREN
2773 if (IS_DREG ($3) && IS_DREG ($5))
2774 $$ = ALU2OP (&$3, &$5, 8);
2776 return yyerror ("Bad registers for DIVQ");
2779 | DIVS LPAREN REG COMMA REG RPAREN
2781 if (IS_DREG ($3) && IS_DREG ($5))
2782 $$ = ALU2OP (&$3, &$5, 9);
2784 return yyerror ("Bad registers for DIVS");
2787 | REG ASSIGN MINUS REG vsmod
2789 if (IS_DREG ($1) && IS_DREG ($4))
2791 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2793 notethat ("ALU2op: dregs = - dregs\n");
2794 $$ = ALU2OP (&$1, &$4, 14);
2796 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2798 notethat ("dsp32alu: dregs = - dregs (.)\n");
2799 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2803 notethat ("dsp32alu: dregs = - dregs (.)\n");
2804 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2808 return yyerror ("Dregs expected");
2811 | REG ASSIGN TILDA REG
2813 if (IS_DREG ($1) && IS_DREG ($4))
2815 notethat ("ALU2op: dregs = ~dregs\n");
2816 $$ = ALU2OP (&$1, &$4, 15);
2819 return yyerror ("Dregs expected");
2822 | REG _GREATER_GREATER_ASSIGN REG
2824 if (IS_DREG ($1) && IS_DREG ($3))
2826 notethat ("ALU2op: dregs >>= dregs\n");
2827 $$ = ALU2OP (&$1, &$3, 1);
2830 return yyerror ("Dregs expected");
2833 | REG _GREATER_GREATER_ASSIGN expr
2835 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2837 notethat ("LOGI2op: dregs >>= uimm5\n");
2838 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2841 return yyerror ("Dregs expected or value error");
2844 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2846 if (IS_DREG ($1) && IS_DREG ($3))
2848 notethat ("ALU2op: dregs >>>= dregs\n");
2849 $$ = ALU2OP (&$1, &$3, 0);
2852 return yyerror ("Dregs expected");
2855 | REG _LESS_LESS_ASSIGN REG
2857 if (IS_DREG ($1) && IS_DREG ($3))
2859 notethat ("ALU2op: dregs <<= dregs\n");
2860 $$ = ALU2OP (&$1, &$3, 2);
2863 return yyerror ("Dregs expected");
2866 | REG _LESS_LESS_ASSIGN expr
2868 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2870 notethat ("LOGI2op: dregs <<= uimm5\n");
2871 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2874 return yyerror ("Dregs expected or const value error");
2878 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2880 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2882 notethat ("LOGI2op: dregs >>>= uimm5\n");
2883 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2886 return yyerror ("Dregs expected");
2889 /* Cache Control. */
2891 | FLUSH LBRACK REG RBRACK
2893 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2895 $$ = CACTRL (&$3, 0, 2);
2897 return yyerror ("Bad register(s) for FLUSH");
2900 | FLUSH reg_with_postinc
2904 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2905 $$ = CACTRL (&$2, 1, 2);
2908 return yyerror ("Bad register(s) for FLUSH");
2911 | FLUSHINV LBRACK REG RBRACK
2915 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2916 $$ = CACTRL (&$3, 0, 1);
2919 return yyerror ("Bad register(s) for FLUSH");
2922 | FLUSHINV reg_with_postinc
2926 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2927 $$ = CACTRL (&$2, 1, 1);
2930 return yyerror ("Bad register(s) for FLUSH");
2933 /* CaCTRL: IFLUSH [pregs]. */
2934 | IFLUSH LBRACK REG RBRACK
2938 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2939 $$ = CACTRL (&$3, 0, 3);
2942 return yyerror ("Bad register(s) for FLUSH");
2945 | IFLUSH reg_with_postinc
2949 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2950 $$ = CACTRL (&$2, 1, 3);
2953 return yyerror ("Bad register(s) for FLUSH");
2956 | PREFETCH LBRACK REG RBRACK
2960 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2961 $$ = CACTRL (&$3, 0, 0);
2964 return yyerror ("Bad register(s) for PREFETCH");
2967 | PREFETCH reg_with_postinc
2971 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2972 $$ = CACTRL (&$2, 1, 0);
2975 return yyerror ("Bad register(s) for PREFETCH");
2979 /* LDST: B [ pregs <post_op> ] = dregs. */
2981 | B LBRACK REG post_op RBRACK ASSIGN REG
2984 return yyerror ("Dreg expected for source operand");
2986 return yyerror ("Preg expected in address");
2988 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2989 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2992 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2993 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2995 Expr_Node *tmp = $5;
2998 return yyerror ("Dreg expected for source operand");
3000 return yyerror ("Preg expected in address");
3003 return yyerror ("Plain symbol used as offset");
3006 tmp = unary (Expr_Op_Type_NEG, tmp);
3008 if (in_range_p (tmp, -32768, 32767, 0))
3010 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3011 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3014 return yyerror ("Displacement out of range");
3018 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3019 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3021 Expr_Node *tmp = $5;
3024 return yyerror ("Dreg expected for source operand");
3026 return yyerror ("Preg expected in address");
3029 tmp = unary (Expr_Op_Type_NEG, tmp);
3032 return yyerror ("Plain symbol used as offset");
3034 if (in_range_p (tmp, 0, 30, 1))
3036 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3037 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3039 else if (in_range_p (tmp, -65536, 65535, 1))
3041 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3042 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3045 return yyerror ("Displacement out of range");
3048 /* LDST: W [ pregs <post_op> ] = dregs. */
3049 | W LBRACK REG post_op RBRACK ASSIGN REG
3052 return yyerror ("Dreg expected for source operand");
3054 return yyerror ("Preg expected in address");
3056 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3057 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3060 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3063 return yyerror ("Dreg expected for source operand");
3066 if (!IS_IREG ($3) && !IS_PREG ($3))
3067 return yyerror ("Ireg or Preg expected in address");
3069 else if (!IS_IREG ($3))
3070 return yyerror ("Ireg expected in address");
3074 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3075 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3079 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3080 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3084 /* LDSTiiFP: [ FP - const ] = dpregs. */
3085 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3087 Expr_Node *tmp = $4;
3088 int ispreg = IS_PREG ($7);
3091 return yyerror ("Preg expected in address");
3093 if (!IS_DREG ($7) && !ispreg)
3094 return yyerror ("Preg expected for source operand");
3097 tmp = unary (Expr_Op_Type_NEG, tmp);
3100 return yyerror ("Plain symbol used as offset");
3102 if (in_range_p (tmp, 0, 63, 3))
3104 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3105 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3107 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3109 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3110 tmp = unary (Expr_Op_Type_NEG, tmp);
3111 $$ = LDSTIIFP (tmp, &$7, 1);
3113 else if (in_range_p (tmp, -131072, 131071, 3))
3115 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3116 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3119 return yyerror ("Displacement out of range");
3122 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3124 Expr_Node *tmp = $7;
3126 return yyerror ("Dreg expected for destination operand");
3128 return yyerror ("Preg expected in address");
3131 tmp = unary (Expr_Op_Type_NEG, tmp);
3134 return yyerror ("Plain symbol used as offset");
3136 if (in_range_p (tmp, 0, 30, 1))
3138 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3139 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3141 else if (in_range_p (tmp, -65536, 65535, 1))
3143 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3144 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3147 return yyerror ("Displacement out of range");
3150 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3153 return yyerror ("Dreg expected for source operand");
3156 if (!IS_IREG ($5) && !IS_PREG ($5))
3157 return yyerror ("Ireg or Preg expected in address");
3159 else if (!IS_IREG ($5))
3160 return yyerror ("Ireg expected in address");
3164 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3165 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3169 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3170 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3175 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3178 return yyerror ("Dreg expected for destination operand");
3180 return yyerror ("Preg expected in address");
3182 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3183 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3186 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3189 return yyerror ("Dreg expected for destination operand");
3190 if (!IS_PREG ($5) || !IS_PREG ($7))
3191 return yyerror ("Preg expected in address");
3193 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3194 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3197 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3200 return yyerror ("Dreg expected for destination operand");
3201 if (!IS_PREG ($5) || !IS_PREG ($7))
3202 return yyerror ("Preg expected in address");
3204 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3205 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3208 | LBRACK REG post_op RBRACK ASSIGN REG
3210 if (!IS_IREG ($2) && !IS_PREG ($2))
3211 return yyerror ("Ireg or Preg expected in address");
3212 else if (IS_IREG ($2) && !IS_DREG ($6))
3213 return yyerror ("Dreg expected for source operand");
3214 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3215 return yyerror ("Dreg or Preg expected for source operand");
3219 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3220 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3222 else if (IS_DREG ($6))
3224 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3225 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3229 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3230 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3234 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3237 return yyerror ("Dreg expected for source operand");
3239 if (IS_IREG ($2) && IS_MREG ($4))
3241 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3242 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3244 else if (IS_PREG ($2) && IS_PREG ($4))
3246 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3247 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3250 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3253 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3256 return yyerror ("Dreg expected for source operand");
3258 if (IS_PREG ($3) && IS_PREG ($5))
3260 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3261 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3264 return yyerror ("Preg ++ Preg expected in address");
3267 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3269 Expr_Node *tmp = $7;
3271 return yyerror ("Dreg expected for destination operand");
3273 return yyerror ("Preg expected in address");
3276 tmp = unary (Expr_Op_Type_NEG, tmp);
3279 return yyerror ("Plain symbol used as offset");
3281 if (in_range_p (tmp, -32768, 32767, 0))
3283 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3285 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3288 return yyerror ("Displacement out of range");
3291 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3294 return yyerror ("Dreg expected for destination operand");
3296 return yyerror ("Preg expected in address");
3298 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3300 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3303 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3306 return yyerror ("Dreg expected for destination operand");
3308 if (IS_IREG ($4) && IS_MREG ($6))
3310 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3311 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3313 else if (IS_PREG ($4) && IS_PREG ($6))
3315 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3316 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3319 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3322 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3324 Expr_Node *tmp = $6;
3325 int ispreg = IS_PREG ($1);
3326 int isgot = IS_RELOC($6);
3329 return yyerror ("Preg expected in address");
3331 if (!IS_DREG ($1) && !ispreg)
3332 return yyerror ("Dreg or Preg expected for destination operand");
3334 if (tmp->type == Expr_Node_Reloc
3335 && strcmp (tmp->value.s_value,
3336 "_current_shared_library_p5_offset_") != 0)
3337 return yyerror ("Plain symbol used as offset");
3340 tmp = unary (Expr_Op_Type_NEG, tmp);
3344 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3345 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3347 else if (in_range_p (tmp, 0, 63, 3))
3349 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3350 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3352 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3354 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3355 tmp = unary (Expr_Op_Type_NEG, tmp);
3356 $$ = LDSTIIFP (tmp, &$1, 0);
3358 else if (in_range_p (tmp, -131072, 131071, 3))
3360 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3361 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3365 return yyerror ("Displacement out of range");
3368 | REG ASSIGN LBRACK REG post_op RBRACK
3370 if (!IS_IREG ($4) && !IS_PREG ($4))
3371 return yyerror ("Ireg or Preg expected in address");
3372 else if (IS_IREG ($4) && !IS_DREG ($1))
3373 return yyerror ("Dreg expected in destination operand");
3374 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3375 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3376 return yyerror ("Dreg or Preg expected in destination operand");
3380 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3381 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3383 else if (IS_DREG ($1))
3385 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3386 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3388 else if (IS_PREG ($1))
3390 if (REG_SAME ($1, $4) && $5.x0 != 2)
3391 return yyerror ("Pregs can't be same");
3393 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3394 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3398 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3399 $$ = PUSHPOPREG (&$1, 0);
3404 /* PushPopMultiple. */
3405 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3407 if ($1.regno != REG_SP)
3408 yyerror ("Stack Pointer expected");
3409 if ($4.regno == REG_R7
3410 && IN_RANGE ($6, 0, 7)
3411 && $8.regno == REG_P5
3412 && IN_RANGE ($10, 0, 5))
3414 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3415 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3418 return yyerror ("Bad register for PushPopMultiple");
3421 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3423 if ($1.regno != REG_SP)
3424 yyerror ("Stack Pointer expected");
3426 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3428 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3429 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3431 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3433 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3434 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3437 return yyerror ("Bad register for PushPopMultiple");
3440 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3442 if ($11.regno != REG_SP)
3443 yyerror ("Stack Pointer expected");
3444 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3445 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3447 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3448 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3451 return yyerror ("Bad register range for PushPopMultiple");
3454 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3456 if ($7.regno != REG_SP)
3457 yyerror ("Stack Pointer expected");
3459 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3461 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3462 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3464 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3466 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3467 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3470 return yyerror ("Bad register range for PushPopMultiple");
3473 | reg_with_predec ASSIGN REG
3475 if ($1.regno != REG_SP)
3476 yyerror ("Stack Pointer expected");
3480 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3481 $$ = PUSHPOPREG (&$3, 1);
3484 return yyerror ("Bad register for PushPopReg");
3491 if (IS_URANGE (16, $2, 0, 4))
3492 $$ = LINKAGE (0, uimm16s4 ($2));
3494 return yyerror ("Bad constant for LINK");
3499 notethat ("linkage: UNLINK\n");
3500 $$ = LINKAGE (1, 0);
3506 | LSETUP LPAREN expr COMMA expr RPAREN REG
3508 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3510 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3511 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3514 return yyerror ("Bad register or values for LSETUP");
3517 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3519 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3520 && IS_PREG ($9) && IS_CREG ($7))
3522 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3523 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3526 return yyerror ("Bad register or values for LSETUP");
3529 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3531 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3532 && IS_PREG ($9) && IS_CREG ($7)
3533 && EXPR_VALUE ($11) == 1)
3535 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3536 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3539 return yyerror ("Bad register or values for LSETUP");
3546 return yyerror ("Invalid expression in loop statement");
3548 return yyerror ("Invalid loop counter register");
3549 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3551 | LOOP expr REG ASSIGN REG
3553 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3555 notethat ("Loop: LOOP expr counters = pregs\n");
3556 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3559 return yyerror ("Bad register or values for LOOP");
3561 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3563 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3565 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3566 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3569 return yyerror ("Bad register or values for LOOP");
3575 Expr_Node_Value val;
3577 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3578 bfin_loop_attempt_create_label (tmp, 1);
3579 if (!IS_RELOC (tmp))
3580 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3581 bfin_loop_beginend (tmp, 1);
3587 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3589 bfin_loop_beginend ($2, 1);
3596 Expr_Node_Value val;
3598 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3599 bfin_loop_attempt_create_label (tmp, 1);
3600 if (!IS_RELOC (tmp))
3601 return yyerror ("Invalid expression in LOOP_END statement");
3602 bfin_loop_beginend (tmp, 0);
3608 return yyerror ("Invalid expression in LOOP_END statement");
3610 bfin_loop_beginend ($2, 0);
3618 notethat ("psedoDEBUG: ABORT\n");
3619 $$ = bfin_gen_pseudodbg (3, 3, 0);
3624 notethat ("pseudoDEBUG: DBG\n");
3625 $$ = bfin_gen_pseudodbg (3, 7, 0);
3629 notethat ("pseudoDEBUG: DBG REG_A\n");
3630 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3634 notethat ("pseudoDEBUG: DBG allregs\n");
3635 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3638 | DBGCMPLX LPAREN REG RPAREN
3641 return yyerror ("Dregs expected");
3642 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3643 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3648 notethat ("psedoDEBUG: DBGHALT\n");
3649 $$ = bfin_gen_pseudodbg (3, 5, 0);
3654 notethat ("psedoDEBUG: HLT\n");
3655 $$ = bfin_gen_pseudodbg (3, 4, 0);
3658 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3660 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3661 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3664 | DBGAH LPAREN REG COMMA expr RPAREN
3666 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3667 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3670 | DBGAL LPAREN REG COMMA expr RPAREN
3672 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3673 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3678 if (!IS_UIMM ($2, 8))
3679 return yyerror ("Constant out of range");
3680 notethat ("psedodbg_assert: OUTC uimm8\n");
3681 $$ = bfin_gen_pseudochr (uimm8 ($2));
3687 return yyerror ("Dregs expected");
3688 notethat ("psedodbg_assert: OUTC dreg\n");
3689 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3696 /* Register rules. */
3698 REG_A: REG_A_DOUBLE_ZERO
3716 | LPAREN M COMMA MMOD RPAREN
3721 | LPAREN MMOD COMMA M RPAREN
3726 | LPAREN MMOD RPAREN
3738 asr_asl: LPAREN ASL RPAREN
3819 | LPAREN asr_asl_0 RPAREN
3831 | LPAREN asr_asl_0 COMMA sco RPAREN
3837 | LPAREN sco COMMA asr_asl_0 RPAREN
3897 | LPAREN V COMMA S RPAREN
3902 | LPAREN S COMMA V RPAREN
3964 | LPAREN MMOD RPAREN
3967 return yyerror ("Bad modifier");
3971 | LPAREN MMOD COMMA R RPAREN
3974 return yyerror ("Bad modifier");
3978 | LPAREN R COMMA MMOD RPAREN
3981 return yyerror ("Bad modifier");
4008 | LPAREN MMOD RPAREN
4013 return yyerror ("Only (W32) allowed");
4021 | LPAREN MMOD RPAREN
4026 return yyerror ("(IU) expected");
4030 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4036 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4088 $$.r0 = 1; /* HL. */
4091 $$.aop = 0; /* aop. */
4096 $$.r0 = 1; /* HL. */
4099 $$.aop = 1; /* aop. */
4102 | LPAREN RNDL RPAREN
4104 $$.r0 = 0; /* HL. */
4107 $$.aop = 0; /* aop. */
4112 $$.r0 = 0; /* HL. */
4118 | LPAREN RNDH COMMA R RPAREN
4120 $$.r0 = 1; /* HL. */
4123 $$.aop = 0; /* aop. */
4125 | LPAREN TH COMMA R RPAREN
4127 $$.r0 = 1; /* HL. */
4130 $$.aop = 1; /* aop. */
4132 | LPAREN RNDL COMMA R RPAREN
4134 $$.r0 = 0; /* HL. */
4137 $$.aop = 0; /* aop. */
4140 | LPAREN TL COMMA R RPAREN
4142 $$.r0 = 0; /* HL. */
4145 $$.aop = 1; /* aop. */
4153 $$.x0 = 0; /* HL. */
4158 $$.x0 = 1; /* HL. */
4160 | LPAREN LO COMMA R RPAREN
4163 $$.x0 = 0; /* HL. */
4165 | LPAREN HI COMMA R RPAREN
4168 $$.x0 = 1; /* HL. */
4186 /* Assignments, Macfuncs. */
4212 if (IS_A1 ($3) && IS_EVEN ($1))
4213 return yyerror ("Cannot move A1 to even register");
4214 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4215 return yyerror ("Cannot move A0 to odd register");
4231 | REG ASSIGN LPAREN a_macfunc RPAREN
4233 if ($4.n && IS_EVEN ($1))
4234 return yyerror ("Cannot move A1 to even register");
4235 else if (!$4.n && !IS_EVEN ($1))
4236 return yyerror ("Cannot move A0 to odd register");
4244 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4246 if ($4.n && !IS_H ($1))
4247 return yyerror ("Cannot move A1 to low half of register");
4248 else if (!$4.n && IS_H ($1))
4249 return yyerror ("Cannot move A0 to high half of register");
4257 | HALF_REG ASSIGN REG_A
4259 if (IS_A1 ($3) && !IS_H ($1))
4260 return yyerror ("Cannot move A1 to low half of register");
4261 else if (!IS_A1 ($3) && IS_H ($1))
4262 return yyerror ("Cannot move A0 to high half of register");
4275 a_assign multiply_halfregs
4282 | a_plusassign multiply_halfregs
4289 | a_minusassign multiply_halfregs
4299 HALF_REG STAR HALF_REG
4301 if (IS_DREG ($1) && IS_DREG ($3))
4307 return yyerror ("Dregs expected");
4331 CCREG cc_op STATUS_REG
4343 | STATUS_REG cc_op CCREG
4357 /* Expressions and Symbols. */
4361 Expr_Node_Value val;
4362 val.s_value = S_GET_NAME($1);
4363 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4369 { $$ = BFD_RELOC_BFIN_GOT; }
4371 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4373 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4376 got: symbol AT any_gotrel
4378 Expr_Node_Value val;
4380 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4403 Expr_Node_Value val;
4405 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4411 | LPAREN expr_1 RPAREN
4417 $$ = unary (Expr_Op_Type_COMP, $2);
4419 | MINUS expr_1 %prec TILDA
4421 $$ = unary (Expr_Op_Type_NEG, $2);
4431 expr_1: expr_1 STAR expr_1
4433 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4435 | expr_1 SLASH expr_1
4437 $$ = binary (Expr_Op_Type_Div, $1, $3);
4439 | expr_1 PERCENT expr_1
4441 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4443 | expr_1 PLUS expr_1
4445 $$ = binary (Expr_Op_Type_Add, $1, $3);
4447 | expr_1 MINUS expr_1
4449 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4451 | expr_1 LESS_LESS expr_1
4453 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4455 | expr_1 GREATER_GREATER expr_1
4457 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4459 | expr_1 AMPERSAND expr_1
4461 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4463 | expr_1 CARET expr_1
4465 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4469 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4481 mkexpr (int x, SYMBOL_T s)
4483 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4490 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4492 int umax = (1 << sz) - 1;
4493 int min = -1 << (sz - 1);
4494 int max = (1 << (sz - 1)) - 1;
4496 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4500 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4511 if (v >= min && v <= max) return 1;
4514 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4518 if (v <= umax && v >= 0)
4521 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4526 /* Return the expression structure that allows symbol operations.
4527 If the left and right children are constants, do the operation. */
4529 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4531 Expr_Node_Value val;
4533 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4537 case Expr_Op_Type_Add:
4538 x->value.i_value += y->value.i_value;
4540 case Expr_Op_Type_Sub:
4541 x->value.i_value -= y->value.i_value;
4543 case Expr_Op_Type_Mult:
4544 x->value.i_value *= y->value.i_value;
4546 case Expr_Op_Type_Div:
4547 if (y->value.i_value == 0)
4548 error ("Illegal Expression: Division by zero.");
4550 x->value.i_value /= y->value.i_value;
4552 case Expr_Op_Type_Mod:
4553 x->value.i_value %= y->value.i_value;
4555 case Expr_Op_Type_Lshift:
4556 x->value.i_value <<= y->value.i_value;
4558 case Expr_Op_Type_Rshift:
4559 x->value.i_value >>= y->value.i_value;
4561 case Expr_Op_Type_BAND:
4562 x->value.i_value &= y->value.i_value;
4564 case Expr_Op_Type_BOR:
4565 x->value.i_value |= y->value.i_value;
4567 case Expr_Op_Type_BXOR:
4568 x->value.i_value ^= y->value.i_value;
4570 case Expr_Op_Type_LAND:
4571 x->value.i_value = x->value.i_value && y->value.i_value;
4573 case Expr_Op_Type_LOR:
4574 x->value.i_value = x->value.i_value || y->value.i_value;
4578 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4582 /* Canonicalize order to EXPR OP CONSTANT. */
4583 if (x->type == Expr_Node_Constant)
4589 /* Canonicalize subtraction of const to addition of negated const. */
4590 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4592 op = Expr_Op_Type_Add;
4593 y->value.i_value = -y->value.i_value;
4595 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4596 && x->Right_Child->type == Expr_Node_Constant)
4598 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4600 x->Right_Child->value.i_value += y->value.i_value;
4605 /* Create a new expression structure. */
4607 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4611 unary (Expr_Op_Type op, Expr_Node *x)
4613 if (x->type == Expr_Node_Constant)
4617 case Expr_Op_Type_NEG:
4618 x->value.i_value = -x->value.i_value;
4620 case Expr_Op_Type_COMP:
4621 x->value.i_value = ~x->value.i_value;
4624 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4630 /* Create a new expression structure. */
4631 Expr_Node_Value val;
4633 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4637 int debug_codeselection = 0;
4639 notethat (char *format, ...)
4642 va_start (ap, format);
4643 if (debug_codeselection)
4645 vfprintf (errorf, format, ap);
4651 main (int argc, char **argv)