1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *, int, int, int, int);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *, ...);
165 char *current_inputline;
167 int yyerror (char *);
169 void error (char *format, ...)
172 static char buffer[2000];
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
178 as_bad ("%s", buffer);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (exp);
199 if (exp->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define uimm8(x) EXPR_VALUE (x)
216 #define imm16(x) EXPR_VALUE (x)
217 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
218 #define uimm16(x) EXPR_VALUE (x)
220 /* Return true if a value is inside a range. */
221 #define IN_RANGE(x, low, high) \
222 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
224 /* Auxiliary functions. */
227 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
229 if (!IS_DREG (*reg1))
231 yyerror ("Dregs expected");
235 if (reg1->regno != 1 && reg1->regno != 3)
237 yyerror ("Bad register pair");
241 if (imm7 (reg2) != reg1->regno - 1)
243 yyerror ("Bad register pair");
252 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
254 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
255 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
256 return yyerror ("Source multiplication register mismatch");
262 /* Check mac option. */
265 check_macfunc_option (Macfunc *a, Opt_mode *opt)
267 /* Default option is always valid. */
271 if ((a->w == 1 && a->P == 1
272 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
273 && opt->mod != M_S2RND && opt->mod != M_ISS2)
274 || (a->w == 1 && a->P == 0
275 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
276 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
277 && opt->mod != M_ISS2 && opt->mod != M_IH)
278 || (a->w == 0 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
285 /* Check (vector) mac funcs and ops. */
288 check_macfuncs (Macfunc *aa, Opt_mode *opa,
289 Macfunc *ab, Opt_mode *opb)
291 /* Variables for swapping. */
295 /* The option mode should be put at the end of the second instruction
296 of the vector except M, which should follow MAC1 instruction. */
298 return yyerror ("Bad opt mode");
300 /* If a0macfunc comes before a1macfunc, swap them. */
304 /* (M) is not allowed here. */
306 return yyerror ("(M) not allowed with A0MAC");
308 return yyerror ("Vector AxMACs can't be same");
310 mtmp = *aa; *aa = *ab; *ab = mtmp;
311 otmp = *opa; *opa = *opb; *opb = otmp;
316 return yyerror ("(M) not allowed with A0MAC");
318 return yyerror ("Vector AxMACs can't be same");
321 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
322 assignment_or_macfuncs. */
323 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
324 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
326 if (check_multiply_halfregs (aa, ab) < 0)
331 /* Only one of the assign_macfuncs has a half reg multiply
332 Evil trick: Just 'OR' their source register codes:
333 We can do that, because we know they were initialized to 0
334 in the rules that don't use multiply_halfregs. */
335 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
336 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
339 if (aa->w == ab->w && aa->P != ab->P)
341 return yyerror ("macfuncs must differ");
342 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
343 return yyerror ("Destination Dregs must differ by one");
346 /* Make sure mod flags get ORed, too. */
347 opb->mod |= opa->mod;
350 if (check_macfunc_option (aa, opb) < 0
351 && check_macfunc_option (ab, opb) < 0)
352 return yyerror ("bad option");
354 /* Make sure first macfunc has got both P flags ORed. */
362 is_group1 (INSTR_T x)
364 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
365 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
372 is_group2 (INSTR_T x)
374 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
375 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
376 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
377 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
378 || (x->value == 0x0000))
384 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
386 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
387 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
388 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
390 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
391 yyerror ("resource conflict in multi-issue instruction");
393 /* Anomaly 05000074 */
394 if (ENABLE_AC_05000074
395 && dsp32 != NULL && dsp16_grp1 != NULL
396 && (dsp32->value & 0xf780) == 0xc680
397 && ((dsp16_grp1->value & 0xfe40) == 0x9240
398 || (dsp16_grp1->value & 0xfe08) == 0xba08
399 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
400 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
401 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
403 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
415 struct { int r0; int s0; int x0; int aop; } modcodes;
416 struct { int r0; } r0;
423 /* Vector Specific. */
424 %token BYTEOP16P BYTEOP16M
425 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
426 %token BYTEUNPACK BYTEPACK
429 %token ALIGN8 ALIGN16 ALIGN24
431 %token EXTRACT DEPOSIT EXPADJ SEARCH
432 %token ONES SIGN SIGNBITS
440 %token CCREG BYTE_DREG
441 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
442 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
447 %token RTI RTS RTX RTN RTE
458 %token JUMP JUMP_DOT_S JUMP_DOT_L
465 %token NOT TILDA BANG
471 %token MINUS PLUS STAR SLASH
475 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
476 %token _MINUS_MINUS _PLUS_PLUS
478 /* Shift/rotate ops. */
479 %token SHIFT LSHIFT ASHIFT BXORSHIFT
480 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
482 %token LESS_LESS GREATER_GREATER
483 %token _GREATER_GREATER_GREATER
484 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
487 /* In place operators. */
488 %token ASSIGN _STAR_ASSIGN
489 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
490 %token _MINUS_ASSIGN _PLUS_ASSIGN
492 /* Assignments, comparisons. */
493 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
498 %token FLUSHINV FLUSH
499 %token IFLUSH PREFETCH
516 %token R RND RNDL RNDH RND12 RND20
521 %token BITTGL BITCLR BITSET BITTST BITMUX
524 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
526 /* Semantic auxiliaries. */
529 %token COLON SEMICOLON
530 %token RPAREN LPAREN LBRACK RBRACK
534 %token GOT GOT17M4 FUNCDESC_GOT17M4
544 %type <modcodes> byteop_mod
546 %type <reg> a_plusassign
547 %type <reg> a_minusassign
548 %type <macfunc> multiply_halfregs
549 %type <macfunc> assign_macfunc
550 %type <macfunc> a_macfunc
554 %type <modcodes> vsmod
555 %type <modcodes> ccstat
558 %type <reg> reg_with_postinc
559 %type <reg> reg_with_predec
563 %type <symbol> SYMBOL
566 %type <reg> BYTE_DREG
567 %type <reg> REG_A_DOUBLE_ZERO
568 %type <reg> REG_A_DOUBLE_ONE
570 %type <reg> STATUS_REG
574 %type <modcodes> smod
575 %type <modcodes> b3_op
576 %type <modcodes> rnd_op
577 %type <modcodes> post_op
579 %type <r0> iu_or_nothing
580 %type <r0> plus_minus
584 %type <modcodes> amod0
585 %type <modcodes> amod1
586 %type <modcodes> amod2
588 %type <r0> w32_or_nothing
592 %type <expr> got_or_expr
594 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
596 /* Precedence rules. */
600 %left LESS_LESS GREATER_GREATER
602 %left STAR SLASH PERCENT
613 if (insn == (INSTR_T) 0)
614 return NO_INSN_GENERATED;
615 else if (insn == (INSTR_T) - 1)
616 return SEMANTIC_ERROR;
618 return INSN_GENERATED;
623 /* Parallel instructions. */
624 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
626 if (($1->value & 0xf800) == 0xc000)
628 if (is_group1 ($3) && is_group2 ($5))
629 $$ = gen_multi_instr_1 ($1, $3, $5);
630 else if (is_group2 ($3) && is_group1 ($5))
631 $$ = gen_multi_instr_1 ($1, $5, $3);
633 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
635 else if (($3->value & 0xf800) == 0xc000)
637 if (is_group1 ($1) && is_group2 ($5))
638 $$ = gen_multi_instr_1 ($3, $1, $5);
639 else if (is_group2 ($1) && is_group1 ($5))
640 $$ = gen_multi_instr_1 ($3, $5, $1);
642 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
644 else if (($5->value & 0xf800) == 0xc000)
646 if (is_group1 ($1) && is_group2 ($3))
647 $$ = gen_multi_instr_1 ($5, $1, $3);
648 else if (is_group2 ($1) && is_group1 ($3))
649 $$ = gen_multi_instr_1 ($5, $3, $1);
651 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
654 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
657 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
659 if (($1->value & 0xf800) == 0xc000)
662 $$ = gen_multi_instr_1 ($1, $3, 0);
663 else if (is_group2 ($3))
664 $$ = gen_multi_instr_1 ($1, 0, $3);
666 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
668 else if (($3->value & 0xf800) == 0xc000)
671 $$ = gen_multi_instr_1 ($3, $1, 0);
672 else if (is_group2 ($1))
673 $$ = gen_multi_instr_1 ($3, 0, $1);
675 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
677 else if (is_group1 ($1) && is_group2 ($3))
678 $$ = gen_multi_instr_1 (0, $1, $3);
679 else if (is_group2 ($1) && is_group1 ($3))
680 $$ = gen_multi_instr_1 (0, $3, $1);
682 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
697 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
699 | assign_macfunc opt_mode
703 int h00, h10, h01, h11;
705 if (check_macfunc_option (&$1, &$2) < 0)
706 return yyerror ("bad option");
711 return yyerror ("(m) not allowed with a0 unit");
730 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
731 &$1.dst, op0, &$1.s0, &$1.s1, w0);
737 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
741 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
743 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
750 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
751 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
752 dst, $4.op, &$1.s0, &$1.s1, $4.w);
759 notethat ("dsp32alu: DISALGNEXCPT\n");
760 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
762 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
764 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
766 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
767 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
770 return yyerror ("Register mismatch");
772 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
774 if (!IS_A1 ($4) && IS_A1 ($5))
776 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
777 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
780 return yyerror ("Register mismatch");
782 | A_ZERO_DOT_H ASSIGN HALF_REG
784 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
785 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
787 | A_ONE_DOT_H ASSIGN HALF_REG
789 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
790 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
792 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
793 COLON expr COMMA REG COLON expr RPAREN aligndir
795 if (!IS_DREG ($2) || !IS_DREG ($4))
796 return yyerror ("Dregs expected");
797 else if (!valid_dreg_pair (&$9, $11))
798 return yyerror ("Bad dreg pair");
799 else if (!valid_dreg_pair (&$13, $15))
800 return yyerror ("Bad dreg pair");
803 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
804 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
808 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
809 REG COLON expr RPAREN aligndir
811 if (!IS_DREG ($2) || !IS_DREG ($4))
812 return yyerror ("Dregs expected");
813 else if (!valid_dreg_pair (&$9, $11))
814 return yyerror ("Bad dreg pair");
815 else if (!valid_dreg_pair (&$13, $15))
816 return yyerror ("Bad dreg pair");
819 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
820 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
824 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
826 if (!IS_DREG ($2) || !IS_DREG ($4))
827 return yyerror ("Dregs expected");
828 else if (!valid_dreg_pair (&$8, $10))
829 return yyerror ("Bad dreg pair");
832 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
833 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
836 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
838 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
840 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
841 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
844 return yyerror ("Register mismatch");
846 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
847 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
849 if (IS_DREG ($1) && IS_DREG ($7))
851 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
852 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
855 return yyerror ("Register mismatch");
859 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
861 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
862 && IS_A1 ($9) && !IS_A1 ($11))
864 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
865 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
868 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
869 && !IS_A1 ($9) && IS_A1 ($11))
871 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
872 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
875 return yyerror ("Register mismatch");
878 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
881 return yyerror ("Operators must differ");
883 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
884 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
886 notethat ("dsp32alu: dregs = dregs + dregs,"
887 "dregs = dregs - dregs (amod1)\n");
888 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
891 return yyerror ("Register mismatch");
894 /* Bar Operations. */
896 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
898 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
899 return yyerror ("Differing source registers");
901 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
902 return yyerror ("Dregs expected");
905 if ($4.r0 == 1 && $10.r0 == 2)
907 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
908 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
910 else if ($4.r0 == 0 && $10.r0 == 3)
912 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
913 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
916 return yyerror ("Bar operand mismatch");
919 | REG ASSIGN ABS REG vmod
923 if (IS_DREG ($1) && IS_DREG ($4))
927 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
932 /* Vector version of ABS. */
933 notethat ("dsp32alu: dregs = ABS dregs\n");
936 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
939 return yyerror ("Dregs expected");
943 notethat ("dsp32alu: Ax = ABS Ax\n");
944 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
946 | A_ZERO_DOT_L ASSIGN HALF_REG
950 notethat ("dsp32alu: A0.l = reg_half\n");
951 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
954 return yyerror ("A0.l = Rx.l expected");
956 | A_ONE_DOT_L ASSIGN HALF_REG
960 notethat ("dsp32alu: A1.l = reg_half\n");
961 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
964 return yyerror ("A1.l = Rx.l expected");
967 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
969 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
971 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
972 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
975 return yyerror ("Dregs expected");
978 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
981 return yyerror ("Dregs expected");
982 else if (!valid_dreg_pair (&$5, $7))
983 return yyerror ("Bad dreg pair");
984 else if (!valid_dreg_pair (&$9, $11))
985 return yyerror ("Bad dreg pair");
988 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
989 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
992 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
995 return yyerror ("Dregs expected");
996 else if (!valid_dreg_pair (&$5, $7))
997 return yyerror ("Bad dreg pair");
998 else if (!valid_dreg_pair (&$9, $11))
999 return yyerror ("Bad dreg pair");
1002 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1003 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1007 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1011 return yyerror ("Dregs expected");
1012 else if (!valid_dreg_pair (&$5, $7))
1013 return yyerror ("Bad dreg pair");
1014 else if (!valid_dreg_pair (&$9, $11))
1015 return yyerror ("Bad dreg pair");
1018 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1019 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1023 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1027 return yyerror ("Dregs expected");
1028 else if (!valid_dreg_pair (&$5, $7))
1029 return yyerror ("Bad dreg pair");
1030 else if (!valid_dreg_pair (&$9, $11))
1031 return yyerror ("Bad dreg pair");
1034 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1035 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1039 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1043 return yyerror ("Dregs expected");
1044 else if (!valid_dreg_pair (&$5, $7))
1045 return yyerror ("Bad dreg pair");
1046 else if (!valid_dreg_pair (&$9, $11))
1047 return yyerror ("Bad dreg pair");
1050 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1051 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1055 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1057 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1059 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1060 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1063 return yyerror ("Dregs expected");
1066 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1067 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1069 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1071 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1072 "SIGN (dregs_hi) * dregs_hi + "
1073 "SIGN (dregs_lo) * dregs_lo \n");
1075 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1078 return yyerror ("Dregs expected");
1080 | REG ASSIGN REG plus_minus REG amod1
1082 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1086 /* No saturation flag specified, generate the 16 bit variant. */
1087 notethat ("COMP3op: dregs = dregs +- dregs\n");
1088 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1092 /* Saturation flag specified, generate the 32 bit variant. */
1093 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1094 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1098 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1100 notethat ("COMP3op: pregs = pregs + pregs\n");
1101 $$ = COMP3OP (&$1, &$3, &$5, 5);
1104 return yyerror ("Dregs expected");
1106 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1110 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1117 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1118 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1121 return yyerror ("Dregs expected");
1124 | a_assign MINUS REG_A
1126 notethat ("dsp32alu: Ax = - Ax\n");
1127 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1129 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1131 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1132 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1133 $6.s0, $6.x0, HL2 ($3, $5));
1135 | a_assign a_assign expr
1137 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1139 notethat ("dsp32alu: A1 = A0 = 0\n");
1140 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1143 return yyerror ("Bad value, 0 expected");
1147 | a_assign REG_A LPAREN S RPAREN
1149 if (REG_SAME ($1, $2))
1151 notethat ("dsp32alu: Ax = Ax (S)\n");
1152 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1155 return yyerror ("Registers must be equal");
1158 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1162 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1163 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1166 return yyerror ("Dregs expected");
1169 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1171 if (IS_DREG ($3) && IS_DREG ($5))
1173 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1174 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1177 return yyerror ("Dregs expected");
1180 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1182 if (IS_DREG ($3) && IS_DREG ($5))
1184 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1185 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1188 return yyerror ("Dregs expected");
1193 if (!REG_SAME ($1, $2))
1195 notethat ("dsp32alu: An = Am\n");
1196 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1199 return yyerror ("Accu reg arguments must differ");
1206 notethat ("dsp32alu: An = dregs\n");
1207 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1210 return yyerror ("Dregs expected");
1213 | REG ASSIGN HALF_REG xpmod
1217 if ($1.regno == REG_A0x && IS_DREG ($3))
1219 notethat ("dsp32alu: A0.x = dregs_lo\n");
1220 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1222 else if ($1.regno == REG_A1x && IS_DREG ($3))
1224 notethat ("dsp32alu: A1.x = dregs_lo\n");
1225 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1227 else if (IS_DREG ($1) && IS_DREG ($3))
1229 notethat ("ALU2op: dregs = dregs_lo\n");
1230 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1233 return yyerror ("Register mismatch");
1236 return yyerror ("Low reg expected");
1239 | HALF_REG ASSIGN expr
1241 notethat ("LDIMMhalf: pregs_half = imm16\n");
1243 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1244 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1245 return yyerror ("Wrong register for load immediate");
1247 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1248 return yyerror ("Constant out of range");
1250 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1255 notethat ("dsp32alu: An = 0\n");
1258 return yyerror ("0 expected");
1260 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1263 | REG ASSIGN expr xpmod1
1265 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1266 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1267 return yyerror ("Wrong register for load immediate");
1271 /* 7 bit immediate value if possible.
1272 We will check for that constant value for efficiency
1273 If it goes to reloc, it will be 16 bit. */
1274 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1276 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1277 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1279 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1281 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1282 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1286 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1287 return yyerror ("Immediate value out of range");
1289 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1291 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1296 /* (z) There is no 7 bit zero extended instruction.
1297 If the expr is a relocation, generate it. */
1299 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1300 return yyerror ("Immediate value out of range");
1302 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1304 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1308 | HALF_REG ASSIGN REG
1311 return yyerror ("Low reg expected");
1313 if (IS_DREG ($1) && $3.regno == REG_A0x)
1315 notethat ("dsp32alu: dregs_lo = A0.x\n");
1316 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1318 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1320 notethat ("dsp32alu: dregs_lo = A1.x\n");
1321 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1324 return yyerror ("Register mismatch");
1327 | REG ASSIGN REG op_bar_op REG amod0
1329 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1331 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1332 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1335 return yyerror ("Register mismatch");
1338 | REG ASSIGN BYTE_DREG xpmod
1340 if (IS_DREG ($1) && IS_DREG ($3))
1342 notethat ("ALU2op: dregs = dregs_byte\n");
1343 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1346 return yyerror ("Register mismatch");
1349 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1351 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1353 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1354 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1357 return yyerror ("Register mismatch");
1360 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1362 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1364 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1365 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1368 return yyerror ("Register mismatch");
1371 | a_minusassign REG_A w32_or_nothing
1373 if (!IS_A1 ($1) && IS_A1 ($2))
1375 notethat ("dsp32alu: A0 -= A1\n");
1376 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1379 return yyerror ("Register mismatch");
1382 | REG _MINUS_ASSIGN expr
1384 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1386 notethat ("dagMODik: iregs -= 4\n");
1387 $$ = DAGMODIK (&$1, 3);
1389 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1391 notethat ("dagMODik: iregs -= 2\n");
1392 $$ = DAGMODIK (&$1, 1);
1395 return yyerror ("Register or value mismatch");
1398 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1400 if (IS_IREG ($1) && IS_MREG ($3))
1402 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1404 $$ = DAGMODIM (&$1, &$3, 0, 1);
1406 else if (IS_PREG ($1) && IS_PREG ($3))
1408 notethat ("PTR2op: pregs += pregs (BREV )\n");
1409 $$ = PTR2OP (&$1, &$3, 5);
1412 return yyerror ("Register mismatch");
1415 | REG _MINUS_ASSIGN REG
1417 if (IS_IREG ($1) && IS_MREG ($3))
1419 notethat ("dagMODim: iregs -= mregs\n");
1420 $$ = DAGMODIM (&$1, &$3, 1, 0);
1422 else if (IS_PREG ($1) && IS_PREG ($3))
1424 notethat ("PTR2op: pregs -= pregs\n");
1425 $$ = PTR2OP (&$1, &$3, 0);
1428 return yyerror ("Register mismatch");
1431 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1433 if (!IS_A1 ($1) && IS_A1 ($3))
1435 notethat ("dsp32alu: A0 += A1 (W32)\n");
1436 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1439 return yyerror ("Register mismatch");
1442 | REG _PLUS_ASSIGN REG
1444 if (IS_IREG ($1) && IS_MREG ($3))
1446 notethat ("dagMODim: iregs += mregs\n");
1447 $$ = DAGMODIM (&$1, &$3, 0, 0);
1450 return yyerror ("iregs += mregs expected");
1453 | REG _PLUS_ASSIGN expr
1457 if (EXPR_VALUE ($3) == 4)
1459 notethat ("dagMODik: iregs += 4\n");
1460 $$ = DAGMODIK (&$1, 2);
1462 else if (EXPR_VALUE ($3) == 2)
1464 notethat ("dagMODik: iregs += 2\n");
1465 $$ = DAGMODIK (&$1, 0);
1468 return yyerror ("iregs += [ 2 | 4 ");
1470 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1472 notethat ("COMPI2opP: pregs += imm7\n");
1473 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1475 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1477 notethat ("COMPI2opD: dregs += imm7\n");
1478 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1480 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1481 return yyerror ("Immediate value out of range");
1483 return yyerror ("Register mismatch");
1486 | REG _STAR_ASSIGN REG
1488 if (IS_DREG ($1) && IS_DREG ($3))
1490 notethat ("ALU2op: dregs *= dregs\n");
1491 $$ = ALU2OP (&$1, &$3, 3);
1494 return yyerror ("Register mismatch");
1497 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1499 if (!valid_dreg_pair (&$3, $5))
1500 return yyerror ("Bad dreg pair");
1501 else if (!valid_dreg_pair (&$7, $9))
1502 return yyerror ("Bad dreg pair");
1505 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1506 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1510 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1512 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1514 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1515 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1518 return yyerror ("Register mismatch");
1521 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1523 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1524 && REG_SAME ($1, $4))
1526 if (EXPR_VALUE ($9) == 1)
1528 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1529 $$ = ALU2OP (&$1, &$6, 4);
1531 else if (EXPR_VALUE ($9) == 2)
1533 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1534 $$ = ALU2OP (&$1, &$6, 5);
1537 return yyerror ("Bad shift value");
1539 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1540 && REG_SAME ($1, $4))
1542 if (EXPR_VALUE ($9) == 1)
1544 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1545 $$ = PTR2OP (&$1, &$6, 6);
1547 else if (EXPR_VALUE ($9) == 2)
1549 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1550 $$ = PTR2OP (&$1, &$6, 7);
1553 return yyerror ("Bad shift value");
1556 return yyerror ("Register mismatch");
1560 | REG ASSIGN REG BAR REG
1562 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1564 notethat ("COMP3op: dregs = dregs | dregs\n");
1565 $$ = COMP3OP (&$1, &$3, &$5, 3);
1568 return yyerror ("Dregs expected");
1570 | REG ASSIGN REG CARET REG
1572 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1574 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1575 $$ = COMP3OP (&$1, &$3, &$5, 4);
1578 return yyerror ("Dregs expected");
1580 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1582 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1584 if (EXPR_VALUE ($8) == 1)
1586 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1587 $$ = COMP3OP (&$1, &$3, &$6, 6);
1589 else if (EXPR_VALUE ($8) == 2)
1591 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1592 $$ = COMP3OP (&$1, &$3, &$6, 7);
1595 return yyerror ("Bad shift value");
1598 return yyerror ("Dregs expected");
1600 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1602 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1604 notethat ("CCflag: CC = A0 == A1\n");
1605 $$ = CCFLAG (0, 0, 5, 0, 0);
1608 return yyerror ("AREGs are in bad order or same");
1610 | CCREG ASSIGN REG_A LESS_THAN REG_A
1612 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1614 notethat ("CCflag: CC = A0 < A1\n");
1615 $$ = CCFLAG (0, 0, 6, 0, 0);
1618 return yyerror ("AREGs are in bad order or same");
1620 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1622 if ((IS_DREG ($3) && IS_DREG ($5))
1623 || (IS_PREG ($3) && IS_PREG ($5)))
1625 notethat ("CCflag: CC = dpregs < dpregs\n");
1626 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1629 return yyerror ("Bad register in comparison");
1631 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1633 if (!IS_DREG ($3) && !IS_PREG ($3))
1634 return yyerror ("Bad register in comparison");
1636 if (($6.r0 == 1 && IS_IMM ($5, 3))
1637 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1639 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1640 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1643 return yyerror ("Bad constant value");
1645 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1647 if ((IS_DREG ($3) && IS_DREG ($5))
1648 || (IS_PREG ($3) && IS_PREG ($5)))
1650 notethat ("CCflag: CC = dpregs == dpregs\n");
1651 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1654 return yyerror ("Bad register in comparison");
1656 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1658 if (!IS_DREG ($3) && !IS_PREG ($3))
1659 return yyerror ("Bad register in comparison");
1663 notethat ("CCflag: CC = dpregs == imm3\n");
1664 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1667 return yyerror ("Bad constant range");
1669 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1671 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1673 notethat ("CCflag: CC = A0 <= A1\n");
1674 $$ = CCFLAG (0, 0, 7, 0, 0);
1677 return yyerror ("AREGs are in bad order or same");
1679 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1681 if ((IS_DREG ($3) && IS_DREG ($5))
1682 || (IS_PREG ($3) && IS_PREG ($5)))
1684 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1685 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1686 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1689 return yyerror ("Bad register in comparison");
1691 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1693 if (!IS_DREG ($3) && !IS_PREG ($3))
1694 return yyerror ("Bad register in comparison");
1696 if (($6.r0 == 1 && IS_IMM ($5, 3))
1697 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1699 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1700 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1703 return yyerror ("Bad constant value");
1706 | REG ASSIGN REG AMPERSAND REG
1708 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1710 notethat ("COMP3op: dregs = dregs & dregs\n");
1711 $$ = COMP3OP (&$1, &$3, &$5, 2);
1714 return yyerror ("Dregs expected");
1719 notethat ("CC2stat operation\n");
1720 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1725 if ((IS_GENREG ($1) && IS_GENREG ($3))
1726 || (IS_GENREG ($1) && IS_DAGREG ($3))
1727 || (IS_DAGREG ($1) && IS_GENREG ($3))
1728 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1729 || (IS_GENREG ($1) && $3.regno == REG_USP)
1730 || ($1.regno == REG_USP && IS_GENREG ($3))
1731 || (IS_DREG ($1) && IS_SYSREG ($3))
1732 || (IS_PREG ($1) && IS_SYSREG ($3))
1733 || (IS_SYSREG ($1) && IS_DREG ($3))
1734 || (IS_SYSREG ($1) && IS_PREG ($3))
1735 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1737 $$ = bfin_gen_regmv (&$3, &$1);
1740 return yyerror ("Register mismatch");
1747 notethat ("CC2dreg: CC = dregs\n");
1748 $$ = bfin_gen_cc2dreg (1, &$3);
1751 return yyerror ("Register mismatch");
1758 notethat ("CC2dreg: dregs = CC\n");
1759 $$ = bfin_gen_cc2dreg (0, &$1);
1762 return yyerror ("Register mismatch");
1765 | CCREG _ASSIGN_BANG CCREG
1767 notethat ("CC2dreg: CC =! CC\n");
1768 $$ = bfin_gen_cc2dreg (3, 0);
1773 | HALF_REG ASSIGN multiply_halfregs opt_mode
1775 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1777 if (!IS_H ($1) && $4.MM)
1778 return yyerror ("(M) not allowed with MAC0");
1780 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1781 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1782 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1783 return yyerror ("bad option.");
1787 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1788 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1789 &$1, 0, &$3.s0, &$3.s1, 0);
1793 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1794 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1795 &$1, 0, &$3.s0, &$3.s1, 1);
1799 | REG ASSIGN multiply_halfregs opt_mode
1801 /* Odd registers can use (M). */
1803 return yyerror ("Dreg expected");
1805 if (IS_EVEN ($1) && $4.MM)
1806 return yyerror ("(M) not allowed with MAC0");
1808 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1809 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1810 return yyerror ("bad option");
1814 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1816 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1817 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1818 &$1, 0, &$3.s0, &$3.s1, 0);
1822 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1823 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1824 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1825 &$1, 0, &$3.s0, &$3.s1, 1);
1829 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1830 HALF_REG ASSIGN multiply_halfregs opt_mode
1832 if (!IS_DREG ($1) || !IS_DREG ($6))
1833 return yyerror ("Dregs expected");
1835 if (!IS_HCOMPL($1, $6))
1836 return yyerror ("Dest registers mismatch");
1838 if (check_multiply_halfregs (&$3, &$8) < 0)
1841 if ((!IS_H ($1) && $4.MM)
1842 || (!IS_H ($6) && $9.MM))
1843 return yyerror ("(M) not allowed with MAC0");
1845 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1846 "dregs_lo = multiply_halfregs opt_mode\n");
1849 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1850 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1851 &$1, 0, &$3.s0, &$3.s1, 1);
1853 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1854 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1855 &$1, 0, &$3.s0, &$3.s1, 1);
1858 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1860 if (!IS_DREG ($1) || !IS_DREG ($6))
1861 return yyerror ("Dregs expected");
1863 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1864 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1865 return yyerror ("Dest registers mismatch");
1867 if (check_multiply_halfregs (&$3, &$8) < 0)
1870 if ((IS_EVEN ($1) && $4.MM)
1871 || (IS_EVEN ($6) && $9.MM))
1872 return yyerror ("(M) not allowed with MAC0");
1874 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1875 "dregs = multiply_halfregs opt_mode\n");
1878 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1879 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1880 &$1, 0, &$3.s0, &$3.s1, 1);
1882 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1883 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1884 &$1, 0, &$3.s0, &$3.s1, 1);
1889 | a_assign ASHIFT REG_A BY HALF_REG
1891 if (!REG_SAME ($1, $3))
1892 return yyerror ("Aregs must be same");
1894 if (IS_DREG ($5) && !IS_H ($5))
1896 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1897 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1900 return yyerror ("Dregs expected");
1903 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1905 if (IS_DREG ($6) && !IS_H ($6))
1907 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1908 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1911 return yyerror ("Dregs expected");
1914 | a_assign REG_A LESS_LESS expr
1916 if (!REG_SAME ($1, $2))
1917 return yyerror ("Aregs must be same");
1919 if (IS_UIMM ($4, 5))
1921 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1922 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1925 return yyerror ("Bad shift value");
1928 | REG ASSIGN REG LESS_LESS expr vsmod
1930 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1935 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1936 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1940 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1941 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1944 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1946 if (EXPR_VALUE ($5) == 2)
1948 notethat ("PTR2op: pregs = pregs << 2\n");
1949 $$ = PTR2OP (&$1, &$3, 1);
1951 else if (EXPR_VALUE ($5) == 1)
1953 notethat ("COMP3op: pregs = pregs << 1\n");
1954 $$ = COMP3OP (&$1, &$3, &$3, 5);
1957 return yyerror ("Bad shift value");
1960 return yyerror ("Bad shift value or register");
1962 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1964 if (IS_UIMM ($5, 4))
1968 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
1969 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1973 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1974 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1978 return yyerror ("Bad shift value");
1980 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1984 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1989 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1990 "dregs_lo (V, .)\n");
1996 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1998 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2001 return yyerror ("Dregs expected");
2005 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2007 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2009 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2010 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2013 return yyerror ("Bad shift value or register");
2017 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2019 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2021 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2022 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2024 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2026 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2027 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2030 return yyerror ("Bad shift value or register");
2035 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2037 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2039 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2040 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2043 return yyerror ("Register mismatch");
2046 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2048 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2050 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2051 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2054 return yyerror ("Register mismatch");
2057 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2059 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2061 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2062 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2065 return yyerror ("Register mismatch");
2068 | a_assign REG_A _GREATER_GREATER_GREATER expr
2070 if (!REG_SAME ($1, $2))
2071 return yyerror ("Aregs must be same");
2073 if (IS_UIMM ($4, 5))
2075 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2076 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2079 return yyerror ("Shift value range error");
2081 | a_assign LSHIFT REG_A BY HALF_REG
2083 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2085 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2086 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2089 return yyerror ("Register mismatch");
2092 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2094 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2096 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2097 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2100 return yyerror ("Register mismatch");
2103 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2105 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2107 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2108 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2111 return yyerror ("Register mismatch");
2114 | REG ASSIGN SHIFT REG BY HALF_REG
2116 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2118 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2119 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2122 return yyerror ("Register mismatch");
2125 | a_assign REG_A GREATER_GREATER expr
2127 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2129 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2130 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2133 return yyerror ("Accu register expected");
2136 | REG ASSIGN REG GREATER_GREATER expr vmod
2140 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2142 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2143 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2146 return yyerror ("Register mismatch");
2150 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2152 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2153 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2155 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2157 notethat ("PTR2op: pregs = pregs >> 2\n");
2158 $$ = PTR2OP (&$1, &$3, 3);
2160 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2162 notethat ("PTR2op: pregs = pregs >> 1\n");
2163 $$ = PTR2OP (&$1, &$3, 4);
2166 return yyerror ("Register mismatch");
2169 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2171 if (IS_UIMM ($5, 5))
2173 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2174 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2177 return yyerror ("Register mismatch");
2179 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2181 if (IS_UIMM ($5, 5))
2183 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2184 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2185 $6.s0, HL2 ($1, $3));
2188 return yyerror ("Register or modifier mismatch");
2192 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2194 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2199 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2200 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2204 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2205 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2209 return yyerror ("Register mismatch");
2212 | HALF_REG ASSIGN ONES REG
2214 if (IS_DREG_L ($1) && IS_DREG ($4))
2216 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2217 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2220 return yyerror ("Register mismatch");
2223 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2225 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2227 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2228 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2231 return yyerror ("Register mismatch");
2234 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2237 && $7.regno == REG_A0
2238 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2240 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2241 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2244 return yyerror ("Register mismatch");
2247 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2250 && $7.regno == REG_A0
2251 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2253 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2254 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2257 return yyerror ("Register mismatch");
2260 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2262 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2264 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2265 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2268 return yyerror ("Register mismatch");
2271 | a_assign ROT REG_A BY HALF_REG
2273 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2275 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2276 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2279 return yyerror ("Register mismatch");
2282 | REG ASSIGN ROT REG BY HALF_REG
2284 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2286 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2287 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2290 return yyerror ("Register mismatch");
2293 | a_assign ROT REG_A BY expr
2297 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2298 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2301 return yyerror ("Register mismatch");
2304 | REG ASSIGN ROT REG BY expr
2306 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2308 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2311 return yyerror ("Register mismatch");
2314 | HALF_REG ASSIGN SIGNBITS REG_A
2318 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2319 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2322 return yyerror ("Register mismatch");
2325 | HALF_REG ASSIGN SIGNBITS REG
2327 if (IS_DREG_L ($1) && IS_DREG ($4))
2329 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2330 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2333 return yyerror ("Register mismatch");
2336 | HALF_REG ASSIGN SIGNBITS HALF_REG
2340 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2341 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2344 return yyerror ("Register mismatch");
2347 /* The ASR bit is just inverted here. */
2348 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2350 if (IS_DREG_L ($1) && IS_DREG ($5))
2352 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2353 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2356 return yyerror ("Register mismatch");
2359 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2361 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2363 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2364 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2367 return yyerror ("Register mismatch");
2370 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2372 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2374 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2375 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2378 return yyerror ("Register mismatch");
2381 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2383 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2385 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2386 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2389 return yyerror ("Dregs expected");
2393 /* LOGI2op: BITCLR (dregs, uimm5). */
2394 | BITCLR LPAREN REG COMMA expr RPAREN
2396 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2398 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2399 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2402 return yyerror ("Register mismatch");
2405 /* LOGI2op: BITSET (dregs, uimm5). */
2406 | BITSET LPAREN REG COMMA expr RPAREN
2408 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2410 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2411 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2414 return yyerror ("Register mismatch");
2417 /* LOGI2op: BITTGL (dregs, uimm5). */
2418 | BITTGL LPAREN REG COMMA expr RPAREN
2420 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2422 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2423 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2426 return yyerror ("Register mismatch");
2429 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2431 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2433 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2434 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2437 return yyerror ("Register mismatch or value error");
2440 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2442 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2444 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2445 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2448 return yyerror ("Register mismatch or value error");
2451 | IF BANG CCREG REG ASSIGN REG
2453 if ((IS_DREG ($4) || IS_PREG ($4))
2454 && (IS_DREG ($6) || IS_PREG ($6)))
2456 notethat ("ccMV: IF ! CC gregs = gregs\n");
2457 $$ = CCMV (&$6, &$4, 0);
2460 return yyerror ("Register mismatch");
2463 | IF CCREG REG ASSIGN REG
2465 if ((IS_DREG ($5) || IS_PREG ($5))
2466 && (IS_DREG ($3) || IS_PREG ($3)))
2468 notethat ("ccMV: IF CC gregs = gregs\n");
2469 $$ = CCMV (&$5, &$3, 1);
2472 return yyerror ("Register mismatch");
2475 | IF BANG CCREG JUMP expr
2477 if (IS_PCREL10 ($5))
2479 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2480 $$ = BRCC (0, 0, $5);
2483 return yyerror ("Bad jump offset");
2486 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2488 if (IS_PCREL10 ($5))
2490 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2491 $$ = BRCC (0, 1, $5);
2494 return yyerror ("Bad jump offset");
2497 | IF CCREG JUMP expr
2499 if (IS_PCREL10 ($4))
2501 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2502 $$ = BRCC (1, 0, $4);
2505 return yyerror ("Bad jump offset");
2508 | IF CCREG JUMP expr LPAREN BP RPAREN
2510 if (IS_PCREL10 ($4))
2512 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2513 $$ = BRCC (1, 1, $4);
2516 return yyerror ("Bad jump offset");
2520 notethat ("ProgCtrl: NOP\n");
2521 $$ = PROGCTRL (0, 0);
2526 notethat ("ProgCtrl: RTS\n");
2527 $$ = PROGCTRL (1, 0);
2532 notethat ("ProgCtrl: RTI\n");
2533 $$ = PROGCTRL (1, 1);
2538 notethat ("ProgCtrl: RTX\n");
2539 $$ = PROGCTRL (1, 2);
2544 notethat ("ProgCtrl: RTN\n");
2545 $$ = PROGCTRL (1, 3);
2550 notethat ("ProgCtrl: RTE\n");
2551 $$ = PROGCTRL (1, 4);
2556 notethat ("ProgCtrl: IDLE\n");
2557 $$ = PROGCTRL (2, 0);
2562 notethat ("ProgCtrl: CSYNC\n");
2563 $$ = PROGCTRL (2, 3);
2568 notethat ("ProgCtrl: SSYNC\n");
2569 $$ = PROGCTRL (2, 4);
2574 notethat ("ProgCtrl: EMUEXCPT\n");
2575 $$ = PROGCTRL (2, 5);
2582 notethat ("ProgCtrl: CLI dregs\n");
2583 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2586 return yyerror ("Dreg expected for CLI");
2593 notethat ("ProgCtrl: STI dregs\n");
2594 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2597 return yyerror ("Dreg expected for STI");
2600 | JUMP LPAREN REG RPAREN
2604 notethat ("ProgCtrl: JUMP (pregs )\n");
2605 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2608 return yyerror ("Bad register for indirect jump");
2611 | CALL LPAREN REG RPAREN
2615 notethat ("ProgCtrl: CALL (pregs )\n");
2616 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2619 return yyerror ("Bad register for indirect call");
2622 | CALL LPAREN PC PLUS REG RPAREN
2626 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2627 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2630 return yyerror ("Bad register for indirect call");
2633 | JUMP LPAREN PC PLUS REG RPAREN
2637 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2638 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2641 return yyerror ("Bad register for indirect jump");
2646 if (IS_UIMM ($2, 4))
2648 notethat ("ProgCtrl: RAISE uimm4\n");
2649 $$ = PROGCTRL (9, uimm4 ($2));
2652 return yyerror ("Bad value for RAISE");
2657 notethat ("ProgCtrl: EMUEXCPT\n");
2658 $$ = PROGCTRL (10, uimm4 ($2));
2661 | TESTSET LPAREN REG RPAREN
2665 notethat ("ProgCtrl: TESTSET (pregs )\n");
2666 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2669 return yyerror ("Preg expected");
2674 if (IS_PCREL12 ($2))
2676 notethat ("UJUMP: JUMP pcrel12\n");
2680 return yyerror ("Bad value for relative jump");
2685 if (IS_PCREL12 ($2))
2687 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2691 return yyerror ("Bad value for relative jump");
2696 if (IS_PCREL24 ($2))
2698 notethat ("CALLa: jump.l pcrel24\n");
2702 return yyerror ("Bad value for long jump");
2707 if (IS_PCREL24 ($2))
2709 notethat ("CALLa: jump.l pcrel24\n");
2713 return yyerror ("Bad value for long jump");
2718 if (IS_PCREL24 ($2))
2720 notethat ("CALLa: CALL pcrel25m2\n");
2724 return yyerror ("Bad call address");
2728 if (IS_PCREL24 ($2))
2730 notethat ("CALLa: CALL pcrel25m2\n");
2734 return yyerror ("Bad call address");
2738 /* ALU2op: DIVQ (dregs, dregs). */
2739 | DIVQ LPAREN REG COMMA REG RPAREN
2741 if (IS_DREG ($3) && IS_DREG ($5))
2742 $$ = ALU2OP (&$3, &$5, 8);
2744 return yyerror ("Bad registers for DIVQ");
2747 | DIVS LPAREN REG COMMA REG RPAREN
2749 if (IS_DREG ($3) && IS_DREG ($5))
2750 $$ = ALU2OP (&$3, &$5, 9);
2752 return yyerror ("Bad registers for DIVS");
2755 | REG ASSIGN MINUS REG vsmod
2757 if (IS_DREG ($1) && IS_DREG ($4))
2759 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2761 notethat ("ALU2op: dregs = - dregs\n");
2762 $$ = ALU2OP (&$1, &$4, 14);
2764 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2766 notethat ("dsp32alu: dregs = - dregs (.)\n");
2767 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2771 notethat ("dsp32alu: dregs = - dregs (.)\n");
2772 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2776 return yyerror ("Dregs expected");
2779 | REG ASSIGN TILDA REG
2781 if (IS_DREG ($1) && IS_DREG ($4))
2783 notethat ("ALU2op: dregs = ~dregs\n");
2784 $$ = ALU2OP (&$1, &$4, 15);
2787 return yyerror ("Dregs expected");
2790 | REG _GREATER_GREATER_ASSIGN REG
2792 if (IS_DREG ($1) && IS_DREG ($3))
2794 notethat ("ALU2op: dregs >>= dregs\n");
2795 $$ = ALU2OP (&$1, &$3, 1);
2798 return yyerror ("Dregs expected");
2801 | REG _GREATER_GREATER_ASSIGN expr
2803 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2805 notethat ("LOGI2op: dregs >>= uimm5\n");
2806 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2809 return yyerror ("Dregs expected or value error");
2812 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2814 if (IS_DREG ($1) && IS_DREG ($3))
2816 notethat ("ALU2op: dregs >>>= dregs\n");
2817 $$ = ALU2OP (&$1, &$3, 0);
2820 return yyerror ("Dregs expected");
2823 | REG _LESS_LESS_ASSIGN REG
2825 if (IS_DREG ($1) && IS_DREG ($3))
2827 notethat ("ALU2op: dregs <<= dregs\n");
2828 $$ = ALU2OP (&$1, &$3, 2);
2831 return yyerror ("Dregs expected");
2834 | REG _LESS_LESS_ASSIGN expr
2836 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2838 notethat ("LOGI2op: dregs <<= uimm5\n");
2839 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2842 return yyerror ("Dregs expected or const value error");
2846 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2848 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2850 notethat ("LOGI2op: dregs >>>= uimm5\n");
2851 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2854 return yyerror ("Dregs expected");
2857 /* Cache Control. */
2859 | FLUSH LBRACK REG RBRACK
2861 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2863 $$ = CACTRL (&$3, 0, 2);
2865 return yyerror ("Bad register(s) for FLUSH");
2868 | FLUSH reg_with_postinc
2872 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2873 $$ = CACTRL (&$2, 1, 2);
2876 return yyerror ("Bad register(s) for FLUSH");
2879 | FLUSHINV LBRACK REG RBRACK
2883 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2884 $$ = CACTRL (&$3, 0, 1);
2887 return yyerror ("Bad register(s) for FLUSH");
2890 | FLUSHINV reg_with_postinc
2894 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2895 $$ = CACTRL (&$2, 1, 1);
2898 return yyerror ("Bad register(s) for FLUSH");
2901 /* CaCTRL: IFLUSH [pregs]. */
2902 | IFLUSH LBRACK REG RBRACK
2906 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2907 $$ = CACTRL (&$3, 0, 3);
2910 return yyerror ("Bad register(s) for FLUSH");
2913 | IFLUSH reg_with_postinc
2917 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2918 $$ = CACTRL (&$2, 1, 3);
2921 return yyerror ("Bad register(s) for FLUSH");
2924 | PREFETCH LBRACK REG RBRACK
2928 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2929 $$ = CACTRL (&$3, 0, 0);
2932 return yyerror ("Bad register(s) for PREFETCH");
2935 | PREFETCH reg_with_postinc
2939 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2940 $$ = CACTRL (&$2, 1, 0);
2943 return yyerror ("Bad register(s) for PREFETCH");
2947 /* LDST: B [ pregs <post_op> ] = dregs. */
2949 | B LBRACK REG post_op RBRACK ASSIGN REG
2952 return yyerror ("Dreg expected for source operand");
2954 return yyerror ("Preg expected in address");
2956 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2957 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2960 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2961 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2963 Expr_Node *tmp = $5;
2966 return yyerror ("Dreg expected for source operand");
2968 return yyerror ("Preg expected in address");
2971 return yyerror ("Plain symbol used as offset");
2974 tmp = unary (Expr_Op_Type_NEG, tmp);
2976 if (in_range_p (tmp, -32768, 32767, 0))
2978 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2979 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2982 return yyerror ("Displacement out of range");
2986 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2987 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2989 Expr_Node *tmp = $5;
2992 return yyerror ("Dreg expected for source operand");
2994 return yyerror ("Preg expected in address");
2997 tmp = unary (Expr_Op_Type_NEG, tmp);
3000 return yyerror ("Plain symbol used as offset");
3002 if (in_range_p (tmp, 0, 30, 1))
3004 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3005 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3007 else if (in_range_p (tmp, -65536, 65535, 1))
3009 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3010 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3013 return yyerror ("Displacement out of range");
3016 /* LDST: W [ pregs <post_op> ] = dregs. */
3017 | W LBRACK REG post_op RBRACK ASSIGN REG
3020 return yyerror ("Dreg expected for source operand");
3022 return yyerror ("Preg expected in address");
3024 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3025 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3028 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3031 return yyerror ("Dreg expected for source operand");
3034 if (!IS_IREG ($3) && !IS_PREG ($3))
3035 return yyerror ("Ireg or Preg expected in address");
3037 else if (!IS_IREG ($3))
3038 return yyerror ("Ireg expected in address");
3042 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3043 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3047 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3048 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3052 /* LDSTiiFP: [ FP - const ] = dpregs. */
3053 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3055 Expr_Node *tmp = $4;
3056 int ispreg = IS_PREG ($7);
3059 return yyerror ("Preg expected in address");
3061 if (!IS_DREG ($7) && !ispreg)
3062 return yyerror ("Preg expected for source operand");
3065 tmp = unary (Expr_Op_Type_NEG, tmp);
3068 return yyerror ("Plain symbol used as offset");
3070 if (in_range_p (tmp, 0, 63, 3))
3072 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3073 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3075 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3077 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3078 tmp = unary (Expr_Op_Type_NEG, tmp);
3079 $$ = LDSTIIFP (tmp, &$7, 1);
3081 else if (in_range_p (tmp, -131072, 131071, 3))
3083 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3084 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3087 return yyerror ("Displacement out of range");
3090 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3092 Expr_Node *tmp = $7;
3094 return yyerror ("Dreg expected for destination operand");
3096 return yyerror ("Preg expected in address");
3099 tmp = unary (Expr_Op_Type_NEG, tmp);
3102 return yyerror ("Plain symbol used as offset");
3104 if (in_range_p (tmp, 0, 30, 1))
3106 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3107 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3109 else if (in_range_p (tmp, -65536, 65535, 1))
3111 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3112 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3115 return yyerror ("Displacement out of range");
3118 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3121 return yyerror ("Dreg expected for source operand");
3124 if (!IS_IREG ($5) && !IS_PREG ($5))
3125 return yyerror ("Ireg or Preg expected in address");
3127 else if (!IS_IREG ($5))
3128 return yyerror ("Ireg expected in address");
3132 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3133 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3137 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3138 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3143 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3146 return yyerror ("Dreg expected for destination operand");
3148 return yyerror ("Preg expected in address");
3150 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3151 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3154 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3157 return yyerror ("Dreg expected for destination operand");
3158 if (!IS_PREG ($5) || !IS_PREG ($7))
3159 return yyerror ("Preg expected in address");
3161 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3162 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3165 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3168 return yyerror ("Dreg expected for destination operand");
3169 if (!IS_PREG ($5) || !IS_PREG ($7))
3170 return yyerror ("Preg expected in address");
3172 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3173 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3176 | LBRACK REG post_op RBRACK ASSIGN REG
3178 if (!IS_IREG ($2) && !IS_PREG ($2))
3179 return yyerror ("Ireg or Preg expected in address");
3180 else if (IS_IREG ($2) && !IS_DREG ($6))
3181 return yyerror ("Dreg expected for source operand");
3182 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3183 return yyerror ("Dreg or Preg expected for source operand");
3187 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3188 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3190 else if (IS_DREG ($6))
3192 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3193 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3197 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3198 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3202 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3205 return yyerror ("Dreg expected for source operand");
3207 if (IS_IREG ($2) && IS_MREG ($4))
3209 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3210 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3212 else if (IS_PREG ($2) && IS_PREG ($4))
3214 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3215 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3218 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3221 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3224 return yyerror ("Dreg expected for source operand");
3226 if (IS_PREG ($3) && IS_PREG ($5))
3228 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3229 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3232 return yyerror ("Preg ++ Preg expected in address");
3235 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3237 Expr_Node *tmp = $7;
3239 return yyerror ("Dreg expected for destination operand");
3241 return yyerror ("Preg expected in address");
3244 tmp = unary (Expr_Op_Type_NEG, tmp);
3247 return yyerror ("Plain symbol used as offset");
3249 if (in_range_p (tmp, -32768, 32767, 0))
3251 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3253 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3256 return yyerror ("Displacement out of range");
3259 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3262 return yyerror ("Dreg expected for destination operand");
3264 return yyerror ("Preg expected in address");
3266 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3268 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3271 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3274 return yyerror ("Dreg expected for destination operand");
3276 if (IS_IREG ($4) && IS_MREG ($6))
3278 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3279 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3281 else if (IS_PREG ($4) && IS_PREG ($6))
3283 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3284 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3287 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3290 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3292 Expr_Node *tmp = $6;
3293 int ispreg = IS_PREG ($1);
3294 int isgot = IS_RELOC($6);
3297 return yyerror ("Preg expected in address");
3299 if (!IS_DREG ($1) && !ispreg)
3300 return yyerror ("Dreg or Preg expected for destination operand");
3302 if (tmp->type == Expr_Node_Reloc
3303 && strcmp (tmp->value.s_value,
3304 "_current_shared_library_p5_offset_") != 0)
3305 return yyerror ("Plain symbol used as offset");
3308 tmp = unary (Expr_Op_Type_NEG, tmp);
3312 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3313 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3315 else if (in_range_p (tmp, 0, 63, 3))
3317 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3318 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3320 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3322 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3323 tmp = unary (Expr_Op_Type_NEG, tmp);
3324 $$ = LDSTIIFP (tmp, &$1, 0);
3326 else if (in_range_p (tmp, -131072, 131071, 3))
3328 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3329 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3333 return yyerror ("Displacement out of range");
3336 | REG ASSIGN LBRACK REG post_op RBRACK
3338 if (!IS_IREG ($4) && !IS_PREG ($4))
3339 return yyerror ("Ireg or Preg expected in address");
3340 else if (IS_IREG ($4) && !IS_DREG ($1))
3341 return yyerror ("Dreg expected in destination operand");
3342 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3343 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3344 return yyerror ("Dreg or Preg expected in destination operand");
3348 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3349 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3351 else if (IS_DREG ($1))
3353 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3354 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3356 else if (IS_PREG ($1))
3358 if (REG_SAME ($1, $4) && $5.x0 != 2)
3359 return yyerror ("Pregs can't be same");
3361 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3362 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3366 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3367 $$ = PUSHPOPREG (&$1, 0);
3372 /* PushPopMultiple. */
3373 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3375 if ($1.regno != REG_SP)
3376 yyerror ("Stack Pointer expected");
3377 if ($4.regno == REG_R7
3378 && IN_RANGE ($6, 0, 7)
3379 && $8.regno == REG_P5
3380 && IN_RANGE ($10, 0, 5))
3382 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3383 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3386 return yyerror ("Bad register for PushPopMultiple");
3389 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3391 if ($1.regno != REG_SP)
3392 yyerror ("Stack Pointer expected");
3394 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3396 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3397 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3399 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3401 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3402 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3405 return yyerror ("Bad register for PushPopMultiple");
3408 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3410 if ($11.regno != REG_SP)
3411 yyerror ("Stack Pointer expected");
3412 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3413 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3415 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3416 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3419 return yyerror ("Bad register range for PushPopMultiple");
3422 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3424 if ($7.regno != REG_SP)
3425 yyerror ("Stack Pointer expected");
3427 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3429 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3430 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3432 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3434 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3435 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3438 return yyerror ("Bad register range for PushPopMultiple");
3441 | reg_with_predec ASSIGN REG
3443 if ($1.regno != REG_SP)
3444 yyerror ("Stack Pointer expected");
3448 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3449 $$ = PUSHPOPREG (&$3, 1);
3452 return yyerror ("Bad register for PushPopReg");
3459 if (IS_URANGE (16, $2, 0, 4))
3460 $$ = LINKAGE (0, uimm16s4 ($2));
3462 return yyerror ("Bad constant for LINK");
3467 notethat ("linkage: UNLINK\n");
3468 $$ = LINKAGE (1, 0);
3474 | LSETUP LPAREN expr COMMA expr RPAREN REG
3476 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3478 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3479 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3482 return yyerror ("Bad register or values for LSETUP");
3485 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3487 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3488 && IS_PREG ($9) && IS_CREG ($7))
3490 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3491 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3494 return yyerror ("Bad register or values for LSETUP");
3497 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3499 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3500 && IS_PREG ($9) && IS_CREG ($7)
3501 && EXPR_VALUE ($11) == 1)
3503 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3504 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3507 return yyerror ("Bad register or values for LSETUP");
3514 return yyerror ("Invalid expression in loop statement");
3516 return yyerror ("Invalid loop counter register");
3517 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3519 | LOOP expr REG ASSIGN REG
3521 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3523 notethat ("Loop: LOOP expr counters = pregs\n");
3524 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3527 return yyerror ("Bad register or values for LOOP");
3529 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3531 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3533 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3534 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3537 return yyerror ("Bad register or values for LOOP");
3544 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3546 bfin_loop_beginend ($2, 1);
3554 return yyerror ("Invalid expression in LOOP_END statement");
3556 bfin_loop_beginend ($2, 0);
3564 notethat ("psedoDEBUG: ABORT\n");
3565 $$ = bfin_gen_pseudodbg (3, 3, 0);
3570 notethat ("pseudoDEBUG: DBG\n");
3571 $$ = bfin_gen_pseudodbg (3, 7, 0);
3575 notethat ("pseudoDEBUG: DBG REG_A\n");
3576 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3580 notethat ("pseudoDEBUG: DBG allregs\n");
3581 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3584 | DBGCMPLX LPAREN REG RPAREN
3587 return yyerror ("Dregs expected");
3588 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3589 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3594 notethat ("psedoDEBUG: DBGHALT\n");
3595 $$ = bfin_gen_pseudodbg (3, 5, 0);
3600 notethat ("psedoDEBUG: HLT\n");
3601 $$ = bfin_gen_pseudodbg (3, 4, 0);
3604 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3606 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3607 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3610 | DBGAH LPAREN REG COMMA expr RPAREN
3612 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3613 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3616 | DBGAL LPAREN REG COMMA expr RPAREN
3618 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3619 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3624 if (!IS_UIMM ($2, 8))
3625 return yyerror ("Constant out of range");
3626 notethat ("psedodbg_assert: OUTC uimm8\n");
3627 $$ = bfin_gen_pseudochr (uimm8 ($2));
3633 return yyerror ("Dregs expected");
3634 notethat ("psedodbg_assert: OUTC dreg\n");
3635 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3642 /* Register rules. */
3644 REG_A: REG_A_DOUBLE_ZERO
3662 | LPAREN M COMMA MMOD RPAREN
3667 | LPAREN MMOD COMMA M RPAREN
3672 | LPAREN MMOD RPAREN
3684 asr_asl: LPAREN ASL RPAREN
3765 | LPAREN asr_asl_0 RPAREN
3777 | LPAREN asr_asl_0 COMMA sco RPAREN
3783 | LPAREN sco COMMA asr_asl_0 RPAREN
3843 | LPAREN V COMMA S RPAREN
3848 | LPAREN S COMMA V RPAREN
3910 | LPAREN MMOD RPAREN
3913 return yyerror ("Bad modifier");
3917 | LPAREN MMOD COMMA R RPAREN
3920 return yyerror ("Bad modifier");
3924 | LPAREN R COMMA MMOD RPAREN
3927 return yyerror ("Bad modifier");
3954 | LPAREN MMOD RPAREN
3959 return yyerror ("Only (W32) allowed");
3967 | LPAREN MMOD RPAREN
3972 return yyerror ("(IU) expected");
3976 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3982 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4034 $$.r0 = 1; /* HL. */
4037 $$.aop = 0; /* aop. */
4042 $$.r0 = 1; /* HL. */
4045 $$.aop = 1; /* aop. */
4048 | LPAREN RNDL RPAREN
4050 $$.r0 = 0; /* HL. */
4053 $$.aop = 0; /* aop. */
4058 $$.r0 = 0; /* HL. */
4064 | LPAREN RNDH COMMA R RPAREN
4066 $$.r0 = 1; /* HL. */
4069 $$.aop = 0; /* aop. */
4071 | LPAREN TH COMMA R RPAREN
4073 $$.r0 = 1; /* HL. */
4076 $$.aop = 1; /* aop. */
4078 | LPAREN RNDL COMMA R RPAREN
4080 $$.r0 = 0; /* HL. */
4083 $$.aop = 0; /* aop. */
4086 | LPAREN TL COMMA R RPAREN
4088 $$.r0 = 0; /* HL. */
4091 $$.aop = 1; /* aop. */
4099 $$.x0 = 0; /* HL. */
4104 $$.x0 = 1; /* HL. */
4106 | LPAREN LO COMMA R RPAREN
4109 $$.x0 = 0; /* HL. */
4111 | LPAREN HI COMMA R RPAREN
4114 $$.x0 = 1; /* HL. */
4132 /* Assignments, Macfuncs. */
4158 if (IS_A1 ($3) && IS_EVEN ($1))
4159 return yyerror ("Cannot move A1 to even register");
4160 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4161 return yyerror ("Cannot move A0 to odd register");
4177 | REG ASSIGN LPAREN a_macfunc RPAREN
4179 if ($4.n && IS_EVEN ($1))
4180 return yyerror ("Cannot move A1 to even register");
4181 else if (!$4.n && !IS_EVEN ($1))
4182 return yyerror ("Cannot move A0 to odd register");
4190 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4192 if ($4.n && !IS_H ($1))
4193 return yyerror ("Cannot move A1 to low half of register");
4194 else if (!$4.n && IS_H ($1))
4195 return yyerror ("Cannot move A0 to high half of register");
4203 | HALF_REG ASSIGN REG_A
4205 if (IS_A1 ($3) && !IS_H ($1))
4206 return yyerror ("Cannot move A1 to low half of register");
4207 else if (!IS_A1 ($3) && IS_H ($1))
4208 return yyerror ("Cannot move A0 to high half of register");
4221 a_assign multiply_halfregs
4228 | a_plusassign multiply_halfregs
4235 | a_minusassign multiply_halfregs
4245 HALF_REG STAR HALF_REG
4247 if (IS_DREG ($1) && IS_DREG ($3))
4253 return yyerror ("Dregs expected");
4277 CCREG cc_op STATUS_REG
4289 | STATUS_REG cc_op CCREG
4303 /* Expressions and Symbols. */
4307 Expr_Node_Value val;
4308 val.s_value = S_GET_NAME($1);
4309 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4315 { $$ = BFD_RELOC_BFIN_GOT; }
4317 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4319 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4322 got: symbol AT any_gotrel
4324 Expr_Node_Value val;
4326 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4349 Expr_Node_Value val;
4351 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4357 | LPAREN expr_1 RPAREN
4363 $$ = unary (Expr_Op_Type_COMP, $2);
4365 | MINUS expr_1 %prec TILDA
4367 $$ = unary (Expr_Op_Type_NEG, $2);
4377 expr_1: expr_1 STAR expr_1
4379 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4381 | expr_1 SLASH expr_1
4383 $$ = binary (Expr_Op_Type_Div, $1, $3);
4385 | expr_1 PERCENT expr_1
4387 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4389 | expr_1 PLUS expr_1
4391 $$ = binary (Expr_Op_Type_Add, $1, $3);
4393 | expr_1 MINUS expr_1
4395 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4397 | expr_1 LESS_LESS expr_1
4399 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4401 | expr_1 GREATER_GREATER expr_1
4403 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4405 | expr_1 AMPERSAND expr_1
4407 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4409 | expr_1 CARET expr_1
4411 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4415 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4427 mkexpr (int x, SYMBOL_T s)
4429 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4436 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4438 int umax = (1 << sz) - 1;
4439 int min = -1 << (sz - 1);
4440 int max = (1 << (sz - 1)) - 1;
4442 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4446 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4457 if (v >= min && v <= max) return 1;
4460 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4464 if (v <= umax && v >= 0)
4467 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4472 /* Return the expression structure that allows symbol operations.
4473 If the left and right children are constants, do the operation. */
4475 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4477 Expr_Node_Value val;
4479 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4483 case Expr_Op_Type_Add:
4484 x->value.i_value += y->value.i_value;
4486 case Expr_Op_Type_Sub:
4487 x->value.i_value -= y->value.i_value;
4489 case Expr_Op_Type_Mult:
4490 x->value.i_value *= y->value.i_value;
4492 case Expr_Op_Type_Div:
4493 if (y->value.i_value == 0)
4494 error ("Illegal Expression: Division by zero.");
4496 x->value.i_value /= y->value.i_value;
4498 case Expr_Op_Type_Mod:
4499 x->value.i_value %= y->value.i_value;
4501 case Expr_Op_Type_Lshift:
4502 x->value.i_value <<= y->value.i_value;
4504 case Expr_Op_Type_Rshift:
4505 x->value.i_value >>= y->value.i_value;
4507 case Expr_Op_Type_BAND:
4508 x->value.i_value &= y->value.i_value;
4510 case Expr_Op_Type_BOR:
4511 x->value.i_value |= y->value.i_value;
4513 case Expr_Op_Type_BXOR:
4514 x->value.i_value ^= y->value.i_value;
4516 case Expr_Op_Type_LAND:
4517 x->value.i_value = x->value.i_value && y->value.i_value;
4519 case Expr_Op_Type_LOR:
4520 x->value.i_value = x->value.i_value || y->value.i_value;
4524 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4528 /* Canonicalize order to EXPR OP CONSTANT. */
4529 if (x->type == Expr_Node_Constant)
4535 /* Canonicalize subtraction of const to addition of negated const. */
4536 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4538 op = Expr_Op_Type_Add;
4539 y->value.i_value = -y->value.i_value;
4541 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4542 && x->Right_Child->type == Expr_Node_Constant)
4544 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4546 x->Right_Child->value.i_value += y->value.i_value;
4551 /* Create a new expression structure. */
4553 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4557 unary (Expr_Op_Type op, Expr_Node *x)
4559 if (x->type == Expr_Node_Constant)
4563 case Expr_Op_Type_NEG:
4564 x->value.i_value = -x->value.i_value;
4566 case Expr_Op_Type_COMP:
4567 x->value.i_value = ~x->value.i_value;
4570 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4576 /* Create a new expression structure. */
4577 Expr_Node_Value val;
4579 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4583 int debug_codeselection = 0;
4585 notethat (char *format, ...)
4588 va_start (ap, format);
4589 if (debug_codeselection)
4591 vfprintf (errorf, format, ap);
4597 main (int argc, char **argv)