1 /* bfin-parse.y ADI Blackfin parser
2 Copyright (C) 2005-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
25 #include "bfin-aux.h" /* Opcode generating auxiliaries. */
27 #include "elf/common.h"
30 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
31 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
33 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
34 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
37 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
38 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
41 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
42 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
44 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
45 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
47 #define LDIMMHALF_R(reg, h, s, z, hword) \
48 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
50 #define LDIMMHALF_R5(reg, h, s, z, hword) \
51 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
53 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
54 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
56 #define LDST(ptr, reg, aop, sz, z, w) \
57 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
59 #define LDSTII(ptr, reg, offset, w, op) \
60 bfin_gen_ldstii (ptr, reg, offset, w, op)
62 #define DSPLDST(i, m, reg, aop, w) \
63 bfin_gen_dspldst (i, reg, aop, w, m)
65 #define LDSTPMOD(ptr, reg, idx, aop, w) \
66 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
68 #define LDSTIIFP(offset, reg, w) \
69 bfin_gen_ldstiifp (reg, offset, w)
71 #define LOGI2OP(dst, src, opc) \
72 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
74 #define ALU2OP(dst, src, opc) \
75 bfin_gen_alu2op (dst, src, opc)
77 #define BRCC(t, b, offset) \
78 bfin_gen_brcc (t, b, offset)
80 #define UJUMP(offset) \
81 bfin_gen_ujump (offset)
83 #define PROGCTRL(prgfunc, poprnd) \
84 bfin_gen_progctrl (prgfunc, poprnd)
86 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
87 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
89 #define PUSHPOPREG(reg, w) \
90 bfin_gen_pushpopreg (reg, w)
92 #define CALLA(addr, s) \
93 bfin_gen_calla (addr, s)
95 #define LINKAGE(r, framesize) \
96 bfin_gen_linkage (r, framesize)
98 #define COMPI2OPD(dst, src, op) \
99 bfin_gen_compi2opd (dst, src, op)
101 #define COMPI2OPP(dst, src, op) \
102 bfin_gen_compi2opp (dst, src, op)
104 #define DAGMODIK(i, op) \
105 bfin_gen_dagmodik (i, op)
107 #define DAGMODIM(i, m, op, br) \
108 bfin_gen_dagmodim (i, m, op, br)
110 #define COMP3OP(dst, src0, src1, opc) \
111 bfin_gen_comp3op (src0, src1, dst, opc)
113 #define PTR2OP(dst, src, opc) \
114 bfin_gen_ptr2op (dst, src, opc)
116 #define CCFLAG(x, y, opc, i, g) \
117 bfin_gen_ccflag (x, y, opc, i, g)
119 #define CCMV(src, dst, t) \
120 bfin_gen_ccmv (src, dst, t)
122 #define CACTRL(reg, a, op) \
123 bfin_gen_cactrl (reg, a, op)
125 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
126 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
128 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
129 #define IS_RANGE(bits, expr, sign, mul) \
130 value_match(expr, bits, sign, mul, 1)
131 #define IS_URANGE(bits, expr, sign, mul) \
132 value_match(expr, bits, sign, mul, 0)
133 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
134 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
135 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
136 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
138 #define IS_PCREL4(expr) \
139 (value_match (expr, 4, 0, 2, 0))
141 #define IS_LPPCREL10(expr) \
142 (value_match (expr, 10, 0, 2, 0))
144 #define IS_PCREL10(expr) \
145 (value_match (expr, 10, 0, 2, 1))
147 #define IS_PCREL12(expr) \
148 (value_match (expr, 12, 0, 2, 1))
150 #define IS_PCREL24(expr) \
151 (value_match (expr, 24, 0, 2, 1))
154 static int value_match (Expr_Node *, int, int, int, int);
159 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
160 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
162 static void notethat (char *, ...);
164 char *current_inputline;
166 int yyerror (char *);
168 /* Used to set SRCx fields to all 1s as described in the PRM. */
169 static Register reg7 = {REG_R7, 0};
171 void error (char *format, ...)
174 static char buffer[2000];
176 va_start (ap, format);
177 vsprintf (buffer, format, ap);
180 as_bad ("%s", buffer);
189 else if (yytext[0] != ';')
190 error ("%s. Input text was %s.", msg, yytext);
198 in_range_p (Expr_Node *exp, int from, int to, unsigned int mask)
200 int val = EXPR_VALUE (exp);
201 if (exp->type != Expr_Node_Constant)
203 if (val < from || val > to)
205 return (val & mask) == 0;
208 extern int yylex (void);
210 #define imm3(x) EXPR_VALUE (x)
211 #define imm4(x) EXPR_VALUE (x)
212 #define uimm4(x) EXPR_VALUE (x)
213 #define imm5(x) EXPR_VALUE (x)
214 #define uimm5(x) EXPR_VALUE (x)
215 #define imm6(x) EXPR_VALUE (x)
216 #define imm7(x) EXPR_VALUE (x)
217 #define uimm8(x) EXPR_VALUE (x)
218 #define imm16(x) EXPR_VALUE (x)
219 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
220 #define uimm16(x) EXPR_VALUE (x)
222 /* Return true if a value is inside a range. */
223 #define IN_RANGE(x, low, high) \
224 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
226 /* Auxiliary functions. */
229 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
231 if (!IS_DREG (*reg1))
233 yyerror ("Dregs expected");
237 if (reg1->regno != 1 && reg1->regno != 3)
239 yyerror ("Bad register pair");
243 if (imm7 (reg2) != reg1->regno - 1)
245 yyerror ("Bad register pair");
254 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
256 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
257 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
258 return yyerror ("Source multiplication register mismatch");
264 /* Check mac option. */
267 check_macfunc_option (Macfunc *a, Opt_mode *opt)
269 /* Default option is always valid. */
273 if ((a->w == 1 && a->P == 1
274 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
275 && opt->mod != M_S2RND && opt->mod != M_ISS2)
276 || (a->w == 1 && a->P == 0
277 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
278 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
279 && opt->mod != M_ISS2 && opt->mod != M_IH)
280 || (a->w == 0 && a->P == 0
281 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32))
287 /* Check (vector) mac funcs and ops. */
290 check_macfuncs (Macfunc *aa, Opt_mode *opa,
291 Macfunc *ab, Opt_mode *opb)
293 /* Variables for swapping. */
297 /* The option mode should be put at the end of the second instruction
298 of the vector except M, which should follow MAC1 instruction. */
300 return yyerror ("Bad opt mode");
302 /* If a0macfunc comes before a1macfunc, swap them. */
306 /* (M) is not allowed here. */
308 return yyerror ("(M) not allowed with A0MAC");
310 return yyerror ("Vector AxMACs can't be same");
312 mtmp = *aa; *aa = *ab; *ab = mtmp;
313 otmp = *opa; *opa = *opb; *opb = otmp;
318 return yyerror ("(M) not allowed with A0MAC");
320 return yyerror ("Vector AxMACs can't be same");
323 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
324 assignment_or_macfuncs. */
325 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
326 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
328 if (check_multiply_halfregs (aa, ab) < 0)
333 /* Only one of the assign_macfuncs has a half reg multiply
334 Evil trick: Just 'OR' their source register codes:
335 We can do that, because we know they were initialized to 0
336 in the rules that don't use multiply_halfregs. */
337 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
338 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
341 if (aa->w == ab->w && aa->P != ab->P)
342 return yyerror ("Destination Dreg sizes (full or half) must match");
346 if (aa->P && (aa->dst.regno - ab->dst.regno) != 1)
347 return yyerror ("Destination Dregs (full) must differ by one");
348 if (!aa->P && aa->dst.regno != ab->dst.regno)
349 return yyerror ("Destination Dregs (half) must match");
352 /* Make sure mod flags get ORed, too. */
353 opb->mod |= opa->mod;
356 if (check_macfunc_option (aa, opb) < 0
357 && check_macfunc_option (ab, opb) < 0)
358 return yyerror ("bad option");
360 /* Make sure first macfunc has got both P flags ORed. */
368 is_group1 (INSTR_T x)
370 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
371 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
378 is_group2 (INSTR_T x)
380 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
381 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
382 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
383 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
384 || (x->value == 0x0000))
395 if ((x->value & 0xf000) == 0x8000)
397 int aop = ((x->value >> 9) & 0x3);
398 int w = ((x->value >> 11) & 0x1);
404 if (((x->value & 0xFF60) == 0x9E60) || /* dagMODim_0 */
405 ((x->value & 0xFFF0) == 0x9F60)) /* dagMODik_0 */
408 /* decode_dspLDST_0 */
409 if ((x->value & 0xFC00) == 0x9C00)
411 int w = ((x->value >> 9) & 0x1);
420 gen_multi_instr_1 (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
422 int mask1 = dsp32 ? insn_regmask (dsp32->value, dsp32->next->value) : 0;
423 int mask2 = dsp16_grp1 ? insn_regmask (dsp16_grp1->value, 0) : 0;
424 int mask3 = dsp16_grp2 ? insn_regmask (dsp16_grp2->value, 0) : 0;
426 if ((mask1 & mask2) || (mask1 & mask3) || (mask2 & mask3))
427 yyerror ("resource conflict in multi-issue instruction");
429 /* Anomaly 05000074 */
430 if (ENABLE_AC_05000074
431 && dsp32 != NULL && dsp16_grp1 != NULL
432 && (dsp32->value & 0xf780) == 0xc680
433 && ((dsp16_grp1->value & 0xfe40) == 0x9240
434 || (dsp16_grp1->value & 0xfe08) == 0xba08
435 || (dsp16_grp1->value & 0xfc00) == 0xbc00))
436 yyerror ("anomaly 05000074 - Multi-Issue Instruction with \
437 dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported");
439 if (is_store (dsp16_grp1) && is_store (dsp16_grp2))
440 yyerror ("Only one instruction in multi-issue instruction can be a store");
442 return bfin_gen_multi_instr (dsp32, dsp16_grp1, dsp16_grp2);
454 struct { int r0; int s0; int x0; int aop; } modcodes;
455 struct { int r0; } r0;
462 /* Vector Specific. */
463 %token BYTEOP16P BYTEOP16M
464 %token BYTEOP1P BYTEOP2P BYTEOP3P
465 %token BYTEUNPACK BYTEPACK
468 %token ALIGN8 ALIGN16 ALIGN24
470 %token EXTRACT DEPOSIT EXPADJ SEARCH
471 %token ONES SIGN SIGNBITS
479 %token CCREG BYTE_DREG
480 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
481 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
486 %token RTI RTS RTX RTN RTE
497 %token JUMP JUMP_DOT_S JUMP_DOT_L
504 %token NOT TILDA BANG
510 %token MINUS PLUS STAR SLASH
514 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
515 %token _MINUS_MINUS _PLUS_PLUS
517 /* Shift/rotate ops. */
518 %token SHIFT LSHIFT ASHIFT BXORSHIFT
519 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
521 %token LESS_LESS GREATER_GREATER
522 %token _GREATER_GREATER_GREATER
523 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
526 /* In place operators. */
527 %token ASSIGN _STAR_ASSIGN
528 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
529 %token _MINUS_ASSIGN _PLUS_ASSIGN
531 /* Assignments, comparisons. */
532 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
537 %token FLUSHINV FLUSH
538 %token IFLUSH PREFETCH
555 %token R RND RNDL RNDH RND12 RND20
560 %token BITTGL BITCLR BITSET BITTST BITMUX
563 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
565 /* Semantic auxiliaries. */
568 %token COLON SEMICOLON
569 %token RPAREN LPAREN LBRACK RBRACK
573 %token GOT GOT17M4 FUNCDESC_GOT17M4
583 %type <modcodes> byteop_mod
585 %type <reg> a_plusassign
586 %type <reg> a_minusassign
587 %type <macfunc> multiply_halfregs
588 %type <macfunc> assign_macfunc
589 %type <macfunc> a_macfunc
593 %type <modcodes> vsmod
594 %type <modcodes> ccstat
597 %type <reg> reg_with_postinc
598 %type <reg> reg_with_predec
602 %type <symbol> SYMBOL
605 %type <reg> BYTE_DREG
606 %type <reg> REG_A_DOUBLE_ZERO
607 %type <reg> REG_A_DOUBLE_ONE
609 %type <reg> STATUS_REG
613 %type <modcodes> smod
614 %type <modcodes> b3_op
615 %type <modcodes> rnd_op
616 %type <modcodes> post_op
618 %type <r0> iu_or_nothing
619 %type <r0> plus_minus
623 %type <modcodes> amod0
624 %type <modcodes> amod1
625 %type <modcodes> amod2
627 %type <r0> w32_or_nothing
631 %type <expr> got_or_expr
633 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
635 /* Precedence rules. */
639 %left LESS_LESS GREATER_GREATER
641 %left STAR SLASH PERCENT
652 if (insn == (INSTR_T) 0)
653 return NO_INSN_GENERATED;
654 else if (insn == (INSTR_T) - 1)
655 return SEMANTIC_ERROR;
657 return INSN_GENERATED;
662 /* Parallel instructions. */
663 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
665 if (($1->value & 0xf800) == 0xc000)
667 if (is_group1 ($3) && is_group2 ($5))
668 $$ = gen_multi_instr_1 ($1, $3, $5);
669 else if (is_group2 ($3) && is_group1 ($5))
670 $$ = gen_multi_instr_1 ($1, $5, $3);
672 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
674 else if (($3->value & 0xf800) == 0xc000)
676 if (is_group1 ($1) && is_group2 ($5))
677 $$ = gen_multi_instr_1 ($3, $1, $5);
678 else if (is_group2 ($1) && is_group1 ($5))
679 $$ = gen_multi_instr_1 ($3, $5, $1);
681 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
683 else if (($5->value & 0xf800) == 0xc000)
685 if (is_group1 ($1) && is_group2 ($3))
686 $$ = gen_multi_instr_1 ($5, $1, $3);
687 else if (is_group2 ($1) && is_group1 ($3))
688 $$ = gen_multi_instr_1 ($5, $3, $1);
690 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
693 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
696 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
698 if (($1->value & 0xf800) == 0xc000)
701 $$ = gen_multi_instr_1 ($1, $3, 0);
702 else if (is_group2 ($3))
703 $$ = gen_multi_instr_1 ($1, 0, $3);
705 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
707 else if (($3->value & 0xf800) == 0xc000)
710 $$ = gen_multi_instr_1 ($3, $1, 0);
711 else if (is_group2 ($1))
712 $$ = gen_multi_instr_1 ($3, 0, $1);
714 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
716 else if (is_group1 ($1) && is_group2 ($3))
717 $$ = gen_multi_instr_1 (0, $1, $3);
718 else if (is_group2 ($1) && is_group1 ($3))
719 $$ = gen_multi_instr_1 (0, $3, $1);
721 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
736 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
738 | assign_macfunc opt_mode
742 int h00, h10, h01, h11;
744 if (check_macfunc_option (&$1, &$2) < 0)
745 return yyerror ("bad option");
750 return yyerror ("(m) not allowed with a0 unit");
769 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
770 &$1.dst, op0, &$1.s0, &$1.s1, w0);
776 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
780 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
782 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
789 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
790 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
791 dst, $4.op, &$1.s0, &$1.s1, $4.w);
798 notethat ("dsp32alu: DISALGNEXCPT\n");
799 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
801 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
803 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
805 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
806 $$ = DSP32ALU (11, 0, 0, &$1, ®7, ®7, 0, 0, 0);
809 return yyerror ("Register mismatch");
811 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
813 if (!IS_A1 ($4) && IS_A1 ($5))
815 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
816 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, ®7, ®7, 0, 0, 1);
819 return yyerror ("Register mismatch");
821 | A_ZERO_DOT_H ASSIGN HALF_REG
823 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
824 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
826 | A_ONE_DOT_H ASSIGN HALF_REG
828 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
829 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
831 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
832 COLON expr COMMA REG COLON expr RPAREN aligndir
834 if (!IS_DREG ($2) || !IS_DREG ($4))
835 return yyerror ("Dregs expected");
836 else if (REG_SAME ($2, $4))
837 return yyerror ("Illegal dest register combination");
838 else if (!valid_dreg_pair (&$9, $11))
839 return yyerror ("Bad dreg pair");
840 else if (!valid_dreg_pair (&$13, $15))
841 return yyerror ("Bad dreg pair");
844 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (aligndir)\n");
845 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
849 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
850 REG COLON expr RPAREN aligndir
852 if (!IS_DREG ($2) || !IS_DREG ($4))
853 return yyerror ("Dregs expected");
854 else if (REG_SAME ($2, $4))
855 return yyerror ("Illegal dest register combination");
856 else if (!valid_dreg_pair (&$9, $11))
857 return yyerror ("Bad dreg pair");
858 else if (!valid_dreg_pair (&$13, $15))
859 return yyerror ("Bad dreg pair");
862 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
863 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
867 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
869 if (!IS_DREG ($2) || !IS_DREG ($4))
870 return yyerror ("Dregs expected");
871 else if (REG_SAME ($2, $4))
872 return yyerror ("Illegal dest register combination");
873 else if (!valid_dreg_pair (&$8, $10))
874 return yyerror ("Bad dreg pair");
877 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
878 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
881 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
883 if (REG_SAME ($2, $4))
884 return yyerror ("Illegal dest register combination");
886 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
888 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
889 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
892 return yyerror ("Register mismatch");
894 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
895 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
897 if (REG_SAME ($1, $7))
898 return yyerror ("Illegal dest register combination");
900 if (IS_DREG ($1) && IS_DREG ($7))
902 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
903 $$ = DSP32ALU (12, 0, &$1, &$7, ®7, ®7, 0, 0, 1);
906 return yyerror ("Register mismatch");
910 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
912 if (REG_SAME ($1, $7))
913 return yyerror ("Resource conflict in dest reg");
915 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
916 && IS_A1 ($9) && !IS_A1 ($11))
918 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
919 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 0);
922 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
923 && !IS_A1 ($9) && IS_A1 ($11))
925 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
926 $$ = DSP32ALU (17, 0, &$1, &$7, ®7, ®7, $12.s0, $12.x0, 1);
929 return yyerror ("Register mismatch");
932 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
935 return yyerror ("Operators must differ");
937 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
938 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
940 notethat ("dsp32alu: dregs = dregs + dregs,"
941 "dregs = dregs - dregs (amod1)\n");
942 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
945 return yyerror ("Register mismatch");
948 /* Bar Operations. */
950 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
952 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
953 return yyerror ("Differing source registers");
955 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
956 return yyerror ("Dregs expected");
958 if (REG_SAME ($1, $7))
959 return yyerror ("Resource conflict in dest reg");
961 if ($4.r0 == 1 && $10.r0 == 2)
963 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
964 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
966 else if ($4.r0 == 0 && $10.r0 == 3)
968 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
969 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
972 return yyerror ("Bar operand mismatch");
975 | REG ASSIGN ABS REG vmod
979 if (IS_DREG ($1) && IS_DREG ($4))
983 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
988 /* Vector version of ABS. */
989 notethat ("dsp32alu: dregs = ABS dregs\n");
992 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
995 return yyerror ("Dregs expected");
999 notethat ("dsp32alu: Ax = ABS Ax\n");
1000 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3));
1002 | A_ZERO_DOT_L ASSIGN HALF_REG
1006 notethat ("dsp32alu: A0.l = reg_half\n");
1007 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
1010 return yyerror ("A0.l = Rx.l expected");
1012 | A_ONE_DOT_L ASSIGN HALF_REG
1016 notethat ("dsp32alu: A1.l = reg_half\n");
1017 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
1020 return yyerror ("A1.l = Rx.l expected");
1023 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
1025 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1027 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
1028 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
1031 return yyerror ("Dregs expected");
1034 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
1037 return yyerror ("Dregs expected");
1038 else if (!valid_dreg_pair (&$5, $7))
1039 return yyerror ("Bad dreg pair");
1040 else if (!valid_dreg_pair (&$9, $11))
1041 return yyerror ("Bad dreg pair");
1044 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1045 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
1048 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1051 return yyerror ("Dregs expected");
1052 else if (!valid_dreg_pair (&$5, $7))
1053 return yyerror ("Bad dreg pair");
1054 else if (!valid_dreg_pair (&$9, $11))
1055 return yyerror ("Bad dreg pair");
1058 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
1059 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1063 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1067 return yyerror ("Dregs expected");
1068 else if (!valid_dreg_pair (&$5, $7))
1069 return yyerror ("Bad dreg pair");
1070 else if (!valid_dreg_pair (&$9, $11))
1071 return yyerror ("Bad dreg pair");
1074 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1075 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1079 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1083 return yyerror ("Dregs expected");
1084 else if (!valid_dreg_pair (&$5, $7))
1085 return yyerror ("Bad dreg pair");
1086 else if (!valid_dreg_pair (&$9, $11))
1087 return yyerror ("Bad dreg pair");
1090 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1091 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1095 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1097 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1099 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1100 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1103 return yyerror ("Dregs expected");
1106 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1107 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1109 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1111 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1112 "SIGN (dregs_hi) * dregs_hi + "
1113 "SIGN (dregs_lo) * dregs_lo \n");
1115 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1118 return yyerror ("Dregs expected");
1120 | REG ASSIGN REG plus_minus REG amod1
1122 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1126 /* No saturation flag specified, generate the 16 bit variant. */
1127 notethat ("COMP3op: dregs = dregs +- dregs\n");
1128 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1132 /* Saturation flag specified, generate the 32 bit variant. */
1133 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1134 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1138 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1140 notethat ("COMP3op: pregs = pregs + pregs\n");
1141 $$ = COMP3OP (&$1, &$3, &$5, 5);
1144 return yyerror ("Dregs expected");
1146 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1150 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1157 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1158 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1161 return yyerror ("Dregs expected");
1164 | a_assign MINUS REG_A
1166 notethat ("dsp32alu: Ax = - Ax\n");
1167 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, ®7, ®7, 0, 0, IS_A1 ($3));
1169 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1171 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1172 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1173 $6.s0, $6.x0, HL2 ($3, $5));
1175 | a_assign a_assign expr
1177 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1179 notethat ("dsp32alu: A1 = A0 = 0\n");
1180 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 0, 0, 2);
1183 return yyerror ("Bad value, 0 expected");
1187 | a_assign REG_A LPAREN S RPAREN
1189 if (REG_SAME ($1, $2))
1191 notethat ("dsp32alu: Ax = Ax (S)\n");
1192 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, IS_A1 ($1));
1195 return yyerror ("Registers must be equal");
1198 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1202 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1203 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1206 return yyerror ("Dregs expected");
1209 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1211 if (IS_DREG ($3) && IS_DREG ($5))
1213 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1214 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1217 return yyerror ("Dregs expected");
1220 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1222 if (IS_DREG ($3) && IS_DREG ($5))
1224 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1225 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1228 return yyerror ("Dregs expected");
1233 if (!REG_SAME ($1, $2))
1235 notethat ("dsp32alu: An = Am\n");
1236 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, IS_A1 ($1), 0, 3);
1239 return yyerror ("Accu reg arguments must differ");
1246 notethat ("dsp32alu: An = dregs\n");
1247 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1250 return yyerror ("Dregs expected");
1253 | REG ASSIGN HALF_REG xpmod
1257 if ($1.regno == REG_A0x && IS_DREG ($3))
1259 notethat ("dsp32alu: A0.x = dregs_lo\n");
1260 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1262 else if ($1.regno == REG_A1x && IS_DREG ($3))
1264 notethat ("dsp32alu: A1.x = dregs_lo\n");
1265 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1267 else if (IS_DREG ($1) && IS_DREG ($3))
1269 notethat ("ALU2op: dregs = dregs_lo\n");
1270 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1273 return yyerror ("Register mismatch");
1276 return yyerror ("Low reg expected");
1279 | HALF_REG ASSIGN expr
1281 notethat ("LDIMMhalf: pregs_half = imm16\n");
1283 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1284 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1285 return yyerror ("Wrong register for load immediate");
1287 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1288 return yyerror ("Constant out of range");
1290 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1295 notethat ("dsp32alu: An = 0\n");
1298 return yyerror ("0 expected");
1300 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1303 | REG ASSIGN expr xpmod1
1305 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1306 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1307 return yyerror ("Wrong register for load immediate");
1311 /* 7 bit immediate value if possible.
1312 We will check for that constant value for efficiency
1313 If it goes to reloc, it will be 16 bit. */
1314 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1316 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1317 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1319 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1321 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1322 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1326 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1327 return yyerror ("Immediate value out of range");
1329 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1331 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1336 /* (z) There is no 7 bit zero extended instruction.
1337 If the expr is a relocation, generate it. */
1339 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1340 return yyerror ("Immediate value out of range");
1342 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1344 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1348 | HALF_REG ASSIGN REG
1351 return yyerror ("Low reg expected");
1353 if (IS_DREG ($1) && $3.regno == REG_A0x)
1355 notethat ("dsp32alu: dregs_lo = A0.x\n");
1356 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 0);
1358 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1360 notethat ("dsp32alu: dregs_lo = A1.x\n");
1361 $$ = DSP32ALU (10, 0, 0, &$1, ®7, ®7, 0, 0, 1);
1364 return yyerror ("Register mismatch");
1367 | REG ASSIGN REG op_bar_op REG amod0
1369 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1371 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1372 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1375 return yyerror ("Register mismatch");
1378 | REG ASSIGN BYTE_DREG xpmod
1380 if (IS_DREG ($1) && IS_DREG ($3))
1382 notethat ("ALU2op: dregs = dregs_byte\n");
1383 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1386 return yyerror ("Register mismatch");
1389 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1391 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1393 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1394 $$ = DSP32ALU (16, 0, 0, 0, ®7, ®7, 0, 0, 3);
1397 return yyerror ("Register mismatch");
1400 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1402 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1404 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1405 $$ = DSP32ALU (14, 0, 0, 0, ®7, ®7, 0, 0, 3);
1408 return yyerror ("Register mismatch");
1411 | a_minusassign REG_A w32_or_nothing
1413 if (!IS_A1 ($1) && IS_A1 ($2))
1415 notethat ("dsp32alu: A0 -= A1\n");
1416 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $3.r0, 0, 3);
1419 return yyerror ("Register mismatch");
1422 | REG _MINUS_ASSIGN expr
1424 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1426 notethat ("dagMODik: iregs -= 4\n");
1427 $$ = DAGMODIK (&$1, 3);
1429 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1431 notethat ("dagMODik: iregs -= 2\n");
1432 $$ = DAGMODIK (&$1, 1);
1435 return yyerror ("Register or value mismatch");
1438 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1440 if (IS_IREG ($1) && IS_MREG ($3))
1442 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1444 $$ = DAGMODIM (&$1, &$3, 0, 1);
1446 else if (IS_PREG ($1) && IS_PREG ($3))
1448 notethat ("PTR2op: pregs += pregs (BREV )\n");
1449 $$ = PTR2OP (&$1, &$3, 5);
1452 return yyerror ("Register mismatch");
1455 | REG _MINUS_ASSIGN REG
1457 if (IS_IREG ($1) && IS_MREG ($3))
1459 notethat ("dagMODim: iregs -= mregs\n");
1460 $$ = DAGMODIM (&$1, &$3, 1, 0);
1462 else if (IS_PREG ($1) && IS_PREG ($3))
1464 notethat ("PTR2op: pregs -= pregs\n");
1465 $$ = PTR2OP (&$1, &$3, 0);
1468 return yyerror ("Register mismatch");
1471 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1473 if (!IS_A1 ($1) && IS_A1 ($3))
1475 notethat ("dsp32alu: A0 += A1 (W32)\n");
1476 $$ = DSP32ALU (11, 0, 0, 0, ®7, ®7, $4.r0, 0, 2);
1479 return yyerror ("Register mismatch");
1482 | REG _PLUS_ASSIGN REG
1484 if (IS_IREG ($1) && IS_MREG ($3))
1486 notethat ("dagMODim: iregs += mregs\n");
1487 $$ = DAGMODIM (&$1, &$3, 0, 0);
1490 return yyerror ("iregs += mregs expected");
1493 | REG _PLUS_ASSIGN expr
1497 if (EXPR_VALUE ($3) == 4)
1499 notethat ("dagMODik: iregs += 4\n");
1500 $$ = DAGMODIK (&$1, 2);
1502 else if (EXPR_VALUE ($3) == 2)
1504 notethat ("dagMODik: iregs += 2\n");
1505 $$ = DAGMODIK (&$1, 0);
1508 return yyerror ("iregs += [ 2 | 4 ");
1510 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1512 notethat ("COMPI2opP: pregs += imm7\n");
1513 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1515 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1517 notethat ("COMPI2opD: dregs += imm7\n");
1518 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1520 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1521 return yyerror ("Immediate value out of range");
1523 return yyerror ("Register mismatch");
1526 | REG _STAR_ASSIGN REG
1528 if (IS_DREG ($1) && IS_DREG ($3))
1530 notethat ("ALU2op: dregs *= dregs\n");
1531 $$ = ALU2OP (&$1, &$3, 3);
1534 return yyerror ("Register mismatch");
1537 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1539 if (!valid_dreg_pair (&$3, $5))
1540 return yyerror ("Bad dreg pair");
1541 else if (!valid_dreg_pair (&$7, $9))
1542 return yyerror ("Bad dreg pair");
1545 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1546 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1550 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1552 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1554 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1555 $$ = DSP32ALU (8, 0, 0, 0, ®7, ®7, 1, 0, 2);
1558 return yyerror ("Register mismatch");
1561 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1563 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1564 && REG_SAME ($1, $4))
1566 if (EXPR_VALUE ($9) == 1)
1568 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1569 $$ = ALU2OP (&$1, &$6, 4);
1571 else if (EXPR_VALUE ($9) == 2)
1573 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1574 $$ = ALU2OP (&$1, &$6, 5);
1577 return yyerror ("Bad shift value");
1579 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1580 && REG_SAME ($1, $4))
1582 if (EXPR_VALUE ($9) == 1)
1584 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1585 $$ = PTR2OP (&$1, &$6, 6);
1587 else if (EXPR_VALUE ($9) == 2)
1589 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1590 $$ = PTR2OP (&$1, &$6, 7);
1593 return yyerror ("Bad shift value");
1596 return yyerror ("Register mismatch");
1600 | REG ASSIGN REG BAR REG
1602 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1604 notethat ("COMP3op: dregs = dregs | dregs\n");
1605 $$ = COMP3OP (&$1, &$3, &$5, 3);
1608 return yyerror ("Dregs expected");
1610 | REG ASSIGN REG CARET REG
1612 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1614 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1615 $$ = COMP3OP (&$1, &$3, &$5, 4);
1618 return yyerror ("Dregs expected");
1620 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1622 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1624 if (EXPR_VALUE ($8) == 1)
1626 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1627 $$ = COMP3OP (&$1, &$3, &$6, 6);
1629 else if (EXPR_VALUE ($8) == 2)
1631 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1632 $$ = COMP3OP (&$1, &$3, &$6, 7);
1635 return yyerror ("Bad shift value");
1638 return yyerror ("Dregs expected");
1640 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1642 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1644 notethat ("CCflag: CC = A0 == A1\n");
1645 $$ = CCFLAG (0, 0, 5, 0, 0);
1648 return yyerror ("AREGs are in bad order or same");
1650 | CCREG ASSIGN REG_A LESS_THAN REG_A
1652 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1654 notethat ("CCflag: CC = A0 < A1\n");
1655 $$ = CCFLAG (0, 0, 6, 0, 0);
1658 return yyerror ("AREGs are in bad order or same");
1660 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1662 if ((IS_DREG ($3) && IS_DREG ($5))
1663 || (IS_PREG ($3) && IS_PREG ($5)))
1665 notethat ("CCflag: CC = dpregs < dpregs\n");
1666 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1669 return yyerror ("Bad register in comparison");
1671 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1673 if (!IS_DREG ($3) && !IS_PREG ($3))
1674 return yyerror ("Bad register in comparison");
1676 if (($6.r0 == 1 && IS_IMM ($5, 3))
1677 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1679 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1680 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1683 return yyerror ("Bad constant value");
1685 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1687 if ((IS_DREG ($3) && IS_DREG ($5))
1688 || (IS_PREG ($3) && IS_PREG ($5)))
1690 notethat ("CCflag: CC = dpregs == dpregs\n");
1691 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1694 return yyerror ("Bad register in comparison");
1696 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1698 if (!IS_DREG ($3) && !IS_PREG ($3))
1699 return yyerror ("Bad register in comparison");
1703 notethat ("CCflag: CC = dpregs == imm3\n");
1704 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1707 return yyerror ("Bad constant range");
1709 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1711 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1713 notethat ("CCflag: CC = A0 <= A1\n");
1714 $$ = CCFLAG (0, 0, 7, 0, 0);
1717 return yyerror ("AREGs are in bad order or same");
1719 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1721 if ((IS_DREG ($3) && IS_DREG ($5))
1722 || (IS_PREG ($3) && IS_PREG ($5)))
1724 notethat ("CCflag: CC = dpregs <= dpregs (..)\n");
1725 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1726 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1729 return yyerror ("Bad register in comparison");
1731 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1733 if (!IS_DREG ($3) && !IS_PREG ($3))
1734 return yyerror ("Bad register in comparison");
1736 if (($6.r0 == 1 && IS_IMM ($5, 3))
1737 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1739 notethat ("CCflag: CC = dpregs <= (u)imm3\n");
1740 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1743 return yyerror ("Bad constant value");
1746 | REG ASSIGN REG AMPERSAND REG
1748 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1750 notethat ("COMP3op: dregs = dregs & dregs\n");
1751 $$ = COMP3OP (&$1, &$3, &$5, 2);
1754 return yyerror ("Dregs expected");
1759 notethat ("CC2stat operation\n");
1760 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1765 if ((IS_GENREG ($1) && IS_GENREG ($3))
1766 || (IS_GENREG ($1) && IS_DAGREG ($3))
1767 || (IS_DAGREG ($1) && IS_GENREG ($3))
1768 || (IS_DAGREG ($1) && IS_DAGREG ($3))
1769 || (IS_GENREG ($1) && $3.regno == REG_USP)
1770 || ($1.regno == REG_USP && IS_GENREG ($3))
1771 || ($1.regno == REG_USP && $3.regno == REG_USP)
1772 || (IS_DREG ($1) && IS_SYSREG ($3))
1773 || (IS_PREG ($1) && IS_SYSREG ($3))
1774 || (IS_SYSREG ($1) && IS_GENREG ($3))
1775 || (IS_ALLREG ($1) && IS_EMUDAT ($3))
1776 || (IS_EMUDAT ($1) && IS_ALLREG ($3))
1777 || (IS_SYSREG ($1) && $3.regno == REG_USP))
1779 $$ = bfin_gen_regmv (&$3, &$1);
1782 return yyerror ("Unsupported register move");
1789 notethat ("CC2dreg: CC = dregs\n");
1790 $$ = bfin_gen_cc2dreg (1, &$3);
1793 return yyerror ("Only 'CC = Dreg' supported");
1800 notethat ("CC2dreg: dregs = CC\n");
1801 $$ = bfin_gen_cc2dreg (0, &$1);
1804 return yyerror ("Only 'Dreg = CC' supported");
1807 | CCREG _ASSIGN_BANG CCREG
1809 notethat ("CC2dreg: CC =! CC\n");
1810 $$ = bfin_gen_cc2dreg (3, 0);
1815 | HALF_REG ASSIGN multiply_halfregs opt_mode
1817 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1819 if (!IS_H ($1) && $4.MM)
1820 return yyerror ("(M) not allowed with MAC0");
1822 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1823 && $4.mod != M_IU && $4.mod != M_T && $4.mod != M_TFU
1824 && $4.mod != M_S2RND && $4.mod != M_ISS2 && $4.mod != M_IH)
1825 return yyerror ("bad option.");
1829 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1830 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1831 &$1, 0, &$3.s0, &$3.s1, 0);
1835 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1836 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1837 &$1, 0, &$3.s0, &$3.s1, 1);
1841 | REG ASSIGN multiply_halfregs opt_mode
1843 /* Odd registers can use (M). */
1845 return yyerror ("Dreg expected");
1847 if (IS_EVEN ($1) && $4.MM)
1848 return yyerror ("(M) not allowed with MAC0");
1850 if ($4.mod != 0 && $4.mod != M_FU && $4.mod != M_IS
1851 && $4.mod != M_S2RND && $4.mod != M_ISS2)
1852 return yyerror ("bad option");
1856 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1858 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1859 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1860 &$1, 0, &$3.s0, &$3.s1, 0);
1864 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1865 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1866 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1867 &$1, 0, &$3.s0, &$3.s1, 1);
1871 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1872 HALF_REG ASSIGN multiply_halfregs opt_mode
1874 if (!IS_DREG ($1) || !IS_DREG ($6))
1875 return yyerror ("Dregs expected");
1877 if (!IS_HCOMPL($1, $6))
1878 return yyerror ("Dest registers mismatch");
1880 if (check_multiply_halfregs (&$3, &$8) < 0)
1883 if ((!IS_H ($1) && $4.MM)
1884 || (!IS_H ($6) && $9.MM))
1885 return yyerror ("(M) not allowed with MAC0");
1887 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1888 "dregs_lo = multiply_halfregs opt_mode\n");
1891 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1892 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1893 &$1, 0, &$3.s0, &$3.s1, 1);
1895 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1896 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1897 &$1, 0, &$3.s0, &$3.s1, 1);
1900 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1902 if (!IS_DREG ($1) || !IS_DREG ($6))
1903 return yyerror ("Dregs expected");
1905 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1906 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1907 return yyerror ("Dest registers mismatch");
1909 if (check_multiply_halfregs (&$3, &$8) < 0)
1912 if ((IS_EVEN ($1) && $4.MM)
1913 || (IS_EVEN ($6) && $9.MM))
1914 return yyerror ("(M) not allowed with MAC0");
1916 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1917 "dregs = multiply_halfregs opt_mode\n");
1920 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1921 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1922 &$1, 0, &$3.s0, &$3.s1, 1);
1924 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1925 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1926 &$1, 0, &$3.s0, &$3.s1, 1);
1931 | a_assign ASHIFT REG_A BY HALF_REG
1933 if (!REG_SAME ($1, $3))
1934 return yyerror ("Aregs must be same");
1936 if (IS_DREG ($5) && !IS_H ($5))
1938 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1939 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1942 return yyerror ("Dregs expected");
1945 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1947 if (IS_DREG ($6) && !IS_H ($6))
1949 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1950 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1953 return yyerror ("Dregs expected");
1956 | a_assign REG_A LESS_LESS expr
1958 if (!REG_SAME ($1, $2))
1959 return yyerror ("Aregs must be same");
1961 if (IS_UIMM ($4, 5))
1963 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1964 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1967 return yyerror ("Bad shift value");
1970 | REG ASSIGN REG LESS_LESS expr vsmod
1972 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1977 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1978 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1982 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1983 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1986 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1988 if (EXPR_VALUE ($5) == 2)
1990 notethat ("PTR2op: pregs = pregs << 2\n");
1991 $$ = PTR2OP (&$1, &$3, 1);
1993 else if (EXPR_VALUE ($5) == 1)
1995 notethat ("COMP3op: pregs = pregs << 1\n");
1996 $$ = COMP3OP (&$1, &$3, &$3, 5);
1999 return yyerror ("Bad shift value");
2002 return yyerror ("Bad shift value or register");
2004 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
2006 if (IS_UIMM ($5, 4))
2010 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
2011 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2015 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
2016 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
2020 return yyerror ("Bad shift value");
2022 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
2026 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
2031 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
2032 "dregs_lo (V, .)\n");
2038 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
2040 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
2043 return yyerror ("Dregs expected");
2047 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
2049 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2051 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
2052 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
2055 return yyerror ("Bad shift value or register");
2059 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
2061 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2063 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2064 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2066 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2068 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2069 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2072 return yyerror ("Bad shift value or register");
2077 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2079 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2081 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2082 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2085 return yyerror ("Register mismatch");
2088 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2090 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2092 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2093 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2096 return yyerror ("Register mismatch");
2099 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2101 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2103 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2104 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2107 return yyerror ("Register mismatch");
2110 | a_assign REG_A _GREATER_GREATER_GREATER expr
2112 if (!REG_SAME ($1, $2))
2113 return yyerror ("Aregs must be same");
2115 if (IS_UIMM ($4, 5))
2117 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2118 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2121 return yyerror ("Shift value range error");
2123 | a_assign LSHIFT REG_A BY HALF_REG
2125 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2127 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2128 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2131 return yyerror ("Register mismatch");
2134 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2136 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2138 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2139 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2142 return yyerror ("Register mismatch");
2145 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2147 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2149 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2150 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2153 return yyerror ("Register mismatch");
2156 | REG ASSIGN SHIFT REG BY HALF_REG
2158 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2160 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2161 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2164 return yyerror ("Register mismatch");
2167 | a_assign REG_A GREATER_GREATER expr
2169 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2171 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2172 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2175 return yyerror ("Accu register expected");
2178 | REG ASSIGN REG GREATER_GREATER expr vmod
2182 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2184 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2185 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2188 return yyerror ("Register mismatch");
2192 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2194 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2195 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2197 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2199 notethat ("PTR2op: pregs = pregs >> 2\n");
2200 $$ = PTR2OP (&$1, &$3, 3);
2202 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2204 notethat ("PTR2op: pregs = pregs >> 1\n");
2205 $$ = PTR2OP (&$1, &$3, 4);
2208 return yyerror ("Register mismatch");
2211 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2213 if (IS_UIMM ($5, 5))
2215 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2216 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2219 return yyerror ("Register mismatch");
2221 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2223 if (IS_UIMM ($5, 5))
2225 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2226 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2227 $6.s0, HL2 ($1, $3));
2230 return yyerror ("Register or modifier mismatch");
2234 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2236 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2241 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2242 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2246 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2247 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2251 return yyerror ("Register mismatch");
2254 | HALF_REG ASSIGN ONES REG
2256 if (IS_DREG_L ($1) && IS_DREG ($4))
2258 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2259 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2262 return yyerror ("Register mismatch");
2265 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2267 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2269 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2270 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2273 return yyerror ("Register mismatch");
2276 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2279 && $7.regno == REG_A0
2280 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2282 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2283 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2286 return yyerror ("Register mismatch");
2289 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2292 && $7.regno == REG_A0
2293 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2295 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2296 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2299 return yyerror ("Register mismatch");
2302 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2304 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2306 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2307 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2310 return yyerror ("Register mismatch");
2313 | a_assign ROT REG_A BY HALF_REG
2315 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2317 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2318 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2321 return yyerror ("Register mismatch");
2324 | REG ASSIGN ROT REG BY HALF_REG
2326 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2328 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2329 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2332 return yyerror ("Register mismatch");
2335 | a_assign ROT REG_A BY expr
2339 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2340 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2343 return yyerror ("Register mismatch");
2346 | REG ASSIGN ROT REG BY expr
2348 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2350 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2353 return yyerror ("Register mismatch");
2356 | HALF_REG ASSIGN SIGNBITS REG_A
2360 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2361 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2364 return yyerror ("Register mismatch");
2367 | HALF_REG ASSIGN SIGNBITS REG
2369 if (IS_DREG_L ($1) && IS_DREG ($4))
2371 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2372 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2375 return yyerror ("Register mismatch");
2378 | HALF_REG ASSIGN SIGNBITS HALF_REG
2382 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2383 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2386 return yyerror ("Register mismatch");
2389 /* The ASR bit is just inverted here. */
2390 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2392 if (IS_DREG_L ($1) && IS_DREG ($5))
2394 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2395 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2398 return yyerror ("Register mismatch");
2401 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2403 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2405 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2406 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2409 return yyerror ("Register mismatch");
2412 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2414 if (REG_SAME ($3, $5))
2415 return yyerror ("Illegal source register combination");
2417 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2419 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2420 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2423 return yyerror ("Register mismatch");
2426 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2428 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2430 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2431 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2434 return yyerror ("Dregs expected");
2438 /* LOGI2op: BITCLR (dregs, uimm5). */
2439 | BITCLR LPAREN REG COMMA expr RPAREN
2441 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2443 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2444 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2447 return yyerror ("Register mismatch");
2450 /* LOGI2op: BITSET (dregs, uimm5). */
2451 | BITSET LPAREN REG COMMA expr RPAREN
2453 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2455 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2456 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2459 return yyerror ("Register mismatch");
2462 /* LOGI2op: BITTGL (dregs, uimm5). */
2463 | BITTGL LPAREN REG COMMA expr RPAREN
2465 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2467 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2468 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2471 return yyerror ("Register mismatch");
2474 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2476 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2478 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2479 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2482 return yyerror ("Register mismatch or value error");
2485 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2487 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2489 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2490 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2493 return yyerror ("Register mismatch or value error");
2496 | IF BANG CCREG REG ASSIGN REG
2498 if ((IS_DREG ($4) || IS_PREG ($4))
2499 && (IS_DREG ($6) || IS_PREG ($6)))
2501 notethat ("ccMV: IF ! CC gregs = gregs\n");
2502 $$ = CCMV (&$6, &$4, 0);
2505 return yyerror ("Register mismatch");
2508 | IF CCREG REG ASSIGN REG
2510 if ((IS_DREG ($5) || IS_PREG ($5))
2511 && (IS_DREG ($3) || IS_PREG ($3)))
2513 notethat ("ccMV: IF CC gregs = gregs\n");
2514 $$ = CCMV (&$5, &$3, 1);
2517 return yyerror ("Register mismatch");
2520 | IF BANG CCREG JUMP expr
2522 if (IS_PCREL10 ($5))
2524 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2525 $$ = BRCC (0, 0, $5);
2528 return yyerror ("Bad jump offset");
2531 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2533 if (IS_PCREL10 ($5))
2535 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2536 $$ = BRCC (0, 1, $5);
2539 return yyerror ("Bad jump offset");
2542 | IF CCREG JUMP expr
2544 if (IS_PCREL10 ($4))
2546 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2547 $$ = BRCC (1, 0, $4);
2550 return yyerror ("Bad jump offset");
2553 | IF CCREG JUMP expr LPAREN BP RPAREN
2555 if (IS_PCREL10 ($4))
2557 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2558 $$ = BRCC (1, 1, $4);
2561 return yyerror ("Bad jump offset");
2565 notethat ("ProgCtrl: NOP\n");
2566 $$ = PROGCTRL (0, 0);
2571 notethat ("ProgCtrl: RTS\n");
2572 $$ = PROGCTRL (1, 0);
2577 notethat ("ProgCtrl: RTI\n");
2578 $$ = PROGCTRL (1, 1);
2583 notethat ("ProgCtrl: RTX\n");
2584 $$ = PROGCTRL (1, 2);
2589 notethat ("ProgCtrl: RTN\n");
2590 $$ = PROGCTRL (1, 3);
2595 notethat ("ProgCtrl: RTE\n");
2596 $$ = PROGCTRL (1, 4);
2601 notethat ("ProgCtrl: IDLE\n");
2602 $$ = PROGCTRL (2, 0);
2607 notethat ("ProgCtrl: CSYNC\n");
2608 $$ = PROGCTRL (2, 3);
2613 notethat ("ProgCtrl: SSYNC\n");
2614 $$ = PROGCTRL (2, 4);
2619 notethat ("ProgCtrl: EMUEXCPT\n");
2620 $$ = PROGCTRL (2, 5);
2627 notethat ("ProgCtrl: CLI dregs\n");
2628 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2631 return yyerror ("Dreg expected for CLI");
2638 notethat ("ProgCtrl: STI dregs\n");
2639 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2642 return yyerror ("Dreg expected for STI");
2645 | JUMP LPAREN REG RPAREN
2649 notethat ("ProgCtrl: JUMP (pregs )\n");
2650 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2653 return yyerror ("Bad register for indirect jump");
2656 | CALL LPAREN REG RPAREN
2660 notethat ("ProgCtrl: CALL (pregs )\n");
2661 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2664 return yyerror ("Bad register for indirect call");
2667 | CALL LPAREN PC PLUS REG RPAREN
2671 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2672 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2675 return yyerror ("Bad register for indirect call");
2678 | JUMP LPAREN PC PLUS REG RPAREN
2682 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2683 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2686 return yyerror ("Bad register for indirect jump");
2691 if (IS_UIMM ($2, 4))
2693 notethat ("ProgCtrl: RAISE uimm4\n");
2694 $$ = PROGCTRL (9, uimm4 ($2));
2697 return yyerror ("Bad value for RAISE");
2702 notethat ("ProgCtrl: EMUEXCPT\n");
2703 $$ = PROGCTRL (10, uimm4 ($2));
2706 | TESTSET LPAREN REG RPAREN
2710 if ($3.regno == REG_SP || $3.regno == REG_FP)
2711 return yyerror ("Bad register for TESTSET");
2713 notethat ("ProgCtrl: TESTSET (pregs )\n");
2714 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2717 return yyerror ("Preg expected");
2722 if (IS_PCREL12 ($2))
2724 notethat ("UJUMP: JUMP pcrel12\n");
2728 return yyerror ("Bad value for relative jump");
2733 if (IS_PCREL12 ($2))
2735 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2739 return yyerror ("Bad value for relative jump");
2744 if (IS_PCREL24 ($2))
2746 notethat ("CALLa: jump.l pcrel24\n");
2750 return yyerror ("Bad value for long jump");
2755 if (IS_PCREL24 ($2))
2757 notethat ("CALLa: jump.l pcrel24\n");
2761 return yyerror ("Bad value for long jump");
2766 if (IS_PCREL24 ($2))
2768 notethat ("CALLa: CALL pcrel25m2\n");
2772 return yyerror ("Bad call address");
2776 if (IS_PCREL24 ($2))
2778 notethat ("CALLa: CALL pcrel25m2\n");
2782 return yyerror ("Bad call address");
2786 /* ALU2op: DIVQ (dregs, dregs). */
2787 | DIVQ LPAREN REG COMMA REG RPAREN
2789 if (IS_DREG ($3) && IS_DREG ($5))
2790 $$ = ALU2OP (&$3, &$5, 8);
2792 return yyerror ("Bad registers for DIVQ");
2795 | DIVS LPAREN REG COMMA REG RPAREN
2797 if (IS_DREG ($3) && IS_DREG ($5))
2798 $$ = ALU2OP (&$3, &$5, 9);
2800 return yyerror ("Bad registers for DIVS");
2803 | REG ASSIGN MINUS REG vsmod
2805 if (IS_DREG ($1) && IS_DREG ($4))
2807 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2809 notethat ("ALU2op: dregs = - dregs\n");
2810 $$ = ALU2OP (&$1, &$4, 14);
2812 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2814 notethat ("dsp32alu: dregs = - dregs (.)\n");
2815 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2819 notethat ("dsp32alu: dregs = - dregs (.)\n");
2820 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2824 return yyerror ("Dregs expected");
2827 | REG ASSIGN TILDA REG
2829 if (IS_DREG ($1) && IS_DREG ($4))
2831 notethat ("ALU2op: dregs = ~dregs\n");
2832 $$ = ALU2OP (&$1, &$4, 15);
2835 return yyerror ("Dregs expected");
2838 | REG _GREATER_GREATER_ASSIGN REG
2840 if (IS_DREG ($1) && IS_DREG ($3))
2842 notethat ("ALU2op: dregs >>= dregs\n");
2843 $$ = ALU2OP (&$1, &$3, 1);
2846 return yyerror ("Dregs expected");
2849 | REG _GREATER_GREATER_ASSIGN expr
2851 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2853 notethat ("LOGI2op: dregs >>= uimm5\n");
2854 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2857 return yyerror ("Dregs expected or value error");
2860 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2862 if (IS_DREG ($1) && IS_DREG ($3))
2864 notethat ("ALU2op: dregs >>>= dregs\n");
2865 $$ = ALU2OP (&$1, &$3, 0);
2868 return yyerror ("Dregs expected");
2871 | REG _LESS_LESS_ASSIGN REG
2873 if (IS_DREG ($1) && IS_DREG ($3))
2875 notethat ("ALU2op: dregs <<= dregs\n");
2876 $$ = ALU2OP (&$1, &$3, 2);
2879 return yyerror ("Dregs expected");
2882 | REG _LESS_LESS_ASSIGN expr
2884 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2886 notethat ("LOGI2op: dregs <<= uimm5\n");
2887 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2890 return yyerror ("Dregs expected or const value error");
2894 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2896 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2898 notethat ("LOGI2op: dregs >>>= uimm5\n");
2899 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2902 return yyerror ("Dregs expected");
2905 /* Cache Control. */
2907 | FLUSH LBRACK REG RBRACK
2909 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2911 $$ = CACTRL (&$3, 0, 2);
2913 return yyerror ("Bad register(s) for FLUSH");
2916 | FLUSH reg_with_postinc
2920 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2921 $$ = CACTRL (&$2, 1, 2);
2924 return yyerror ("Bad register(s) for FLUSH");
2927 | FLUSHINV LBRACK REG RBRACK
2931 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2932 $$ = CACTRL (&$3, 0, 1);
2935 return yyerror ("Bad register(s) for FLUSH");
2938 | FLUSHINV reg_with_postinc
2942 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2943 $$ = CACTRL (&$2, 1, 1);
2946 return yyerror ("Bad register(s) for FLUSH");
2949 /* CaCTRL: IFLUSH [pregs]. */
2950 | IFLUSH LBRACK REG RBRACK
2954 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2955 $$ = CACTRL (&$3, 0, 3);
2958 return yyerror ("Bad register(s) for FLUSH");
2961 | IFLUSH reg_with_postinc
2965 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2966 $$ = CACTRL (&$2, 1, 3);
2969 return yyerror ("Bad register(s) for FLUSH");
2972 | PREFETCH LBRACK REG RBRACK
2976 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2977 $$ = CACTRL (&$3, 0, 0);
2980 return yyerror ("Bad register(s) for PREFETCH");
2983 | PREFETCH reg_with_postinc
2987 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2988 $$ = CACTRL (&$2, 1, 0);
2991 return yyerror ("Bad register(s) for PREFETCH");
2995 /* LDST: B [ pregs <post_op> ] = dregs. */
2997 | B LBRACK REG post_op RBRACK ASSIGN REG
3000 return yyerror ("Dreg expected for source operand");
3002 return yyerror ("Preg expected in address");
3004 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
3005 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
3008 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
3009 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
3011 Expr_Node *tmp = $5;
3014 return yyerror ("Dreg expected for source operand");
3016 return yyerror ("Preg expected in address");
3019 return yyerror ("Plain symbol used as offset");
3022 tmp = unary (Expr_Op_Type_NEG, tmp);
3024 if (in_range_p (tmp, -32768, 32767, 0))
3026 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
3027 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
3030 return yyerror ("Displacement out of range");
3034 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
3035 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
3037 Expr_Node *tmp = $5;
3040 return yyerror ("Dreg expected for source operand");
3042 return yyerror ("Preg expected in address");
3045 tmp = unary (Expr_Op_Type_NEG, tmp);
3048 return yyerror ("Plain symbol used as offset");
3050 if (in_range_p (tmp, 0, 30, 1))
3052 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
3053 $$ = LDSTII (&$3, &$8, tmp, 1, 1);
3055 else if (in_range_p (tmp, -65536, 65535, 1))
3057 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
3058 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, tmp);
3061 return yyerror ("Displacement out of range");
3064 /* LDST: W [ pregs <post_op> ] = dregs. */
3065 | W LBRACK REG post_op RBRACK ASSIGN REG
3068 return yyerror ("Dreg expected for source operand");
3070 return yyerror ("Preg expected in address");
3072 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
3073 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
3076 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
3079 return yyerror ("Dreg expected for source operand");
3082 if (!IS_IREG ($3) && !IS_PREG ($3))
3083 return yyerror ("Ireg or Preg expected in address");
3085 else if (!IS_IREG ($3))
3086 return yyerror ("Ireg expected in address");
3090 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
3091 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
3095 notethat ("LDSTpmod: W [ pregs ] = dregs_half\n");
3096 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3100 /* LDSTiiFP: [ FP - const ] = dpregs. */
3101 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3103 Expr_Node *tmp = $4;
3104 int ispreg = IS_PREG ($7);
3107 return yyerror ("Preg expected in address");
3109 if (!IS_DREG ($7) && !ispreg)
3110 return yyerror ("Preg expected for source operand");
3113 tmp = unary (Expr_Op_Type_NEG, tmp);
3116 return yyerror ("Plain symbol used as offset");
3118 if (in_range_p (tmp, 0, 63, 3))
3120 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3121 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3123 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3125 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3126 tmp = unary (Expr_Op_Type_NEG, tmp);
3127 $$ = LDSTIIFP (tmp, &$7, 1);
3129 else if (in_range_p (tmp, -131072, 131071, 3))
3131 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3132 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1 : 0, tmp);
3135 return yyerror ("Displacement out of range");
3138 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3140 Expr_Node *tmp = $7;
3142 return yyerror ("Dreg expected for destination operand");
3144 return yyerror ("Preg expected in address");
3147 tmp = unary (Expr_Op_Type_NEG, tmp);
3150 return yyerror ("Plain symbol used as offset");
3152 if (in_range_p (tmp, 0, 30, 1))
3154 notethat ("LDSTii: dregs = W [ pregs + uimm5m2 ] (.)\n");
3155 $$ = LDSTII (&$5, &$1, tmp, 0, 1 << $9.r0);
3157 else if (in_range_p (tmp, -65536, 65535, 1))
3159 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3160 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, tmp);
3163 return yyerror ("Displacement out of range");
3166 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3169 return yyerror ("Dreg expected for source operand");
3172 if (!IS_IREG ($5) && !IS_PREG ($5))
3173 return yyerror ("Ireg or Preg expected in address");
3175 else if (!IS_IREG ($5))
3176 return yyerror ("Ireg expected in address");
3180 notethat ("dspLDST: dregs_half = W [ iregs <post_op> ]\n");
3181 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3185 notethat ("LDSTpmod: dregs_half = W [ pregs <post_op> ]\n");
3186 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3191 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3194 return yyerror ("Dreg expected for destination operand");
3196 return yyerror ("Preg expected in address");
3198 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3199 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3202 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3205 return yyerror ("Dreg expected for destination operand");
3206 if (!IS_PREG ($5) || !IS_PREG ($7))
3207 return yyerror ("Preg expected in address");
3209 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3210 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3213 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3216 return yyerror ("Dreg expected for destination operand");
3217 if (!IS_PREG ($5) || !IS_PREG ($7))
3218 return yyerror ("Preg expected in address");
3220 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3221 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3224 | LBRACK REG post_op RBRACK ASSIGN REG
3226 if (!IS_IREG ($2) && !IS_PREG ($2))
3227 return yyerror ("Ireg or Preg expected in address");
3228 else if (IS_IREG ($2) && !IS_DREG ($6))
3229 return yyerror ("Dreg expected for source operand");
3230 else if (IS_PREG ($2) && !IS_DREG ($6) && !IS_PREG ($6))
3231 return yyerror ("Dreg or Preg expected for source operand");
3235 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3236 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3238 else if (IS_DREG ($6))
3240 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3241 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3245 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3246 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3250 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3253 return yyerror ("Dreg expected for source operand");
3255 if (IS_IREG ($2) && IS_MREG ($4))
3257 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3258 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3260 else if (IS_PREG ($2) && IS_PREG ($4))
3262 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3263 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3266 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3269 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3272 return yyerror ("Dreg expected for source operand");
3274 if (IS_PREG ($3) && IS_PREG ($5))
3276 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3277 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3280 return yyerror ("Preg ++ Preg expected in address");
3283 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3285 Expr_Node *tmp = $7;
3287 return yyerror ("Dreg expected for destination operand");
3289 return yyerror ("Preg expected in address");
3292 tmp = unary (Expr_Op_Type_NEG, tmp);
3295 return yyerror ("Plain symbol used as offset");
3297 if (in_range_p (tmp, -32768, 32767, 0))
3299 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3301 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, tmp);
3304 return yyerror ("Displacement out of range");
3307 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3310 return yyerror ("Dreg expected for destination operand");
3312 return yyerror ("Preg expected in address");
3314 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3316 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3319 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3322 return yyerror ("Dreg expected for destination operand");
3324 if (IS_IREG ($4) && IS_MREG ($6))
3326 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3327 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3329 else if (IS_PREG ($4) && IS_PREG ($6))
3331 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3332 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3335 return yyerror ("Preg ++ Preg or Ireg ++ Mreg expected in address");
3338 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3340 Expr_Node *tmp = $6;
3341 int ispreg = IS_PREG ($1);
3342 int isgot = IS_RELOC($6);
3345 return yyerror ("Preg expected in address");
3347 if (!IS_DREG ($1) && !ispreg)
3348 return yyerror ("Dreg or Preg expected for destination operand");
3350 if (tmp->type == Expr_Node_Reloc
3351 && strcmp (tmp->value.s_value,
3352 "_current_shared_library_p5_offset_") != 0)
3353 return yyerror ("Plain symbol used as offset");
3356 tmp = unary (Expr_Op_Type_NEG, tmp);
3360 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3361 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3363 else if (in_range_p (tmp, 0, 63, 3))
3365 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3366 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3368 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3370 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3371 tmp = unary (Expr_Op_Type_NEG, tmp);
3372 $$ = LDSTIIFP (tmp, &$1, 0);
3374 else if (in_range_p (tmp, -131072, 131071, 3))
3376 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3377 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1 : 0, tmp);
3381 return yyerror ("Displacement out of range");
3384 | REG ASSIGN LBRACK REG post_op RBRACK
3386 if (!IS_IREG ($4) && !IS_PREG ($4))
3387 return yyerror ("Ireg or Preg expected in address");
3388 else if (IS_IREG ($4) && !IS_DREG ($1))
3389 return yyerror ("Dreg expected in destination operand");
3390 else if (IS_PREG ($4) && !IS_DREG ($1) && !IS_PREG ($1)
3391 && ($4.regno != REG_SP || !IS_ALLREG ($1) || $5.x0 != 0))
3392 return yyerror ("Dreg or Preg expected in destination operand");
3396 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3397 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3399 else if (IS_DREG ($1))
3401 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3402 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3404 else if (IS_PREG ($1))
3406 if (REG_SAME ($1, $4) && $5.x0 != 2)
3407 return yyerror ("Pregs can't be same");
3409 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3410 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3414 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3415 $$ = PUSHPOPREG (&$1, 0);
3420 /* PushPopMultiple. */
3421 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3423 if ($1.regno != REG_SP)
3424 yyerror ("Stack Pointer expected");
3425 if ($4.regno == REG_R7
3426 && IN_RANGE ($6, 0, 7)
3427 && $8.regno == REG_P5
3428 && IN_RANGE ($10, 0, 5))
3430 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3431 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3434 return yyerror ("Bad register for PushPopMultiple");
3437 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3439 if ($1.regno != REG_SP)
3440 yyerror ("Stack Pointer expected");
3442 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3444 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3445 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3447 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3449 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3450 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3453 return yyerror ("Bad register for PushPopMultiple");
3456 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3458 if ($11.regno != REG_SP)
3459 yyerror ("Stack Pointer expected");
3460 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3461 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3463 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3464 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3467 return yyerror ("Bad register range for PushPopMultiple");
3470 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3472 if ($7.regno != REG_SP)
3473 yyerror ("Stack Pointer expected");
3475 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3477 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3478 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3480 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3482 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3483 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3486 return yyerror ("Bad register range for PushPopMultiple");
3489 | reg_with_predec ASSIGN REG
3491 if ($1.regno != REG_SP)
3492 yyerror ("Stack Pointer expected");
3496 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3497 $$ = PUSHPOPREG (&$3, 1);
3500 return yyerror ("Bad register for PushPopReg");
3507 if (IS_URANGE (16, $2, 0, 4))
3508 $$ = LINKAGE (0, uimm16s4 ($2));
3510 return yyerror ("Bad constant for LINK");
3515 notethat ("linkage: UNLINK\n");
3516 $$ = LINKAGE (1, 0);
3522 | LSETUP LPAREN expr COMMA expr RPAREN REG
3524 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3526 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3527 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3530 return yyerror ("Bad register or values for LSETUP");
3533 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3535 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3536 && IS_PREG ($9) && IS_CREG ($7))
3538 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3539 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3542 return yyerror ("Bad register or values for LSETUP");
3545 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3547 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3548 && IS_PREG ($9) && IS_CREG ($7)
3549 && EXPR_VALUE ($11) == 1)
3551 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3552 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3555 return yyerror ("Bad register or values for LSETUP");
3562 return yyerror ("Invalid expression in loop statement");
3564 return yyerror ("Invalid loop counter register");
3565 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3567 | LOOP expr REG ASSIGN REG
3569 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3571 notethat ("Loop: LOOP expr counters = pregs\n");
3572 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3575 return yyerror ("Bad register or values for LOOP");
3577 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3579 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3581 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3582 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3585 return yyerror ("Bad register or values for LOOP");
3591 Expr_Node_Value val;
3593 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3594 bfin_loop_attempt_create_label (tmp, 1);
3595 if (!IS_RELOC (tmp))
3596 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3597 bfin_loop_beginend (tmp, 1);
3603 return yyerror ("Invalid expression in LOOP_BEGIN statement");
3605 bfin_loop_beginend ($2, 1);
3612 Expr_Node_Value val;
3614 Expr_Node *tmp = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
3615 bfin_loop_attempt_create_label (tmp, 1);
3616 if (!IS_RELOC (tmp))
3617 return yyerror ("Invalid expression in LOOP_END statement");
3618 bfin_loop_beginend (tmp, 0);
3624 return yyerror ("Invalid expression in LOOP_END statement");
3626 bfin_loop_beginend ($2, 0);
3634 notethat ("psedoDEBUG: ABORT\n");
3635 $$ = bfin_gen_pseudodbg (3, 3, 0);
3640 notethat ("pseudoDEBUG: DBG\n");
3641 $$ = bfin_gen_pseudodbg (3, 7, 0);
3645 notethat ("pseudoDEBUG: DBG REG_A\n");
3646 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3650 notethat ("pseudoDEBUG: DBG allregs\n");
3651 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, ($2.regno & CLASS_MASK) >> 4);
3654 | DBGCMPLX LPAREN REG RPAREN
3657 return yyerror ("Dregs expected");
3658 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3659 $$ = bfin_gen_pseudodbg (3, 6, ($3.regno & CODE_MASK) >> 4);
3664 notethat ("psedoDEBUG: DBGHALT\n");
3665 $$ = bfin_gen_pseudodbg (3, 5, 0);
3670 notethat ("psedoDEBUG: HLT\n");
3671 $$ = bfin_gen_pseudodbg (3, 4, 0);
3674 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3676 notethat ("pseudodbg_assert: DBGA (regs_lo/hi , uimm16 )\n");
3677 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3680 | DBGAH LPAREN REG COMMA expr RPAREN
3682 notethat ("pseudodbg_assert: DBGAH (regs , uimm16 )\n");
3683 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3686 | DBGAL LPAREN REG COMMA expr RPAREN
3688 notethat ("psedodbg_assert: DBGAL (regs , uimm16 )\n");
3689 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3694 if (!IS_UIMM ($2, 8))
3695 return yyerror ("Constant out of range");
3696 notethat ("psedodbg_assert: OUTC uimm8\n");
3697 $$ = bfin_gen_pseudochr (uimm8 ($2));
3703 return yyerror ("Dregs expected");
3704 notethat ("psedodbg_assert: OUTC dreg\n");
3705 $$ = bfin_gen_pseudodbg (2, $2.regno & CODE_MASK, 0);
3712 /* Register rules. */
3714 REG_A: REG_A_DOUBLE_ZERO
3732 | LPAREN M COMMA MMOD RPAREN
3737 | LPAREN MMOD COMMA M RPAREN
3742 | LPAREN MMOD RPAREN
3754 asr_asl: LPAREN ASL RPAREN
3835 | LPAREN asr_asl_0 RPAREN
3847 | LPAREN asr_asl_0 COMMA sco RPAREN
3853 | LPAREN sco COMMA asr_asl_0 RPAREN
3913 | LPAREN V COMMA S RPAREN
3918 | LPAREN S COMMA V RPAREN
3980 | LPAREN MMOD RPAREN
3983 return yyerror ("Bad modifier");
3987 | LPAREN MMOD COMMA R RPAREN
3990 return yyerror ("Bad modifier");
3994 | LPAREN R COMMA MMOD RPAREN
3997 return yyerror ("Bad modifier");
4024 | LPAREN MMOD RPAREN
4029 return yyerror ("Only (W32) allowed");
4037 | LPAREN MMOD RPAREN
4042 return yyerror ("(IU) expected");
4046 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
4052 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
4104 $$.r0 = 1; /* HL. */
4107 $$.aop = 0; /* aop. */
4112 $$.r0 = 1; /* HL. */
4115 $$.aop = 1; /* aop. */
4118 | LPAREN RNDL RPAREN
4120 $$.r0 = 0; /* HL. */
4123 $$.aop = 0; /* aop. */
4128 $$.r0 = 0; /* HL. */
4134 | LPAREN RNDH COMMA R RPAREN
4136 $$.r0 = 1; /* HL. */
4139 $$.aop = 0; /* aop. */
4141 | LPAREN TH COMMA R RPAREN
4143 $$.r0 = 1; /* HL. */
4146 $$.aop = 1; /* aop. */
4148 | LPAREN RNDL COMMA R RPAREN
4150 $$.r0 = 0; /* HL. */
4153 $$.aop = 0; /* aop. */
4156 | LPAREN TL COMMA R RPAREN
4158 $$.r0 = 0; /* HL. */
4161 $$.aop = 1; /* aop. */
4169 $$.x0 = 0; /* HL. */
4174 $$.x0 = 1; /* HL. */
4176 | LPAREN LO COMMA R RPAREN
4179 $$.x0 = 0; /* HL. */
4181 | LPAREN HI COMMA R RPAREN
4184 $$.x0 = 1; /* HL. */
4202 /* Assignments, Macfuncs. */
4228 if (IS_A1 ($3) && IS_EVEN ($1))
4229 return yyerror ("Cannot move A1 to even register");
4230 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4231 return yyerror ("Cannot move A0 to odd register");
4247 | REG ASSIGN LPAREN a_macfunc RPAREN
4249 if ($4.n && IS_EVEN ($1))
4250 return yyerror ("Cannot move A1 to even register");
4251 else if (!$4.n && !IS_EVEN ($1))
4252 return yyerror ("Cannot move A0 to odd register");
4260 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4262 if ($4.n && !IS_H ($1))
4263 return yyerror ("Cannot move A1 to low half of register");
4264 else if (!$4.n && IS_H ($1))
4265 return yyerror ("Cannot move A0 to high half of register");
4273 | HALF_REG ASSIGN REG_A
4275 if (IS_A1 ($3) && !IS_H ($1))
4276 return yyerror ("Cannot move A1 to low half of register");
4277 else if (!IS_A1 ($3) && IS_H ($1))
4278 return yyerror ("Cannot move A0 to high half of register");
4291 a_assign multiply_halfregs
4298 | a_plusassign multiply_halfregs
4305 | a_minusassign multiply_halfregs
4315 HALF_REG STAR HALF_REG
4317 if (IS_DREG ($1) && IS_DREG ($3))
4323 return yyerror ("Dregs expected");
4347 CCREG cc_op STATUS_REG
4359 | STATUS_REG cc_op CCREG
4373 /* Expressions and Symbols. */
4377 Expr_Node_Value val;
4378 val.s_value = S_GET_NAME($1);
4379 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4385 { $$ = BFD_RELOC_BFIN_GOT; }
4387 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4389 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4392 got: symbol AT any_gotrel
4394 Expr_Node_Value val;
4396 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4419 Expr_Node_Value val;
4421 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4427 | LPAREN expr_1 RPAREN
4433 $$ = unary (Expr_Op_Type_COMP, $2);
4435 | MINUS expr_1 %prec TILDA
4437 $$ = unary (Expr_Op_Type_NEG, $2);
4447 expr_1: expr_1 STAR expr_1
4449 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4451 | expr_1 SLASH expr_1
4453 $$ = binary (Expr_Op_Type_Div, $1, $3);
4455 | expr_1 PERCENT expr_1
4457 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4459 | expr_1 PLUS expr_1
4461 $$ = binary (Expr_Op_Type_Add, $1, $3);
4463 | expr_1 MINUS expr_1
4465 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4467 | expr_1 LESS_LESS expr_1
4469 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4471 | expr_1 GREATER_GREATER expr_1
4473 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4475 | expr_1 AMPERSAND expr_1
4477 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4479 | expr_1 CARET expr_1
4481 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4485 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4497 mkexpr (int x, SYMBOL_T s)
4499 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4506 value_match (Expr_Node *exp, int sz, int sign, int mul, int issigned)
4508 int umax = (1 << sz) - 1;
4509 int min = -1 << (sz - 1);
4510 int max = (1 << (sz - 1)) - 1;
4512 int v = (EXPR_VALUE (exp)) & 0xffffffff;
4516 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4527 if (v >= min && v <= max) return 1;
4530 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4534 if (v <= umax && v >= 0)
4537 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4542 /* Return the expression structure that allows symbol operations.
4543 If the left and right children are constants, do the operation. */
4545 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4547 Expr_Node_Value val;
4549 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4553 case Expr_Op_Type_Add:
4554 x->value.i_value += y->value.i_value;
4556 case Expr_Op_Type_Sub:
4557 x->value.i_value -= y->value.i_value;
4559 case Expr_Op_Type_Mult:
4560 x->value.i_value *= y->value.i_value;
4562 case Expr_Op_Type_Div:
4563 if (y->value.i_value == 0)
4564 error ("Illegal Expression: Division by zero.");
4566 x->value.i_value /= y->value.i_value;
4568 case Expr_Op_Type_Mod:
4569 x->value.i_value %= y->value.i_value;
4571 case Expr_Op_Type_Lshift:
4572 x->value.i_value <<= y->value.i_value;
4574 case Expr_Op_Type_Rshift:
4575 x->value.i_value >>= y->value.i_value;
4577 case Expr_Op_Type_BAND:
4578 x->value.i_value &= y->value.i_value;
4580 case Expr_Op_Type_BOR:
4581 x->value.i_value |= y->value.i_value;
4583 case Expr_Op_Type_BXOR:
4584 x->value.i_value ^= y->value.i_value;
4586 case Expr_Op_Type_LAND:
4587 x->value.i_value = x->value.i_value && y->value.i_value;
4589 case Expr_Op_Type_LOR:
4590 x->value.i_value = x->value.i_value || y->value.i_value;
4594 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4598 /* Canonicalize order to EXPR OP CONSTANT. */
4599 if (x->type == Expr_Node_Constant)
4605 /* Canonicalize subtraction of const to addition of negated const. */
4606 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4608 op = Expr_Op_Type_Add;
4609 y->value.i_value = -y->value.i_value;
4611 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4612 && x->Right_Child->type == Expr_Node_Constant)
4614 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4616 x->Right_Child->value.i_value += y->value.i_value;
4621 /* Create a new expression structure. */
4623 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4627 unary (Expr_Op_Type op, Expr_Node *x)
4629 if (x->type == Expr_Node_Constant)
4633 case Expr_Op_Type_NEG:
4634 x->value.i_value = -x->value.i_value;
4636 case Expr_Op_Type_COMP:
4637 x->value.i_value = ~x->value.i_value;
4640 error ("%s:%d: Internal assembler error\n", __FILE__, __LINE__);
4646 /* Create a new expression structure. */
4647 Expr_Node_Value val;
4649 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4653 int debug_codeselection = 0;
4655 notethat (char *format, ...)
4658 va_start (ap, format);
4659 if (debug_codeselection)
4661 vfprintf (errorf, format, ap);
4667 main (int argc, char **argv)