1 /* bfin-parse.y ADI Blackfin parser
2 Copyright 2005, 2006, 2007
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
26 #include "bfin-aux.h" // opcode generating auxiliaries
28 #include "elf/common.h"
31 #define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
32 bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
34 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
35 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
38 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
39 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
42 #define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls) \
43 bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
45 #define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls) \
46 bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
48 #define LDIMMHALF_R(reg, h, s, z, hword) \
49 bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
51 #define LDIMMHALF_R5(reg, h, s, z, hword) \
52 bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
54 #define LDSTIDXI(ptr, reg, w, sz, z, offset) \
55 bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
57 #define LDST(ptr, reg, aop, sz, z, w) \
58 bfin_gen_ldst (ptr, reg, aop, sz, z, w)
60 #define LDSTII(ptr, reg, offset, w, op) \
61 bfin_gen_ldstii (ptr, reg, offset, w, op)
63 #define DSPLDST(i, m, reg, aop, w) \
64 bfin_gen_dspldst (i, reg, aop, w, m)
66 #define LDSTPMOD(ptr, reg, idx, aop, w) \
67 bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
69 #define LDSTIIFP(offset, reg, w) \
70 bfin_gen_ldstiifp (reg, offset, w)
72 #define LOGI2OP(dst, src, opc) \
73 bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
75 #define ALU2OP(dst, src, opc) \
76 bfin_gen_alu2op (dst, src, opc)
78 #define BRCC(t, b, offset) \
79 bfin_gen_brcc (t, b, offset)
81 #define UJUMP(offset) \
82 bfin_gen_ujump (offset)
84 #define PROGCTRL(prgfunc, poprnd) \
85 bfin_gen_progctrl (prgfunc, poprnd)
87 #define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
88 bfin_gen_pushpopmultiple (dr, pr, d, p, w)
90 #define PUSHPOPREG(reg, w) \
91 bfin_gen_pushpopreg (reg, w)
93 #define CALLA(addr, s) \
94 bfin_gen_calla (addr, s)
96 #define LINKAGE(r, framesize) \
97 bfin_gen_linkage (r, framesize)
99 #define COMPI2OPD(dst, src, op) \
100 bfin_gen_compi2opd (dst, src, op)
102 #define COMPI2OPP(dst, src, op) \
103 bfin_gen_compi2opp (dst, src, op)
105 #define DAGMODIK(i, op) \
106 bfin_gen_dagmodik (i, op)
108 #define DAGMODIM(i, m, op, br) \
109 bfin_gen_dagmodim (i, m, op, br)
111 #define COMP3OP(dst, src0, src1, opc) \
112 bfin_gen_comp3op (src0, src1, dst, opc)
114 #define PTR2OP(dst, src, opc) \
115 bfin_gen_ptr2op (dst, src, opc)
117 #define CCFLAG(x, y, opc, i, g) \
118 bfin_gen_ccflag (x, y, opc, i, g)
120 #define CCMV(src, dst, t) \
121 bfin_gen_ccmv (src, dst, t)
123 #define CACTRL(reg, a, op) \
124 bfin_gen_cactrl (reg, a, op)
126 #define LOOPSETUP(soffset, c, rop, eoffset, reg) \
127 bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
129 #define HL2(r1, r0) (IS_H (r1) << 1 | IS_H (r0))
130 #define IS_RANGE(bits, expr, sign, mul) \
131 value_match(expr, bits, sign, mul, 1)
132 #define IS_URANGE(bits, expr, sign, mul) \
133 value_match(expr, bits, sign, mul, 0)
134 #define IS_CONST(expr) (expr->type == Expr_Node_Constant)
135 #define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
136 #define IS_IMM(expr, bits) value_match (expr, bits, 0, 1, 1)
137 #define IS_UIMM(expr, bits) value_match (expr, bits, 0, 1, 0)
139 #define IS_PCREL4(expr) \
140 (value_match (expr, 4, 0, 2, 0))
142 #define IS_LPPCREL10(expr) \
143 (value_match (expr, 10, 0, 2, 0))
145 #define IS_PCREL10(expr) \
146 (value_match (expr, 10, 0, 2, 1))
148 #define IS_PCREL12(expr) \
149 (value_match (expr, 12, 0, 2, 1))
151 #define IS_PCREL24(expr) \
152 (value_match (expr, 24, 0, 2, 1))
155 static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
160 static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
161 static Expr_Node *unary (Expr_Op_Type, Expr_Node *);
163 static void notethat (char *format, ...);
165 char *current_inputline;
167 int yyerror (char *msg);
169 void error (char *format, ...)
174 va_start (ap, format);
175 vsprintf (buffer, format, ap);
187 else if (yytext[0] != ';')
188 error ("%s. Input text was %s.", msg, yytext);
196 in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
198 int val = EXPR_VALUE (expr);
199 if (expr->type != Expr_Node_Constant)
201 if (val < from || val > to)
203 return (val & mask) == 0;
206 extern int yylex (void);
208 #define imm3(x) EXPR_VALUE (x)
209 #define imm4(x) EXPR_VALUE (x)
210 #define uimm4(x) EXPR_VALUE (x)
211 #define imm5(x) EXPR_VALUE (x)
212 #define uimm5(x) EXPR_VALUE (x)
213 #define imm6(x) EXPR_VALUE (x)
214 #define imm7(x) EXPR_VALUE (x)
215 #define imm16(x) EXPR_VALUE (x)
216 #define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
217 #define uimm16(x) EXPR_VALUE (x)
219 /* Return true if a value is inside a range. */
220 #define IN_RANGE(x, low, high) \
221 (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
223 /* Auxiliary functions. */
226 neg_value (Expr_Node *expr)
228 expr->value.i_value = -expr->value.i_value;
232 valid_dreg_pair (Register *reg1, Expr_Node *reg2)
234 if (!IS_DREG (*reg1))
236 yyerror ("Dregs expected");
240 if (reg1->regno != 1 && reg1->regno != 3)
242 yyerror ("Bad register pair");
246 if (imm7 (reg2) != reg1->regno - 1)
248 yyerror ("Bad register pair");
257 check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
259 if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
260 || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
261 return yyerror ("Source multiplication register mismatch");
267 /* Check mac option. */
270 check_macfunc_option (Macfunc *a, Opt_mode *opt)
272 /* Default option is always valid. */
276 if ((a->op == 3 && a->w == 1 && a->P == 1
277 && opt->mod != M_FU && opt->mod != M_S2RND && opt->mod != M_ISS2)
278 || (a->op == 3 && a->w == 1 && a->P == 0
279 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
280 && opt->mod != M_T && opt->mod != M_S2RND && opt->mod != M_ISS2
282 || (a->w == 0 && a->P == 0
283 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_W32)
284 || (a->w == 1 && a->P == 1
285 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_S2RND
286 && opt->mod != M_ISS2)
287 || (a->w == 1 && a->P == 0
288 && opt->mod != M_FU && opt->mod != M_IS && opt->mod != M_IU
289 && opt->mod != M_T && opt->mod != M_TFU && opt->mod != M_S2RND
290 && opt->mod != M_ISS2 && opt->mod != M_IH))
296 /* Check (vector) mac funcs and ops. */
299 check_macfuncs (Macfunc *aa, Opt_mode *opa,
300 Macfunc *ab, Opt_mode *opb)
302 /* Variables for swapping. */
306 /* The option mode should be put at the end of the second instruction
307 of the vector except M, which should follow MAC1 instruction. */
309 return yyerror ("Bad opt mode");
311 /* If a0macfunc comes before a1macfunc, swap them. */
315 /* (M) is not allowed here. */
317 return yyerror ("(M) not allowed with A0MAC");
319 return yyerror ("Vector AxMACs can't be same");
321 mtmp = *aa; *aa = *ab; *ab = mtmp;
322 otmp = *opa; *opa = *opb; *opb = otmp;
327 return yyerror ("(M) not allowed with A0MAC");
329 return yyerror ("Vector AxMACs can't be same");
332 /* If both ops are one of 0, 1, or 2, we have multiply_halfregs in both
333 assignment_or_macfuncs. */
334 if ((aa->op == 0 || aa->op == 1 || aa->op == 2)
335 && (ab->op == 0 || ab->op == 1 || ab->op == 2))
337 if (check_multiply_halfregs (aa, ab) < 0)
342 /* Only one of the assign_macfuncs has a half reg multiply
343 Evil trick: Just 'OR' their source register codes:
344 We can do that, because we know they were initialized to 0
345 in the rules that don't use multiply_halfregs. */
346 aa->s0.regno |= (ab->s0.regno & CODE_MASK);
347 aa->s1.regno |= (ab->s1.regno & CODE_MASK);
350 if (aa->w == ab->w && aa->P != ab->P)
352 return yyerror ("macfuncs must differ");
353 if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
354 return yyerror ("Destination Dregs must differ by one");
356 /* We assign to full regs, thus obey even/odd rules. */
357 else if ((aa->w && aa->P && IS_EVEN (aa->dst))
358 || (ab->w && ab->P && !IS_EVEN (ab->dst)))
359 return yyerror ("Even/Odd register assignment mismatch");
360 /* We assign to half regs, thus obey hi/low rules. */
361 else if ( (aa->w && !aa->P && !IS_H (aa->dst))
362 || (ab->w && !aa->P && IS_H (ab->dst)))
363 return yyerror ("High/Low register assignment mismatch");
365 /* Make sure mod flags get ORed, too. */
366 opb->mod |= opa->mod;
369 if (check_macfunc_option (aa, opb) < 0
370 && check_macfunc_option (ab, opb) < 0)
371 return yyerror ("bad option");
373 /* Make sure first macfunc has got both P flags ORed. */
381 is_group1 (INSTR_T x)
383 /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii. */
384 if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
391 is_group2 (INSTR_T x)
393 if ((((x->value & 0xfc00) == 0x9c00) /* dspLDST. */
394 && !((x->value & 0xfde0) == 0x9c60) /* dagMODim. */
395 && !((x->value & 0xfde0) == 0x9ce0) /* dagMODim with bit rev. */
396 && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik. */
397 || (x->value == 0x0000))
411 struct { int r0; int s0; int x0; int aop; } modcodes;
412 struct { int r0; } r0;
419 /* Vector Specific. */
420 %token BYTEOP16P BYTEOP16M
421 %token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
422 %token BYTEUNPACK BYTEPACK
425 %token ALIGN8 ALIGN16 ALIGN24
427 %token EXTRACT DEPOSIT EXPADJ SEARCH
428 %token ONES SIGN SIGNBITS
436 %token CCREG BYTE_DREG
437 %token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
438 %token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
443 %token RTI RTS RTX RTN RTE
454 %token JUMP JUMP_DOT_S JUMP_DOT_L
461 %token NOT TILDA BANG
467 %token MINUS PLUS STAR SLASH
471 %token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
472 %token _MINUS_MINUS _PLUS_PLUS
474 /* Shift/rotate ops. */
475 %token SHIFT LSHIFT ASHIFT BXORSHIFT
476 %token _GREATER_GREATER_GREATER_THAN_ASSIGN
478 %token LESS_LESS GREATER_GREATER
479 %token _GREATER_GREATER_GREATER
480 %token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
483 /* In place operators. */
484 %token ASSIGN _STAR_ASSIGN
485 %token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
486 %token _MINUS_ASSIGN _PLUS_ASSIGN
488 /* Assignments, comparisons. */
489 %token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
494 %token FLUSHINV FLUSH
495 %token IFLUSH PREFETCH
512 %token R RND RNDL RNDH RND12 RND20
517 %token BITTGL BITCLR BITSET BITTST BITMUX
520 %token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
522 /* Semantic auxiliaries. */
525 %token COLON SEMICOLON
526 %token RPAREN LPAREN LBRACK RBRACK
530 %token GOT GOT17M4 FUNCDESC_GOT17M4
540 %type <modcodes> byteop_mod
542 %type <reg> a_plusassign
543 %type <reg> a_minusassign
544 %type <macfunc> multiply_halfregs
545 %type <macfunc> assign_macfunc
546 %type <macfunc> a_macfunc
550 %type <modcodes> vsmod
551 %type <modcodes> ccstat
554 %type <reg> reg_with_postinc
555 %type <reg> reg_with_predec
559 %type <symbol> SYMBOL
562 %type <reg> BYTE_DREG
563 %type <reg> REG_A_DOUBLE_ZERO
564 %type <reg> REG_A_DOUBLE_ONE
566 %type <reg> STATUS_REG
570 %type <modcodes> smod
571 %type <modcodes> b3_op
572 %type <modcodes> rnd_op
573 %type <modcodes> post_op
575 %type <r0> iu_or_nothing
576 %type <r0> plus_minus
580 %type <modcodes> amod0
581 %type <modcodes> amod1
582 %type <modcodes> amod2
584 %type <r0> w32_or_nothing
588 %type <expr> got_or_expr
590 %type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
592 /* Precedence rules. */
596 %left LESS_LESS GREATER_GREATER
598 %left STAR SLASH PERCENT
609 if (insn == (INSTR_T) 0)
610 return NO_INSN_GENERATED;
611 else if (insn == (INSTR_T) - 1)
612 return SEMANTIC_ERROR;
614 return INSN_GENERATED;
619 /* Parallel instructions. */
620 | asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
622 if (($1->value & 0xf800) == 0xc000)
624 if (is_group1 ($3) && is_group2 ($5))
625 $$ = bfin_gen_multi_instr ($1, $3, $5);
626 else if (is_group2 ($3) && is_group1 ($5))
627 $$ = bfin_gen_multi_instr ($1, $5, $3);
629 return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
631 else if (($3->value & 0xf800) == 0xc000)
633 if (is_group1 ($1) && is_group2 ($5))
634 $$ = bfin_gen_multi_instr ($3, $1, $5);
635 else if (is_group2 ($1) && is_group1 ($5))
636 $$ = bfin_gen_multi_instr ($3, $5, $1);
638 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
640 else if (($5->value & 0xf800) == 0xc000)
642 if (is_group1 ($1) && is_group2 ($3))
643 $$ = bfin_gen_multi_instr ($5, $1, $3);
644 else if (is_group2 ($1) && is_group1 ($3))
645 $$ = bfin_gen_multi_instr ($5, $3, $1);
647 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
650 error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
653 | asm_1 DOUBLE_BAR asm_1 SEMICOLON
655 if (($1->value & 0xf800) == 0xc000)
658 $$ = bfin_gen_multi_instr ($1, $3, 0);
659 else if (is_group2 ($3))
660 $$ = bfin_gen_multi_instr ($1, 0, $3);
662 return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
664 else if (($3->value & 0xf800) == 0xc000)
667 $$ = bfin_gen_multi_instr ($3, $1, 0);
668 else if (is_group2 ($1))
669 $$ = bfin_gen_multi_instr ($3, 0, $1);
671 return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
673 else if (is_group1 ($1) && is_group2 ($3))
674 $$ = bfin_gen_multi_instr (0, $1, $3);
675 else if (is_group2 ($1) && is_group1 ($3))
676 $$ = bfin_gen_multi_instr (0, $3, $1);
678 return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
693 $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
695 | assign_macfunc opt_mode
699 int h00, h10, h01, h11;
701 if (check_macfunc_option (&$1, &$2) < 0)
702 return yyerror ("bad option");
707 return yyerror ("(m) not allowed with a0 unit");
726 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
727 &$1.dst, op0, &$1.s0, &$1.s1, w0);
733 | assign_macfunc opt_mode COMMA assign_macfunc opt_mode
737 if (check_macfuncs (&$1, &$2, &$4, &$5) < 0)
739 notethat ("assign_macfunc (.), assign_macfunc (.)\n");
746 $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
747 IS_H ($1.s0), IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
748 dst, $4.op, &$1.s0, &$1.s1, $4.w);
755 notethat ("dsp32alu: DISALGNEXCPT\n");
756 $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
758 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
760 if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
762 notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
763 $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
766 return yyerror ("Register mismatch");
768 | HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
770 if (!IS_A1 ($4) && IS_A1 ($5))
772 notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
773 $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
776 return yyerror ("Register mismatch");
778 | A_ZERO_DOT_H ASSIGN HALF_REG
780 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
781 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
783 | A_ONE_DOT_H ASSIGN HALF_REG
785 notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
786 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
788 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
789 COLON expr COMMA REG COLON expr RPAREN aligndir
791 if (!IS_DREG ($2) || !IS_DREG ($4))
792 return yyerror ("Dregs expected");
793 else if (!valid_dreg_pair (&$9, $11))
794 return yyerror ("Bad dreg pair");
795 else if (!valid_dreg_pair (&$13, $15))
796 return yyerror ("Bad dreg pair");
799 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
800 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
804 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
805 REG COLON expr RPAREN aligndir
807 if (!IS_DREG ($2) || !IS_DREG($4))
808 return yyerror ("Dregs expected");
809 else if (!valid_dreg_pair (&$9, $11))
810 return yyerror ("Bad dreg pair");
811 else if (!valid_dreg_pair (&$13, $15))
812 return yyerror ("Bad dreg pair");
815 notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
816 $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
820 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
822 if (!IS_DREG ($2) || !IS_DREG ($4))
823 return yyerror ("Dregs expected");
824 else if (!valid_dreg_pair (&$8, $10))
825 return yyerror ("Bad dreg pair");
828 notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
829 $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
832 | LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
834 if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
836 notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
837 $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
840 return yyerror ("Register mismatch");
842 | REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
843 REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
845 if (IS_DREG ($1) && IS_DREG ($7))
847 notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h \n");
848 $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
851 return yyerror ("Register mismatch");
855 | REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1
857 if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
858 && IS_A1 ($9) && !IS_A1 ($11))
860 notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
861 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
864 else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
865 && !IS_A1 ($9) && IS_A1 ($11))
867 notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
868 $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
871 return yyerror ("Register mismatch");
874 | REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
877 return yyerror ("Operators must differ");
879 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
880 && REG_SAME ($3, $9) && REG_SAME ($5, $11))
882 notethat ("dsp32alu: dregs = dregs + dregs,"
883 "dregs = dregs - dregs (amod1)\n");
884 $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
887 return yyerror ("Register mismatch");
890 /* Bar Operations. */
892 | REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2
894 if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
895 return yyerror ("Differing source registers");
897 if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7))
898 return yyerror ("Dregs expected");
901 if ($4.r0 == 1 && $10.r0 == 2)
903 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
904 $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
906 else if ($4.r0 == 0 && $10.r0 == 3)
908 notethat ("dsp32alu: dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
909 $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
912 return yyerror ("Bar operand mismatch");
915 | REG ASSIGN ABS REG vmod
919 if (IS_DREG ($1) && IS_DREG ($4))
923 notethat ("dsp32alu: dregs = ABS dregs (v)\n");
928 /* Vector version of ABS. */
929 notethat ("dsp32alu: dregs = ABS dregs\n");
932 $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
935 return yyerror ("Dregs expected");
939 notethat ("dsp32alu: Ax = ABS Ax\n");
940 $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
942 | A_ZERO_DOT_L ASSIGN HALF_REG
946 notethat ("dsp32alu: A0.l = reg_half\n");
947 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
950 return yyerror ("A0.l = Rx.l expected");
952 | A_ONE_DOT_L ASSIGN HALF_REG
956 notethat ("dsp32alu: A1.l = reg_half\n");
957 $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
960 return yyerror ("A1.l = Rx.l expected");
963 | REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
965 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
967 notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
968 $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
971 return yyerror ("Dregs expected");
974 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
977 return yyerror ("Dregs expected");
978 else if (!valid_dreg_pair (&$5, $7))
979 return yyerror ("Bad dreg pair");
980 else if (!valid_dreg_pair (&$9, $11))
981 return yyerror ("Bad dreg pair");
984 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
985 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
988 | REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
991 return yyerror ("Dregs expected");
992 else if (!valid_dreg_pair (&$5, $7))
993 return yyerror ("Bad dreg pair");
994 else if (!valid_dreg_pair (&$9, $11))
995 return yyerror ("Bad dreg pair");
998 notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
999 $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
1003 | REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1007 return yyerror ("Dregs expected");
1008 else if (!valid_dreg_pair (&$5, $7))
1009 return yyerror ("Bad dreg pair");
1010 else if (!valid_dreg_pair (&$9, $11))
1011 return yyerror ("Bad dreg pair");
1014 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1015 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
1019 | REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1023 return yyerror ("Dregs expected");
1024 else if (!valid_dreg_pair (&$5, $7))
1025 return yyerror ("Bad dreg pair");
1026 else if (!valid_dreg_pair (&$9, $11))
1027 return yyerror ("Bad dreg pair");
1030 notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
1031 $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
1035 | REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
1039 return yyerror ("Dregs expected");
1040 else if (!valid_dreg_pair (&$5, $7))
1041 return yyerror ("Bad dreg pair");
1042 else if (!valid_dreg_pair (&$9, $11))
1043 return yyerror ("Bad dreg pair");
1046 notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
1047 $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
1051 | REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
1053 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1055 notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
1056 $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
1059 return yyerror ("Dregs expected");
1062 | HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
1063 HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG
1065 if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
1067 notethat ("dsp32alu: dregs_hi = dregs_lo ="
1068 "SIGN (dregs_hi) * dregs_hi + "
1069 "SIGN (dregs_lo) * dregs_lo \n");
1071 $$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
1074 return yyerror ("Dregs expected");
1076 | REG ASSIGN REG plus_minus REG amod1
1078 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1082 /* No saturation flag specified, generate the 16 bit variant. */
1083 notethat ("COMP3op: dregs = dregs +- dregs\n");
1084 $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
1088 /* Saturation flag specified, generate the 32 bit variant. */
1089 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
1090 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1094 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
1096 notethat ("COMP3op: pregs = pregs + pregs\n");
1097 $$ = COMP3OP (&$1, &$3, &$5, 5);
1100 return yyerror ("Dregs expected");
1102 | REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
1106 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
1113 notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
1114 $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
1117 return yyerror ("Dregs expected");
1120 | a_assign MINUS REG_A
1122 notethat ("dsp32alu: Ax = - Ax\n");
1123 $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
1125 | HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
1127 notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
1128 $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
1129 $6.s0, $6.x0, HL2 ($3, $5));
1131 | a_assign a_assign expr
1133 if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
1135 notethat ("dsp32alu: A1 = A0 = 0\n");
1136 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
1139 return yyerror ("Bad value, 0 expected");
1143 | a_assign REG_A LPAREN S RPAREN
1145 if (REG_SAME ($1, $2))
1147 notethat ("dsp32alu: Ax = Ax (S)\n");
1148 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
1151 return yyerror ("Registers must be equal");
1154 | HALF_REG ASSIGN REG LPAREN RND RPAREN
1158 notethat ("dsp32alu: dregs_half = dregs (RND)\n");
1159 $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
1162 return yyerror ("Dregs expected");
1165 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
1167 if (IS_DREG ($3) && IS_DREG ($5))
1169 notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
1170 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
1173 return yyerror ("Dregs expected");
1176 | HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
1178 if (IS_DREG ($3) && IS_DREG ($5))
1180 notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
1181 $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
1184 return yyerror ("Dregs expected");
1189 if (!REG_SAME ($1, $2))
1191 notethat ("dsp32alu: An = Am\n");
1192 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
1195 return yyerror ("Accu reg arguments must differ");
1202 notethat ("dsp32alu: An = dregs\n");
1203 $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
1206 return yyerror ("Dregs expected");
1209 | REG ASSIGN HALF_REG xpmod
1213 if ($1.regno == REG_A0x && IS_DREG ($3))
1215 notethat ("dsp32alu: A0.x = dregs_lo\n");
1216 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
1218 else if ($1.regno == REG_A1x && IS_DREG ($3))
1220 notethat ("dsp32alu: A1.x = dregs_lo\n");
1221 $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
1223 else if (IS_DREG ($1) && IS_DREG ($3))
1225 notethat ("ALU2op: dregs = dregs_lo\n");
1226 $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
1229 return yyerror ("Register mismatch");
1232 return yyerror ("Low reg expected");
1235 | HALF_REG ASSIGN expr
1237 notethat ("LDIMMhalf: pregs_half = imm16\n");
1239 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1240 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1241 return yyerror ("Wrong register for load immediate");
1243 if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
1244 return yyerror ("Constant out of range");
1246 $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
1251 notethat ("dsp32alu: An = 0\n");
1254 return yyerror ("0 expected");
1256 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
1259 | REG ASSIGN expr xpmod1
1261 if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
1262 && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
1263 return yyerror ("Wrong register for load immediate");
1267 /* 7 bit immediate value if possible.
1268 We will check for that constant value for efficiency
1269 If it goes to reloc, it will be 16 bit. */
1270 if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
1272 notethat ("COMPI2opD: dregs = imm7 (x) \n");
1273 $$ = COMPI2OPD (&$1, imm7 ($3), 0);
1275 else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
1277 notethat ("COMPI2opP: pregs = imm7 (x)\n");
1278 $$ = COMPI2OPP (&$1, imm7 ($3), 0);
1282 if (IS_CONST ($3) && !IS_IMM ($3, 16))
1283 return yyerror ("Immediate value out of range");
1285 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1287 $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
1292 /* (z) There is no 7 bit zero extended instruction.
1293 If the expr is a relocation, generate it. */
1295 if (IS_CONST ($3) && !IS_UIMM ($3, 16))
1296 return yyerror ("Immediate value out of range");
1298 notethat ("LDIMMhalf: regs = luimm16 (x)\n");
1300 $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
1304 | HALF_REG ASSIGN REG
1307 return yyerror ("Low reg expected");
1309 if (IS_DREG ($1) && $3.regno == REG_A0x)
1311 notethat ("dsp32alu: dregs_lo = A0.x\n");
1312 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
1314 else if (IS_DREG ($1) && $3.regno == REG_A1x)
1316 notethat ("dsp32alu: dregs_lo = A1.x\n");
1317 $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
1320 return yyerror ("Register mismatch");
1323 | REG ASSIGN REG op_bar_op REG amod0
1325 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1327 notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
1328 $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
1331 return yyerror ("Register mismatch");
1334 | REG ASSIGN BYTE_DREG xpmod
1336 if (IS_DREG ($1) && IS_DREG ($3))
1338 notethat ("ALU2op: dregs = dregs_byte\n");
1339 $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
1342 return yyerror ("Register mismatch");
1345 | a_assign ABS REG_A COMMA a_assign ABS REG_A
1347 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1349 notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
1350 $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
1353 return yyerror ("Register mismatch");
1356 | a_assign MINUS REG_A COMMA a_assign MINUS REG_A
1358 if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
1360 notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
1361 $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
1364 return yyerror ("Register mismatch");
1367 | a_minusassign REG_A w32_or_nothing
1369 if (!IS_A1 ($1) && IS_A1 ($2))
1371 notethat ("dsp32alu: A0 -= A1\n");
1372 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
1375 return yyerror ("Register mismatch");
1378 | REG _MINUS_ASSIGN expr
1380 if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
1382 notethat ("dagMODik: iregs -= 4\n");
1383 $$ = DAGMODIK (&$1, 3);
1385 else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
1387 notethat ("dagMODik: iregs -= 2\n");
1388 $$ = DAGMODIK (&$1, 1);
1391 return yyerror ("Register or value mismatch");
1394 | REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
1396 if (IS_IREG ($1) && IS_MREG ($3))
1398 notethat ("dagMODim: iregs += mregs (opt_brev)\n");
1400 $$ = DAGMODIM (&$1, &$3, 0, 1);
1402 else if (IS_PREG ($1) && IS_PREG ($3))
1404 notethat ("PTR2op: pregs += pregs (BREV )\n");
1405 $$ = PTR2OP (&$1, &$3, 5);
1408 return yyerror ("Register mismatch");
1411 | REG _MINUS_ASSIGN REG
1413 if (IS_IREG ($1) && IS_MREG ($3))
1415 notethat ("dagMODim: iregs -= mregs\n");
1416 $$ = DAGMODIM (&$1, &$3, 1, 0);
1418 else if (IS_PREG ($1) && IS_PREG ($3))
1420 notethat ("PTR2op: pregs -= pregs\n");
1421 $$ = PTR2OP (&$1, &$3, 0);
1424 return yyerror ("Register mismatch");
1427 | REG_A _PLUS_ASSIGN REG_A w32_or_nothing
1429 if (!IS_A1 ($1) && IS_A1 ($3))
1431 notethat ("dsp32alu: A0 += A1 (W32)\n");
1432 $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
1435 return yyerror ("Register mismatch");
1438 | REG _PLUS_ASSIGN REG
1440 if (IS_IREG ($1) && IS_MREG ($3))
1442 notethat ("dagMODim: iregs += mregs\n");
1443 $$ = DAGMODIM (&$1, &$3, 0, 0);
1446 return yyerror ("iregs += mregs expected");
1449 | REG _PLUS_ASSIGN expr
1453 if (EXPR_VALUE ($3) == 4)
1455 notethat ("dagMODik: iregs += 4\n");
1456 $$ = DAGMODIK (&$1, 2);
1458 else if (EXPR_VALUE ($3) == 2)
1460 notethat ("dagMODik: iregs += 2\n");
1461 $$ = DAGMODIK (&$1, 0);
1464 return yyerror ("iregs += [ 2 | 4 ");
1466 else if (IS_PREG ($1) && IS_IMM ($3, 7))
1468 notethat ("COMPI2opP: pregs += imm7\n");
1469 $$ = COMPI2OPP (&$1, imm7 ($3), 1);
1471 else if (IS_DREG ($1) && IS_IMM ($3, 7))
1473 notethat ("COMPI2opD: dregs += imm7\n");
1474 $$ = COMPI2OPD (&$1, imm7 ($3), 1);
1476 else if ((IS_DREG ($1) || IS_PREG ($1)) && IS_CONST ($3))
1477 return yyerror ("Immediate value out of range");
1479 return yyerror ("Register mismatch");
1482 | REG _STAR_ASSIGN REG
1484 if (IS_DREG ($1) && IS_DREG ($3))
1486 notethat ("ALU2op: dregs *= dregs\n");
1487 $$ = ALU2OP (&$1, &$3, 3);
1490 return yyerror ("Register mismatch");
1493 | SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
1495 if (!valid_dreg_pair (&$3, $5))
1496 return yyerror ("Bad dreg pair");
1497 else if (!valid_dreg_pair (&$7, $9))
1498 return yyerror ("Bad dreg pair");
1501 notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
1502 $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
1506 | a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
1508 if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
1510 notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
1511 $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
1514 return yyerror ("Register mismatch");
1517 | REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
1519 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
1520 && REG_SAME ($1, $4))
1522 if (EXPR_VALUE ($9) == 1)
1524 notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
1525 $$ = ALU2OP (&$1, &$6, 4);
1527 else if (EXPR_VALUE ($9) == 2)
1529 notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
1530 $$ = ALU2OP (&$1, &$6, 5);
1533 return yyerror ("Bad shift value");
1535 else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
1536 && REG_SAME ($1, $4))
1538 if (EXPR_VALUE ($9) == 1)
1540 notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
1541 $$ = PTR2OP (&$1, &$6, 6);
1543 else if (EXPR_VALUE ($9) == 2)
1545 notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
1546 $$ = PTR2OP (&$1, &$6, 7);
1549 return yyerror ("Bad shift value");
1552 return yyerror ("Register mismatch");
1556 | REG ASSIGN REG BAR REG
1558 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1560 notethat ("COMP3op: dregs = dregs | dregs\n");
1561 $$ = COMP3OP (&$1, &$3, &$5, 3);
1564 return yyerror ("Dregs expected");
1566 | REG ASSIGN REG CARET REG
1568 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1570 notethat ("COMP3op: dregs = dregs ^ dregs\n");
1571 $$ = COMP3OP (&$1, &$3, &$5, 4);
1574 return yyerror ("Dregs expected");
1576 | REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
1578 if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
1580 if (EXPR_VALUE ($8) == 1)
1582 notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
1583 $$ = COMP3OP (&$1, &$3, &$6, 6);
1585 else if (EXPR_VALUE ($8) == 2)
1587 notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
1588 $$ = COMP3OP (&$1, &$3, &$6, 7);
1591 return yyerror ("Bad shift value");
1594 return yyerror ("Dregs expected");
1596 | CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
1598 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1600 notethat ("CCflag: CC = A0 == A1\n");
1601 $$ = CCFLAG (0, 0, 5, 0, 0);
1604 return yyerror ("AREGs are in bad order or same");
1606 | CCREG ASSIGN REG_A LESS_THAN REG_A
1608 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1610 notethat ("CCflag: CC = A0 < A1\n");
1611 $$ = CCFLAG (0, 0, 6, 0, 0);
1614 return yyerror ("AREGs are in bad order or same");
1616 | CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
1618 if (REG_CLASS($3) == REG_CLASS($5))
1620 notethat ("CCflag: CC = dpregs < dpregs\n");
1621 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1624 return yyerror ("Compare only of same register class");
1626 | CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
1628 if (($6.r0 == 1 && IS_IMM ($5, 3))
1629 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1631 notethat ("CCflag: CC = dpregs < (u)imm3\n");
1632 $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
1635 return yyerror ("Bad constant value");
1637 | CCREG ASSIGN REG _ASSIGN_ASSIGN REG
1639 if (REG_CLASS($3) == REG_CLASS($5))
1641 notethat ("CCflag: CC = dpregs == dpregs\n");
1642 $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
1645 return yyerror ("Compare only of same register class");
1647 | CCREG ASSIGN REG _ASSIGN_ASSIGN expr
1651 notethat ("CCflag: CC = dpregs == imm3\n");
1652 $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
1655 return yyerror ("Bad constant range");
1657 | CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
1659 if ($3.regno == REG_A0 && $5.regno == REG_A1)
1661 notethat ("CCflag: CC = A0 <= A1\n");
1662 $$ = CCFLAG (0, 0, 7, 0, 0);
1665 return yyerror ("AREGs are in bad order or same");
1667 | CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
1669 if (REG_CLASS($3) == REG_CLASS($5))
1671 notethat ("CCflag: CC = pregs <= pregs (..)\n");
1672 $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
1673 1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
1676 return yyerror ("Compare only of same register class");
1678 | CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
1680 if (($6.r0 == 1 && IS_IMM ($5, 3))
1681 || ($6.r0 == 3 && IS_UIMM ($5, 3)))
1685 notethat ("CCflag: CC = dregs <= (u)imm3\n");
1687 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
1689 else if (IS_PREG ($3))
1691 notethat ("CCflag: CC = pregs <= (u)imm3\n");
1693 $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
1696 return yyerror ("Dreg or Preg expected");
1699 return yyerror ("Bad constant value");
1702 | REG ASSIGN REG AMPERSAND REG
1704 if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
1706 notethat ("COMP3op: dregs = dregs & dregs\n");
1707 $$ = COMP3OP (&$1, &$3, &$5, 2);
1710 return yyerror ("Dregs expected");
1715 notethat ("CC2stat operation\n");
1716 $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
1721 if (IS_ALLREG ($1) && IS_ALLREG ($3))
1723 notethat ("REGMV: allregs = allregs\n");
1724 $$ = bfin_gen_regmv (&$3, &$1);
1727 return yyerror ("Register mismatch");
1734 notethat ("CC2dreg: CC = dregs\n");
1735 $$ = bfin_gen_cc2dreg (1, &$3);
1738 return yyerror ("Register mismatch");
1745 notethat ("CC2dreg: dregs = CC\n");
1746 $$ = bfin_gen_cc2dreg (0, &$1);
1749 return yyerror ("Register mismatch");
1752 | CCREG _ASSIGN_BANG CCREG
1754 notethat ("CC2dreg: CC =! CC\n");
1755 $$ = bfin_gen_cc2dreg (3, 0);
1760 | HALF_REG ASSIGN multiply_halfregs opt_mode
1762 notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
1764 if (!IS_H ($1) && $4.MM)
1765 return yyerror ("(M) not allowed with MAC0");
1769 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
1770 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1771 &$1, 0, &$3.s0, &$3.s1, 0);
1775 $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
1776 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1777 &$1, 0, &$3.s0, &$3.s1, 1);
1781 | REG ASSIGN multiply_halfregs opt_mode
1783 /* Odd registers can use (M). */
1785 return yyerror ("Dreg expected");
1787 if (IS_EVEN ($1) && $4.MM)
1788 return yyerror ("(M) not allowed with MAC0");
1792 notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
1794 $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
1795 IS_H ($3.s0), IS_H ($3.s1), 0, 0,
1796 &$1, 0, &$3.s0, &$3.s1, 0);
1800 notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
1801 $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
1802 0, 0, IS_H ($3.s0), IS_H ($3.s1),
1803 &$1, 0, &$3.s0, &$3.s1, 1);
1807 | HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
1808 HALF_REG ASSIGN multiply_halfregs opt_mode
1810 if (!IS_DREG ($1) || !IS_DREG ($6))
1811 return yyerror ("Dregs expected");
1813 if (!IS_HCOMPL($1, $6))
1814 return yyerror ("Dest registers mismatch");
1816 if (check_multiply_halfregs (&$3, &$8) < 0)
1819 if ((!IS_H ($1) && $4.MM)
1820 || (!IS_H ($6) && $9.MM))
1821 return yyerror ("(M) not allowed with MAC0");
1823 notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
1824 "dregs_lo = multiply_halfregs opt_mode\n");
1827 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
1828 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1829 &$1, 0, &$3.s0, &$3.s1, 1);
1831 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
1832 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1833 &$1, 0, &$3.s0, &$3.s1, 1);
1836 | REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode
1838 if (!IS_DREG ($1) || !IS_DREG ($6))
1839 return yyerror ("Dregs expected");
1841 if ((IS_EVEN ($1) && $6.regno - $1.regno != 1)
1842 || (IS_EVEN ($6) && $1.regno - $6.regno != 1))
1843 return yyerror ("Dest registers mismatch");
1845 if (check_multiply_halfregs (&$3, &$8) < 0)
1848 if ((IS_EVEN ($1) && $4.MM)
1849 || (IS_EVEN ($6) && $9.MM))
1850 return yyerror ("(M) not allowed with MAC0");
1852 notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
1853 "dregs = multiply_halfregs opt_mode\n");
1856 $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
1857 IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
1858 &$1, 0, &$3.s0, &$3.s1, 1);
1860 $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 1,
1861 IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
1862 &$1, 0, &$3.s0, &$3.s1, 1);
1867 | a_assign ASHIFT REG_A BY HALF_REG
1869 if (!REG_SAME ($1, $3))
1870 return yyerror ("Aregs must be same");
1872 if (IS_DREG ($5) && !IS_H ($5))
1874 notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
1875 $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
1878 return yyerror ("Dregs expected");
1881 | HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
1883 if (IS_DREG ($6) && !IS_H ($6))
1885 notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
1886 $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
1889 return yyerror ("Dregs expected");
1892 | a_assign REG_A LESS_LESS expr
1894 if (!REG_SAME ($1, $2))
1895 return yyerror ("Aregs must be same");
1897 if (IS_UIMM ($4, 5))
1899 notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
1900 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
1903 return yyerror ("Bad shift value");
1906 | REG ASSIGN REG LESS_LESS expr vsmod
1908 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
1913 notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
1914 $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
1918 notethat ("dsp32shiftimm: dregs = dregs << uimm5 (.)\n");
1919 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
1922 else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
1924 if (EXPR_VALUE ($5) == 2)
1926 notethat ("PTR2op: pregs = pregs << 2\n");
1927 $$ = PTR2OP (&$1, &$3, 1);
1929 else if (EXPR_VALUE ($5) == 1)
1931 notethat ("COMP3op: pregs = pregs << 1\n");
1932 $$ = COMP3OP (&$1, &$3, &$3, 5);
1935 return yyerror ("Bad shift value");
1938 return yyerror ("Bad shift value or register");
1940 | HALF_REG ASSIGN HALF_REG LESS_LESS expr
1942 if (IS_UIMM ($5, 4))
1944 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1945 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
1948 return yyerror ("Bad shift value");
1950 | HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
1952 if (IS_UIMM ($5, 4))
1954 notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
1955 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
1958 return yyerror ("Bad shift value");
1960 | REG ASSIGN ASHIFT REG BY HALF_REG vsmod
1964 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
1969 notethat ("dsp32shift: dregs = ASHIFT dregs BY "
1970 "dregs_lo (V, .)\n");
1976 notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
1978 $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
1981 return yyerror ("Dregs expected");
1985 | HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
1987 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
1989 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
1990 $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
1993 return yyerror ("Bad shift value or register");
1997 | HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
1999 if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
2001 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
2002 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
2004 else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
2006 notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
2007 $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
2010 return yyerror ("Bad shift value or register");
2015 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
2017 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2019 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
2020 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
2023 return yyerror ("Register mismatch");
2026 | REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
2028 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2030 notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
2031 $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
2034 return yyerror ("Register mismatch");
2037 | REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod
2039 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
2041 notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
2042 $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
2045 return yyerror ("Register mismatch");
2048 | a_assign REG_A _GREATER_GREATER_GREATER expr
2050 if (!REG_SAME ($1, $2))
2051 return yyerror ("Aregs must be same");
2053 if (IS_UIMM ($4, 5))
2055 notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
2056 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
2059 return yyerror ("Shift value range error");
2061 | a_assign LSHIFT REG_A BY HALF_REG
2063 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2065 notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
2066 $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
2069 return yyerror ("Register mismatch");
2072 | HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
2074 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2076 notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
2077 $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
2080 return yyerror ("Register mismatch");
2083 | REG ASSIGN LSHIFT REG BY HALF_REG vmod
2085 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2087 notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
2088 $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
2091 return yyerror ("Register mismatch");
2094 | REG ASSIGN SHIFT REG BY HALF_REG
2096 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2098 notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
2099 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
2102 return yyerror ("Register mismatch");
2105 | a_assign REG_A GREATER_GREATER expr
2107 if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
2109 notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
2110 $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
2113 return yyerror ("Accu register expected");
2116 | REG ASSIGN REG GREATER_GREATER expr vmod
2120 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2122 notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
2123 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
2126 return yyerror ("Register mismatch");
2130 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2132 notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
2133 $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
2135 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
2137 notethat ("PTR2op: pregs = pregs >> 2\n");
2138 $$ = PTR2OP (&$1, &$3, 3);
2140 else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
2142 notethat ("PTR2op: pregs = pregs >> 1\n");
2143 $$ = PTR2OP (&$1, &$3, 4);
2146 return yyerror ("Register mismatch");
2149 | HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
2151 if (IS_UIMM ($5, 5))
2153 notethat ("dsp32shiftimm: dregs_half = dregs_half >> uimm5\n");
2154 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
2157 return yyerror ("Register mismatch");
2159 | HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
2161 if (IS_UIMM ($5, 5))
2163 notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
2164 $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
2165 $6.s0, HL2 ($1, $3));
2168 return yyerror ("Register or modifier mismatch");
2172 | REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
2174 if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
2179 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (V, .)\n");
2180 $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2184 notethat ("dsp32shiftimm: dregs = dregs >>> uimm5 (.)\n");
2185 $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
2189 return yyerror ("Register mismatch");
2192 | HALF_REG ASSIGN ONES REG
2194 if (IS_DREG_L ($1) && IS_DREG ($4))
2196 notethat ("dsp32shift: dregs_lo = ONES dregs\n");
2197 $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
2200 return yyerror ("Register mismatch");
2203 | REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
2205 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2207 notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
2208 $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
2211 return yyerror ("Register mismatch");
2214 | HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN
2217 && $7.regno == REG_A0
2218 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2220 notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
2221 $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
2224 return yyerror ("Register mismatch");
2227 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
2230 && $7.regno == REG_A0
2231 && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
2233 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
2234 $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
2237 return yyerror ("Register mismatch");
2240 | HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2242 if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
2244 notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
2245 $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
2248 return yyerror ("Register mismatch");
2251 | a_assign ROT REG_A BY HALF_REG
2253 if (REG_SAME ($1, $3) && IS_DREG_L ($5))
2255 notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
2256 $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
2259 return yyerror ("Register mismatch");
2262 | REG ASSIGN ROT REG BY HALF_REG
2264 if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
2266 notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
2267 $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
2270 return yyerror ("Register mismatch");
2273 | a_assign ROT REG_A BY expr
2277 notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
2278 $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
2281 return yyerror ("Register mismatch");
2284 | REG ASSIGN ROT REG BY expr
2286 if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
2288 $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
2291 return yyerror ("Register mismatch");
2294 | HALF_REG ASSIGN SIGNBITS REG_A
2298 notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
2299 $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
2302 return yyerror ("Register mismatch");
2305 | HALF_REG ASSIGN SIGNBITS REG
2307 if (IS_DREG_L ($1) && IS_DREG ($4))
2309 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
2310 $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
2313 return yyerror ("Register mismatch");
2316 | HALF_REG ASSIGN SIGNBITS HALF_REG
2320 notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
2321 $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
2324 return yyerror ("Register mismatch");
2327 /* The ASR bit is just inverted here. */
2328 | HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl
2330 if (IS_DREG_L ($1) && IS_DREG ($5))
2332 notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
2333 $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
2336 return yyerror ("Register mismatch");
2339 | REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl
2341 if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
2343 notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
2344 $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
2347 return yyerror ("Register mismatch");
2350 | BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
2352 if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
2354 notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
2355 $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
2358 return yyerror ("Register mismatch");
2361 | a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
2363 if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
2365 notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
2366 $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
2369 return yyerror ("Dregs expected");
2373 /* LOGI2op: BITCLR (dregs, uimm5). */
2374 | BITCLR LPAREN REG COMMA expr RPAREN
2376 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2378 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2379 $$ = LOGI2OP ($3, uimm5 ($5), 4);
2382 return yyerror ("Register mismatch");
2385 /* LOGI2op: BITSET (dregs, uimm5). */
2386 | BITSET LPAREN REG COMMA expr RPAREN
2388 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2390 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2391 $$ = LOGI2OP ($3, uimm5 ($5), 2);
2394 return yyerror ("Register mismatch");
2397 /* LOGI2op: BITTGL (dregs, uimm5). */
2398 | BITTGL LPAREN REG COMMA expr RPAREN
2400 if (IS_DREG ($3) && IS_UIMM ($5, 5))
2402 notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
2403 $$ = LOGI2OP ($3, uimm5 ($5), 3);
2406 return yyerror ("Register mismatch");
2409 | CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
2411 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2413 notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
2414 $$ = LOGI2OP ($5, uimm5 ($7), 0);
2417 return yyerror ("Register mismatch or value error");
2420 | CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
2422 if (IS_DREG ($5) && IS_UIMM ($7, 5))
2424 notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
2425 $$ = LOGI2OP ($5, uimm5 ($7), 1);
2428 return yyerror ("Register mismatch or value error");
2431 | IF BANG CCREG REG ASSIGN REG
2433 if ((IS_DREG ($4) || IS_PREG ($4))
2434 && (IS_DREG ($6) || IS_PREG ($6)))
2436 notethat ("ccMV: IF ! CC gregs = gregs\n");
2437 $$ = CCMV (&$6, &$4, 0);
2440 return yyerror ("Register mismatch");
2443 | IF CCREG REG ASSIGN REG
2445 if ((IS_DREG ($5) || IS_PREG ($5))
2446 && (IS_DREG ($3) || IS_PREG ($3)))
2448 notethat ("ccMV: IF CC gregs = gregs\n");
2449 $$ = CCMV (&$5, &$3, 1);
2452 return yyerror ("Register mismatch");
2455 | IF BANG CCREG JUMP expr
2457 if (IS_PCREL10 ($5))
2459 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2460 $$ = BRCC (0, 0, $5);
2463 return yyerror ("Bad jump offset");
2466 | IF BANG CCREG JUMP expr LPAREN BP RPAREN
2468 if (IS_PCREL10 ($5))
2470 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2471 $$ = BRCC (0, 1, $5);
2474 return yyerror ("Bad jump offset");
2477 | IF CCREG JUMP expr
2479 if (IS_PCREL10 ($4))
2481 notethat ("BRCC: IF CC JUMP pcrel11m2\n");
2482 $$ = BRCC (1, 0, $4);
2485 return yyerror ("Bad jump offset");
2488 | IF CCREG JUMP expr LPAREN BP RPAREN
2490 if (IS_PCREL10 ($4))
2492 notethat ("BRCC: IF !CC JUMP pcrel11m2\n");
2493 $$ = BRCC (1, 1, $4);
2496 return yyerror ("Bad jump offset");
2500 notethat ("ProgCtrl: NOP\n");
2501 $$ = PROGCTRL (0, 0);
2506 notethat ("ProgCtrl: RTS\n");
2507 $$ = PROGCTRL (1, 0);
2512 notethat ("ProgCtrl: RTI\n");
2513 $$ = PROGCTRL (1, 1);
2518 notethat ("ProgCtrl: RTX\n");
2519 $$ = PROGCTRL (1, 2);
2524 notethat ("ProgCtrl: RTN\n");
2525 $$ = PROGCTRL (1, 3);
2530 notethat ("ProgCtrl: RTE\n");
2531 $$ = PROGCTRL (1, 4);
2536 notethat ("ProgCtrl: IDLE\n");
2537 $$ = PROGCTRL (2, 0);
2542 notethat ("ProgCtrl: CSYNC\n");
2543 $$ = PROGCTRL (2, 3);
2548 notethat ("ProgCtrl: SSYNC\n");
2549 $$ = PROGCTRL (2, 4);
2554 notethat ("ProgCtrl: EMUEXCPT\n");
2555 $$ = PROGCTRL (2, 5);
2562 notethat ("ProgCtrl: CLI dregs\n");
2563 $$ = PROGCTRL (3, $2.regno & CODE_MASK);
2566 return yyerror ("Dreg expected for CLI");
2573 notethat ("ProgCtrl: STI dregs\n");
2574 $$ = PROGCTRL (4, $2.regno & CODE_MASK);
2577 return yyerror ("Dreg expected for STI");
2580 | JUMP LPAREN REG RPAREN
2584 notethat ("ProgCtrl: JUMP (pregs )\n");
2585 $$ = PROGCTRL (5, $3.regno & CODE_MASK);
2588 return yyerror ("Bad register for indirect jump");
2591 | CALL LPAREN REG RPAREN
2595 notethat ("ProgCtrl: CALL (pregs )\n");
2596 $$ = PROGCTRL (6, $3.regno & CODE_MASK);
2599 return yyerror ("Bad register for indirect call");
2602 | CALL LPAREN PC PLUS REG RPAREN
2606 notethat ("ProgCtrl: CALL (PC + pregs )\n");
2607 $$ = PROGCTRL (7, $5.regno & CODE_MASK);
2610 return yyerror ("Bad register for indirect call");
2613 | JUMP LPAREN PC PLUS REG RPAREN
2617 notethat ("ProgCtrl: JUMP (PC + pregs )\n");
2618 $$ = PROGCTRL (8, $5.regno & CODE_MASK);
2621 return yyerror ("Bad register for indirect jump");
2626 if (IS_UIMM ($2, 4))
2628 notethat ("ProgCtrl: RAISE uimm4\n");
2629 $$ = PROGCTRL (9, uimm4 ($2));
2632 return yyerror ("Bad value for RAISE");
2637 notethat ("ProgCtrl: EMUEXCPT\n");
2638 $$ = PROGCTRL (10, uimm4 ($2));
2641 | TESTSET LPAREN REG RPAREN
2645 notethat ("ProgCtrl: TESTSET (pregs )\n");
2646 $$ = PROGCTRL (11, $3.regno & CODE_MASK);
2649 return yyerror ("Preg expected");
2654 if (IS_PCREL12 ($2))
2656 notethat ("UJUMP: JUMP pcrel12\n");
2660 return yyerror ("Bad value for relative jump");
2665 if (IS_PCREL12 ($2))
2667 notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
2671 return yyerror ("Bad value for relative jump");
2676 if (IS_PCREL24 ($2))
2678 notethat ("CALLa: jump.l pcrel24\n");
2682 return yyerror ("Bad value for long jump");
2687 if (IS_PCREL24 ($2))
2689 notethat ("CALLa: jump.l pcrel24\n");
2693 return yyerror ("Bad value for long jump");
2698 if (IS_PCREL24 ($2))
2700 notethat ("CALLa: CALL pcrel25m2\n");
2704 return yyerror ("Bad call address");
2708 if (IS_PCREL24 ($2))
2710 notethat ("CALLa: CALL pcrel25m2\n");
2714 return yyerror ("Bad call address");
2718 /* ALU2op: DIVQ (dregs, dregs). */
2719 | DIVQ LPAREN REG COMMA REG RPAREN
2721 if (IS_DREG ($3) && IS_DREG ($5))
2722 $$ = ALU2OP (&$3, &$5, 8);
2724 return yyerror ("Bad registers for DIVQ");
2727 | DIVS LPAREN REG COMMA REG RPAREN
2729 if (IS_DREG ($3) && IS_DREG ($5))
2730 $$ = ALU2OP (&$3, &$5, 9);
2732 return yyerror ("Bad registers for DIVS");
2735 | REG ASSIGN MINUS REG vsmod
2737 if (IS_DREG ($1) && IS_DREG ($4))
2739 if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
2741 notethat ("ALU2op: dregs = - dregs\n");
2742 $$ = ALU2OP (&$1, &$4, 14);
2744 else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
2746 notethat ("dsp32alu: dregs = - dregs (.)\n");
2747 $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2751 notethat ("dsp32alu: dregs = - dregs (.)\n");
2752 $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
2756 return yyerror ("Dregs expected");
2759 | REG ASSIGN TILDA REG
2761 if (IS_DREG ($1) && IS_DREG ($4))
2763 notethat ("ALU2op: dregs = ~dregs\n");
2764 $$ = ALU2OP (&$1, &$4, 15);
2767 return yyerror ("Dregs expected");
2770 | REG _GREATER_GREATER_ASSIGN REG
2772 if (IS_DREG ($1) && IS_DREG ($3))
2774 notethat ("ALU2op: dregs >>= dregs\n");
2775 $$ = ALU2OP (&$1, &$3, 1);
2778 return yyerror ("Dregs expected");
2781 | REG _GREATER_GREATER_ASSIGN expr
2783 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2785 notethat ("LOGI2op: dregs >>= uimm5\n");
2786 $$ = LOGI2OP ($1, uimm5 ($3), 6);
2789 return yyerror ("Dregs expected or value error");
2792 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
2794 if (IS_DREG ($1) && IS_DREG ($3))
2796 notethat ("ALU2op: dregs >>>= dregs\n");
2797 $$ = ALU2OP (&$1, &$3, 0);
2800 return yyerror ("Dregs expected");
2803 | REG _LESS_LESS_ASSIGN REG
2805 if (IS_DREG ($1) && IS_DREG ($3))
2807 notethat ("ALU2op: dregs <<= dregs\n");
2808 $$ = ALU2OP (&$1, &$3, 2);
2811 return yyerror ("Dregs expected");
2814 | REG _LESS_LESS_ASSIGN expr
2816 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2818 notethat ("LOGI2op: dregs <<= uimm5\n");
2819 $$ = LOGI2OP ($1, uimm5 ($3), 7);
2822 return yyerror ("Dregs expected or const value error");
2826 | REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
2828 if (IS_DREG ($1) && IS_UIMM ($3, 5))
2830 notethat ("LOGI2op: dregs >>>= uimm5\n");
2831 $$ = LOGI2OP ($1, uimm5 ($3), 5);
2834 return yyerror ("Dregs expected");
2837 /* Cache Control. */
2839 | FLUSH LBRACK REG RBRACK
2841 notethat ("CaCTRL: FLUSH [ pregs ]\n");
2843 $$ = CACTRL (&$3, 0, 2);
2845 return yyerror ("Bad register(s) for FLUSH");
2848 | FLUSH reg_with_postinc
2852 notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
2853 $$ = CACTRL (&$2, 1, 2);
2856 return yyerror ("Bad register(s) for FLUSH");
2859 | FLUSHINV LBRACK REG RBRACK
2863 notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
2864 $$ = CACTRL (&$3, 0, 1);
2867 return yyerror ("Bad register(s) for FLUSH");
2870 | FLUSHINV reg_with_postinc
2874 notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
2875 $$ = CACTRL (&$2, 1, 1);
2878 return yyerror ("Bad register(s) for FLUSH");
2881 /* CaCTRL: IFLUSH [pregs]. */
2882 | IFLUSH LBRACK REG RBRACK
2886 notethat ("CaCTRL: IFLUSH [ pregs ]\n");
2887 $$ = CACTRL (&$3, 0, 3);
2890 return yyerror ("Bad register(s) for FLUSH");
2893 | IFLUSH reg_with_postinc
2897 notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
2898 $$ = CACTRL (&$2, 1, 3);
2901 return yyerror ("Bad register(s) for FLUSH");
2904 | PREFETCH LBRACK REG RBRACK
2908 notethat ("CaCTRL: PREFETCH [ pregs ]\n");
2909 $$ = CACTRL (&$3, 0, 0);
2912 return yyerror ("Bad register(s) for PREFETCH");
2915 | PREFETCH reg_with_postinc
2919 notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
2920 $$ = CACTRL (&$2, 1, 0);
2923 return yyerror ("Bad register(s) for PREFETCH");
2927 /* LDST: B [ pregs <post_op> ] = dregs. */
2929 | B LBRACK REG post_op RBRACK ASSIGN REG
2931 if (IS_PREG ($3) && IS_DREG ($7))
2933 notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
2934 $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
2937 return yyerror ("Register mismatch");
2940 /* LDSTidxI: B [ pregs + imm16 ] = dregs. */
2941 | B LBRACK REG plus_minus expr RBRACK ASSIGN REG
2943 if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
2945 notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
2948 $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
2951 return yyerror ("Register mismatch or const size wrong");
2955 /* LDSTii: W [ pregs + uimm4s2 ] = dregs. */
2956 | W LBRACK REG plus_minus expr RBRACK ASSIGN REG
2958 if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
2960 notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
2961 $$ = LDSTII (&$3, &$8, $5, 1, 1);
2963 else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
2965 notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
2968 $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
2971 return yyerror ("Bad register(s) or wrong constant size");
2974 /* LDST: W [ pregs <post_op> ] = dregs. */
2975 | W LBRACK REG post_op RBRACK ASSIGN REG
2977 if (IS_PREG ($3) && IS_DREG ($7))
2979 notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
2980 $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
2983 return yyerror ("Bad register(s) for STORE");
2986 | W LBRACK REG post_op RBRACK ASSIGN HALF_REG
2990 notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
2991 $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
2993 else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
2995 notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
2996 $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
3000 return yyerror ("Bad register(s) for STORE");
3003 /* LDSTiiFP: [ FP - const ] = dpregs. */
3004 | LBRACK REG plus_minus expr RBRACK ASSIGN REG
3006 Expr_Node *tmp = $4;
3007 int ispreg = IS_PREG ($7);
3010 return yyerror ("Preg expected for indirect");
3012 if (!IS_DREG ($7) && !ispreg)
3013 return yyerror ("Bad source register for STORE");
3016 tmp = unary (Expr_Op_Type_NEG, tmp);
3018 if (in_range_p (tmp, 0, 63, 3))
3020 notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
3021 $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
3023 else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3025 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3026 tmp = unary (Expr_Op_Type_NEG, tmp);
3027 $$ = LDSTIIFP (tmp, &$7, 1);
3029 else if (in_range_p (tmp, -131072, 131071, 3))
3031 notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
3032 $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
3035 return yyerror ("Displacement out of range for store");
3038 | REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
3040 if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
3042 notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
3043 $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
3045 else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
3047 notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
3050 $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
3053 return yyerror ("Bad register or constant for LOAD");
3056 | HALF_REG ASSIGN W LBRACK REG post_op RBRACK
3060 notethat ("dspLDST: dregs_half = W [ iregs ]\n");
3061 $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
3063 else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
3065 notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
3066 $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
3069 return yyerror ("Bad register or post_op for LOAD");
3073 | REG ASSIGN W LBRACK REG post_op RBRACK xpmod
3075 if (IS_DREG ($1) && IS_PREG ($5))
3077 notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
3078 $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
3081 return yyerror ("Bad register for LOAD");
3084 | REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
3086 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3088 notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
3089 $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
3092 return yyerror ("Bad register for LOAD");
3095 | HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
3097 if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
3099 notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
3100 $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
3103 return yyerror ("Bad register for LOAD");
3106 | LBRACK REG post_op RBRACK ASSIGN REG
3108 if (IS_IREG ($2) && IS_DREG ($6))
3110 notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
3111 $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
3113 else if (IS_PREG ($2) && IS_DREG ($6))
3115 notethat ("LDST: [ pregs <post_op> ] = dregs\n");
3116 $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
3118 else if (IS_PREG ($2) && IS_PREG ($6))
3120 notethat ("LDST: [ pregs <post_op> ] = pregs\n");
3121 $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
3124 return yyerror ("Bad register for STORE");
3127 | LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
3130 return yyerror ("Expected Dreg for last argument");
3132 if (IS_IREG ($2) && IS_MREG ($4))
3134 notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
3135 $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
3137 else if (IS_PREG ($2) && IS_PREG ($4))
3139 notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
3140 $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
3143 return yyerror ("Bad register for STORE");
3146 | W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
3149 return yyerror ("Expect Dreg as last argument");
3150 if (IS_PREG ($3) && IS_PREG ($5))
3152 notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
3153 $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
3156 return yyerror ("Bad register for STORE");
3159 | REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
3161 if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
3163 notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
3167 $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
3170 return yyerror ("Bad register or value for LOAD");
3173 | REG ASSIGN B LBRACK REG post_op RBRACK xpmod
3175 if (IS_DREG ($1) && IS_PREG ($5))
3177 notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
3179 $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
3182 return yyerror ("Bad register for LOAD");
3185 | REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
3187 if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
3189 notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
3190 $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
3192 else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
3194 notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
3195 $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
3198 return yyerror ("Bad register for LOAD");
3201 | REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
3203 Expr_Node *tmp = $6;
3204 int ispreg = IS_PREG ($1);
3205 int isgot = IS_RELOC($6);
3208 return yyerror ("Preg expected for indirect");
3210 if (!IS_DREG ($1) && !ispreg)
3211 return yyerror ("Bad destination register for LOAD");
3214 tmp = unary (Expr_Op_Type_NEG, tmp);
3217 notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
3218 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3220 else if (in_range_p (tmp, 0, 63, 3))
3222 notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
3223 $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
3225 else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
3227 notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
3228 tmp = unary (Expr_Op_Type_NEG, tmp);
3229 $$ = LDSTIIFP (tmp, &$1, 0);
3231 else if (in_range_p (tmp, -131072, 131071, 3))
3233 notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
3234 $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
3238 return yyerror ("Displacement out of range for load");
3241 | REG ASSIGN LBRACK REG post_op RBRACK
3243 if (IS_DREG ($1) && IS_IREG ($4))
3245 notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
3246 $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
3248 else if (IS_DREG ($1) && IS_PREG ($4))
3250 notethat ("LDST: dregs = [ pregs <post_op> ]\n");
3251 $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
3253 else if (IS_PREG ($1) && IS_PREG ($4))
3255 if (REG_SAME ($1, $4) && $5.x0 != 2)
3256 return yyerror ("Pregs can't be same");
3258 notethat ("LDST: pregs = [ pregs <post_op> ]\n");
3259 $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
3261 else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
3263 notethat ("PushPopReg: allregs = [ SP ++ ]\n");
3264 $$ = PUSHPOPREG (&$1, 0);
3267 return yyerror ("Bad register or value");
3271 /* PushPopMultiple. */
3272 | reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
3274 if ($1.regno != REG_SP)
3275 yyerror ("Stack Pointer expected");
3276 if ($4.regno == REG_R7
3277 && IN_RANGE ($6, 0, 7)
3278 && $8.regno == REG_P5
3279 && IN_RANGE ($10, 0, 5))
3281 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
3282 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3285 return yyerror ("Bad register for PushPopMultiple");
3288 | reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
3290 if ($1.regno != REG_SP)
3291 yyerror ("Stack Pointer expected");
3293 if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
3295 notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
3296 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3298 else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
3300 notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
3301 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3304 return yyerror ("Bad register for PushPopMultiple");
3307 | LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
3309 if ($11.regno != REG_SP)
3310 yyerror ("Stack Pointer expected");
3311 if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
3312 && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
3314 notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
3315 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
3318 return yyerror ("Bad register range for PushPopMultiple");
3321 | LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
3323 if ($7.regno != REG_SP)
3324 yyerror ("Stack Pointer expected");
3326 if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
3328 notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
3329 $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
3331 else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
3333 notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
3334 $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
3337 return yyerror ("Bad register range for PushPopMultiple");
3340 | reg_with_predec ASSIGN REG
3342 if ($1.regno != REG_SP)
3343 yyerror ("Stack Pointer expected");
3347 notethat ("PushPopReg: [ -- SP ] = allregs\n");
3348 $$ = PUSHPOPREG (&$3, 1);
3351 return yyerror ("Bad register for PushPopReg");
3358 if (IS_URANGE (16, $2, 0, 4))
3359 $$ = LINKAGE (0, uimm16s4 ($2));
3361 return yyerror ("Bad constant for LINK");
3366 notethat ("linkage: UNLINK\n");
3367 $$ = LINKAGE (1, 0);
3373 | LSETUP LPAREN expr COMMA expr RPAREN REG
3375 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
3377 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
3378 $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
3381 return yyerror ("Bad register or values for LSETUP");
3384 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
3386 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3387 && IS_PREG ($9) && IS_CREG ($7))
3389 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
3390 $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
3393 return yyerror ("Bad register or values for LSETUP");
3396 | LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
3398 if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
3399 && IS_PREG ($9) && IS_CREG ($7)
3400 && EXPR_VALUE ($11) == 1)
3402 notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
3403 $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
3406 return yyerror ("Bad register or values for LSETUP");
3413 return yyerror ("Invalid expression in loop statement");
3415 return yyerror ("Invalid loop counter register");
3416 $$ = bfin_gen_loop ($2, &$3, 0, 0);
3418 | LOOP expr REG ASSIGN REG
3420 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
3422 notethat ("Loop: LOOP expr counters = pregs\n");
3423 $$ = bfin_gen_loop ($2, &$3, 1, &$5);
3426 return yyerror ("Bad register or values for LOOP");
3428 | LOOP expr REG ASSIGN REG GREATER_GREATER expr
3430 if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
3432 notethat ("Loop: LOOP expr counters = pregs >> 1\n");
3433 $$ = bfin_gen_loop ($2, &$3, 3, &$5);
3436 return yyerror ("Bad register or values for LOOP");
3442 notethat ("pseudoDEBUG: DBG\n");
3443 $$ = bfin_gen_pseudodbg (3, 7, 0);
3447 notethat ("pseudoDEBUG: DBG REG_A\n");
3448 $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
3452 notethat ("pseudoDEBUG: DBG allregs\n");
3453 $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
3456 | DBGCMPLX LPAREN REG RPAREN
3459 return yyerror ("Dregs expected");
3460 notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
3461 $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
3466 notethat ("psedoDEBUG: DBGHALT\n");
3467 $$ = bfin_gen_pseudodbg (3, 5, 0);
3470 | DBGA LPAREN HALF_REG COMMA expr RPAREN
3472 notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
3473 $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
3476 | DBGAH LPAREN REG COMMA expr RPAREN
3478 notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
3479 $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
3482 | DBGAL LPAREN REG COMMA expr RPAREN
3484 notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
3485 $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
3493 /* Register rules. */
3495 REG_A: REG_A_DOUBLE_ZERO
3513 | LPAREN M COMMA MMOD RPAREN
3518 | LPAREN MMOD COMMA M RPAREN
3523 | LPAREN MMOD RPAREN
3535 asr_asl: LPAREN ASL RPAREN
3616 | LPAREN asr_asl_0 RPAREN
3628 | LPAREN asr_asl_0 COMMA sco RPAREN
3634 | LPAREN sco COMMA asr_asl_0 RPAREN
3694 | LPAREN V COMMA S RPAREN
3699 | LPAREN S COMMA V RPAREN
3761 | LPAREN MMOD RPAREN
3764 return yyerror ("Bad modifier");
3768 | LPAREN MMOD COMMA R RPAREN
3771 return yyerror ("Bad modifier");
3775 | LPAREN R COMMA MMOD RPAREN
3778 return yyerror ("Bad modifier");
3805 | LPAREN MMOD RPAREN
3810 return yyerror ("Only (W32) allowed");
3818 | LPAREN MMOD RPAREN
3823 return yyerror ("(IU) expected");
3827 reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
3833 reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
3885 $$.r0 = 1; /* HL. */
3888 $$.aop = 0; /* aop. */
3893 $$.r0 = 1; /* HL. */
3896 $$.aop = 1; /* aop. */
3899 | LPAREN RNDL RPAREN
3901 $$.r0 = 0; /* HL. */
3904 $$.aop = 0; /* aop. */
3909 $$.r0 = 0; /* HL. */
3915 | LPAREN RNDH COMMA R RPAREN
3917 $$.r0 = 1; /* HL. */
3920 $$.aop = 0; /* aop. */
3922 | LPAREN TH COMMA R RPAREN
3924 $$.r0 = 1; /* HL. */
3927 $$.aop = 1; /* aop. */
3929 | LPAREN RNDL COMMA R RPAREN
3931 $$.r0 = 0; /* HL. */
3934 $$.aop = 0; /* aop. */
3937 | LPAREN TL COMMA R RPAREN
3939 $$.r0 = 0; /* HL. */
3942 $$.aop = 1; /* aop. */
3950 $$.x0 = 0; /* HL. */
3955 $$.x0 = 1; /* HL. */
3957 | LPAREN LO COMMA R RPAREN
3960 $$.x0 = 0; /* HL. */
3962 | LPAREN HI COMMA R RPAREN
3965 $$.x0 = 1; /* HL. */
3983 /* Assignments, Macfuncs. */
4017 if (IS_A1 ($3) && IS_EVEN ($1))
4018 return yyerror ("Cannot move A1 to even register");
4019 else if (!IS_A1 ($3) && !IS_EVEN ($1))
4020 return yyerror ("Cannot move A0 to odd register");
4028 | REG ASSIGN LPAREN a_macfunc RPAREN
4036 | HALF_REG ASSIGN LPAREN a_macfunc RPAREN
4044 | HALF_REG ASSIGN REG_A
4054 if (IS_A1 ($3) && !IS_H ($1))
4055 return yyerror ("Cannot move A1 to low half of register");
4056 else if (!IS_A1 ($3) && IS_H ($1))
4057 return yyerror ("Cannot move A0 to high half of register");
4062 a_assign multiply_halfregs
4069 | a_plusassign multiply_halfregs
4076 | a_minusassign multiply_halfregs
4086 HALF_REG STAR HALF_REG
4088 if (IS_DREG ($1) && IS_DREG ($3))
4094 return yyerror ("Dregs expected");
4118 CCREG cc_op STATUS_REG
4130 | STATUS_REG cc_op CCREG
4144 /* Expressions and Symbols. */
4148 Expr_Node_Value val;
4149 val.s_value = S_GET_NAME($1);
4150 $$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
4156 { $$ = BFD_RELOC_BFIN_GOT; }
4158 { $$ = BFD_RELOC_BFIN_GOT17M4; }
4160 { $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
4163 got: symbol AT any_gotrel
4165 Expr_Node_Value val;
4167 $$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
4190 Expr_Node_Value val;
4192 $$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
4198 | LPAREN expr_1 RPAREN
4204 $$ = unary (Expr_Op_Type_COMP, $2);
4206 | MINUS expr_1 %prec TILDA
4208 $$ = unary (Expr_Op_Type_NEG, $2);
4218 expr_1: expr_1 STAR expr_1
4220 $$ = binary (Expr_Op_Type_Mult, $1, $3);
4222 | expr_1 SLASH expr_1
4224 $$ = binary (Expr_Op_Type_Div, $1, $3);
4226 | expr_1 PERCENT expr_1
4228 $$ = binary (Expr_Op_Type_Mod, $1, $3);
4230 | expr_1 PLUS expr_1
4232 $$ = binary (Expr_Op_Type_Add, $1, $3);
4234 | expr_1 MINUS expr_1
4236 $$ = binary (Expr_Op_Type_Sub, $1, $3);
4238 | expr_1 LESS_LESS expr_1
4240 $$ = binary (Expr_Op_Type_Lshift, $1, $3);
4242 | expr_1 GREATER_GREATER expr_1
4244 $$ = binary (Expr_Op_Type_Rshift, $1, $3);
4246 | expr_1 AMPERSAND expr_1
4248 $$ = binary (Expr_Op_Type_BAND, $1, $3);
4250 | expr_1 CARET expr_1
4252 $$ = binary (Expr_Op_Type_LOR, $1, $3);
4256 $$ = binary (Expr_Op_Type_BOR, $1, $3);
4268 mkexpr (int x, SYMBOL_T s)
4270 EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
4277 value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
4279 long umax = (1L << sz) - 1;
4280 long min = -1L << (sz - 1);
4281 long max = (1L << (sz - 1)) - 1;
4283 long v = EXPR_VALUE (expr);
4287 error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul);
4298 if (v >= min && v <= max) return 1;
4301 fprintf(stderr, "signed value %lx out of range\n", v * mul);
4305 if (v <= umax && v >= 0)
4308 fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
4313 /* Return the expression structure that allows symbol operations.
4314 If the left and right children are constants, do the operation. */
4316 binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
4318 Expr_Node_Value val;
4320 if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
4324 case Expr_Op_Type_Add:
4325 x->value.i_value += y->value.i_value;
4327 case Expr_Op_Type_Sub:
4328 x->value.i_value -= y->value.i_value;
4330 case Expr_Op_Type_Mult:
4331 x->value.i_value *= y->value.i_value;
4333 case Expr_Op_Type_Div:
4334 if (y->value.i_value == 0)
4335 error ("Illegal Expression: Division by zero.");
4337 x->value.i_value /= y->value.i_value;
4339 case Expr_Op_Type_Mod:
4340 x->value.i_value %= y->value.i_value;
4342 case Expr_Op_Type_Lshift:
4343 x->value.i_value <<= y->value.i_value;
4345 case Expr_Op_Type_Rshift:
4346 x->value.i_value >>= y->value.i_value;
4348 case Expr_Op_Type_BAND:
4349 x->value.i_value &= y->value.i_value;
4351 case Expr_Op_Type_BOR:
4352 x->value.i_value |= y->value.i_value;
4354 case Expr_Op_Type_BXOR:
4355 x->value.i_value ^= y->value.i_value;
4357 case Expr_Op_Type_LAND:
4358 x->value.i_value = x->value.i_value && y->value.i_value;
4360 case Expr_Op_Type_LOR:
4361 x->value.i_value = x->value.i_value || y->value.i_value;
4365 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4369 /* Canonicalize order to EXPR OP CONSTANT. */
4370 if (x->type == Expr_Node_Constant)
4376 /* Canonicalize subtraction of const to addition of negated const. */
4377 if (op == Expr_Op_Type_Sub && y->type == Expr_Node_Constant)
4379 op = Expr_Op_Type_Add;
4380 y->value.i_value = -y->value.i_value;
4382 if (y->type == Expr_Node_Constant && x->type == Expr_Node_Binop
4383 && x->Right_Child->type == Expr_Node_Constant)
4385 if (op == x->value.op_value && x->value.op_value == Expr_Op_Type_Add)
4387 x->Right_Child->value.i_value += y->value.i_value;
4392 /* Create a new expression structure. */
4394 return Expr_Node_Create (Expr_Node_Binop, val, x, y);
4398 unary (Expr_Op_Type op, Expr_Node *x)
4400 if (x->type == Expr_Node_Constant)
4404 case Expr_Op_Type_NEG:
4405 x->value.i_value = -x->value.i_value;
4407 case Expr_Op_Type_COMP:
4408 x->value.i_value = ~x->value.i_value;
4411 error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__);
4417 /* Create a new expression structure. */
4418 Expr_Node_Value val;
4420 return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
4424 int debug_codeselection = 0;
4426 notethat (char *format, ...)
4429 va_start (ap, format);
4430 if (debug_codeselection)
4432 vfprintf (errorf, format, ap);
4438 main (int argc, char **argv)