gas/config/m68k-parse.h

   1 /* m68k-parse.h -- header file for m68k assembler
   2    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
   3    2003, 2004 Free Software Foundation, Inc.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef M68K_PARSE_H
  23 #define M68K_PARSE_H
  24
  25 /* This header file defines things which are shared between the
  26    operand parser in m68k.y and the m68k assembler proper in
  27    tc-m68k.c.  */
  28
  29 /* The various m68k registers.  */
  30
  31 /* DATA and ADDR have to be contiguous, so that reg-DATA gives
  32    0-7==data reg, 8-15==addr reg for operands that take both types.
  33
  34    We don't use forms like "ADDR0 = ADDR" here because this file is
  35    likely to be used on an Apollo, and the broken Apollo compiler
  36    gives an `undefined variable' error if we do that, according to
  37    troy@cbme.unsw.edu.au.  */
  38
  39 #define DATA DATA0
  40 #define ADDR ADDR0
  41 #define SP ADDR7
  42 #define BAD BAD0
  43 #define BAC BAC0
  44
  45 enum m68k_register
  46 {
  47   DATA0 = 1,                    /*   1- 8 == data registers 0-7 */
  48   DATA1,
  49   DATA2,
  50   DATA3,
  51   DATA4,
  52   DATA5,
  53   DATA6,
  54   DATA7,
  55
  56   ADDR0,
  57   ADDR1,
  58   ADDR2,
  59   ADDR3,
  60   ADDR4,
  61   ADDR5,
  62   ADDR6,
  63   ADDR7,
  64
  65   FP0,                          /* Eight FP registers */
  66   FP1,
  67   FP2,
  68   FP3,
  69   FP4,
  70   FP5,
  71   FP6,
  72   FP7,
  73
  74   COP0,                         /* Co-processor #0-#7 */
  75   COP1,
  76   COP2,
  77   COP3,
  78   COP4,
  79   COP5,
  80   COP6,
  81   COP7,
  82
  83   PC,                           /* Program counter */
  84   ZPC,                          /* Hack for Program space, but 0 addressing */
  85   SR,                           /* Status Reg */
  86   CCR,                          /* Condition code Reg */
  87   ACC,                          /* Accumulator Reg0 (EMAC or ACC on MAC).  */
  88   ACC1,                         /* Accumulator Reg 1 (EMAC).  */
  89   ACC2,                         /* Accumulator Reg 2 (EMAC).  */
  90   ACC3,                         /* Accumulator Reg 3 (EMAC).  */
  91   ACCEXT01,                     /* Accumulator extension 0&1 (EMAC).  */
  92   ACCEXT23,                     /* Accumulator extension 2&3 (EMAC).  */
  93   MACSR,                        /* MAC Status Reg */
  94   MASK,                         /* Modulus Reg */
  95
  96   /* These have to be grouped together for the movec instruction to work.  */
  97   USP,                          /*  User Stack Pointer */
  98   ISP,                          /*  Interrupt stack pointer */
  99   SFC,
 100   DFC,
 101   CACR,
 102   VBR,
 103   CAAR,
 104   MSP,
 105   ITT0,
 106   ITT1,
 107   DTT0,
 108   DTT1,
 109   MMUSR,
 110   TC,
 111   SRP,
 112   URP,
 113   BUSCR,                        /* 68060 added these.  */
 114   PCR,
 115   ROMBAR,                       /* mcf5200 added these.  */
 116   RAMBAR0,
 117   RAMBAR1,
 118   MMUBAR,                       /* mcfv4e added these.  */
 119   ROMBAR1,                      /* mcfv4e added these.  */
 120   MPCR, EDRAMBAR, SECMBAR,      /* mcfv4e added these.  */
 121   PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these.  */
 122   PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these.  */
 123   PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these.  */
 124   MBAR0, MBAR1,                 /* mcfv4e added these.  */
 125   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
 126   FLASHBAR, RAMBAR,             /* mcf528x added these.  */
 127   MBAR,
 128 #define last_movec_reg MBAR
 129   /* End of movec ordering constraints.  */
 130
 131   FPI,
 132   FPS,
 133   FPC,
 134
 135   DRP,                          /* 68851 or 68030 MMU regs */
 136   CRP,
 137   CAL,
 138   VAL,
 139   SCC,
 140   AC,
 141   BAD0,
 142   BAD1,
 143   BAD2,
 144   BAD3,
 145   BAD4,
 146   BAD5,
 147   BAD6,
 148   BAD7,
 149   BAC0,
 150   BAC1,
 151   BAC2,
 152   BAC3,
 153   BAC4,
 154   BAC5,
 155   BAC6,
 156   BAC7,
 157   PSR,                          /* aka MMUSR on 68030 (but not MMUSR on 68040)
 158                                    and ACUSR on 68ec030 */
 159   PCSR,
 160
 161   IC,                           /* instruction cache token */
 162   DC,                           /* data cache token */
 163   NC,                           /* no cache token */
 164   BC,                           /* both caches token */
 165
 166   TT0,                          /* 68030 access control unit regs */
 167   TT1,
 168
 169   ZDATA0,                       /* suppressed data registers.  */
 170   ZDATA1,
 171   ZDATA2,
 172   ZDATA3,
 173   ZDATA4,
 174   ZDATA5,
 175   ZDATA6,
 176   ZDATA7,
 177
 178   ZADDR0,                       /* suppressed address registers.  */
 179   ZADDR1,
 180   ZADDR2,
 181   ZADDR3,
 182   ZADDR4,
 183   ZADDR5,
 184   ZADDR6,
 185   ZADDR7,
 186
 187   /* Upper and lower half of data and address registers.  Order *must*
 188      be DATAxL, ADDRxL, DATAxU, ADDRxU.  */
 189   DATA0L,                       /* lower half of data registers */
 190   DATA1L,
 191   DATA2L,
 192   DATA3L,
 193   DATA4L,
 194   DATA5L,
 195   DATA6L,
 196   DATA7L,
 197
 198   ADDR0L,                       /* lower half of address registers */
 199   ADDR1L,
 200   ADDR2L,
 201   ADDR3L,
 202   ADDR4L,
 203   ADDR5L,
 204   ADDR6L,
 205   ADDR7L,
 206
 207   DATA0U,                       /* upper half of data registers */
 208   DATA1U,
 209   DATA2U,
 210   DATA3U,
 211   DATA4U,
 212   DATA5U,
 213   DATA6U,
 214   DATA7U,
 215
 216   ADDR0U,                       /* upper half of address registers */
 217   ADDR1U,
 218   ADDR2U,
 219   ADDR3U,
 220   ADDR4U,
 221   ADDR5U,
 222   ADDR6U,
 223   ADDR7U,
 224 };
 225
 226 /* Size information.  */
 227
 228 enum m68k_size
 229 {
 230   /* Unspecified.  */
 231   SIZE_UNSPEC,
 232
 233   /* Byte.  */
 234   SIZE_BYTE,
 235
 236   /* Word (2 bytes).  */
 237   SIZE_WORD,
 238
 239   /* Longword (4 bytes).  */
 240   SIZE_LONG
 241 };
 242
 243 /* The structure used to hold information about an index register.  */
 244
 245 struct m68k_indexreg
 246 {
 247   /* The index register itself.  */
 248   enum m68k_register reg;
 249
 250   /* The size to use.  */
 251   enum m68k_size size;
 252
 253   /* The value to scale by.  */
 254   int scale;
 255 };
 256
 257 #ifdef OBJ_ELF
 258 /* The type of a PIC expression.  */
 259
 260 enum pic_relocation
 261 {
 262   pic_none,                     /* not pic */
 263   pic_plt_pcrel,                /* @PLTPC */
 264   pic_got_pcrel,                /* @GOTPC */
 265   pic_plt_off,                  /* @PLT */
 266   pic_got_off                   /* @GOT */
 267 };
 268 #endif
 269
 270 /* The structure used to hold information about an expression.  */
 271
 272 struct m68k_exp
 273 {
 274   /* The size to use.  */
 275   enum m68k_size size;
 276
 277 #ifdef OBJ_ELF
 278   /* The type of pic relocation if any.  */
 279   enum pic_relocation pic_reloc;
 280 #endif
 281
 282   /* The expression itself.  */
 283   expressionS exp;
 284 };
 285
 286 /* The operand modes.  */
 287
 288 enum m68k_operand_type
 289 {
 290   IMMED = 1,
 291   ABSL,
 292   DREG,
 293   AREG,
 294   FPREG,
 295   CONTROL,
 296   AINDR,
 297   AINC,
 298   ADEC,
 299   DISP,
 300   BASE,
 301   POST,
 302   PRE,
 303   LSH,  /* MAC/EMAC scalefactor '<<'.  */
 304   RSH,  /* MAC/EMAC scalefactor '>>'.  */
 305   REGLST
 306 };
 307
 308 /* The structure used to hold a parsed operand.  */
 309
 310 struct m68k_op
 311 {
 312   /* The type of operand.  */
 313   enum m68k_operand_type mode;
 314
 315   /* The main register.  */
 316   enum m68k_register reg;
 317
 318   /* The register mask for mode REGLST.  */
 319   unsigned long mask;
 320
 321   /* An error message.  */
 322   const char *error;
 323
 324   /* The index register.  */
 325   struct m68k_indexreg index;
 326
 327   /* The displacement.  */
 328   struct m68k_exp disp;
 329
 330   /* The outer displacement.  */
 331   struct m68k_exp odisp;
 332
 333   /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
 334   int trailing_ampersand;
 335 };
 336
 337 #endif /* ! defined (M68K_PARSE_H) */
 338
 339 /* The parsing function.  */
 340
 341 extern int m68k_ip_op PARAMS ((char *, struct m68k_op *));
 342
 343 /* Whether register prefixes are optional.  */
 344 extern int flag_reg_prefix_optional;