1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum neon_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a single type, e.g. ".8b", leading period included.
825 Only applicable to Vn registers.
827 Return TRUE on success; otherwise return FALSE. */
829 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
835 if (! parse_neon_type_for_operand (vectype
, &str
))
837 first_error (_("vector type expected"));
849 /* Parse a register of the type TYPE.
851 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
852 name or the parsed register is not of TYPE.
854 Otherwise return the register number, and optionally fill in the actual
855 type of the register in *RTYPE when multiple alternatives were given, and
856 return the register shape and element index information in *TYPEINFO.
858 IN_REG_LIST should be set with TRUE if the caller is parsing a register
862 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
863 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
866 const reg_entry
*reg
= parse_reg (&str
);
867 struct neon_type_el atype
;
868 struct neon_type_el parsetype
;
869 bfd_boolean is_typed_vecreg
= FALSE
;
872 atype
.type
= NT_invtype
;
880 set_default_error ();
884 if (! aarch64_check_reg_type (reg
, type
))
886 DEBUG_TRACE ("reg type check failed");
887 set_default_error ();
892 if (type
== REG_TYPE_VN
893 && parse_neon_operand_type (&parsetype
, &str
))
895 /* Register if of the form Vn.[bhsdq]. */
896 is_typed_vecreg
= TRUE
;
898 if (parsetype
.width
== 0)
899 /* Expect index. In the new scheme we cannot have
900 Vn.[bhsdq] represent a scalar. Therefore any
901 Vn.[bhsdq] should have an index following it.
902 Except in reglists ofcourse. */
903 atype
.defined
|= NTA_HASINDEX
;
905 atype
.defined
|= NTA_HASTYPE
;
907 atype
.type
= parsetype
.type
;
908 atype
.width
= parsetype
.width
;
911 if (skip_past_char (&str
, '['))
915 /* Reject Sn[index] syntax. */
916 if (!is_typed_vecreg
)
918 first_error (_("this type of register can't be indexed"));
922 if (in_reg_list
== TRUE
)
924 first_error (_("index not allowed inside register list"));
928 atype
.defined
|= NTA_HASINDEX
;
930 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
932 if (exp
.X_op
!= O_constant
)
934 first_error (_("constant expression required"));
938 if (! skip_past_char (&str
, ']'))
941 atype
.index
= exp
.X_add_number
;
943 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
945 /* Indexed vector register expected. */
946 first_error (_("indexed vector register expected"));
950 /* A vector reg Vn should be typed or indexed. */
951 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
953 first_error (_("invalid use of vector register"));
969 Return the register number on success; return PARSE_FAIL otherwise.
971 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
972 the register (e.g. NEON double or quad reg when either has been requested).
974 If this is a NEON vector register with additional type information, fill
975 in the struct pointed to by VECTYPE (if non-NULL).
977 This parser does not handle register list. */
980 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
981 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
983 struct neon_type_el atype
;
985 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
986 /*in_reg_list= */ FALSE
);
988 if (reg
== PARSE_FAIL
)
999 static inline bfd_boolean
1000 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1004 && e1
.defined
== e2
.defined
1005 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1008 /* This function parses the NEON register list. On success, it returns
1009 the parsed register list information in the following encoded format:
1011 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1012 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1014 The information of the register shape and/or index is returned in
1017 It returns PARSE_FAIL if the register list is invalid.
1019 The list contains one to four registers.
1020 Each register can be one of:
1023 All <T> should be identical.
1024 All <index> should be identical.
1025 There are restrictions on <Vt> numbers which are checked later
1026 (by reg_list_valid_p). */
1029 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1033 struct neon_type_el typeinfo
, typeinfo_first
;
1038 bfd_boolean error
= FALSE
;
1039 bfd_boolean expect_index
= FALSE
;
1043 set_syntax_error (_("expecting {"));
1049 typeinfo_first
.defined
= 0;
1050 typeinfo_first
.type
= NT_invtype
;
1051 typeinfo_first
.width
= -1;
1052 typeinfo_first
.index
= 0;
1061 str
++; /* skip over '-' */
1064 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1065 /*in_reg_list= */ TRUE
);
1066 if (val
== PARSE_FAIL
)
1068 set_first_syntax_error (_("invalid vector register in list"));
1072 /* reject [bhsd]n */
1073 if (typeinfo
.defined
== 0)
1075 set_first_syntax_error (_("invalid scalar register in list"));
1080 if (typeinfo
.defined
& NTA_HASINDEX
)
1081 expect_index
= TRUE
;
1085 if (val
< val_range
)
1087 set_first_syntax_error
1088 (_("invalid range in vector register list"));
1097 typeinfo_first
= typeinfo
;
1098 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1100 set_first_syntax_error
1101 (_("type mismatch in vector register list"));
1106 for (i
= val_range
; i
<= val
; i
++)
1108 ret_val
|= i
<< (5 * nb_regs
);
1113 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1115 skip_whitespace (str
);
1118 set_first_syntax_error (_("end of vector register list not found"));
1123 skip_whitespace (str
);
1127 if (skip_past_char (&str
, '['))
1131 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1132 if (exp
.X_op
!= O_constant
)
1134 set_first_syntax_error (_("constant expression required."));
1137 if (! skip_past_char (&str
, ']'))
1140 typeinfo_first
.index
= exp
.X_add_number
;
1144 set_first_syntax_error (_("expected index"));
1151 set_first_syntax_error (_("too many registers in vector register list"));
1154 else if (nb_regs
== 0)
1156 set_first_syntax_error (_("empty vector register list"));
1162 *vectype
= typeinfo_first
;
1164 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1167 /* Directives: register aliases. */
1170 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1175 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1178 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1181 /* Only warn about a redefinition if it's not defined as the
1183 else if (new->number
!= number
|| new->type
!= type
)
1184 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1189 name
= xstrdup (str
);
1190 new = XNEW (reg_entry
);
1193 new->number
= number
;
1195 new->builtin
= FALSE
;
1197 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1203 /* Look for the .req directive. This is of the form:
1205 new_register_name .req existing_register_name
1207 If we find one, or if it looks sufficiently like one that we want to
1208 handle any error here, return TRUE. Otherwise return FALSE. */
1211 create_register_alias (char *newname
, char *p
)
1213 const reg_entry
*old
;
1214 char *oldname
, *nbuf
;
1217 /* The input scrubber ensures that whitespace after the mnemonic is
1218 collapsed to single spaces. */
1220 if (strncmp (oldname
, " .req ", 6) != 0)
1224 if (*oldname
== '\0')
1227 old
= hash_find (aarch64_reg_hsh
, oldname
);
1230 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1234 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1235 the desired alias name, and p points to its end. If not, then
1236 the desired alias name is in the global original_case_string. */
1237 #ifdef TC_CASE_SENSITIVE
1240 newname
= original_case_string
;
1241 nlen
= strlen (newname
);
1244 nbuf
= xmemdup0 (newname
, nlen
);
1246 /* Create aliases under the new name as stated; an all-lowercase
1247 version of the new name; and an all-uppercase version of the new
1249 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1251 for (p
= nbuf
; *p
; p
++)
1254 if (strncmp (nbuf
, newname
, nlen
))
1256 /* If this attempt to create an additional alias fails, do not bother
1257 trying to create the all-lower case alias. We will fail and issue
1258 a second, duplicate error message. This situation arises when the
1259 programmer does something like:
1262 The second .req creates the "Foo" alias but then fails to create
1263 the artificial FOO alias because it has already been created by the
1265 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1272 for (p
= nbuf
; *p
; p
++)
1275 if (strncmp (nbuf
, newname
, nlen
))
1276 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1283 /* Should never be called, as .req goes between the alias and the
1284 register name, not at the beginning of the line. */
1286 s_req (int a ATTRIBUTE_UNUSED
)
1288 as_bad (_("invalid syntax for .req directive"));
1291 /* The .unreq directive deletes an alias which was previously defined
1292 by .req. For example:
1298 s_unreq (int a ATTRIBUTE_UNUSED
)
1303 name
= input_line_pointer
;
1305 while (*input_line_pointer
!= 0
1306 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1307 ++input_line_pointer
;
1309 saved_char
= *input_line_pointer
;
1310 *input_line_pointer
= 0;
1313 as_bad (_("invalid syntax for .unreq directive"));
1316 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1319 as_bad (_("unknown register alias '%s'"), name
);
1320 else if (reg
->builtin
)
1321 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1328 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1329 free ((char *) reg
->name
);
1332 /* Also locate the all upper case and all lower case versions.
1333 Do not complain if we cannot find one or the other as it
1334 was probably deleted above. */
1336 nbuf
= strdup (name
);
1337 for (p
= nbuf
; *p
; p
++)
1339 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1342 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1343 free ((char *) reg
->name
);
1347 for (p
= nbuf
; *p
; p
++)
1349 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1352 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1353 free ((char *) reg
->name
);
1361 *input_line_pointer
= saved_char
;
1362 demand_empty_rest_of_line ();
1365 /* Directives: Instruction set selection. */
1368 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1369 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1370 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1371 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1373 /* Create a new mapping symbol for the transition to STATE. */
1376 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1379 const char *symname
;
1386 type
= BSF_NO_FLAGS
;
1390 type
= BSF_NO_FLAGS
;
1396 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1397 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1399 /* Save the mapping symbols for future reference. Also check that
1400 we do not place two mapping symbols at the same offset within a
1401 frag. We'll handle overlap between frags in
1402 check_mapping_symbols.
1404 If .fill or other data filling directive generates zero sized data,
1405 the mapping symbol for the following code will have the same value
1406 as the one generated for the data filling directive. In this case,
1407 we replace the old symbol with the new one at the same address. */
1410 if (frag
->tc_frag_data
.first_map
!= NULL
)
1412 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1413 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1416 frag
->tc_frag_data
.first_map
= symbolP
;
1418 if (frag
->tc_frag_data
.last_map
!= NULL
)
1420 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1421 S_GET_VALUE (symbolP
));
1422 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1423 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1426 frag
->tc_frag_data
.last_map
= symbolP
;
1429 /* We must sometimes convert a region marked as code to data during
1430 code alignment, if an odd number of bytes have to be padded. The
1431 code mapping symbol is pushed to an aligned address. */
1434 insert_data_mapping_symbol (enum mstate state
,
1435 valueT value
, fragS
* frag
, offsetT bytes
)
1437 /* If there was already a mapping symbol, remove it. */
1438 if (frag
->tc_frag_data
.last_map
!= NULL
1439 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1440 frag
->fr_address
+ value
)
1442 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1446 know (frag
->tc_frag_data
.first_map
== symp
);
1447 frag
->tc_frag_data
.first_map
= NULL
;
1449 frag
->tc_frag_data
.last_map
= NULL
;
1450 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1453 make_mapping_symbol (MAP_DATA
, value
, frag
);
1454 make_mapping_symbol (state
, value
+ bytes
, frag
);
1457 static void mapping_state_2 (enum mstate state
, int max_chars
);
1459 /* Set the mapping state to STATE. Only call this when about to
1460 emit some STATE bytes to the file. */
1463 mapping_state (enum mstate state
)
1465 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1467 if (state
== MAP_INSN
)
1468 /* AArch64 instructions require 4-byte alignment. When emitting
1469 instructions into any section, record the appropriate section
1471 record_alignment (now_seg
, 2);
1473 if (mapstate
== state
)
1474 /* The mapping symbol has already been emitted.
1475 There is nothing else to do. */
1478 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1479 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1480 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1481 evaluated later in the next else. */
1483 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1485 /* Only add the symbol if the offset is > 0:
1486 if we're at the first frag, check it's size > 0;
1487 if we're not at the first frag, then for sure
1488 the offset is > 0. */
1489 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1490 const int add_symbol
= (frag_now
!= frag_first
)
1491 || (frag_now_fix () > 0);
1494 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1498 mapping_state_2 (state
, 0);
1501 /* Same as mapping_state, but MAX_CHARS bytes have already been
1502 allocated. Put the mapping symbol that far back. */
1505 mapping_state_2 (enum mstate state
, int max_chars
)
1507 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1509 if (!SEG_NORMAL (now_seg
))
1512 if (mapstate
== state
)
1513 /* The mapping symbol has already been emitted.
1514 There is nothing else to do. */
1517 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1518 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1521 #define mapping_state(x) /* nothing */
1522 #define mapping_state_2(x, y) /* nothing */
1525 /* Directives: sectioning and alignment. */
1528 s_bss (int ignore ATTRIBUTE_UNUSED
)
1530 /* We don't support putting frags in the BSS segment, we fake it by
1531 marking in_bss, then looking at s_skip for clues. */
1532 subseg_set (bss_section
, 0);
1533 demand_empty_rest_of_line ();
1534 mapping_state (MAP_DATA
);
1538 s_even (int ignore ATTRIBUTE_UNUSED
)
1540 /* Never make frag if expect extra pass. */
1542 frag_align (1, 0, 0);
1544 record_alignment (now_seg
, 1);
1546 demand_empty_rest_of_line ();
1549 /* Directives: Literal pools. */
1551 static literal_pool
*
1552 find_literal_pool (int size
)
1556 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1558 if (pool
->section
== now_seg
1559 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1566 static literal_pool
*
1567 find_or_make_literal_pool (int size
)
1569 /* Next literal pool ID number. */
1570 static unsigned int latest_pool_num
= 1;
1573 pool
= find_literal_pool (size
);
1577 /* Create a new pool. */
1578 pool
= XNEW (literal_pool
);
1582 /* Currently we always put the literal pool in the current text
1583 section. If we were generating "small" model code where we
1584 knew that all code and initialised data was within 1MB then
1585 we could output literals to mergeable, read-only data
1588 pool
->next_free_entry
= 0;
1589 pool
->section
= now_seg
;
1590 pool
->sub_section
= now_subseg
;
1592 pool
->next
= list_of_pools
;
1593 pool
->symbol
= NULL
;
1595 /* Add it to the list. */
1596 list_of_pools
= pool
;
1599 /* New pools, and emptied pools, will have a NULL symbol. */
1600 if (pool
->symbol
== NULL
)
1602 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1603 (valueT
) 0, &zero_address_frag
);
1604 pool
->id
= latest_pool_num
++;
1611 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1612 Return TRUE on success, otherwise return FALSE. */
1614 add_to_lit_pool (expressionS
*exp
, int size
)
1619 pool
= find_or_make_literal_pool (size
);
1621 /* Check if this literal value is already in the pool. */
1622 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1624 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1626 if ((litexp
->X_op
== exp
->X_op
)
1627 && (exp
->X_op
== O_constant
)
1628 && (litexp
->X_add_number
== exp
->X_add_number
)
1629 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1632 if ((litexp
->X_op
== exp
->X_op
)
1633 && (exp
->X_op
== O_symbol
)
1634 && (litexp
->X_add_number
== exp
->X_add_number
)
1635 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1636 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1640 /* Do we need to create a new entry? */
1641 if (entry
== pool
->next_free_entry
)
1643 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1645 set_syntax_error (_("literal pool overflow"));
1649 pool
->literals
[entry
].exp
= *exp
;
1650 pool
->next_free_entry
+= 1;
1651 if (exp
->X_op
== O_big
)
1653 /* PR 16688: Bignums are held in a single global array. We must
1654 copy and preserve that value now, before it is overwritten. */
1655 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1657 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1658 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1661 pool
->literals
[entry
].bignum
= NULL
;
1664 exp
->X_op
= O_symbol
;
1665 exp
->X_add_number
= ((int) entry
) * size
;
1666 exp
->X_add_symbol
= pool
->symbol
;
1671 /* Can't use symbol_new here, so have to create a symbol and then at
1672 a later date assign it a value. Thats what these functions do. */
1675 symbol_locate (symbolS
* symbolP
,
1676 const char *name
,/* It is copied, the caller can modify. */
1677 segT segment
, /* Segment identifier (SEG_<something>). */
1678 valueT valu
, /* Symbol value. */
1679 fragS
* frag
) /* Associated fragment. */
1682 char *preserved_copy_of_name
;
1684 name_length
= strlen (name
) + 1; /* +1 for \0. */
1685 obstack_grow (¬es
, name
, name_length
);
1686 preserved_copy_of_name
= obstack_finish (¬es
);
1688 #ifdef tc_canonicalize_symbol_name
1689 preserved_copy_of_name
=
1690 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1693 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1695 S_SET_SEGMENT (symbolP
, segment
);
1696 S_SET_VALUE (symbolP
, valu
);
1697 symbol_clear_list_pointers (symbolP
);
1699 symbol_set_frag (symbolP
, frag
);
1701 /* Link to end of symbol chain. */
1703 extern int symbol_table_frozen
;
1705 if (symbol_table_frozen
)
1709 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1711 obj_symbol_new_hook (symbolP
);
1713 #ifdef tc_symbol_new_hook
1714 tc_symbol_new_hook (symbolP
);
1718 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1719 #endif /* DEBUG_SYMS */
1724 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1731 for (align
= 2; align
<= 4; align
++)
1733 int size
= 1 << align
;
1735 pool
= find_literal_pool (size
);
1736 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1739 mapping_state (MAP_DATA
);
1741 /* Align pool as you have word accesses.
1742 Only make a frag if we have to. */
1744 frag_align (align
, 0, 0);
1746 record_alignment (now_seg
, align
);
1748 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1750 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1751 (valueT
) frag_now_fix (), frag_now
);
1752 symbol_table_insert (pool
->symbol
);
1754 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1756 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1758 if (exp
->X_op
== O_big
)
1760 /* PR 16688: Restore the global bignum value. */
1761 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1762 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1763 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1766 /* First output the expression in the instruction to the pool. */
1767 emit_expr (exp
, size
); /* .word|.xword */
1769 if (exp
->X_op
== O_big
)
1771 free (pool
->literals
[entry
].bignum
);
1772 pool
->literals
[entry
].bignum
= NULL
;
1776 /* Mark the pool as empty. */
1777 pool
->next_free_entry
= 0;
1778 pool
->symbol
= NULL
;
1783 /* Forward declarations for functions below, in the MD interface
1785 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1786 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1788 /* Directives: Data. */
1789 /* N.B. the support for relocation suffix in this directive needs to be
1790 implemented properly. */
1793 s_aarch64_elf_cons (int nbytes
)
1797 #ifdef md_flush_pending_output
1798 md_flush_pending_output ();
1801 if (is_it_end_of_statement ())
1803 demand_empty_rest_of_line ();
1807 #ifdef md_cons_align
1808 md_cons_align (nbytes
);
1811 mapping_state (MAP_DATA
);
1814 struct reloc_table_entry
*reloc
;
1818 if (exp
.X_op
!= O_symbol
)
1819 emit_expr (&exp
, (unsigned int) nbytes
);
1822 skip_past_char (&input_line_pointer
, '#');
1823 if (skip_past_char (&input_line_pointer
, ':'))
1825 reloc
= find_reloc_table_entry (&input_line_pointer
);
1827 as_bad (_("unrecognized relocation suffix"));
1829 as_bad (_("unimplemented relocation suffix"));
1830 ignore_rest_of_line ();
1834 emit_expr (&exp
, (unsigned int) nbytes
);
1837 while (*input_line_pointer
++ == ',');
1839 /* Put terminator back into stream. */
1840 input_line_pointer
--;
1841 demand_empty_rest_of_line ();
1844 #endif /* OBJ_ELF */
1846 /* Output a 32-bit word, but mark as an instruction. */
1849 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1853 #ifdef md_flush_pending_output
1854 md_flush_pending_output ();
1857 if (is_it_end_of_statement ())
1859 demand_empty_rest_of_line ();
1863 /* Sections are assumed to start aligned. In executable section, there is no
1864 MAP_DATA symbol pending. So we only align the address during
1865 MAP_DATA --> MAP_INSN transition.
1866 For other sections, this is not guaranteed. */
1867 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1868 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1869 frag_align_code (2, 0);
1872 mapping_state (MAP_INSN
);
1878 if (exp
.X_op
!= O_constant
)
1880 as_bad (_("constant expression required"));
1881 ignore_rest_of_line ();
1885 if (target_big_endian
)
1887 unsigned int val
= exp
.X_add_number
;
1888 exp
.X_add_number
= SWAP_32 (val
);
1890 emit_expr (&exp
, 4);
1892 while (*input_line_pointer
++ == ',');
1894 /* Put terminator back into stream. */
1895 input_line_pointer
--;
1896 demand_empty_rest_of_line ();
1900 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1903 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1909 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1910 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1912 demand_empty_rest_of_line ();
1915 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1918 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1922 /* Since we're just labelling the code, there's no need to define a
1925 /* Make sure there is enough room in this frag for the following
1926 blr. This trick only works if the blr follows immediately after
1927 the .tlsdesc directive. */
1929 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1930 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1932 demand_empty_rest_of_line ();
1935 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1938 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1944 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1945 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1947 demand_empty_rest_of_line ();
1949 #endif /* OBJ_ELF */
1951 static void s_aarch64_arch (int);
1952 static void s_aarch64_cpu (int);
1953 static void s_aarch64_arch_extension (int);
1955 /* This table describes all the machine specific pseudo-ops the assembler
1956 has to support. The fields are:
1957 pseudo-op name without dot
1958 function to call to execute this pseudo-op
1959 Integer arg to pass to the function. */
1961 const pseudo_typeS md_pseudo_table
[] = {
1962 /* Never called because '.req' does not start a line. */
1964 {"unreq", s_unreq
, 0},
1966 {"even", s_even
, 0},
1967 {"ltorg", s_ltorg
, 0},
1968 {"pool", s_ltorg
, 0},
1969 {"cpu", s_aarch64_cpu
, 0},
1970 {"arch", s_aarch64_arch
, 0},
1971 {"arch_extension", s_aarch64_arch_extension
, 0},
1972 {"inst", s_aarch64_inst
, 0},
1974 {"tlsdescadd", s_tlsdescadd
, 0},
1975 {"tlsdesccall", s_tlsdesccall
, 0},
1976 {"tlsdescldr", s_tlsdescldr
, 0},
1977 {"word", s_aarch64_elf_cons
, 4},
1978 {"long", s_aarch64_elf_cons
, 4},
1979 {"xword", s_aarch64_elf_cons
, 8},
1980 {"dword", s_aarch64_elf_cons
, 8},
1986 /* Check whether STR points to a register name followed by a comma or the
1987 end of line; REG_TYPE indicates which register types are checked
1988 against. Return TRUE if STR is such a register name; otherwise return
1989 FALSE. The function does not intend to produce any diagnostics, but since
1990 the register parser aarch64_reg_parse, which is called by this function,
1991 does produce diagnostics, we call clear_error to clear any diagnostics
1992 that may be generated by aarch64_reg_parse.
1993 Also, the function returns FALSE directly if there is any user error
1994 present at the function entry. This prevents the existing diagnostics
1995 state from being spoiled.
1996 The function currently serves parse_constant_immediate and
1997 parse_big_immediate only. */
1999 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2003 /* Prevent the diagnostics state from being spoiled. */
2007 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2009 /* Clear the parsing error that may be set by the reg parser. */
2012 if (reg
== PARSE_FAIL
)
2015 skip_whitespace (str
);
2016 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2022 /* Parser functions used exclusively in instruction operands. */
2024 /* Parse an immediate expression which may not be constant.
2026 To prevent the expression parser from pushing a register name
2027 into the symbol table as an undefined symbol, firstly a check is
2028 done to find out whether STR is a valid register name followed
2029 by a comma or the end of line. Return FALSE if STR is such a
2033 parse_immediate_expression (char **str
, expressionS
*exp
)
2035 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2037 set_recoverable_error (_("immediate operand required"));
2041 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2043 if (exp
->X_op
== O_absent
)
2045 set_fatal_syntax_error (_("missing immediate expression"));
2052 /* Constant immediate-value read function for use in insn parsing.
2053 STR points to the beginning of the immediate (with the optional
2054 leading #); *VAL receives the value.
2056 Return TRUE on success; otherwise return FALSE. */
2059 parse_constant_immediate (char **str
, int64_t * val
)
2063 if (! parse_immediate_expression (str
, &exp
))
2066 if (exp
.X_op
!= O_constant
)
2068 set_syntax_error (_("constant expression required"));
2072 *val
= exp
.X_add_number
;
2077 encode_imm_float_bits (uint32_t imm
)
2079 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2080 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2083 /* Return TRUE if the single-precision floating-point value encoded in IMM
2084 can be expressed in the AArch64 8-bit signed floating-point format with
2085 3-bit exponent and normalized 4 bits of precision; in other words, the
2086 floating-point value must be expressable as
2087 (+/-) n / 16 * power (2, r)
2088 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2091 aarch64_imm_float_p (uint32_t imm
)
2093 /* If a single-precision floating-point value has the following bit
2094 pattern, it can be expressed in the AArch64 8-bit floating-point
2097 3 32222222 2221111111111
2098 1 09876543 21098765432109876543210
2099 n Eeeeeexx xxxx0000000000000000000
2101 where n, e and each x are either 0 or 1 independently, with
2106 /* Prepare the pattern for 'Eeeeee'. */
2107 if (((imm
>> 30) & 0x1) == 0)
2108 pattern
= 0x3e000000;
2110 pattern
= 0x40000000;
2112 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2113 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2116 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2118 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2119 8-bit signed floating-point format with 3-bit exponent and normalized 4
2120 bits of precision (i.e. can be used in an FMOV instruction); return the
2121 equivalent single-precision encoding in *FPWORD.
2123 Otherwise return FALSE. */
2126 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2128 /* If a double-precision floating-point value has the following bit
2129 pattern, it can be expressed in the AArch64 8-bit floating-point
2132 6 66655555555 554444444...21111111111
2133 3 21098765432 109876543...098765432109876543210
2134 n Eeeeeeeeexx xxxx00000...000000000000000000000
2136 where n, e and each x are either 0 or 1 independently, with
2140 uint32_t high32
= imm
>> 32;
2142 /* Lower 32 bits need to be 0s. */
2143 if ((imm
& 0xffffffff) != 0)
2146 /* Prepare the pattern for 'Eeeeeeeee'. */
2147 if (((high32
>> 30) & 0x1) == 0)
2148 pattern
= 0x3fc00000;
2150 pattern
= 0x40000000;
2152 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2153 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2155 /* Convert to the single-precision encoding.
2157 n Eeeeeeeeexx xxxx00000...000000000000000000000
2159 n Eeeeeexx xxxx0000000000000000000. */
2160 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2161 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2168 /* Parse a floating-point immediate. Return TRUE on success and return the
2169 value in *IMMED in the format of IEEE754 single-precision encoding.
2170 *CCP points to the start of the string; DP_P is TRUE when the immediate
2171 is expected to be in double-precision (N.B. this only matters when
2172 hexadecimal representation is involved).
2174 N.B. 0.0 is accepted by this function. */
2177 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2181 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2182 int found_fpchar
= 0;
2184 unsigned fpword
= 0;
2185 bfd_boolean hex_p
= FALSE
;
2187 skip_past_char (&str
, '#');
2190 skip_whitespace (fpnum
);
2192 if (strncmp (fpnum
, "0x", 2) == 0)
2194 /* Support the hexadecimal representation of the IEEE754 encoding.
2195 Double-precision is expected when DP_P is TRUE, otherwise the
2196 representation should be in single-precision. */
2197 if (! parse_constant_immediate (&str
, &val
))
2202 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2205 else if ((uint64_t) val
> 0xffffffff)
2214 /* We must not accidentally parse an integer as a floating-point number.
2215 Make sure that the value we parse is not an integer by checking for
2216 special characters '.' or 'e'. */
2217 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2218 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2232 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2235 /* Our FP word must be 32 bits (single-precision FP). */
2236 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2238 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2243 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2251 set_fatal_syntax_error (_("invalid floating-point constant"));
2255 /* Less-generic immediate-value read function with the possibility of loading
2256 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2259 To prevent the expression parser from pushing a register name into the
2260 symbol table as an undefined symbol, a check is firstly done to find
2261 out whether STR is a valid register name followed by a comma or the end
2262 of line. Return FALSE if STR is such a register. */
2265 parse_big_immediate (char **str
, int64_t *imm
)
2269 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2271 set_syntax_error (_("immediate operand required"));
2275 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2277 if (inst
.reloc
.exp
.X_op
== O_constant
)
2278 *imm
= inst
.reloc
.exp
.X_add_number
;
2285 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2286 if NEED_LIBOPCODES is non-zero, the fixup will need
2287 assistance from the libopcodes. */
2290 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2291 const aarch64_opnd_info
*operand
,
2292 int need_libopcodes_p
)
2294 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2295 reloc
->opnd
= operand
->type
;
2296 if (need_libopcodes_p
)
2297 reloc
->need_libopcodes_p
= 1;
2300 /* Return TRUE if the instruction needs to be fixed up later internally by
2301 the GAS; otherwise return FALSE. */
2303 static inline bfd_boolean
2304 aarch64_gas_internal_fixup_p (void)
2306 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2309 /* Assign the immediate value to the relavant field in *OPERAND if
2310 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2311 needs an internal fixup in a later stage.
2312 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2313 IMM.VALUE that may get assigned with the constant. */
2315 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2316 aarch64_opnd_info
*operand
,
2318 int need_libopcodes_p
,
2321 if (reloc
->exp
.X_op
== O_constant
)
2324 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2326 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2327 reloc
->type
= BFD_RELOC_UNUSED
;
2331 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2332 /* Tell libopcodes to ignore this operand or not. This is helpful
2333 when one of the operands needs to be fixed up later but we need
2334 libopcodes to check the other operands. */
2335 operand
->skip
= skip_p
;
2339 /* Relocation modifiers. Each entry in the table contains the textual
2340 name for the relocation which may be placed before a symbol used as
2341 a load/store offset, or add immediate. It must be surrounded by a
2342 leading and trailing colon, for example:
2344 ldr x0, [x1, #:rello:varsym]
2345 add x0, x1, #:rello:varsym */
2347 struct reloc_table_entry
2351 bfd_reloc_code_real_type adr_type
;
2352 bfd_reloc_code_real_type adrp_type
;
2353 bfd_reloc_code_real_type movw_type
;
2354 bfd_reloc_code_real_type add_type
;
2355 bfd_reloc_code_real_type ldst_type
;
2356 bfd_reloc_code_real_type ld_literal_type
;
2359 static struct reloc_table_entry reloc_table
[] = {
2360 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2365 BFD_RELOC_AARCH64_ADD_LO12
,
2366 BFD_RELOC_AARCH64_LDST_LO12
,
2369 /* Higher 21 bits of pc-relative page offset: ADRP */
2372 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2378 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2381 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2387 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2391 BFD_RELOC_AARCH64_MOVW_G0
,
2396 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2400 BFD_RELOC_AARCH64_MOVW_G0_S
,
2405 /* Less significant bits 0-15 of address/value: MOVK, no check */
2409 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2414 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2418 BFD_RELOC_AARCH64_MOVW_G1
,
2423 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2427 BFD_RELOC_AARCH64_MOVW_G1_S
,
2432 /* Less significant bits 16-31 of address/value: MOVK, no check */
2436 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2441 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2445 BFD_RELOC_AARCH64_MOVW_G2
,
2450 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2454 BFD_RELOC_AARCH64_MOVW_G2_S
,
2459 /* Less significant bits 32-47 of address/value: MOVK, no check */
2463 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2468 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2472 BFD_RELOC_AARCH64_MOVW_G3
,
2477 /* Get to the page containing GOT entry for a symbol. */
2480 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2484 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2486 /* 12 bit offset into the page containing GOT entry for that symbol. */
2492 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2495 /* 0-15 bits of address/value: MOVk, no check. */
2499 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2504 /* Most significant bits 16-31 of address/value: MOVZ. */
2508 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2513 /* 15 bit offset into the page containing GOT entry for that symbol. */
2519 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2522 /* Get to the page containing GOT TLS entry for a symbol */
2523 {"gottprel_g0_nc", 0,
2526 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2531 /* Get to the page containing GOT TLS entry for a symbol */
2535 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2540 /* Get to the page containing GOT TLS entry for a symbol */
2542 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2543 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2549 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2554 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2558 /* Lower 16 bits address/value: MOVk. */
2562 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2567 /* Most significant bits 16-31 of address/value: MOVZ. */
2571 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2576 /* Get to the page containing GOT TLS entry for a symbol */
2578 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2579 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2583 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2585 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2590 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2591 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2594 /* Get to the page containing GOT TLS entry for a symbol.
2595 The same as GD, we allocate two consecutive GOT slots
2596 for module index and module offset, the only difference
2597 with GD is the module offset should be intialized to
2598 zero without any outstanding runtime relocation. */
2600 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2601 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2607 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2608 {"tlsldm_lo12_nc", 0,
2612 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2616 /* 12 bit offset into the module TLS base address. */
2621 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2622 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2625 /* Same as dtprel_lo12, no overflow check. */
2626 {"dtprel_lo12_nc", 0,
2630 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2631 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2634 /* bits[23:12] of offset to the module TLS base address. */
2639 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2643 /* bits[15:0] of offset to the module TLS base address. */
2647 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2652 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2656 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2661 /* bits[31:16] of offset to the module TLS base address. */
2665 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2670 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2674 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2679 /* bits[47:32] of offset to the module TLS base address. */
2683 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2688 /* Lower 16 bit offset into GOT entry for a symbol */
2689 {"tlsdesc_off_g0_nc", 0,
2692 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2697 /* Higher 16 bit offset into GOT entry for a symbol */
2698 {"tlsdesc_off_g1", 0,
2701 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2706 /* Get to the page containing GOT TLS entry for a symbol */
2709 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2713 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2715 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2716 {"gottprel_lo12", 0,
2721 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2724 /* Get tp offset for a symbol. */
2729 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2733 /* Get tp offset for a symbol. */
2738 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2742 /* Get tp offset for a symbol. */
2747 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2751 /* Get tp offset for a symbol. */
2752 {"tprel_lo12_nc", 0,
2756 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2760 /* Most significant bits 32-47 of address/value: MOVZ. */
2764 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2769 /* Most significant bits 16-31 of address/value: MOVZ. */
2773 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2778 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2782 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2787 /* Most significant bits 0-15 of address/value: MOVZ. */
2791 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2796 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2800 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2805 /* 15bit offset from got entry to base address of GOT table. */
2811 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2814 /* 14bit offset from got entry to base address of GOT table. */
2820 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2824 /* Given the address of a pointer pointing to the textual name of a
2825 relocation as may appear in assembler source, attempt to find its
2826 details in reloc_table. The pointer will be updated to the character
2827 after the trailing colon. On failure, NULL will be returned;
2828 otherwise return the reloc_table_entry. */
2830 static struct reloc_table_entry
*
2831 find_reloc_table_entry (char **str
)
2834 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2836 int length
= strlen (reloc_table
[i
].name
);
2838 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2839 && (*str
)[length
] == ':')
2841 *str
+= (length
+ 1);
2842 return &reloc_table
[i
];
2849 /* Mode argument to parse_shift and parser_shifter_operand. */
2850 enum parse_shift_mode
2852 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2854 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2856 SHIFTED_LSL
, /* bare "lsl #n" */
2857 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2858 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2861 /* Parse a <shift> operator on an AArch64 data processing instruction.
2862 Return TRUE on success; otherwise return FALSE. */
2864 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2866 const struct aarch64_name_value_pair
*shift_op
;
2867 enum aarch64_modifier_kind kind
;
2873 for (p
= *str
; ISALPHA (*p
); p
++)
2878 set_syntax_error (_("shift expression expected"));
2882 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2884 if (shift_op
== NULL
)
2886 set_syntax_error (_("shift operator expected"));
2890 kind
= aarch64_get_operand_modifier (shift_op
);
2892 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2894 set_syntax_error (_("invalid use of 'MSL'"));
2900 case SHIFTED_LOGIC_IMM
:
2901 if (aarch64_extend_operator_p (kind
) == TRUE
)
2903 set_syntax_error (_("extending shift is not permitted"));
2908 case SHIFTED_ARITH_IMM
:
2909 if (kind
== AARCH64_MOD_ROR
)
2911 set_syntax_error (_("'ROR' shift is not permitted"));
2917 if (kind
!= AARCH64_MOD_LSL
)
2919 set_syntax_error (_("only 'LSL' shift is permitted"));
2924 case SHIFTED_REG_OFFSET
:
2925 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2926 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2928 set_fatal_syntax_error
2929 (_("invalid shift for the register offset addressing mode"));
2934 case SHIFTED_LSL_MSL
:
2935 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2937 set_syntax_error (_("invalid shift operator"));
2946 /* Whitespace can appear here if the next thing is a bare digit. */
2947 skip_whitespace (p
);
2949 /* Parse shift amount. */
2951 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2952 exp
.X_op
= O_absent
;
2955 if (is_immediate_prefix (*p
))
2960 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2962 if (exp
.X_op
== O_absent
)
2964 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2966 set_syntax_error (_("missing shift amount"));
2969 operand
->shifter
.amount
= 0;
2971 else if (exp
.X_op
!= O_constant
)
2973 set_syntax_error (_("constant shift amount required"));
2976 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2978 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2983 operand
->shifter
.amount
= exp
.X_add_number
;
2984 operand
->shifter
.amount_present
= 1;
2987 operand
->shifter
.operator_present
= 1;
2988 operand
->shifter
.kind
= kind
;
2994 /* Parse a <shifter_operand> for a data processing instruction:
2997 #<immediate>, LSL #imm
2999 Validation of immediate operands is deferred to md_apply_fix.
3001 Return TRUE on success; otherwise return FALSE. */
3004 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3005 enum parse_shift_mode mode
)
3009 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3014 /* Accept an immediate expression. */
3015 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3018 /* Accept optional LSL for arithmetic immediate values. */
3019 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3020 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3023 /* Not accept any shifter for logical immediate values. */
3024 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3025 && parse_shift (&p
, operand
, mode
))
3027 set_syntax_error (_("unexpected shift operator"));
3035 /* Parse a <shifter_operand> for a data processing instruction:
3040 #<immediate>, LSL #imm
3042 where <shift> is handled by parse_shift above, and the last two
3043 cases are handled by the function above.
3045 Validation of immediate operands is deferred to md_apply_fix.
3047 Return TRUE on success; otherwise return FALSE. */
3050 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3051 enum parse_shift_mode mode
)
3054 int isreg32
, isregzero
;
3055 enum aarch64_operand_class opd_class
3056 = aarch64_get_operand_class (operand
->type
);
3059 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3061 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3063 set_syntax_error (_("unexpected register in the immediate operand"));
3067 if (!isregzero
&& reg
== REG_SP
)
3069 set_syntax_error (BAD_SP
);
3073 operand
->reg
.regno
= reg
;
3074 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3076 /* Accept optional shift operation on register. */
3077 if (! skip_past_comma (str
))
3080 if (! parse_shift (str
, operand
, mode
))
3085 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3088 (_("integer register expected in the extended/shifted operand "
3093 /* We have a shifted immediate variable. */
3094 return parse_shifter_operand_imm (str
, operand
, mode
);
3097 /* Return TRUE on success; return FALSE otherwise. */
3100 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3101 enum parse_shift_mode mode
)
3105 /* Determine if we have the sequence of characters #: or just :
3106 coming next. If we do, then we check for a :rello: relocation
3107 modifier. If we don't, punt the whole lot to
3108 parse_shifter_operand. */
3110 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3112 struct reloc_table_entry
*entry
;
3120 /* Try to parse a relocation. Anything else is an error. */
3121 if (!(entry
= find_reloc_table_entry (str
)))
3123 set_syntax_error (_("unknown relocation modifier"));
3127 if (entry
->add_type
== 0)
3130 (_("this relocation modifier is not allowed on this instruction"));
3134 /* Save str before we decompose it. */
3137 /* Next, we parse the expression. */
3138 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3141 /* Record the relocation type (use the ADD variant here). */
3142 inst
.reloc
.type
= entry
->add_type
;
3143 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3145 /* If str is empty, we've reached the end, stop here. */
3149 /* Otherwise, we have a shifted reloc modifier, so rewind to
3150 recover the variable name and continue parsing for the shifter. */
3152 return parse_shifter_operand_imm (str
, operand
, mode
);
3155 return parse_shifter_operand (str
, operand
, mode
);
3158 /* Parse all forms of an address expression. Information is written
3159 to *OPERAND and/or inst.reloc.
3161 The A64 instruction set has the following addressing modes:
3164 [base] // in SIMD ld/st structure
3165 [base{,#0}] // in ld/st exclusive
3167 [base,Xm{,LSL #imm}]
3168 [base,Xm,SXTX {#imm}]
3169 [base,Wm,(S|U)XTW {#imm}]
3174 [base],Xm // in SIMD ld/st structure
3175 PC-relative (literal)
3179 (As a convenience, the notation "=immediate" is permitted in conjunction
3180 with the pc-relative literal load instructions to automatically place an
3181 immediate value or symbolic address in a nearby literal pool and generate
3182 a hidden label which references it.)
3184 Upon a successful parsing, the address structure in *OPERAND will be
3185 filled in the following way:
3187 .base_regno = <base>
3188 .offset.is_reg // 1 if the offset is a register
3190 .offset.regno = <Rm>
3192 For different addressing modes defined in the A64 ISA:
3195 .pcrel=0; .preind=1; .postind=0; .writeback=0
3197 .pcrel=0; .preind=1; .postind=0; .writeback=1
3199 .pcrel=0; .preind=0; .postind=1; .writeback=1
3200 PC-relative (literal)
3201 .pcrel=1; .preind=1; .postind=0; .writeback=0
3203 The shift/extension information, if any, will be stored in .shifter.
3205 It is the caller's responsibility to check for addressing modes not
3206 supported by the instruction, and to set inst.reloc.type. */
3209 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3210 int accept_reg_post_index
)
3214 int isreg32
, isregzero
;
3215 expressionS
*exp
= &inst
.reloc
.exp
;
3217 if (! skip_past_char (&p
, '['))
3219 /* =immediate or label. */
3220 operand
->addr
.pcrel
= 1;
3221 operand
->addr
.preind
= 1;
3223 /* #:<reloc_op>:<symbol> */
3224 skip_past_char (&p
, '#');
3225 if (reloc
&& skip_past_char (&p
, ':'))
3227 bfd_reloc_code_real_type ty
;
3228 struct reloc_table_entry
*entry
;
3230 /* Try to parse a relocation modifier. Anything else is
3232 entry
= find_reloc_table_entry (&p
);
3235 set_syntax_error (_("unknown relocation modifier"));
3239 switch (operand
->type
)
3241 case AARCH64_OPND_ADDR_PCREL21
:
3243 ty
= entry
->adr_type
;
3247 ty
= entry
->ld_literal_type
;
3254 (_("this relocation modifier is not allowed on this "
3260 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3262 set_syntax_error (_("invalid relocation expression"));
3266 /* #:<reloc_op>:<expr> */
3267 /* Record the relocation type. */
3268 inst
.reloc
.type
= ty
;
3269 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3274 if (skip_past_char (&p
, '='))
3275 /* =immediate; need to generate the literal in the literal pool. */
3276 inst
.gen_lit_pool
= 1;
3278 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3280 set_syntax_error (_("invalid address"));
3291 /* Accept SP and reject ZR */
3292 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3293 if (reg
== PARSE_FAIL
|| isreg32
)
3295 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3298 operand
->addr
.base_regno
= reg
;
3301 if (skip_past_comma (&p
))
3304 operand
->addr
.preind
= 1;
3306 /* Reject SP and accept ZR */
3307 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3308 if (reg
!= PARSE_FAIL
)
3311 operand
->addr
.offset
.regno
= reg
;
3312 operand
->addr
.offset
.is_reg
= 1;
3313 /* Shifted index. */
3314 if (skip_past_comma (&p
))
3317 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3318 /* Use the diagnostics set in parse_shift, so not set new
3319 error message here. */
3323 [base,Xm{,LSL #imm}]
3324 [base,Xm,SXTX {#imm}]
3325 [base,Wm,(S|U)XTW {#imm}] */
3326 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3327 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3328 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3332 set_syntax_error (_("invalid use of 32-bit register offset"));
3338 set_syntax_error (_("invalid use of 64-bit register offset"));
3344 /* [Xn,#:<reloc_op>:<symbol> */
3345 skip_past_char (&p
, '#');
3346 if (reloc
&& skip_past_char (&p
, ':'))
3348 struct reloc_table_entry
*entry
;
3350 /* Try to parse a relocation modifier. Anything else is
3352 if (!(entry
= find_reloc_table_entry (&p
)))
3354 set_syntax_error (_("unknown relocation modifier"));
3358 if (entry
->ldst_type
== 0)
3361 (_("this relocation modifier is not allowed on this "
3366 /* [Xn,#:<reloc_op>: */
3367 /* We now have the group relocation table entry corresponding to
3368 the name in the assembler source. Next, we parse the
3370 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3372 set_syntax_error (_("invalid relocation expression"));
3376 /* [Xn,#:<reloc_op>:<expr> */
3377 /* Record the load/store relocation type. */
3378 inst
.reloc
.type
= entry
->ldst_type
;
3379 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3381 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3383 set_syntax_error (_("invalid expression in the address"));
3390 if (! skip_past_char (&p
, ']'))
3392 set_syntax_error (_("']' expected"));
3396 if (skip_past_char (&p
, '!'))
3398 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3400 set_syntax_error (_("register offset not allowed in pre-indexed "
3401 "addressing mode"));
3405 operand
->addr
.writeback
= 1;
3407 else if (skip_past_comma (&p
))
3410 operand
->addr
.postind
= 1;
3411 operand
->addr
.writeback
= 1;
3413 if (operand
->addr
.preind
)
3415 set_syntax_error (_("cannot combine pre- and post-indexing"));
3419 if (accept_reg_post_index
3420 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3421 &isregzero
)) != PARSE_FAIL
)
3426 set_syntax_error (_("invalid 32-bit register offset"));
3429 operand
->addr
.offset
.regno
= reg
;
3430 operand
->addr
.offset
.is_reg
= 1;
3432 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3435 set_syntax_error (_("invalid expression in the address"));
3440 /* If at this point neither .preind nor .postind is set, we have a
3441 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3442 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3444 if (operand
->addr
.writeback
)
3447 set_syntax_error (_("missing offset in the pre-indexed address"));
3450 operand
->addr
.preind
= 1;
3451 inst
.reloc
.exp
.X_op
= O_constant
;
3452 inst
.reloc
.exp
.X_add_number
= 0;
3459 /* Return TRUE on success; otherwise return FALSE. */
3461 parse_address (char **str
, aarch64_opnd_info
*operand
,
3462 int accept_reg_post_index
)
3464 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3467 /* Return TRUE on success; otherwise return FALSE. */
3469 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3471 return parse_address_main (str
, operand
, 1, 0);
3474 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3475 Return TRUE on success; otherwise return FALSE. */
3477 parse_half (char **str
, int *internal_fixup_p
)
3481 skip_past_char (&p
, '#');
3483 gas_assert (internal_fixup_p
);
3484 *internal_fixup_p
= 0;
3488 struct reloc_table_entry
*entry
;
3490 /* Try to parse a relocation. Anything else is an error. */
3492 if (!(entry
= find_reloc_table_entry (&p
)))
3494 set_syntax_error (_("unknown relocation modifier"));
3498 if (entry
->movw_type
== 0)
3501 (_("this relocation modifier is not allowed on this instruction"));
3505 inst
.reloc
.type
= entry
->movw_type
;
3508 *internal_fixup_p
= 1;
3510 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3517 /* Parse an operand for an ADRP instruction:
3519 Return TRUE on success; otherwise return FALSE. */
3522 parse_adrp (char **str
)
3529 struct reloc_table_entry
*entry
;
3531 /* Try to parse a relocation. Anything else is an error. */
3533 if (!(entry
= find_reloc_table_entry (&p
)))
3535 set_syntax_error (_("unknown relocation modifier"));
3539 if (entry
->adrp_type
== 0)
3542 (_("this relocation modifier is not allowed on this instruction"));
3546 inst
.reloc
.type
= entry
->adrp_type
;
3549 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3551 inst
.reloc
.pc_rel
= 1;
3553 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3560 /* Miscellaneous. */
3562 /* Parse an option for a preload instruction. Returns the encoding for the
3563 option, or PARSE_FAIL. */
3566 parse_pldop (char **str
)
3569 const struct aarch64_name_value_pair
*o
;
3572 while (ISALNUM (*q
))
3575 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3583 /* Parse an option for a barrier instruction. Returns the encoding for the
3584 option, or PARSE_FAIL. */
3587 parse_barrier (char **str
)
3590 const asm_barrier_opt
*o
;
3593 while (ISALPHA (*q
))
3596 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3604 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3605 return 0 if successful. Otherwise return PARSE_FAIL. */
3608 parse_barrier_psb (char **str
,
3609 const struct aarch64_name_value_pair
** hint_opt
)
3612 const struct aarch64_name_value_pair
*o
;
3615 while (ISALPHA (*q
))
3618 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3621 set_fatal_syntax_error
3622 ( _("unknown or missing option to PSB"));
3626 if (o
->value
!= 0x11)
3628 /* PSB only accepts option name 'CSYNC'. */
3630 (_("the specified option is not accepted for PSB"));
3639 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3640 Returns the encoding for the option, or PARSE_FAIL.
3642 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3643 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3645 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3646 field, otherwise as a system register.
3650 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3651 int imple_defined_p
, int pstatefield_p
)
3655 const aarch64_sys_reg
*o
;
3659 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3661 *p
++ = TOLOWER (*q
);
3663 /* Assert that BUF be large enough. */
3664 gas_assert (p
- buf
== q
- *str
);
3666 o
= hash_find (sys_regs
, buf
);
3669 if (!imple_defined_p
)
3673 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3674 unsigned int op0
, op1
, cn
, cm
, op2
;
3676 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3679 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3681 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3686 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3687 as_bad (_("selected processor does not support PSTATE field "
3689 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3690 as_bad (_("selected processor does not support system register "
3692 if (aarch64_sys_reg_deprecated_p (o
))
3693 as_warn (_("system register name '%s' is deprecated and may be "
3694 "removed in a future release"), buf
);
3702 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3703 for the option, or NULL. */
3705 static const aarch64_sys_ins_reg
*
3706 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3710 const aarch64_sys_ins_reg
*o
;
3713 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3715 *p
++ = TOLOWER (*q
);
3718 o
= hash_find (sys_ins_regs
, buf
);
3722 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3723 as_bad (_("selected processor does not support system register "
3730 #define po_char_or_fail(chr) do { \
3731 if (! skip_past_char (&str, chr)) \
3735 #define po_reg_or_fail(regtype) do { \
3736 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3737 if (val == PARSE_FAIL) \
3739 set_default_error (); \
3744 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3745 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3746 &isreg32, &isregzero); \
3747 if (val == PARSE_FAIL) \
3749 set_default_error (); \
3752 info->reg.regno = val; \
3754 info->qualifier = AARCH64_OPND_QLF_W; \
3756 info->qualifier = AARCH64_OPND_QLF_X; \
3759 #define po_imm_nc_or_fail() do { \
3760 if (! parse_constant_immediate (&str, &val)) \
3764 #define po_imm_or_fail(min, max) do { \
3765 if (! parse_constant_immediate (&str, &val)) \
3767 if (val < min || val > max) \
3769 set_fatal_syntax_error (_("immediate value out of range "\
3770 #min " to "#max)); \
3775 #define po_misc_or_fail(expr) do { \
3780 /* encode the 12-bit imm field of Add/sub immediate */
3781 static inline uint32_t
3782 encode_addsub_imm (uint32_t imm
)
3787 /* encode the shift amount field of Add/sub immediate */
3788 static inline uint32_t
3789 encode_addsub_imm_shift_amount (uint32_t cnt
)
3795 /* encode the imm field of Adr instruction */
3796 static inline uint32_t
3797 encode_adr_imm (uint32_t imm
)
3799 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3800 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3803 /* encode the immediate field of Move wide immediate */
3804 static inline uint32_t
3805 encode_movw_imm (uint32_t imm
)
3810 /* encode the 26-bit offset of unconditional branch */
3811 static inline uint32_t
3812 encode_branch_ofs_26 (uint32_t ofs
)
3814 return ofs
& ((1 << 26) - 1);
3817 /* encode the 19-bit offset of conditional branch and compare & branch */
3818 static inline uint32_t
3819 encode_cond_branch_ofs_19 (uint32_t ofs
)
3821 return (ofs
& ((1 << 19) - 1)) << 5;
3824 /* encode the 19-bit offset of ld literal */
3825 static inline uint32_t
3826 encode_ld_lit_ofs_19 (uint32_t ofs
)
3828 return (ofs
& ((1 << 19) - 1)) << 5;
3831 /* Encode the 14-bit offset of test & branch. */
3832 static inline uint32_t
3833 encode_tst_branch_ofs_14 (uint32_t ofs
)
3835 return (ofs
& ((1 << 14) - 1)) << 5;
3838 /* Encode the 16-bit imm field of svc/hvc/smc. */
3839 static inline uint32_t
3840 encode_svc_imm (uint32_t imm
)
3845 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3846 static inline uint32_t
3847 reencode_addsub_switch_add_sub (uint32_t opcode
)
3849 return opcode
^ (1 << 30);
3852 static inline uint32_t
3853 reencode_movzn_to_movz (uint32_t opcode
)
3855 return opcode
| (1 << 30);
3858 static inline uint32_t
3859 reencode_movzn_to_movn (uint32_t opcode
)
3861 return opcode
& ~(1 << 30);
3864 /* Overall per-instruction processing. */
3866 /* We need to be able to fix up arbitrary expressions in some statements.
3867 This is so that we can handle symbols that are an arbitrary distance from
3868 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3869 which returns part of an address in a form which will be valid for
3870 a data instruction. We do this by pushing the expression into a symbol
3871 in the expr_section, and creating a fix for that. */
3874 fix_new_aarch64 (fragS
* frag
,
3876 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3886 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3890 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3897 /* Diagnostics on operands errors. */
3899 /* By default, output verbose error message.
3900 Disable the verbose error message by -mno-verbose-error. */
3901 static int verbose_error_p
= 1;
3903 #ifdef DEBUG_AARCH64
3904 /* N.B. this is only for the purpose of debugging. */
3905 const char* operand_mismatch_kind_names
[] =
3908 "AARCH64_OPDE_RECOVERABLE",
3909 "AARCH64_OPDE_SYNTAX_ERROR",
3910 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3911 "AARCH64_OPDE_INVALID_VARIANT",
3912 "AARCH64_OPDE_OUT_OF_RANGE",
3913 "AARCH64_OPDE_UNALIGNED",
3914 "AARCH64_OPDE_REG_LIST",
3915 "AARCH64_OPDE_OTHER_ERROR",
3917 #endif /* DEBUG_AARCH64 */
3919 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3921 When multiple errors of different kinds are found in the same assembly
3922 line, only the error of the highest severity will be picked up for
3923 issuing the diagnostics. */
3925 static inline bfd_boolean
3926 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3927 enum aarch64_operand_error_kind rhs
)
3929 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3930 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3931 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3932 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3933 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3934 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3935 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3936 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3940 /* Helper routine to get the mnemonic name from the assembly instruction
3941 line; should only be called for the diagnosis purpose, as there is
3942 string copy operation involved, which may affect the runtime
3943 performance if used in elsewhere. */
3946 get_mnemonic_name (const char *str
)
3948 static char mnemonic
[32];
3951 /* Get the first 15 bytes and assume that the full name is included. */
3952 strncpy (mnemonic
, str
, 31);
3953 mnemonic
[31] = '\0';
3955 /* Scan up to the end of the mnemonic, which must end in white space,
3956 '.', or end of string. */
3957 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3962 /* Append '...' to the truncated long name. */
3963 if (ptr
- mnemonic
== 31)
3964 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3970 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3972 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3973 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3976 /* Data strutures storing one user error in the assembly code related to
3979 struct operand_error_record
3981 const aarch64_opcode
*opcode
;
3982 aarch64_operand_error detail
;
3983 struct operand_error_record
*next
;
3986 typedef struct operand_error_record operand_error_record
;
3988 struct operand_errors
3990 operand_error_record
*head
;
3991 operand_error_record
*tail
;
3994 typedef struct operand_errors operand_errors
;
3996 /* Top-level data structure reporting user errors for the current line of
3998 The way md_assemble works is that all opcodes sharing the same mnemonic
3999 name are iterated to find a match to the assembly line. In this data
4000 structure, each of the such opcodes will have one operand_error_record
4001 allocated and inserted. In other words, excessive errors related with
4002 a single opcode are disregarded. */
4003 operand_errors operand_error_report
;
4005 /* Free record nodes. */
4006 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4008 /* Initialize the data structure that stores the operand mismatch
4009 information on assembling one line of the assembly code. */
4011 init_operand_error_report (void)
4013 if (operand_error_report
.head
!= NULL
)
4015 gas_assert (operand_error_report
.tail
!= NULL
);
4016 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4017 free_opnd_error_record_nodes
= operand_error_report
.head
;
4018 operand_error_report
.head
= NULL
;
4019 operand_error_report
.tail
= NULL
;
4022 gas_assert (operand_error_report
.tail
== NULL
);
4025 /* Return TRUE if some operand error has been recorded during the
4026 parsing of the current assembly line using the opcode *OPCODE;
4027 otherwise return FALSE. */
4028 static inline bfd_boolean
4029 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4031 operand_error_record
*record
= operand_error_report
.head
;
4032 return record
&& record
->opcode
== opcode
;
4035 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4036 OPCODE field is initialized with OPCODE.
4037 N.B. only one record for each opcode, i.e. the maximum of one error is
4038 recorded for each instruction template. */
4041 add_operand_error_record (const operand_error_record
* new_record
)
4043 const aarch64_opcode
*opcode
= new_record
->opcode
;
4044 operand_error_record
* record
= operand_error_report
.head
;
4046 /* The record may have been created for this opcode. If not, we need
4048 if (! opcode_has_operand_error_p (opcode
))
4050 /* Get one empty record. */
4051 if (free_opnd_error_record_nodes
== NULL
)
4053 record
= XNEW (operand_error_record
);
4057 record
= free_opnd_error_record_nodes
;
4058 free_opnd_error_record_nodes
= record
->next
;
4060 record
->opcode
= opcode
;
4061 /* Insert at the head. */
4062 record
->next
= operand_error_report
.head
;
4063 operand_error_report
.head
= record
;
4064 if (operand_error_report
.tail
== NULL
)
4065 operand_error_report
.tail
= record
;
4067 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4068 && record
->detail
.index
<= new_record
->detail
.index
4069 && operand_error_higher_severity_p (record
->detail
.kind
,
4070 new_record
->detail
.kind
))
4072 /* In the case of multiple errors found on operands related with a
4073 single opcode, only record the error of the leftmost operand and
4074 only if the error is of higher severity. */
4075 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4076 " the existing error %s on operand %d",
4077 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4078 new_record
->detail
.index
,
4079 operand_mismatch_kind_names
[record
->detail
.kind
],
4080 record
->detail
.index
);
4084 record
->detail
= new_record
->detail
;
4088 record_operand_error_info (const aarch64_opcode
*opcode
,
4089 aarch64_operand_error
*error_info
)
4091 operand_error_record record
;
4092 record
.opcode
= opcode
;
4093 record
.detail
= *error_info
;
4094 add_operand_error_record (&record
);
4097 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4098 error message *ERROR, for operand IDX (count from 0). */
4101 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4102 enum aarch64_operand_error_kind kind
,
4105 aarch64_operand_error info
;
4106 memset(&info
, 0, sizeof (info
));
4110 record_operand_error_info (opcode
, &info
);
4114 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4115 enum aarch64_operand_error_kind kind
,
4116 const char* error
, const int *extra_data
)
4118 aarch64_operand_error info
;
4122 info
.data
[0] = extra_data
[0];
4123 info
.data
[1] = extra_data
[1];
4124 info
.data
[2] = extra_data
[2];
4125 record_operand_error_info (opcode
, &info
);
4129 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4130 const char* error
, int lower_bound
,
4133 int data
[3] = {lower_bound
, upper_bound
, 0};
4134 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4138 /* Remove the operand error record for *OPCODE. */
4139 static void ATTRIBUTE_UNUSED
4140 remove_operand_error_record (const aarch64_opcode
*opcode
)
4142 if (opcode_has_operand_error_p (opcode
))
4144 operand_error_record
* record
= operand_error_report
.head
;
4145 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4146 operand_error_report
.head
= record
->next
;
4147 record
->next
= free_opnd_error_record_nodes
;
4148 free_opnd_error_record_nodes
= record
;
4149 if (operand_error_report
.head
== NULL
)
4151 gas_assert (operand_error_report
.tail
== record
);
4152 operand_error_report
.tail
= NULL
;
4157 /* Given the instruction in *INSTR, return the index of the best matched
4158 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4160 Return -1 if there is no qualifier sequence; return the first match
4161 if there is multiple matches found. */
4164 find_best_match (const aarch64_inst
*instr
,
4165 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4167 int i
, num_opnds
, max_num_matched
, idx
;
4169 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4172 DEBUG_TRACE ("no operand");
4176 max_num_matched
= 0;
4179 /* For each pattern. */
4180 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4183 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4185 /* Most opcodes has much fewer patterns in the list. */
4186 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4188 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4189 if (i
!= 0 && idx
== -1)
4190 /* If nothing has been matched, return the 1st sequence. */
4195 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4196 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4199 if (num_matched
> max_num_matched
)
4201 max_num_matched
= num_matched
;
4206 DEBUG_TRACE ("return with %d", idx
);
4210 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4211 corresponding operands in *INSTR. */
4214 assign_qualifier_sequence (aarch64_inst
*instr
,
4215 const aarch64_opnd_qualifier_t
*qualifiers
)
4218 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4219 gas_assert (num_opnds
);
4220 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4221 instr
->operands
[i
].qualifier
= *qualifiers
;
4224 /* Print operands for the diagnosis purpose. */
4227 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4228 const aarch64_opnd_info
*opnds
)
4232 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4236 /* We regard the opcode operand info more, however we also look into
4237 the inst->operands to support the disassembling of the optional
4239 The two operand code should be the same in all cases, apart from
4240 when the operand can be optional. */
4241 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4242 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4245 /* Generate the operand string in STR. */
4246 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
);
4250 strcat (buf
, i
== 0 ? " " : ",");
4252 /* Append the operand string. */
4257 /* Send to stderr a string as information. */
4260 output_info (const char *format
, ...)
4266 file
= as_where (&line
);
4270 fprintf (stderr
, "%s:%u: ", file
, line
);
4272 fprintf (stderr
, "%s: ", file
);
4274 fprintf (stderr
, _("Info: "));
4275 va_start (args
, format
);
4276 vfprintf (stderr
, format
, args
);
4278 (void) putc ('\n', stderr
);
4281 /* Output one operand error record. */
4284 output_operand_error_record (const operand_error_record
*record
, char *str
)
4286 const aarch64_operand_error
*detail
= &record
->detail
;
4287 int idx
= detail
->index
;
4288 const aarch64_opcode
*opcode
= record
->opcode
;
4289 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4290 : AARCH64_OPND_NIL
);
4292 switch (detail
->kind
)
4294 case AARCH64_OPDE_NIL
:
4298 case AARCH64_OPDE_SYNTAX_ERROR
:
4299 case AARCH64_OPDE_RECOVERABLE
:
4300 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4301 case AARCH64_OPDE_OTHER_ERROR
:
4302 /* Use the prepared error message if there is, otherwise use the
4303 operand description string to describe the error. */
4304 if (detail
->error
!= NULL
)
4307 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4309 as_bad (_("%s at operand %d -- `%s'"),
4310 detail
->error
, idx
+ 1, str
);
4314 gas_assert (idx
>= 0);
4315 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4316 aarch64_get_operand_desc (opd_code
), str
);
4320 case AARCH64_OPDE_INVALID_VARIANT
:
4321 as_bad (_("operand mismatch -- `%s'"), str
);
4322 if (verbose_error_p
)
4324 /* We will try to correct the erroneous instruction and also provide
4325 more information e.g. all other valid variants.
4327 The string representation of the corrected instruction and other
4328 valid variants are generated by
4330 1) obtaining the intermediate representation of the erroneous
4332 2) manipulating the IR, e.g. replacing the operand qualifier;
4333 3) printing out the instruction by calling the printer functions
4334 shared with the disassembler.
4336 The limitation of this method is that the exact input assembly
4337 line cannot be accurately reproduced in some cases, for example an
4338 optional operand present in the actual assembly line will be
4339 omitted in the output; likewise for the optional syntax rules,
4340 e.g. the # before the immediate. Another limitation is that the
4341 assembly symbols and relocation operations in the assembly line
4342 currently cannot be printed out in the error report. Last but not
4343 least, when there is other error(s) co-exist with this error, the
4344 'corrected' instruction may be still incorrect, e.g. given
4345 'ldnp h0,h1,[x0,#6]!'
4346 this diagnosis will provide the version:
4347 'ldnp s0,s1,[x0,#6]!'
4348 which is still not right. */
4349 size_t len
= strlen (get_mnemonic_name (str
));
4353 aarch64_inst
*inst_base
= &inst
.base
;
4354 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4357 reset_aarch64_instruction (&inst
);
4358 inst_base
->opcode
= opcode
;
4360 /* Reset the error report so that there is no side effect on the
4361 following operand parsing. */
4362 init_operand_error_report ();
4365 result
= parse_operands (str
+ len
, opcode
)
4366 && programmer_friendly_fixup (&inst
);
4367 gas_assert (result
);
4368 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4370 gas_assert (!result
);
4372 /* Find the most matched qualifier sequence. */
4373 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4374 gas_assert (qlf_idx
> -1);
4376 /* Assign the qualifiers. */
4377 assign_qualifier_sequence (inst_base
,
4378 opcode
->qualifiers_list
[qlf_idx
]);
4380 /* Print the hint. */
4381 output_info (_(" did you mean this?"));
4382 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4383 print_operands (buf
, opcode
, inst_base
->operands
);
4384 output_info (_(" %s"), buf
);
4386 /* Print out other variant(s) if there is any. */
4388 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4389 output_info (_(" other valid variant(s):"));
4391 /* For each pattern. */
4392 qualifiers_list
= opcode
->qualifiers_list
;
4393 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4395 /* Most opcodes has much fewer patterns in the list.
4396 First NIL qualifier indicates the end in the list. */
4397 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4402 /* Mnemonics name. */
4403 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4405 /* Assign the qualifiers. */
4406 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4408 /* Print instruction. */
4409 print_operands (buf
, opcode
, inst_base
->operands
);
4411 output_info (_(" %s"), buf
);
4417 case AARCH64_OPDE_OUT_OF_RANGE
:
4418 if (detail
->data
[0] != detail
->data
[1])
4419 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4420 detail
->error
? detail
->error
: _("immediate value"),
4421 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4423 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4424 detail
->error
? detail
->error
: _("immediate value"),
4425 detail
->data
[0], idx
+ 1, str
);
4428 case AARCH64_OPDE_REG_LIST
:
4429 if (detail
->data
[0] == 1)
4430 as_bad (_("invalid number of registers in the list; "
4431 "only 1 register is expected at operand %d -- `%s'"),
4434 as_bad (_("invalid number of registers in the list; "
4435 "%d registers are expected at operand %d -- `%s'"),
4436 detail
->data
[0], idx
+ 1, str
);
4439 case AARCH64_OPDE_UNALIGNED
:
4440 as_bad (_("immediate value should be a multiple of "
4441 "%d at operand %d -- `%s'"),
4442 detail
->data
[0], idx
+ 1, str
);
4451 /* Process and output the error message about the operand mismatching.
4453 When this function is called, the operand error information had
4454 been collected for an assembly line and there will be multiple
4455 errors in the case of mulitple instruction templates; output the
4456 error message that most closely describes the problem. */
4459 output_operand_error_report (char *str
)
4461 int largest_error_pos
;
4462 const char *msg
= NULL
;
4463 enum aarch64_operand_error_kind kind
;
4464 operand_error_record
*curr
;
4465 operand_error_record
*head
= operand_error_report
.head
;
4466 operand_error_record
*record
= NULL
;
4468 /* No error to report. */
4472 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4474 /* Only one error. */
4475 if (head
== operand_error_report
.tail
)
4477 DEBUG_TRACE ("single opcode entry with error kind: %s",
4478 operand_mismatch_kind_names
[head
->detail
.kind
]);
4479 output_operand_error_record (head
, str
);
4483 /* Find the error kind of the highest severity. */
4484 DEBUG_TRACE ("multiple opcode entres with error kind");
4485 kind
= AARCH64_OPDE_NIL
;
4486 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4488 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4489 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4490 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4491 kind
= curr
->detail
.kind
;
4493 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4495 /* Pick up one of errors of KIND to report. */
4496 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4497 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4499 if (curr
->detail
.kind
!= kind
)
4501 /* If there are multiple errors, pick up the one with the highest
4502 mismatching operand index. In the case of multiple errors with
4503 the equally highest operand index, pick up the first one or the
4504 first one with non-NULL error message. */
4505 if (curr
->detail
.index
> largest_error_pos
4506 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4507 && curr
->detail
.error
!= NULL
))
4509 largest_error_pos
= curr
->detail
.index
;
4511 msg
= record
->detail
.error
;
4515 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4516 DEBUG_TRACE ("Pick up error kind %s to report",
4517 operand_mismatch_kind_names
[record
->detail
.kind
]);
4520 output_operand_error_record (record
, str
);
4523 /* Write an AARCH64 instruction to buf - always little-endian. */
4525 put_aarch64_insn (char *buf
, uint32_t insn
)
4527 unsigned char *where
= (unsigned char *) buf
;
4529 where
[1] = insn
>> 8;
4530 where
[2] = insn
>> 16;
4531 where
[3] = insn
>> 24;
4535 get_aarch64_insn (char *buf
)
4537 unsigned char *where
= (unsigned char *) buf
;
4539 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4544 output_inst (struct aarch64_inst
*new_inst
)
4548 to
= frag_more (INSN_SIZE
);
4550 frag_now
->tc_frag_data
.recorded
= 1;
4552 put_aarch64_insn (to
, inst
.base
.value
);
4554 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4556 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4557 INSN_SIZE
, &inst
.reloc
.exp
,
4560 DEBUG_TRACE ("Prepared relocation fix up");
4561 /* Don't check the addend value against the instruction size,
4562 that's the job of our code in md_apply_fix(). */
4563 fixp
->fx_no_overflow
= 1;
4564 if (new_inst
!= NULL
)
4565 fixp
->tc_fix_data
.inst
= new_inst
;
4566 if (aarch64_gas_internal_fixup_p ())
4568 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4569 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4570 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4574 dwarf2_emit_insn (INSN_SIZE
);
4577 /* Link together opcodes of the same name. */
4581 aarch64_opcode
*opcode
;
4582 struct templates
*next
;
4585 typedef struct templates templates
;
4588 lookup_mnemonic (const char *start
, int len
)
4590 templates
*templ
= NULL
;
4592 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4596 /* Subroutine of md_assemble, responsible for looking up the primary
4597 opcode from the mnemonic the user wrote. STR points to the
4598 beginning of the mnemonic. */
4601 opcode_lookup (char **str
)
4604 const aarch64_cond
*cond
;
4608 /* Scan up to the end of the mnemonic, which must end in white space,
4609 '.', or end of string. */
4610 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4617 inst
.cond
= COND_ALWAYS
;
4619 /* Handle a possible condition. */
4622 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4625 inst
.cond
= cond
->value
;
4639 if (inst
.cond
== COND_ALWAYS
)
4641 /* Look for unaffixed mnemonic. */
4642 return lookup_mnemonic (base
, len
);
4646 /* append ".c" to mnemonic if conditional */
4647 memcpy (condname
, base
, len
);
4648 memcpy (condname
+ len
, ".c", 2);
4651 return lookup_mnemonic (base
, len
);
4657 /* Internal helper routine converting a vector neon_type_el structure
4658 *VECTYPE to a corresponding operand qualifier. */
4660 static inline aarch64_opnd_qualifier_t
4661 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4663 /* Element size in bytes indexed by neon_el_type. */
4664 const unsigned char ele_size
[5]
4666 const unsigned int ele_base
[5] =
4668 AARCH64_OPND_QLF_V_8B
,
4669 AARCH64_OPND_QLF_V_2H
,
4670 AARCH64_OPND_QLF_V_2S
,
4671 AARCH64_OPND_QLF_V_1D
,
4672 AARCH64_OPND_QLF_V_1Q
4675 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4676 goto vectype_conversion_fail
;
4678 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4680 if (vectype
->defined
& NTA_HASINDEX
)
4681 /* Vector element register. */
4682 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4685 /* Vector register. */
4686 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4689 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4690 goto vectype_conversion_fail
;
4692 /* The conversion is by calculating the offset from the base operand
4693 qualifier for the vector type. The operand qualifiers are regular
4694 enough that the offset can established by shifting the vector width by
4695 a vector-type dependent amount. */
4697 if (vectype
->type
== NT_b
)
4699 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4701 else if (vectype
->type
>= NT_d
)
4706 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4707 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4708 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4712 vectype_conversion_fail
:
4713 first_error (_("bad vector arrangement type"));
4714 return AARCH64_OPND_QLF_NIL
;
4717 /* Process an optional operand that is found omitted from the assembly line.
4718 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4719 instruction's opcode entry while IDX is the index of this omitted operand.
4723 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4724 int idx
, aarch64_opnd_info
*operand
)
4726 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4727 gas_assert (optional_operand_p (opcode
, idx
));
4728 gas_assert (!operand
->present
);
4732 case AARCH64_OPND_Rd
:
4733 case AARCH64_OPND_Rn
:
4734 case AARCH64_OPND_Rm
:
4735 case AARCH64_OPND_Rt
:
4736 case AARCH64_OPND_Rt2
:
4737 case AARCH64_OPND_Rs
:
4738 case AARCH64_OPND_Ra
:
4739 case AARCH64_OPND_Rt_SYS
:
4740 case AARCH64_OPND_Rd_SP
:
4741 case AARCH64_OPND_Rn_SP
:
4742 case AARCH64_OPND_Fd
:
4743 case AARCH64_OPND_Fn
:
4744 case AARCH64_OPND_Fm
:
4745 case AARCH64_OPND_Fa
:
4746 case AARCH64_OPND_Ft
:
4747 case AARCH64_OPND_Ft2
:
4748 case AARCH64_OPND_Sd
:
4749 case AARCH64_OPND_Sn
:
4750 case AARCH64_OPND_Sm
:
4751 case AARCH64_OPND_Vd
:
4752 case AARCH64_OPND_Vn
:
4753 case AARCH64_OPND_Vm
:
4754 case AARCH64_OPND_VdD1
:
4755 case AARCH64_OPND_VnD1
:
4756 operand
->reg
.regno
= default_value
;
4759 case AARCH64_OPND_Ed
:
4760 case AARCH64_OPND_En
:
4761 case AARCH64_OPND_Em
:
4762 operand
->reglane
.regno
= default_value
;
4765 case AARCH64_OPND_IDX
:
4766 case AARCH64_OPND_BIT_NUM
:
4767 case AARCH64_OPND_IMMR
:
4768 case AARCH64_OPND_IMMS
:
4769 case AARCH64_OPND_SHLL_IMM
:
4770 case AARCH64_OPND_IMM_VLSL
:
4771 case AARCH64_OPND_IMM_VLSR
:
4772 case AARCH64_OPND_CCMP_IMM
:
4773 case AARCH64_OPND_FBITS
:
4774 case AARCH64_OPND_UIMM4
:
4775 case AARCH64_OPND_UIMM3_OP1
:
4776 case AARCH64_OPND_UIMM3_OP2
:
4777 case AARCH64_OPND_IMM
:
4778 case AARCH64_OPND_WIDTH
:
4779 case AARCH64_OPND_UIMM7
:
4780 case AARCH64_OPND_NZCV
:
4781 operand
->imm
.value
= default_value
;
4784 case AARCH64_OPND_EXCEPTION
:
4785 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4788 case AARCH64_OPND_BARRIER_ISB
:
4789 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4796 /* Process the relocation type for move wide instructions.
4797 Return TRUE on success; otherwise return FALSE. */
4800 process_movw_reloc_info (void)
4805 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4807 if (inst
.base
.opcode
->op
== OP_MOVK
)
4808 switch (inst
.reloc
.type
)
4810 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4811 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4812 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4813 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4814 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4815 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4816 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4818 (_("the specified relocation type is not allowed for MOVK"));
4824 switch (inst
.reloc
.type
)
4826 case BFD_RELOC_AARCH64_MOVW_G0
:
4827 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4828 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4829 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4830 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4831 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4832 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4833 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4834 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4835 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4836 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4839 case BFD_RELOC_AARCH64_MOVW_G1
:
4840 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4841 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4842 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4843 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4844 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4845 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4846 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4847 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4848 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4849 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4852 case BFD_RELOC_AARCH64_MOVW_G2
:
4853 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4854 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4855 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4856 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4859 set_fatal_syntax_error
4860 (_("the specified relocation type is not allowed for 32-bit "
4866 case BFD_RELOC_AARCH64_MOVW_G3
:
4869 set_fatal_syntax_error
4870 (_("the specified relocation type is not allowed for 32-bit "
4877 /* More cases should be added when more MOVW-related relocation types
4878 are supported in GAS. */
4879 gas_assert (aarch64_gas_internal_fixup_p ());
4880 /* The shift amount should have already been set by the parser. */
4883 inst
.base
.operands
[1].shifter
.amount
= shift
;
4887 /* A primitive log caculator. */
4889 static inline unsigned int
4890 get_logsz (unsigned int size
)
4892 const unsigned char ls
[16] =
4893 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4899 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4900 return ls
[size
- 1];
4903 /* Determine and return the real reloc type code for an instruction
4904 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4906 static inline bfd_reloc_code_real_type
4907 ldst_lo12_determine_real_reloc_type (void)
4910 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4911 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4913 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4915 BFD_RELOC_AARCH64_LDST8_LO12
,
4916 BFD_RELOC_AARCH64_LDST16_LO12
,
4917 BFD_RELOC_AARCH64_LDST32_LO12
,
4918 BFD_RELOC_AARCH64_LDST64_LO12
,
4919 BFD_RELOC_AARCH64_LDST128_LO12
4922 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4923 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4924 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4925 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4926 BFD_RELOC_AARCH64_NONE
4929 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4930 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4931 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4932 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4933 BFD_RELOC_AARCH64_NONE
4937 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4938 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4940 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4941 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4943 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4945 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4947 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4949 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4950 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4951 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4952 gas_assert (logsz
<= 3);
4954 gas_assert (logsz
<= 4);
4956 /* In reloc.c, these pseudo relocation types should be defined in similar
4957 order as above reloc_ldst_lo12 array. Because the array index calcuation
4958 below relies on this. */
4959 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4962 /* Check whether a register list REGINFO is valid. The registers must be
4963 numbered in increasing order (modulo 32), in increments of one or two.
4965 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4968 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4971 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4973 uint32_t i
, nb_regs
, prev_regno
, incr
;
4975 nb_regs
= 1 + (reginfo
& 0x3);
4977 prev_regno
= reginfo
& 0x1f;
4978 incr
= accept_alternate
? 2 : 1;
4980 for (i
= 1; i
< nb_regs
; ++i
)
4982 uint32_t curr_regno
;
4984 curr_regno
= reginfo
& 0x1f;
4985 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4987 prev_regno
= curr_regno
;
4993 /* Generic instruction operand parser. This does no encoding and no
4994 semantic validation; it merely squirrels values away in the inst
4995 structure. Returns TRUE or FALSE depending on whether the
4996 specified grammar matched. */
4999 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5002 char *backtrack_pos
= 0;
5003 const enum aarch64_opnd
*operands
= opcode
->operands
;
5006 skip_whitespace (str
);
5008 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5011 int isreg32
, isregzero
;
5012 int comma_skipped_p
= 0;
5013 aarch64_reg_type rtype
;
5014 struct neon_type_el vectype
;
5015 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5017 DEBUG_TRACE ("parse operand %d", i
);
5019 /* Assign the operand code. */
5020 info
->type
= operands
[i
];
5022 if (optional_operand_p (opcode
, i
))
5024 /* Remember where we are in case we need to backtrack. */
5025 gas_assert (!backtrack_pos
);
5026 backtrack_pos
= str
;
5029 /* Expect comma between operands; the backtrack mechanizm will take
5030 care of cases of omitted optional operand. */
5031 if (i
> 0 && ! skip_past_char (&str
, ','))
5033 set_syntax_error (_("comma expected between operands"));
5037 comma_skipped_p
= 1;
5039 switch (operands
[i
])
5041 case AARCH64_OPND_Rd
:
5042 case AARCH64_OPND_Rn
:
5043 case AARCH64_OPND_Rm
:
5044 case AARCH64_OPND_Rt
:
5045 case AARCH64_OPND_Rt2
:
5046 case AARCH64_OPND_Rs
:
5047 case AARCH64_OPND_Ra
:
5048 case AARCH64_OPND_Rt_SYS
:
5049 case AARCH64_OPND_PAIRREG
:
5050 po_int_reg_or_fail (1, 0);
5053 case AARCH64_OPND_Rd_SP
:
5054 case AARCH64_OPND_Rn_SP
:
5055 po_int_reg_or_fail (0, 1);
5058 case AARCH64_OPND_Rm_EXT
:
5059 case AARCH64_OPND_Rm_SFT
:
5060 po_misc_or_fail (parse_shifter_operand
5061 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5063 : SHIFTED_LOGIC_IMM
)));
5064 if (!info
->shifter
.operator_present
)
5066 /* Default to LSL if not present. Libopcodes prefers shifter
5067 kind to be explicit. */
5068 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5069 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5070 /* For Rm_EXT, libopcodes will carry out further check on whether
5071 or not stack pointer is used in the instruction (Recall that
5072 "the extend operator is not optional unless at least one of
5073 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5077 case AARCH64_OPND_Fd
:
5078 case AARCH64_OPND_Fn
:
5079 case AARCH64_OPND_Fm
:
5080 case AARCH64_OPND_Fa
:
5081 case AARCH64_OPND_Ft
:
5082 case AARCH64_OPND_Ft2
:
5083 case AARCH64_OPND_Sd
:
5084 case AARCH64_OPND_Sn
:
5085 case AARCH64_OPND_Sm
:
5086 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5087 if (val
== PARSE_FAIL
)
5089 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5092 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5094 info
->reg
.regno
= val
;
5095 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5098 case AARCH64_OPND_Vd
:
5099 case AARCH64_OPND_Vn
:
5100 case AARCH64_OPND_Vm
:
5101 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5102 if (val
== PARSE_FAIL
)
5104 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5107 if (vectype
.defined
& NTA_HASINDEX
)
5110 info
->reg
.regno
= val
;
5111 info
->qualifier
= vectype_to_qualifier (&vectype
);
5112 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5116 case AARCH64_OPND_VdD1
:
5117 case AARCH64_OPND_VnD1
:
5118 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5119 if (val
== PARSE_FAIL
)
5121 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5124 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5126 set_fatal_syntax_error
5127 (_("the top half of a 128-bit FP/SIMD register is expected"));
5130 info
->reg
.regno
= val
;
5131 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5132 here; it is correct for the purpose of encoding/decoding since
5133 only the register number is explicitly encoded in the related
5134 instructions, although this appears a bit hacky. */
5135 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5138 case AARCH64_OPND_Ed
:
5139 case AARCH64_OPND_En
:
5140 case AARCH64_OPND_Em
:
5141 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5142 if (val
== PARSE_FAIL
)
5144 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5147 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5150 info
->reglane
.regno
= val
;
5151 info
->reglane
.index
= vectype
.index
;
5152 info
->qualifier
= vectype_to_qualifier (&vectype
);
5153 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5157 case AARCH64_OPND_LVn
:
5158 case AARCH64_OPND_LVt
:
5159 case AARCH64_OPND_LVt_AL
:
5160 case AARCH64_OPND_LEt
:
5161 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5163 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5165 set_fatal_syntax_error (_("invalid register list"));
5168 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5169 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5170 if (operands
[i
] == AARCH64_OPND_LEt
)
5172 if (!(vectype
.defined
& NTA_HASINDEX
))
5174 info
->reglist
.has_index
= 1;
5175 info
->reglist
.index
= vectype
.index
;
5177 else if (!(vectype
.defined
& NTA_HASTYPE
))
5179 info
->qualifier
= vectype_to_qualifier (&vectype
);
5180 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5184 case AARCH64_OPND_Cn
:
5185 case AARCH64_OPND_Cm
:
5186 po_reg_or_fail (REG_TYPE_CN
);
5189 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5192 inst
.base
.operands
[i
].reg
.regno
= val
;
5195 case AARCH64_OPND_SHLL_IMM
:
5196 case AARCH64_OPND_IMM_VLSR
:
5197 po_imm_or_fail (1, 64);
5198 info
->imm
.value
= val
;
5201 case AARCH64_OPND_CCMP_IMM
:
5202 case AARCH64_OPND_FBITS
:
5203 case AARCH64_OPND_UIMM4
:
5204 case AARCH64_OPND_UIMM3_OP1
:
5205 case AARCH64_OPND_UIMM3_OP2
:
5206 case AARCH64_OPND_IMM_VLSL
:
5207 case AARCH64_OPND_IMM
:
5208 case AARCH64_OPND_WIDTH
:
5209 po_imm_nc_or_fail ();
5210 info
->imm
.value
= val
;
5213 case AARCH64_OPND_UIMM7
:
5214 po_imm_or_fail (0, 127);
5215 info
->imm
.value
= val
;
5218 case AARCH64_OPND_IDX
:
5219 case AARCH64_OPND_BIT_NUM
:
5220 case AARCH64_OPND_IMMR
:
5221 case AARCH64_OPND_IMMS
:
5222 po_imm_or_fail (0, 63);
5223 info
->imm
.value
= val
;
5226 case AARCH64_OPND_IMM0
:
5227 po_imm_nc_or_fail ();
5230 set_fatal_syntax_error (_("immediate zero expected"));
5233 info
->imm
.value
= 0;
5236 case AARCH64_OPND_FPIMM0
:
5239 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5240 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5241 it is probably not worth the effort to support it. */
5242 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5243 && !(res2
= parse_constant_immediate (&str
, &val
)))
5245 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5247 info
->imm
.value
= 0;
5248 info
->imm
.is_fp
= 1;
5251 set_fatal_syntax_error (_("immediate zero expected"));
5255 case AARCH64_OPND_IMM_MOV
:
5258 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5259 reg_name_p (str
, REG_TYPE_VN
))
5262 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5264 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5265 later. fix_mov_imm_insn will try to determine a machine
5266 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5267 message if the immediate cannot be moved by a single
5269 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5270 inst
.base
.operands
[i
].skip
= 1;
5274 case AARCH64_OPND_SIMD_IMM
:
5275 case AARCH64_OPND_SIMD_IMM_SFT
:
5276 if (! parse_big_immediate (&str
, &val
))
5278 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5280 /* need_libopcodes_p */ 1,
5283 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5284 shift, we don't check it here; we leave the checking to
5285 the libopcodes (operand_general_constraint_met_p). By
5286 doing this, we achieve better diagnostics. */
5287 if (skip_past_comma (&str
)
5288 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5290 if (!info
->shifter
.operator_present
5291 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5293 /* Default to LSL if not present. Libopcodes prefers shifter
5294 kind to be explicit. */
5295 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5296 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5300 case AARCH64_OPND_FPIMM
:
5301 case AARCH64_OPND_SIMD_FPIMM
:
5305 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5307 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5311 set_fatal_syntax_error (_("invalid floating-point constant"));
5314 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5315 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5319 case AARCH64_OPND_LIMM
:
5320 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5321 SHIFTED_LOGIC_IMM
));
5322 if (info
->shifter
.operator_present
)
5324 set_fatal_syntax_error
5325 (_("shift not allowed for bitmask immediate"));
5328 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5330 /* need_libopcodes_p */ 1,
5334 case AARCH64_OPND_AIMM
:
5335 if (opcode
->op
== OP_ADD
)
5336 /* ADD may have relocation types. */
5337 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5338 SHIFTED_ARITH_IMM
));
5340 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5341 SHIFTED_ARITH_IMM
));
5342 switch (inst
.reloc
.type
)
5344 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5345 info
->shifter
.amount
= 12;
5347 case BFD_RELOC_UNUSED
:
5348 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5349 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5350 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5351 inst
.reloc
.pc_rel
= 0;
5356 info
->imm
.value
= 0;
5357 if (!info
->shifter
.operator_present
)
5359 /* Default to LSL if not present. Libopcodes prefers shifter
5360 kind to be explicit. */
5361 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5362 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5366 case AARCH64_OPND_HALF
:
5368 /* #<imm16> or relocation. */
5369 int internal_fixup_p
;
5370 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5371 if (internal_fixup_p
)
5372 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5373 skip_whitespace (str
);
5374 if (skip_past_comma (&str
))
5376 /* {, LSL #<shift>} */
5377 if (! aarch64_gas_internal_fixup_p ())
5379 set_fatal_syntax_error (_("can't mix relocation modifier "
5380 "with explicit shift"));
5383 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5386 inst
.base
.operands
[i
].shifter
.amount
= 0;
5387 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5388 inst
.base
.operands
[i
].imm
.value
= 0;
5389 if (! process_movw_reloc_info ())
5394 case AARCH64_OPND_EXCEPTION
:
5395 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5396 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5398 /* need_libopcodes_p */ 0,
5402 case AARCH64_OPND_NZCV
:
5404 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5408 info
->imm
.value
= nzcv
->value
;
5411 po_imm_or_fail (0, 15);
5412 info
->imm
.value
= val
;
5416 case AARCH64_OPND_COND
:
5417 case AARCH64_OPND_COND1
:
5418 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5420 if (info
->cond
== NULL
)
5422 set_syntax_error (_("invalid condition"));
5425 else if (operands
[i
] == AARCH64_OPND_COND1
5426 && (info
->cond
->value
& 0xe) == 0xe)
5428 /* Not allow AL or NV. */
5429 set_default_error ();
5434 case AARCH64_OPND_ADDR_ADRP
:
5435 po_misc_or_fail (parse_adrp (&str
));
5436 /* Clear the value as operand needs to be relocated. */
5437 info
->imm
.value
= 0;
5440 case AARCH64_OPND_ADDR_PCREL14
:
5441 case AARCH64_OPND_ADDR_PCREL19
:
5442 case AARCH64_OPND_ADDR_PCREL21
:
5443 case AARCH64_OPND_ADDR_PCREL26
:
5444 po_misc_or_fail (parse_address_reloc (&str
, info
));
5445 if (!info
->addr
.pcrel
)
5447 set_syntax_error (_("invalid pc-relative address"));
5450 if (inst
.gen_lit_pool
5451 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5453 /* Only permit "=value" in the literal load instructions.
5454 The literal will be generated by programmer_friendly_fixup. */
5455 set_syntax_error (_("invalid use of \"=immediate\""));
5458 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5460 set_syntax_error (_("unrecognized relocation suffix"));
5463 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5465 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5466 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5470 info
->imm
.value
= 0;
5471 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5472 switch (opcode
->iclass
)
5476 /* e.g. CBZ or B.COND */
5477 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5478 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5482 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5483 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5487 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5489 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5490 : BFD_RELOC_AARCH64_JUMP26
;
5493 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5494 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5497 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5498 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5504 inst
.reloc
.pc_rel
= 1;
5508 case AARCH64_OPND_ADDR_SIMPLE
:
5509 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5510 /* [<Xn|SP>{, #<simm>}] */
5511 po_char_or_fail ('[');
5512 po_reg_or_fail (REG_TYPE_R64_SP
);
5513 /* Accept optional ", #0". */
5514 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5515 && skip_past_char (&str
, ','))
5517 skip_past_char (&str
, '#');
5518 if (! skip_past_char (&str
, '0'))
5520 set_fatal_syntax_error
5521 (_("the optional immediate offset can only be 0"));
5525 po_char_or_fail (']');
5526 info
->addr
.base_regno
= val
;
5529 case AARCH64_OPND_ADDR_REGOFF
:
5530 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5531 po_misc_or_fail (parse_address (&str
, info
, 0));
5532 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5533 || !info
->addr
.preind
|| info
->addr
.postind
5534 || info
->addr
.writeback
)
5536 set_syntax_error (_("invalid addressing mode"));
5539 if (!info
->shifter
.operator_present
)
5541 /* Default to LSL if not present. Libopcodes prefers shifter
5542 kind to be explicit. */
5543 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5544 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5546 /* Qualifier to be deduced by libopcodes. */
5549 case AARCH64_OPND_ADDR_SIMM7
:
5550 po_misc_or_fail (parse_address (&str
, info
, 0));
5551 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5552 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5554 set_syntax_error (_("invalid addressing mode"));
5557 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5559 /* need_libopcodes_p */ 1,
5563 case AARCH64_OPND_ADDR_SIMM9
:
5564 case AARCH64_OPND_ADDR_SIMM9_2
:
5565 po_misc_or_fail (parse_address_reloc (&str
, info
));
5566 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5567 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5568 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5569 && info
->addr
.writeback
))
5571 set_syntax_error (_("invalid addressing mode"));
5574 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5576 set_syntax_error (_("relocation not allowed"));
5579 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5581 /* need_libopcodes_p */ 1,
5585 case AARCH64_OPND_ADDR_UIMM12
:
5586 po_misc_or_fail (parse_address_reloc (&str
, info
));
5587 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5588 || !info
->addr
.preind
|| info
->addr
.writeback
)
5590 set_syntax_error (_("invalid addressing mode"));
5593 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5594 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5595 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5597 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5599 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5600 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5601 /* Leave qualifier to be determined by libopcodes. */
5604 case AARCH64_OPND_SIMD_ADDR_POST
:
5605 /* [<Xn|SP>], <Xm|#<amount>> */
5606 po_misc_or_fail (parse_address (&str
, info
, 1));
5607 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5609 set_syntax_error (_("invalid addressing mode"));
5612 if (!info
->addr
.offset
.is_reg
)
5614 if (inst
.reloc
.exp
.X_op
== O_constant
)
5615 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5618 set_fatal_syntax_error
5619 (_("writeback value should be an immediate constant"));
5626 case AARCH64_OPND_SYSREG
:
5627 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5630 set_syntax_error (_("unknown or missing system register name"));
5633 inst
.base
.operands
[i
].sysreg
= val
;
5636 case AARCH64_OPND_PSTATEFIELD
:
5637 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5640 set_syntax_error (_("unknown or missing PSTATE field name"));
5643 inst
.base
.operands
[i
].pstatefield
= val
;
5646 case AARCH64_OPND_SYSREG_IC
:
5647 inst
.base
.operands
[i
].sysins_op
=
5648 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5650 case AARCH64_OPND_SYSREG_DC
:
5651 inst
.base
.operands
[i
].sysins_op
=
5652 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5654 case AARCH64_OPND_SYSREG_AT
:
5655 inst
.base
.operands
[i
].sysins_op
=
5656 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5658 case AARCH64_OPND_SYSREG_TLBI
:
5659 inst
.base
.operands
[i
].sysins_op
=
5660 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5662 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5664 set_fatal_syntax_error ( _("unknown or missing operation name"));
5669 case AARCH64_OPND_BARRIER
:
5670 case AARCH64_OPND_BARRIER_ISB
:
5671 val
= parse_barrier (&str
);
5672 if (val
!= PARSE_FAIL
5673 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5675 /* ISB only accepts options name 'sy'. */
5677 (_("the specified option is not accepted in ISB"));
5678 /* Turn off backtrack as this optional operand is present. */
5682 /* This is an extension to accept a 0..15 immediate. */
5683 if (val
== PARSE_FAIL
)
5684 po_imm_or_fail (0, 15);
5685 info
->barrier
= aarch64_barrier_options
+ val
;
5688 case AARCH64_OPND_PRFOP
:
5689 val
= parse_pldop (&str
);
5690 /* This is an extension to accept a 0..31 immediate. */
5691 if (val
== PARSE_FAIL
)
5692 po_imm_or_fail (0, 31);
5693 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5696 case AARCH64_OPND_BARRIER_PSB
:
5697 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5698 if (val
== PARSE_FAIL
)
5703 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5706 /* If we get here, this operand was successfully parsed. */
5707 inst
.base
.operands
[i
].present
= 1;
5711 /* The parse routine should already have set the error, but in case
5712 not, set a default one here. */
5714 set_default_error ();
5716 if (! backtrack_pos
)
5717 goto parse_operands_return
;
5720 /* We reach here because this operand is marked as optional, and
5721 either no operand was supplied or the operand was supplied but it
5722 was syntactically incorrect. In the latter case we report an
5723 error. In the former case we perform a few more checks before
5724 dropping through to the code to insert the default operand. */
5726 char *tmp
= backtrack_pos
;
5727 char endchar
= END_OF_INSN
;
5729 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5731 skip_past_char (&tmp
, ',');
5733 if (*tmp
!= endchar
)
5734 /* The user has supplied an operand in the wrong format. */
5735 goto parse_operands_return
;
5737 /* Make sure there is not a comma before the optional operand.
5738 For example the fifth operand of 'sys' is optional:
5740 sys #0,c0,c0,#0, <--- wrong
5741 sys #0,c0,c0,#0 <--- correct. */
5742 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5744 set_fatal_syntax_error
5745 (_("unexpected comma before the omitted optional operand"));
5746 goto parse_operands_return
;
5750 /* Reaching here means we are dealing with an optional operand that is
5751 omitted from the assembly line. */
5752 gas_assert (optional_operand_p (opcode
, i
));
5754 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5756 /* Try again, skipping the optional operand at backtrack_pos. */
5757 str
= backtrack_pos
;
5760 /* Clear any error record after the omitted optional operand has been
5761 successfully handled. */
5765 /* Check if we have parsed all the operands. */
5766 if (*str
!= '\0' && ! error_p ())
5768 /* Set I to the index of the last present operand; this is
5769 for the purpose of diagnostics. */
5770 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5772 set_fatal_syntax_error
5773 (_("unexpected characters following instruction"));
5776 parse_operands_return
:
5780 DEBUG_TRACE ("parsing FAIL: %s - %s",
5781 operand_mismatch_kind_names
[get_error_kind ()],
5782 get_error_message ());
5783 /* Record the operand error properly; this is useful when there
5784 are multiple instruction templates for a mnemonic name, so that
5785 later on, we can select the error that most closely describes
5787 record_operand_error (opcode
, i
, get_error_kind (),
5788 get_error_message ());
5793 DEBUG_TRACE ("parsing SUCCESS");
5798 /* It does some fix-up to provide some programmer friendly feature while
5799 keeping the libopcodes happy, i.e. libopcodes only accepts
5800 the preferred architectural syntax.
5801 Return FALSE if there is any failure; otherwise return TRUE. */
5804 programmer_friendly_fixup (aarch64_instruction
*instr
)
5806 aarch64_inst
*base
= &instr
->base
;
5807 const aarch64_opcode
*opcode
= base
->opcode
;
5808 enum aarch64_op op
= opcode
->op
;
5809 aarch64_opnd_info
*operands
= base
->operands
;
5811 DEBUG_TRACE ("enter");
5813 switch (opcode
->iclass
)
5816 /* TBNZ Xn|Wn, #uimm6, label
5817 Test and Branch Not Zero: conditionally jumps to label if bit number
5818 uimm6 in register Xn is not zero. The bit number implies the width of
5819 the register, which may be written and should be disassembled as Wn if
5820 uimm is less than 32. */
5821 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5823 if (operands
[1].imm
.value
>= 32)
5825 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5829 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5833 /* LDR Wt, label | =value
5834 As a convenience assemblers will typically permit the notation
5835 "=value" in conjunction with the pc-relative literal load instructions
5836 to automatically place an immediate value or symbolic address in a
5837 nearby literal pool and generate a hidden label which references it.
5838 ISREG has been set to 0 in the case of =value. */
5839 if (instr
->gen_lit_pool
5840 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5842 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5843 if (op
== OP_LDRSW_LIT
)
5845 if (instr
->reloc
.exp
.X_op
!= O_constant
5846 && instr
->reloc
.exp
.X_op
!= O_big
5847 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5849 record_operand_error (opcode
, 1,
5850 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5851 _("constant expression expected"));
5854 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5856 record_operand_error (opcode
, 1,
5857 AARCH64_OPDE_OTHER_ERROR
,
5858 _("literal pool insertion failed"));
5866 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5867 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5868 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5869 A programmer-friendly assembler should accept a destination Xd in
5870 place of Wd, however that is not the preferred form for disassembly.
5872 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5873 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5874 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5875 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5880 /* In the 64-bit form, the final register operand is written as Wm
5881 for all but the (possibly omitted) UXTX/LSL and SXTX
5883 As a programmer-friendly assembler, we accept e.g.
5884 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5885 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5886 int idx
= aarch64_operand_index (opcode
->operands
,
5887 AARCH64_OPND_Rm_EXT
);
5888 gas_assert (idx
== 1 || idx
== 2);
5889 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5890 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5891 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5892 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5893 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5894 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5902 DEBUG_TRACE ("exit with SUCCESS");
5906 /* Check for loads and stores that will cause unpredictable behavior. */
5909 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5911 aarch64_inst
*base
= &instr
->base
;
5912 const aarch64_opcode
*opcode
= base
->opcode
;
5913 const aarch64_opnd_info
*opnds
= base
->operands
;
5914 switch (opcode
->iclass
)
5920 /* Loading/storing the base register is unpredictable if writeback. */
5921 if ((aarch64_get_operand_class (opnds
[0].type
)
5922 == AARCH64_OPND_CLASS_INT_REG
)
5923 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5924 && opnds
[1].addr
.base_regno
!= REG_SP
5925 && opnds
[1].addr
.writeback
)
5926 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5929 case ldstnapair_offs
:
5930 case ldstpair_indexed
:
5931 /* Loading/storing the base register is unpredictable if writeback. */
5932 if ((aarch64_get_operand_class (opnds
[0].type
)
5933 == AARCH64_OPND_CLASS_INT_REG
)
5934 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5935 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5936 && opnds
[2].addr
.base_regno
!= REG_SP
5937 && opnds
[2].addr
.writeback
)
5938 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5939 /* Load operations must load different registers. */
5940 if ((opcode
->opcode
& (1 << 22))
5941 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5942 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5949 /* A wrapper function to interface with libopcodes on encoding and
5950 record the error message if there is any.
5952 Return TRUE on success; otherwise return FALSE. */
5955 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5958 aarch64_operand_error error_info
;
5959 error_info
.kind
= AARCH64_OPDE_NIL
;
5960 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5964 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5965 record_operand_error_info (opcode
, &error_info
);
5970 #ifdef DEBUG_AARCH64
5972 dump_opcode_operands (const aarch64_opcode
*opcode
)
5975 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5977 aarch64_verbose ("\t\t opnd%d: %s", i
,
5978 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5979 ? aarch64_get_operand_name (opcode
->operands
[i
])
5980 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5984 #endif /* DEBUG_AARCH64 */
5986 /* This is the guts of the machine-dependent assembler. STR points to a
5987 machine dependent instruction. This function is supposed to emit
5988 the frags/bytes it assembles to. */
5991 md_assemble (char *str
)
5994 templates
*template;
5995 aarch64_opcode
*opcode
;
5996 aarch64_inst
*inst_base
;
5997 unsigned saved_cond
;
5999 /* Align the previous label if needed. */
6000 if (last_label_seen
!= NULL
)
6002 symbol_set_frag (last_label_seen
, frag_now
);
6003 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6004 S_SET_SEGMENT (last_label_seen
, now_seg
);
6007 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6009 DEBUG_TRACE ("\n\n");
6010 DEBUG_TRACE ("==============================");
6011 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6013 template = opcode_lookup (&p
);
6016 /* It wasn't an instruction, but it might be a register alias of
6017 the form alias .req reg directive. */
6018 if (!create_register_alias (str
, p
))
6019 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6024 skip_whitespace (p
);
6027 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6028 get_mnemonic_name (str
), str
);
6032 init_operand_error_report ();
6034 /* Sections are assumed to start aligned. In executable section, there is no
6035 MAP_DATA symbol pending. So we only align the address during
6036 MAP_DATA --> MAP_INSN transition.
6037 For other sections, this is not guaranteed. */
6038 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6039 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6040 frag_align_code (2, 0);
6042 saved_cond
= inst
.cond
;
6043 reset_aarch64_instruction (&inst
);
6044 inst
.cond
= saved_cond
;
6046 /* Iterate through all opcode entries with the same mnemonic name. */
6049 opcode
= template->opcode
;
6051 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6052 #ifdef DEBUG_AARCH64
6054 dump_opcode_operands (opcode
);
6055 #endif /* DEBUG_AARCH64 */
6057 mapping_state (MAP_INSN
);
6059 inst_base
= &inst
.base
;
6060 inst_base
->opcode
= opcode
;
6062 /* Truly conditionally executed instructions, e.g. b.cond. */
6063 if (opcode
->flags
& F_COND
)
6065 gas_assert (inst
.cond
!= COND_ALWAYS
);
6066 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6067 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6069 else if (inst
.cond
!= COND_ALWAYS
)
6071 /* It shouldn't arrive here, where the assembly looks like a
6072 conditional instruction but the found opcode is unconditional. */
6077 if (parse_operands (p
, opcode
)
6078 && programmer_friendly_fixup (&inst
)
6079 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6081 /* Check that this instruction is supported for this CPU. */
6082 if (!opcode
->avariant
6083 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
6085 as_bad (_("selected processor does not support `%s'"), str
);
6089 warn_unpredictable_ldst (&inst
, str
);
6091 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6092 || !inst
.reloc
.need_libopcodes_p
)
6096 /* If there is relocation generated for the instruction,
6097 store the instruction information for the future fix-up. */
6098 struct aarch64_inst
*copy
;
6099 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6100 copy
= XNEW (struct aarch64_inst
);
6101 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6107 template = template->next
;
6108 if (template != NULL
)
6110 reset_aarch64_instruction (&inst
);
6111 inst
.cond
= saved_cond
;
6114 while (template != NULL
);
6116 /* Issue the error messages if any. */
6117 output_operand_error_report (str
);
6120 /* Various frobbings of labels and their addresses. */
6123 aarch64_start_line_hook (void)
6125 last_label_seen
= NULL
;
6129 aarch64_frob_label (symbolS
* sym
)
6131 last_label_seen
= sym
;
6133 dwarf2_emit_label (sym
);
6137 aarch64_data_in_code (void)
6139 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6141 *input_line_pointer
= '/';
6142 input_line_pointer
+= 5;
6143 *input_line_pointer
= 0;
6151 aarch64_canonicalize_symbol_name (char *name
)
6155 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6156 *(name
+ len
- 5) = 0;
6161 /* Table of all register names defined by default. The user can
6162 define additional names with .req. Note that all register names
6163 should appear in both upper and lowercase variants. Some registers
6164 also have mixed-case names. */
6166 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6167 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6168 #define REGSET31(p,t) \
6169 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6170 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6171 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6172 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6173 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6174 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6175 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6176 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6177 #define REGSET(p,t) \
6178 REGSET31(p,t), REGNUM(p,31,t)
6180 /* These go into aarch64_reg_hsh hash-table. */
6181 static const reg_entry reg_names
[] = {
6182 /* Integer registers. */
6183 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6184 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6186 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6187 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6189 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6190 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6192 /* Coprocessor register numbers. */
6193 REGSET (c
, CN
), REGSET (C
, CN
),
6195 /* Floating-point single precision registers. */
6196 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6198 /* Floating-point double precision registers. */
6199 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6201 /* Floating-point half precision registers. */
6202 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6204 /* Floating-point byte precision registers. */
6205 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6207 /* Floating-point quad precision registers. */
6208 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6210 /* FP/SIMD registers. */
6211 REGSET (v
, VN
), REGSET (V
, VN
),
6226 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6227 static const asm_nzcv nzcv_names
[] = {
6228 {"nzcv", B (n
, z
, c
, v
)},
6229 {"nzcV", B (n
, z
, c
, V
)},
6230 {"nzCv", B (n
, z
, C
, v
)},
6231 {"nzCV", B (n
, z
, C
, V
)},
6232 {"nZcv", B (n
, Z
, c
, v
)},
6233 {"nZcV", B (n
, Z
, c
, V
)},
6234 {"nZCv", B (n
, Z
, C
, v
)},
6235 {"nZCV", B (n
, Z
, C
, V
)},
6236 {"Nzcv", B (N
, z
, c
, v
)},
6237 {"NzcV", B (N
, z
, c
, V
)},
6238 {"NzCv", B (N
, z
, C
, v
)},
6239 {"NzCV", B (N
, z
, C
, V
)},
6240 {"NZcv", B (N
, Z
, c
, v
)},
6241 {"NZcV", B (N
, Z
, c
, V
)},
6242 {"NZCv", B (N
, Z
, C
, v
)},
6243 {"NZCV", B (N
, Z
, C
, V
)}
6256 /* MD interface: bits in the object file. */
6258 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6259 for use in the a.out file, and stores them in the array pointed to by buf.
6260 This knows about the endian-ness of the target machine and does
6261 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6262 2 (short) and 4 (long) Floating numbers are put out as a series of
6263 LITTLENUMS (shorts, here at least). */
6266 md_number_to_chars (char *buf
, valueT val
, int n
)
6268 if (target_big_endian
)
6269 number_to_chars_bigendian (buf
, val
, n
);
6271 number_to_chars_littleendian (buf
, val
, n
);
6274 /* MD interface: Sections. */
6276 /* Estimate the size of a frag before relaxing. Assume everything fits in
6280 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6286 /* Round up a section size to the appropriate boundary. */
6289 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6294 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6295 of an rs_align_code fragment.
6297 Here we fill the frag with the appropriate info for padding the
6298 output stream. The resulting frag will consist of a fixed (fr_fix)
6299 and of a repeating (fr_var) part.
6301 The fixed content is always emitted before the repeating content and
6302 these two parts are used as follows in constructing the output:
6303 - the fixed part will be used to align to a valid instruction word
6304 boundary, in case that we start at a misaligned address; as no
6305 executable instruction can live at the misaligned location, we
6306 simply fill with zeros;
6307 - the variable part will be used to cover the remaining padding and
6308 we fill using the AArch64 NOP instruction.
6310 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6311 enough storage space for up to 3 bytes for padding the back to a valid
6312 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6315 aarch64_handle_align (fragS
* fragP
)
6317 /* NOP = d503201f */
6318 /* AArch64 instructions are always little-endian. */
6319 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6321 int bytes
, fix
, noop_size
;
6324 if (fragP
->fr_type
!= rs_align_code
)
6327 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6328 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6331 gas_assert (fragP
->tc_frag_data
.recorded
);
6334 noop_size
= sizeof (aarch64_noop
);
6336 fix
= bytes
& (noop_size
- 1);
6340 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6344 fragP
->fr_fix
+= fix
;
6348 memcpy (p
, aarch64_noop
, noop_size
);
6349 fragP
->fr_var
= noop_size
;
6352 /* Perform target specific initialisation of a frag.
6353 Note - despite the name this initialisation is not done when the frag
6354 is created, but only when its type is assigned. A frag can be created
6355 and used a long time before its type is set, so beware of assuming that
6356 this initialisationis performed first. */
6360 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6361 int max_chars ATTRIBUTE_UNUSED
)
6365 #else /* OBJ_ELF is defined. */
6367 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6369 /* Record a mapping symbol for alignment frags. We will delete this
6370 later if the alignment ends up empty. */
6371 if (!fragP
->tc_frag_data
.recorded
)
6372 fragP
->tc_frag_data
.recorded
= 1;
6374 switch (fragP
->fr_type
)
6379 mapping_state_2 (MAP_DATA
, max_chars
);
6382 mapping_state_2 (MAP_INSN
, max_chars
);
6389 /* Initialize the DWARF-2 unwind information for this procedure. */
6392 tc_aarch64_frame_initial_instructions (void)
6394 cfi_add_CFA_def_cfa (REG_SP
, 0);
6396 #endif /* OBJ_ELF */
6398 /* Convert REGNAME to a DWARF-2 register number. */
6401 tc_aarch64_regname_to_dw2regnum (char *regname
)
6403 const reg_entry
*reg
= parse_reg (®name
);
6409 case REG_TYPE_SP_32
:
6410 case REG_TYPE_SP_64
:
6420 return reg
->number
+ 64;
6428 /* Implement DWARF2_ADDR_SIZE. */
6431 aarch64_dwarf2_addr_size (void)
6433 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6437 return bfd_arch_bits_per_address (stdoutput
) / 8;
6440 /* MD interface: Symbol and relocation handling. */
6442 /* Return the address within the segment that a PC-relative fixup is
6443 relative to. For AArch64 PC-relative fixups applied to instructions
6444 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6447 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6449 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6451 /* If this is pc-relative and we are going to emit a relocation
6452 then we just want to put out any pipeline compensation that the linker
6453 will need. Otherwise we want to use the calculated base. */
6455 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6456 || aarch64_force_relocation (fixP
)))
6459 /* AArch64 should be consistent for all pc-relative relocations. */
6460 return base
+ AARCH64_PCREL_OFFSET
;
6463 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6464 Otherwise we have no need to default values of symbols. */
6467 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6470 if (name
[0] == '_' && name
[1] == 'G'
6471 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6475 if (symbol_find (name
))
6476 as_bad (_("GOT already in the symbol table"));
6478 GOT_symbol
= symbol_new (name
, undefined_section
,
6479 (valueT
) 0, &zero_address_frag
);
6489 /* Return non-zero if the indicated VALUE has overflowed the maximum
6490 range expressible by a unsigned number with the indicated number of
6494 unsigned_overflow (valueT value
, unsigned bits
)
6497 if (bits
>= sizeof (valueT
) * 8)
6499 lim
= (valueT
) 1 << bits
;
6500 return (value
>= lim
);
6504 /* Return non-zero if the indicated VALUE has overflowed the maximum
6505 range expressible by an signed number with the indicated number of
6509 signed_overflow (offsetT value
, unsigned bits
)
6512 if (bits
>= sizeof (offsetT
) * 8)
6514 lim
= (offsetT
) 1 << (bits
- 1);
6515 return (value
< -lim
|| value
>= lim
);
6518 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6519 unsigned immediate offset load/store instruction, try to encode it as
6520 an unscaled, 9-bit, signed immediate offset load/store instruction.
6521 Return TRUE if it is successful; otherwise return FALSE.
6523 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6524 in response to the standard LDR/STR mnemonics when the immediate offset is
6525 unambiguous, i.e. when it is negative or unaligned. */
6528 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6531 enum aarch64_op new_op
;
6532 const aarch64_opcode
*new_opcode
;
6534 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6536 switch (instr
->opcode
->op
)
6538 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6539 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6540 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6541 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6542 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6543 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6544 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6545 case OP_STR_POS
: new_op
= OP_STUR
; break;
6546 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6547 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6548 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6549 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6550 default: new_op
= OP_NIL
; break;
6553 if (new_op
== OP_NIL
)
6556 new_opcode
= aarch64_get_opcode (new_op
);
6557 gas_assert (new_opcode
!= NULL
);
6559 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6560 instr
->opcode
->op
, new_opcode
->op
);
6562 aarch64_replace_opcode (instr
, new_opcode
);
6564 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6565 qualifier matching may fail because the out-of-date qualifier will
6566 prevent the operand being updated with a new and correct qualifier. */
6567 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6568 AARCH64_OPND_ADDR_SIMM9
);
6569 gas_assert (idx
== 1);
6570 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6572 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6574 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6580 /* Called by fix_insn to fix a MOV immediate alias instruction.
6582 Operand for a generic move immediate instruction, which is an alias
6583 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6584 a 32-bit/64-bit immediate value into general register. An assembler error
6585 shall result if the immediate cannot be created by a single one of these
6586 instructions. If there is a choice, then to ensure reversability an
6587 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6590 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6592 const aarch64_opcode
*opcode
;
6594 /* Need to check if the destination is SP/ZR. The check has to be done
6595 before any aarch64_replace_opcode. */
6596 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6597 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6599 instr
->operands
[1].imm
.value
= value
;
6600 instr
->operands
[1].skip
= 0;
6604 /* Try the MOVZ alias. */
6605 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6606 aarch64_replace_opcode (instr
, opcode
);
6607 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6608 &instr
->value
, NULL
, NULL
))
6610 put_aarch64_insn (buf
, instr
->value
);
6613 /* Try the MOVK alias. */
6614 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6615 aarch64_replace_opcode (instr
, opcode
);
6616 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6617 &instr
->value
, NULL
, NULL
))
6619 put_aarch64_insn (buf
, instr
->value
);
6624 if (try_mov_bitmask_p
)
6626 /* Try the ORR alias. */
6627 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6628 aarch64_replace_opcode (instr
, opcode
);
6629 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6630 &instr
->value
, NULL
, NULL
))
6632 put_aarch64_insn (buf
, instr
->value
);
6637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6638 _("immediate cannot be moved by a single instruction"));
6641 /* An instruction operand which is immediate related may have symbol used
6642 in the assembly, e.g.
6645 .set u32, 0x00ffff00
6647 At the time when the assembly instruction is parsed, a referenced symbol,
6648 like 'u32' in the above example may not have been seen; a fixS is created
6649 in such a case and is handled here after symbols have been resolved.
6650 Instruction is fixed up with VALUE using the information in *FIXP plus
6651 extra information in FLAGS.
6653 This function is called by md_apply_fix to fix up instructions that need
6654 a fix-up described above but does not involve any linker-time relocation. */
6657 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6661 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6662 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6663 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6667 /* Now the instruction is about to be fixed-up, so the operand that
6668 was previously marked as 'ignored' needs to be unmarked in order
6669 to get the encoding done properly. */
6670 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6671 new_inst
->operands
[idx
].skip
= 0;
6674 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6678 case AARCH64_OPND_EXCEPTION
:
6679 if (unsigned_overflow (value
, 16))
6680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6681 _("immediate out of range"));
6682 insn
= get_aarch64_insn (buf
);
6683 insn
|= encode_svc_imm (value
);
6684 put_aarch64_insn (buf
, insn
);
6687 case AARCH64_OPND_AIMM
:
6688 /* ADD or SUB with immediate.
6689 NOTE this assumes we come here with a add/sub shifted reg encoding
6690 3 322|2222|2 2 2 21111 111111
6691 1 098|7654|3 2 1 09876 543210 98765 43210
6692 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6693 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6694 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6695 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6697 3 322|2222|2 2 221111111111
6698 1 098|7654|3 2 109876543210 98765 43210
6699 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6700 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6701 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6702 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6703 Fields sf Rn Rd are already set. */
6704 insn
= get_aarch64_insn (buf
);
6708 insn
= reencode_addsub_switch_add_sub (insn
);
6712 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6713 && unsigned_overflow (value
, 12))
6715 /* Try to shift the value by 12 to make it fit. */
6716 if (((value
>> 12) << 12) == value
6717 && ! unsigned_overflow (value
, 12 + 12))
6720 insn
|= encode_addsub_imm_shift_amount (1);
6724 if (unsigned_overflow (value
, 12))
6725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6726 _("immediate out of range"));
6728 insn
|= encode_addsub_imm (value
);
6730 put_aarch64_insn (buf
, insn
);
6733 case AARCH64_OPND_SIMD_IMM
:
6734 case AARCH64_OPND_SIMD_IMM_SFT
:
6735 case AARCH64_OPND_LIMM
:
6736 /* Bit mask immediate. */
6737 gas_assert (new_inst
!= NULL
);
6738 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6739 new_inst
->operands
[idx
].imm
.value
= value
;
6740 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6741 &new_inst
->value
, NULL
, NULL
))
6742 put_aarch64_insn (buf
, new_inst
->value
);
6744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6745 _("invalid immediate"));
6748 case AARCH64_OPND_HALF
:
6749 /* 16-bit unsigned immediate. */
6750 if (unsigned_overflow (value
, 16))
6751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6752 _("immediate out of range"));
6753 insn
= get_aarch64_insn (buf
);
6754 insn
|= encode_movw_imm (value
& 0xffff);
6755 put_aarch64_insn (buf
, insn
);
6758 case AARCH64_OPND_IMM_MOV
:
6759 /* Operand for a generic move immediate instruction, which is
6760 an alias instruction that generates a single MOVZ, MOVN or ORR
6761 instruction to loads a 32-bit/64-bit immediate value into general
6762 register. An assembler error shall result if the immediate cannot be
6763 created by a single one of these instructions. If there is a choice,
6764 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6765 and MOVZ or MOVN to ORR. */
6766 gas_assert (new_inst
!= NULL
);
6767 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6770 case AARCH64_OPND_ADDR_SIMM7
:
6771 case AARCH64_OPND_ADDR_SIMM9
:
6772 case AARCH64_OPND_ADDR_SIMM9_2
:
6773 case AARCH64_OPND_ADDR_UIMM12
:
6774 /* Immediate offset in an address. */
6775 insn
= get_aarch64_insn (buf
);
6777 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6778 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6779 || new_inst
->opcode
->operands
[2] == opnd
);
6781 /* Get the index of the address operand. */
6782 if (new_inst
->opcode
->operands
[1] == opnd
)
6783 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6786 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6789 /* Update the resolved offset value. */
6790 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6792 /* Encode/fix-up. */
6793 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6794 &new_inst
->value
, NULL
, NULL
))
6796 put_aarch64_insn (buf
, new_inst
->value
);
6799 else if (new_inst
->opcode
->iclass
== ldst_pos
6800 && try_to_encode_as_unscaled_ldst (new_inst
))
6802 put_aarch64_insn (buf
, new_inst
->value
);
6806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6807 _("immediate offset out of range"));
6812 as_fatal (_("unhandled operand code %d"), opnd
);
6816 /* Apply a fixup (fixP) to segment data, once it has been determined
6817 by our caller that we have all the info we need to fix it up.
6819 Parameter valP is the pointer to the value of the bits. */
6822 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6824 offsetT value
= *valP
;
6826 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6828 unsigned flags
= fixP
->fx_addnumber
;
6830 DEBUG_TRACE ("\n\n");
6831 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6832 DEBUG_TRACE ("Enter md_apply_fix");
6834 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6836 /* Note whether this will delete the relocation. */
6838 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6841 /* Process the relocations. */
6842 switch (fixP
->fx_r_type
)
6844 case BFD_RELOC_NONE
:
6845 /* This will need to go in the object file. */
6850 case BFD_RELOC_8_PCREL
:
6851 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6852 md_number_to_chars (buf
, value
, 1);
6856 case BFD_RELOC_16_PCREL
:
6857 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6858 md_number_to_chars (buf
, value
, 2);
6862 case BFD_RELOC_32_PCREL
:
6863 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6864 md_number_to_chars (buf
, value
, 4);
6868 case BFD_RELOC_64_PCREL
:
6869 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6870 md_number_to_chars (buf
, value
, 8);
6873 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6874 /* We claim that these fixups have been processed here, even if
6875 in fact we generate an error because we do not have a reloc
6876 for them, so tc_gen_reloc() will reject them. */
6878 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6880 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6881 _("undefined symbol %s used as an immediate value"),
6882 S_GET_NAME (fixP
->fx_addsy
));
6883 goto apply_fix_return
;
6885 fix_insn (fixP
, flags
, value
);
6888 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6889 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6892 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6893 _("pc-relative load offset not word aligned"));
6894 if (signed_overflow (value
, 21))
6895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6896 _("pc-relative load offset out of range"));
6897 insn
= get_aarch64_insn (buf
);
6898 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6899 put_aarch64_insn (buf
, insn
);
6903 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6904 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6906 if (signed_overflow (value
, 21))
6907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6908 _("pc-relative address offset out of range"));
6909 insn
= get_aarch64_insn (buf
);
6910 insn
|= encode_adr_imm (value
);
6911 put_aarch64_insn (buf
, insn
);
6915 case BFD_RELOC_AARCH64_BRANCH19
:
6916 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6920 _("conditional branch target not word aligned"));
6921 if (signed_overflow (value
, 21))
6922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6923 _("conditional branch out of range"));
6924 insn
= get_aarch64_insn (buf
);
6925 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6926 put_aarch64_insn (buf
, insn
);
6930 case BFD_RELOC_AARCH64_TSTBR14
:
6931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6935 _("conditional branch target not word aligned"));
6936 if (signed_overflow (value
, 16))
6937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6938 _("conditional branch out of range"));
6939 insn
= get_aarch64_insn (buf
);
6940 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6941 put_aarch64_insn (buf
, insn
);
6945 case BFD_RELOC_AARCH64_CALL26
:
6946 case BFD_RELOC_AARCH64_JUMP26
:
6947 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6951 _("branch target not word aligned"));
6952 if (signed_overflow (value
, 28))
6953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6954 _("branch out of range"));
6955 insn
= get_aarch64_insn (buf
);
6956 insn
|= encode_branch_ofs_26 (value
>> 2);
6957 put_aarch64_insn (buf
, insn
);
6961 case BFD_RELOC_AARCH64_MOVW_G0
:
6962 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6963 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6964 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6967 case BFD_RELOC_AARCH64_MOVW_G1
:
6968 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6969 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6970 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6973 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6975 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6976 /* Should always be exported to object file, see
6977 aarch64_force_relocation(). */
6978 gas_assert (!fixP
->fx_done
);
6979 gas_assert (seg
->use_rela_p
);
6981 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6983 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6984 /* Should always be exported to object file, see
6985 aarch64_force_relocation(). */
6986 gas_assert (!fixP
->fx_done
);
6987 gas_assert (seg
->use_rela_p
);
6989 case BFD_RELOC_AARCH64_MOVW_G2
:
6990 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6991 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6994 case BFD_RELOC_AARCH64_MOVW_G3
:
6997 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6999 insn
= get_aarch64_insn (buf
);
7003 /* REL signed addend must fit in 16 bits */
7004 if (signed_overflow (value
, 16))
7005 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7006 _("offset out of range"));
7010 /* Check for overflow and scale. */
7011 switch (fixP
->fx_r_type
)
7013 case BFD_RELOC_AARCH64_MOVW_G0
:
7014 case BFD_RELOC_AARCH64_MOVW_G1
:
7015 case BFD_RELOC_AARCH64_MOVW_G2
:
7016 case BFD_RELOC_AARCH64_MOVW_G3
:
7017 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7018 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7019 if (unsigned_overflow (value
, scale
+ 16))
7020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7021 _("unsigned value out of range"));
7023 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7024 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7025 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7026 /* NOTE: We can only come here with movz or movn. */
7027 if (signed_overflow (value
, scale
+ 16))
7028 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7029 _("signed value out of range"));
7032 /* Force use of MOVN. */
7034 insn
= reencode_movzn_to_movn (insn
);
7038 /* Force use of MOVZ. */
7039 insn
= reencode_movzn_to_movz (insn
);
7043 /* Unchecked relocations. */
7049 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7050 insn
|= encode_movw_imm (value
& 0xffff);
7052 put_aarch64_insn (buf
, insn
);
7056 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7057 fixP
->fx_r_type
= (ilp32_p
7058 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7059 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7060 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7061 /* Should always be exported to object file, see
7062 aarch64_force_relocation(). */
7063 gas_assert (!fixP
->fx_done
);
7064 gas_assert (seg
->use_rela_p
);
7067 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7068 fixP
->fx_r_type
= (ilp32_p
7069 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7070 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7071 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7072 /* Should always be exported to object file, see
7073 aarch64_force_relocation(). */
7074 gas_assert (!fixP
->fx_done
);
7075 gas_assert (seg
->use_rela_p
);
7078 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7079 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7080 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7081 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7082 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7083 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7084 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7085 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7086 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7087 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7088 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7089 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7090 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7091 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7092 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7093 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7094 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7095 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7096 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7097 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7098 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7099 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7100 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7101 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7102 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7103 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7104 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7105 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7106 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7107 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7108 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7109 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7110 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7111 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7112 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7113 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7114 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7115 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7116 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7117 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7118 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7119 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7120 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7121 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7122 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7123 /* Should always be exported to object file, see
7124 aarch64_force_relocation(). */
7125 gas_assert (!fixP
->fx_done
);
7126 gas_assert (seg
->use_rela_p
);
7129 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7130 /* Should always be exported to object file, see
7131 aarch64_force_relocation(). */
7132 fixP
->fx_r_type
= (ilp32_p
7133 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7134 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7135 gas_assert (!fixP
->fx_done
);
7136 gas_assert (seg
->use_rela_p
);
7139 case BFD_RELOC_AARCH64_ADD_LO12
:
7140 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7141 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7142 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7143 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7144 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7145 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7146 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7147 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7148 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7149 case BFD_RELOC_AARCH64_LDST128_LO12
:
7150 case BFD_RELOC_AARCH64_LDST16_LO12
:
7151 case BFD_RELOC_AARCH64_LDST32_LO12
:
7152 case BFD_RELOC_AARCH64_LDST64_LO12
:
7153 case BFD_RELOC_AARCH64_LDST8_LO12
:
7154 /* Should always be exported to object file, see
7155 aarch64_force_relocation(). */
7156 gas_assert (!fixP
->fx_done
);
7157 gas_assert (seg
->use_rela_p
);
7160 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7161 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7162 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7165 case BFD_RELOC_UNUSED
:
7166 /* An error will already have been reported. */
7170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7171 _("unexpected %s fixup"),
7172 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7177 /* Free the allocated the struct aarch64_inst.
7178 N.B. currently there are very limited number of fix-up types actually use
7179 this field, so the impact on the performance should be minimal . */
7180 if (fixP
->tc_fix_data
.inst
!= NULL
)
7181 free (fixP
->tc_fix_data
.inst
);
7186 /* Translate internal representation of relocation info to BFD target
7190 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7193 bfd_reloc_code_real_type code
;
7195 reloc
= XNEW (arelent
);
7197 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7198 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7199 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7203 if (section
->use_rela_p
)
7204 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7206 fixp
->fx_offset
= reloc
->address
;
7208 reloc
->addend
= fixp
->fx_offset
;
7210 code
= fixp
->fx_r_type
;
7215 code
= BFD_RELOC_16_PCREL
;
7220 code
= BFD_RELOC_32_PCREL
;
7225 code
= BFD_RELOC_64_PCREL
;
7232 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7233 if (reloc
->howto
== NULL
)
7235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7237 ("cannot represent %s relocation in this object file format"),
7238 bfd_get_reloc_code_name (code
));
7245 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7248 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7250 bfd_reloc_code_real_type type
;
7254 FIXME: @@ Should look at CPU word size. */
7261 type
= BFD_RELOC_16
;
7264 type
= BFD_RELOC_32
;
7267 type
= BFD_RELOC_64
;
7270 as_bad (_("cannot do %u-byte relocation"), size
);
7271 type
= BFD_RELOC_UNUSED
;
7275 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7279 aarch64_force_relocation (struct fix
*fixp
)
7281 switch (fixp
->fx_r_type
)
7283 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7284 /* Perform these "immediate" internal relocations
7285 even if the symbol is extern or weak. */
7288 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7289 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7290 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7291 /* Pseudo relocs that need to be fixed up according to
7295 case BFD_RELOC_AARCH64_ADD_LO12
:
7296 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7297 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7298 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7299 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7300 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7301 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7302 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7303 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7304 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7305 case BFD_RELOC_AARCH64_LDST128_LO12
:
7306 case BFD_RELOC_AARCH64_LDST16_LO12
:
7307 case BFD_RELOC_AARCH64_LDST32_LO12
:
7308 case BFD_RELOC_AARCH64_LDST64_LO12
:
7309 case BFD_RELOC_AARCH64_LDST8_LO12
:
7310 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7311 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7312 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7313 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7314 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7315 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7316 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7317 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7318 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7319 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7320 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7321 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7322 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7323 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7324 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7325 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7326 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7327 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7328 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7329 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7330 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7331 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7332 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7333 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7334 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7335 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7336 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7337 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7338 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7339 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7340 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7341 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7342 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7343 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7344 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7345 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7346 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7347 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7348 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7349 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7350 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7351 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7352 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7353 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7354 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7355 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7356 /* Always leave these relocations for the linker. */
7363 return generic_force_reloc (fixp
);
7369 elf64_aarch64_target_format (void)
7371 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7373 /* FIXME: What to do for ilp32_p ? */
7374 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7376 if (target_big_endian
)
7377 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7379 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7383 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7385 elf_frob_symbol (symp
, puntp
);
7389 /* MD interface: Finalization. */
7391 /* A good place to do this, although this was probably not intended
7392 for this kind of use. We need to dump the literal pool before
7393 references are made to a null symbol pointer. */
7396 aarch64_cleanup (void)
7400 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7402 /* Put it at the end of the relevant section. */
7403 subseg_set (pool
->section
, pool
->sub_section
);
7409 /* Remove any excess mapping symbols generated for alignment frags in
7410 SEC. We may have created a mapping symbol before a zero byte
7411 alignment; remove it if there's a mapping symbol after the
7414 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7415 void *dummy ATTRIBUTE_UNUSED
)
7417 segment_info_type
*seginfo
= seg_info (sec
);
7420 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7423 for (fragp
= seginfo
->frchainP
->frch_root
;
7424 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7426 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7427 fragS
*next
= fragp
->fr_next
;
7429 /* Variable-sized frags have been converted to fixed size by
7430 this point. But if this was variable-sized to start with,
7431 there will be a fixed-size frag after it. So don't handle
7433 if (sym
== NULL
|| next
== NULL
)
7436 if (S_GET_VALUE (sym
) < next
->fr_address
)
7437 /* Not at the end of this frag. */
7439 know (S_GET_VALUE (sym
) == next
->fr_address
);
7443 if (next
->tc_frag_data
.first_map
!= NULL
)
7445 /* Next frag starts with a mapping symbol. Discard this
7447 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7451 if (next
->fr_next
== NULL
)
7453 /* This mapping symbol is at the end of the section. Discard
7455 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7456 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7460 /* As long as we have empty frags without any mapping symbols,
7462 /* If the next frag is non-empty and does not start with a
7463 mapping symbol, then this mapping symbol is required. */
7464 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7467 next
= next
->fr_next
;
7469 while (next
!= NULL
);
7474 /* Adjust the symbol table. */
7477 aarch64_adjust_symtab (void)
7480 /* Remove any overlapping mapping symbols generated by alignment frags. */
7481 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7482 /* Now do generic ELF adjustments. */
7483 elf_adjust_symtab ();
7488 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7490 const char *hash_err
;
7492 hash_err
= hash_insert (table
, key
, value
);
7494 printf ("Internal Error: Can't hash %s\n", key
);
7498 fill_instruction_hash_table (void)
7500 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7502 while (opcode
->name
!= NULL
)
7504 templates
*templ
, *new_templ
;
7505 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7507 new_templ
= XNEW (templates
);
7508 new_templ
->opcode
= opcode
;
7509 new_templ
->next
= NULL
;
7512 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7515 new_templ
->next
= templ
->next
;
7516 templ
->next
= new_templ
;
7523 convert_to_upper (char *dst
, const char *src
, size_t num
)
7526 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7527 *dst
= TOUPPER (*src
);
7531 /* Assume STR point to a lower-case string, allocate, convert and return
7532 the corresponding upper-case string. */
7533 static inline const char*
7534 get_upper_str (const char *str
)
7537 size_t len
= strlen (str
);
7538 ret
= XNEWVEC (char, len
+ 1);
7539 convert_to_upper (ret
, str
, len
);
7543 /* MD interface: Initialization. */
7551 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7552 || (aarch64_cond_hsh
= hash_new ()) == NULL
7553 || (aarch64_shift_hsh
= hash_new ()) == NULL
7554 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7555 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7556 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7557 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7558 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7559 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7560 || (aarch64_reg_hsh
= hash_new ()) == NULL
7561 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7562 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7563 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7564 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7565 as_fatal (_("virtual memory exhausted"));
7567 fill_instruction_hash_table ();
7569 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7570 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7571 (void *) (aarch64_sys_regs
+ i
));
7573 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7574 checked_hash_insert (aarch64_pstatefield_hsh
,
7575 aarch64_pstatefields
[i
].name
,
7576 (void *) (aarch64_pstatefields
+ i
));
7578 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7579 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7580 aarch64_sys_regs_ic
[i
].name
,
7581 (void *) (aarch64_sys_regs_ic
+ i
));
7583 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7584 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7585 aarch64_sys_regs_dc
[i
].name
,
7586 (void *) (aarch64_sys_regs_dc
+ i
));
7588 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7589 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7590 aarch64_sys_regs_at
[i
].name
,
7591 (void *) (aarch64_sys_regs_at
+ i
));
7593 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7594 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7595 aarch64_sys_regs_tlbi
[i
].name
,
7596 (void *) (aarch64_sys_regs_tlbi
+ i
));
7598 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7599 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7600 (void *) (reg_names
+ i
));
7602 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7603 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7604 (void *) (nzcv_names
+ i
));
7606 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7608 const char *name
= aarch64_operand_modifiers
[i
].name
;
7609 checked_hash_insert (aarch64_shift_hsh
, name
,
7610 (void *) (aarch64_operand_modifiers
+ i
));
7611 /* Also hash the name in the upper case. */
7612 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7613 (void *) (aarch64_operand_modifiers
+ i
));
7616 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7619 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7620 the same condition code. */
7621 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7623 const char *name
= aarch64_conds
[i
].names
[j
];
7626 checked_hash_insert (aarch64_cond_hsh
, name
,
7627 (void *) (aarch64_conds
+ i
));
7628 /* Also hash the name in the upper case. */
7629 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7630 (void *) (aarch64_conds
+ i
));
7634 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7636 const char *name
= aarch64_barrier_options
[i
].name
;
7637 /* Skip xx00 - the unallocated values of option. */
7640 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7641 (void *) (aarch64_barrier_options
+ i
));
7642 /* Also hash the name in the upper case. */
7643 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7644 (void *) (aarch64_barrier_options
+ i
));
7647 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7649 const char* name
= aarch64_prfops
[i
].name
;
7650 /* Skip the unallocated hint encodings. */
7653 checked_hash_insert (aarch64_pldop_hsh
, name
,
7654 (void *) (aarch64_prfops
+ i
));
7655 /* Also hash the name in the upper case. */
7656 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7657 (void *) (aarch64_prfops
+ i
));
7660 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7662 const char* name
= aarch64_hint_options
[i
].name
;
7664 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7665 (void *) (aarch64_hint_options
+ i
));
7666 /* Also hash the name in the upper case. */
7667 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7668 (void *) (aarch64_hint_options
+ i
));
7671 /* Set the cpu variant based on the command-line options. */
7673 mcpu_cpu_opt
= march_cpu_opt
;
7676 mcpu_cpu_opt
= &cpu_default
;
7678 cpu_variant
= *mcpu_cpu_opt
;
7680 /* Record the CPU type. */
7681 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7683 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7686 /* Command line processing. */
7688 const char *md_shortopts
= "m:";
7690 #ifdef AARCH64_BI_ENDIAN
7691 #define OPTION_EB (OPTION_MD_BASE + 0)
7692 #define OPTION_EL (OPTION_MD_BASE + 1)
7694 #if TARGET_BYTES_BIG_ENDIAN
7695 #define OPTION_EB (OPTION_MD_BASE + 0)
7697 #define OPTION_EL (OPTION_MD_BASE + 1)
7701 struct option md_longopts
[] = {
7703 {"EB", no_argument
, NULL
, OPTION_EB
},
7706 {"EL", no_argument
, NULL
, OPTION_EL
},
7708 {NULL
, no_argument
, NULL
, 0}
7711 size_t md_longopts_size
= sizeof (md_longopts
);
7713 struct aarch64_option_table
7715 const char *option
; /* Option name to match. */
7716 const char *help
; /* Help information. */
7717 int *var
; /* Variable to change. */
7718 int value
; /* What to change it to. */
7719 char *deprecated
; /* If non-null, print this message. */
7722 static struct aarch64_option_table aarch64_opts
[] = {
7723 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7724 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7726 #ifdef DEBUG_AARCH64
7727 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7728 #endif /* DEBUG_AARCH64 */
7729 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7731 {"mno-verbose-error", N_("do not output verbose error messages"),
7732 &verbose_error_p
, 0, NULL
},
7733 {NULL
, NULL
, NULL
, 0, NULL
}
7736 struct aarch64_cpu_option_table
7739 const aarch64_feature_set value
;
7740 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7742 const char *canonical_name
;
7745 /* This list should, at a minimum, contain all the cpu names
7746 recognized by GCC. */
7747 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7748 {"all", AARCH64_ANY
, NULL
},
7749 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7750 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7751 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7752 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7753 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7754 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7755 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7756 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7757 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7758 AARCH64_FEATURE_CRC
), "Cortex-A73"},
7759 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7760 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7761 "Samsung Exynos M1"},
7762 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7763 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7764 "Qualcomm QDF24XX"},
7765 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7766 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7768 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7769 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7771 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7772 in earlier releases and is superseded by 'xgene1' in all
7774 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7775 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7776 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7777 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7778 {"generic", AARCH64_ARCH_V8
, NULL
},
7780 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7783 struct aarch64_arch_option_table
7786 const aarch64_feature_set value
;
7789 /* This list should, at a minimum, contain all the architecture names
7790 recognized by GCC. */
7791 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7792 {"all", AARCH64_ANY
},
7793 {"armv8-a", AARCH64_ARCH_V8
},
7794 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7795 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7796 {NULL
, AARCH64_ARCH_NONE
}
7799 /* ISA extensions. */
7800 struct aarch64_option_cpu_value_table
7803 const aarch64_feature_set value
;
7806 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7807 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7808 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7809 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7810 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7811 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7812 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7813 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7814 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0)},
7815 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7816 | AARCH64_FEATURE_RDMA
, 0)},
7817 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7818 | AARCH64_FEATURE_FP
, 0)},
7819 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0)},
7820 {NULL
, AARCH64_ARCH_NONE
}
7823 struct aarch64_long_option_table
7825 const char *option
; /* Substring to match. */
7826 const char *help
; /* Help information. */
7827 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
7828 char *deprecated
; /* If non-null, print this message. */
7832 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
7833 bfd_boolean ext_only
)
7835 /* We insist on extensions being added before being removed. We achieve
7836 this by using the ADDING_VALUE variable to indicate whether we are
7837 adding an extension (1) or removing it (0) and only allowing it to
7838 change in the order -1 -> 1 -> 0. */
7839 int adding_value
= -1;
7840 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
7842 /* Copy the feature set, so that we can modify it. */
7846 while (str
!= NULL
&& *str
!= 0)
7848 const struct aarch64_option_cpu_value_table
*opt
;
7849 const char *ext
= NULL
;
7856 as_bad (_("invalid architectural extension"));
7860 ext
= strchr (++str
, '+');
7866 optlen
= strlen (str
);
7868 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7870 if (adding_value
!= 0)
7875 else if (optlen
> 0)
7877 if (adding_value
== -1)
7879 else if (adding_value
!= 1)
7881 as_bad (_("must specify extensions to add before specifying "
7882 "those to remove"));
7889 as_bad (_("missing architectural extension"));
7893 gas_assert (adding_value
!= -1);
7895 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7896 if (strncmp (opt
->name
, str
, optlen
) == 0)
7898 /* Add or remove the extension. */
7900 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7902 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7906 if (opt
->name
== NULL
)
7908 as_bad (_("unknown architectural extension `%s'"), str
);
7919 aarch64_parse_cpu (const char *str
)
7921 const struct aarch64_cpu_option_table
*opt
;
7922 const char *ext
= strchr (str
, '+');
7928 optlen
= strlen (str
);
7932 as_bad (_("missing cpu name `%s'"), str
);
7936 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7937 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7939 mcpu_cpu_opt
= &opt
->value
;
7941 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7946 as_bad (_("unknown cpu `%s'"), str
);
7951 aarch64_parse_arch (const char *str
)
7953 const struct aarch64_arch_option_table
*opt
;
7954 const char *ext
= strchr (str
, '+');
7960 optlen
= strlen (str
);
7964 as_bad (_("missing architecture name `%s'"), str
);
7968 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7969 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7971 march_cpu_opt
= &opt
->value
;
7973 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7978 as_bad (_("unknown architecture `%s'\n"), str
);
7983 struct aarch64_option_abi_value_table
7986 enum aarch64_abi_type value
;
7989 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7990 {"ilp32", AARCH64_ABI_ILP32
},
7991 {"lp64", AARCH64_ABI_LP64
},
7996 aarch64_parse_abi (const char *str
)
7998 const struct aarch64_option_abi_value_table
*opt
;
7999 size_t optlen
= strlen (str
);
8003 as_bad (_("missing abi name `%s'"), str
);
8007 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
8008 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8010 aarch64_abi
= opt
->value
;
8014 as_bad (_("unknown abi `%s'\n"), str
);
8018 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8020 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8021 aarch64_parse_abi
, NULL
},
8022 #endif /* OBJ_ELF */
8023 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8024 aarch64_parse_cpu
, NULL
},
8025 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8026 aarch64_parse_arch
, NULL
},
8027 {NULL
, NULL
, 0, NULL
}
8031 md_parse_option (int c
, const char *arg
)
8033 struct aarch64_option_table
*opt
;
8034 struct aarch64_long_option_table
*lopt
;
8040 target_big_endian
= 1;
8046 target_big_endian
= 0;
8051 /* Listing option. Just ignore these, we don't support additional
8056 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8058 if (c
== opt
->option
[0]
8059 && ((arg
== NULL
&& opt
->option
[1] == 0)
8060 || streq (arg
, opt
->option
+ 1)))
8062 /* If the option is deprecated, tell the user. */
8063 if (opt
->deprecated
!= NULL
)
8064 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8065 arg
? arg
: "", _(opt
->deprecated
));
8067 if (opt
->var
!= NULL
)
8068 *opt
->var
= opt
->value
;
8074 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8076 /* These options are expected to have an argument. */
8077 if (c
== lopt
->option
[0]
8079 && strncmp (arg
, lopt
->option
+ 1,
8080 strlen (lopt
->option
+ 1)) == 0)
8082 /* If the option is deprecated, tell the user. */
8083 if (lopt
->deprecated
!= NULL
)
8084 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8085 _(lopt
->deprecated
));
8087 /* Call the sup-option parser. */
8088 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8099 md_show_usage (FILE * fp
)
8101 struct aarch64_option_table
*opt
;
8102 struct aarch64_long_option_table
*lopt
;
8104 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8106 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8107 if (opt
->help
!= NULL
)
8108 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8110 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8111 if (lopt
->help
!= NULL
)
8112 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8116 -EB assemble code for a big-endian cpu\n"));
8121 -EL assemble code for a little-endian cpu\n"));
8125 /* Parse a .cpu directive. */
8128 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8130 const struct aarch64_cpu_option_table
*opt
;
8136 name
= input_line_pointer
;
8137 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8138 input_line_pointer
++;
8139 saved_char
= *input_line_pointer
;
8140 *input_line_pointer
= 0;
8142 ext
= strchr (name
, '+');
8145 optlen
= ext
- name
;
8147 optlen
= strlen (name
);
8149 /* Skip the first "all" entry. */
8150 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8151 if (strlen (opt
->name
) == optlen
8152 && strncmp (name
, opt
->name
, optlen
) == 0)
8154 mcpu_cpu_opt
= &opt
->value
;
8156 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8159 cpu_variant
= *mcpu_cpu_opt
;
8161 *input_line_pointer
= saved_char
;
8162 demand_empty_rest_of_line ();
8165 as_bad (_("unknown cpu `%s'"), name
);
8166 *input_line_pointer
= saved_char
;
8167 ignore_rest_of_line ();
8171 /* Parse a .arch directive. */
8174 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8176 const struct aarch64_arch_option_table
*opt
;
8182 name
= input_line_pointer
;
8183 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8184 input_line_pointer
++;
8185 saved_char
= *input_line_pointer
;
8186 *input_line_pointer
= 0;
8188 ext
= strchr (name
, '+');
8191 optlen
= ext
- name
;
8193 optlen
= strlen (name
);
8195 /* Skip the first "all" entry. */
8196 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8197 if (strlen (opt
->name
) == optlen
8198 && strncmp (name
, opt
->name
, optlen
) == 0)
8200 mcpu_cpu_opt
= &opt
->value
;
8202 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8205 cpu_variant
= *mcpu_cpu_opt
;
8207 *input_line_pointer
= saved_char
;
8208 demand_empty_rest_of_line ();
8212 as_bad (_("unknown architecture `%s'\n"), name
);
8213 *input_line_pointer
= saved_char
;
8214 ignore_rest_of_line ();
8217 /* Parse a .arch_extension directive. */
8220 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8223 char *ext
= input_line_pointer
;;
8225 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8226 input_line_pointer
++;
8227 saved_char
= *input_line_pointer
;
8228 *input_line_pointer
= 0;
8230 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8233 cpu_variant
= *mcpu_cpu_opt
;
8235 *input_line_pointer
= saved_char
;
8236 demand_empty_rest_of_line ();
8239 /* Copy symbol information. */
8242 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8244 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);