1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Number of littlenums required to hold an extended precision number. */
242 #define MAX_LITTLENUMS 6
244 /* Return value for certain parsers when the parsing fails; those parsers
245 return the information of the parsed result, e.g. register number, on
247 #define PARSE_FAIL -1
249 /* This is an invalid condition code that means no conditional field is
251 #define COND_ALWAYS 0x10
255 const char *template;
261 const char *template;
268 bfd_reloc_code_real_type reloc
;
271 /* Macros to define the register types and masks for the purpose
274 #undef AARCH64_REG_TYPES
275 #define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
287 BASIC_REG_TYPE(VN) /* v[0-31] */ \
288 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
289 BASIC_REG_TYPE(PN) /* p[0-15] */ \
290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
319 in other contexts. */ \
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* Pseudo type to mark the end of the enumerator sequence. */ \
333 #undef BASIC_REG_TYPE
334 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
335 #undef MULTI_REG_TYPE
336 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
338 /* Register type enumerators. */
339 typedef enum aarch64_reg_type_
341 /* A list of REG_TYPE_*. */
345 #undef BASIC_REG_TYPE
346 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
348 #define REG_TYPE(T) (1 << REG_TYPE_##T)
349 #undef MULTI_REG_TYPE
350 #define MULTI_REG_TYPE(T,V) V,
352 /* Structure for a hash table entry for a register. */
356 unsigned char number
;
357 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
358 unsigned char builtin
;
361 /* Values indexed by aarch64_reg_type to assist the type checking. */
362 static const unsigned reg_type_masks
[] =
367 #undef BASIC_REG_TYPE
369 #undef MULTI_REG_TYPE
370 #undef AARCH64_REG_TYPES
372 /* Diagnostics used when we don't get a register of the expected type.
373 Note: this has to synchronized with aarch64_reg_type definitions
376 get_reg_expected_msg (aarch64_reg_type reg_type
)
383 msg
= N_("integer 32-bit register expected");
386 msg
= N_("integer 64-bit register expected");
389 msg
= N_("integer register expected");
391 case REG_TYPE_R64_SP
:
392 msg
= N_("64-bit integer or SP register expected");
394 case REG_TYPE_SVE_BASE
:
395 msg
= N_("base register expected");
398 msg
= N_("integer or zero register expected");
400 case REG_TYPE_SVE_OFFSET
:
401 msg
= N_("offset register expected");
404 msg
= N_("integer or SP register expected");
406 case REG_TYPE_R_Z_SP
:
407 msg
= N_("integer, zero or SP register expected");
410 msg
= N_("8-bit SIMD scalar register expected");
413 msg
= N_("16-bit SIMD scalar or floating-point half precision "
414 "register expected");
417 msg
= N_("32-bit SIMD scalar or floating-point single precision "
418 "register expected");
421 msg
= N_("64-bit SIMD scalar or floating-point double precision "
422 "register expected");
425 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
426 "register expected");
428 case REG_TYPE_R_Z_BHSDQ_V
:
429 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
430 msg
= N_("register expected");
432 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
433 msg
= N_("SIMD scalar or floating-point register expected");
435 case REG_TYPE_VN
: /* any V reg */
436 msg
= N_("vector register expected");
439 msg
= N_("SVE vector register expected");
442 msg
= N_("SVE predicate register expected");
445 as_fatal (_("invalid register type %d"), reg_type
);
450 /* Some well known registers that we refer to directly elsewhere. */
453 /* Instructions take 4 bytes in the object file. */
456 static struct hash_control
*aarch64_ops_hsh
;
457 static struct hash_control
*aarch64_cond_hsh
;
458 static struct hash_control
*aarch64_shift_hsh
;
459 static struct hash_control
*aarch64_sys_regs_hsh
;
460 static struct hash_control
*aarch64_pstatefield_hsh
;
461 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
462 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
463 static struct hash_control
*aarch64_sys_regs_at_hsh
;
464 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
465 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
466 static struct hash_control
*aarch64_reg_hsh
;
467 static struct hash_control
*aarch64_barrier_opt_hsh
;
468 static struct hash_control
*aarch64_nzcv_hsh
;
469 static struct hash_control
*aarch64_pldop_hsh
;
470 static struct hash_control
*aarch64_hint_opt_hsh
;
472 /* Stuff needed to resolve the label ambiguity
481 static symbolS
*last_label_seen
;
483 /* Literal pool structure. Held on a per-section
484 and per-sub-section basis. */
486 #define MAX_LITERAL_POOL_SIZE 1024
487 typedef struct literal_expression
490 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
491 LITTLENUM_TYPE
* bignum
;
492 } literal_expression
;
494 typedef struct literal_pool
496 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
497 unsigned int next_free_entry
;
503 struct literal_pool
*next
;
506 /* Pointer to a linked list of literal pools. */
507 static literal_pool
*list_of_pools
= NULL
;
511 /* This array holds the chars that always start a comment. If the
512 pre-processor is disabled, these aren't very useful. */
513 const char comment_chars
[] = "";
515 /* This array holds the chars that only start a comment at the beginning of
516 a line. If the line seems to have the form '# 123 filename'
517 .line and .file directives will appear in the pre-processed output. */
518 /* Note that input_file.c hand checks for '#' at the beginning of the
519 first line of the input file. This is because the compiler outputs
520 #NO_APP at the beginning of its output. */
521 /* Also note that comments like this one will always work. */
522 const char line_comment_chars
[] = "#";
524 const char line_separator_chars
[] = ";";
526 /* Chars that can be used to separate mant
527 from exp in floating point numbers. */
528 const char EXP_CHARS
[] = "eE";
530 /* Chars that mean this number is a floating point constant. */
534 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
536 /* Prefix character that indicates the start of an immediate value. */
537 #define is_immediate_prefix(C) ((C) == '#')
539 /* Separator character handling. */
541 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 static inline bfd_boolean
544 skip_past_char (char **str
, char c
)
555 #define skip_past_comma(str) skip_past_char (str, ',')
557 /* Arithmetic expressions (possibly involving symbols). */
559 static bfd_boolean in_my_get_expression_p
= FALSE
;
561 /* Third argument to my_get_expression. */
562 #define GE_NO_PREFIX 0
563 #define GE_OPT_PREFIX 1
565 /* Return TRUE if the string pointed by *STR is successfully parsed
566 as an valid expression; *EP will be filled with the information of
567 such an expression. Otherwise return FALSE. */
570 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
575 int prefix_present_p
= 0;
582 if (is_immediate_prefix (**str
))
585 prefix_present_p
= 1;
592 memset (ep
, 0, sizeof (expressionS
));
594 save_in
= input_line_pointer
;
595 input_line_pointer
= *str
;
596 in_my_get_expression_p
= TRUE
;
597 seg
= expression (ep
);
598 in_my_get_expression_p
= FALSE
;
600 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
602 /* We found a bad expression in md_operand(). */
603 *str
= input_line_pointer
;
604 input_line_pointer
= save_in
;
605 if (prefix_present_p
&& ! error_p ())
606 set_fatal_syntax_error (_("bad expression"));
608 set_first_syntax_error (_("bad expression"));
613 if (seg
!= absolute_section
614 && seg
!= text_section
615 && seg
!= data_section
616 && seg
!= bss_section
&& seg
!= undefined_section
)
618 set_syntax_error (_("bad segment"));
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
632 /* Turn a string in input_line_pointer into a floating point constant
633 of type TYPE, and store the appropriate bytes in *LITP. The number
634 of LITTLENUMS emitted is stored in *SIZEP. An error message is
635 returned, or NULL on OK. */
638 md_atof (int type
, char *litP
, int *sizeP
)
640 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
643 /* We handle all bad expressions here, so that we can report the faulty
644 instruction in the error message. */
646 md_operand (expressionS
* exp
)
648 if (in_my_get_expression_p
)
649 exp
->X_op
= O_illegal
;
652 /* Immediate values. */
654 /* Errors may be set multiple times during parsing or bit encoding
655 (particularly in the Neon bits), but usually the earliest error which is set
656 will be the most meaningful. Avoid overwriting it with later (cascading)
657 errors by calling this function. */
660 first_error (const char *error
)
663 set_syntax_error (error
);
666 /* Similar to first_error, but this function accepts formatted error
669 first_error_fmt (const char *format
, ...)
674 /* N.B. this single buffer will not cause error messages for different
675 instructions to pollute each other; this is because at the end of
676 processing of each assembly line, error message if any will be
677 collected by as_bad. */
678 static char buffer
[size
];
682 int ret ATTRIBUTE_UNUSED
;
683 va_start (args
, format
);
684 ret
= vsnprintf (buffer
, size
, format
, args
);
685 know (ret
<= size
- 1 && ret
>= 0);
687 set_syntax_error (buffer
);
691 /* Register parsing. */
693 /* Generic register parser which is called by other specialized
695 CCP points to what should be the beginning of a register name.
696 If it is indeed a valid register name, advance CCP over it and
697 return the reg_entry structure; otherwise return NULL.
698 It does not issue diagnostics. */
701 parse_reg (char **ccp
)
707 #ifdef REGISTER_PREFIX
708 if (*start
!= REGISTER_PREFIX
)
714 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
719 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
721 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
730 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
733 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
735 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
738 /* Try to parse a base or offset register. Allow SVE base and offset
739 registers if REG_TYPE includes SVE registers. Return the register
740 entry on success, setting *QUALIFIER to the register qualifier.
741 Return null otherwise.
743 Note that this function does not issue any diagnostics. */
745 static const reg_entry
*
746 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
747 aarch64_opnd_qualifier_t
*qualifier
)
750 const reg_entry
*reg
= parse_reg (&str
);
760 *qualifier
= AARCH64_OPND_QLF_W
;
766 *qualifier
= AARCH64_OPND_QLF_X
;
770 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
773 switch (TOLOWER (str
[1]))
776 *qualifier
= AARCH64_OPND_QLF_S_S
;
779 *qualifier
= AARCH64_OPND_QLF_S_D
;
796 /* Try to parse a base or offset register. Return the register entry
797 on success, setting *QUALIFIER to the register qualifier. Return null
800 Note that this function does not issue any diagnostics. */
802 static const reg_entry
*
803 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
805 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
808 /* Parse the qualifier of a vector register or vector element of type
809 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
810 succeeds; otherwise return FALSE.
812 Accept only one occurrence of:
813 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
816 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
817 struct vector_type_el
*parsed_type
, char **str
)
821 unsigned element_size
;
822 enum vector_el_type type
;
825 gas_assert (*ptr
== '.');
828 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
833 width
= strtoul (ptr
, &ptr
, 10);
834 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
836 first_error_fmt (_("bad size %d in vector width specifier"), width
);
841 switch (TOLOWER (*ptr
))
860 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
869 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
871 first_error (_("missing element size"));
874 if (width
!= 0 && width
* element_size
!= 64
875 && width
* element_size
!= 128
876 && !(width
== 2 && element_size
== 16)
877 && !(width
== 4 && element_size
== 8))
880 ("invalid element size %d and vector size combination %c"),
886 parsed_type
->type
= type
;
887 parsed_type
->width
= width
;
894 /* *STR contains an SVE zero/merge predication suffix. Parse it into
895 *PARSED_TYPE and point *STR at the end of the suffix. */
898 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
903 gas_assert (*ptr
== '/');
905 switch (TOLOWER (*ptr
))
908 parsed_type
->type
= NT_zero
;
911 parsed_type
->type
= NT_merge
;
914 if (*ptr
!= '\0' && *ptr
!= ',')
915 first_error_fmt (_("unexpected character `%c' in predication type"),
918 first_error (_("missing predication type"));
921 parsed_type
->width
= 0;
926 /* Parse a register of the type TYPE.
928 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
929 name or the parsed register is not of TYPE.
931 Otherwise return the register number, and optionally fill in the actual
932 type of the register in *RTYPE when multiple alternatives were given, and
933 return the register shape and element index information in *TYPEINFO.
935 IN_REG_LIST should be set with TRUE if the caller is parsing a register
939 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
940 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
943 const reg_entry
*reg
= parse_reg (&str
);
944 struct vector_type_el atype
;
945 struct vector_type_el parsetype
;
946 bfd_boolean is_typed_vecreg
= FALSE
;
949 atype
.type
= NT_invtype
;
957 set_default_error ();
961 if (! aarch64_check_reg_type (reg
, type
))
963 DEBUG_TRACE ("reg type check failed");
964 set_default_error ();
969 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
970 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
974 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
979 if (!parse_predication_for_operand (&parsetype
, &str
))
983 /* Register if of the form Vn.[bhsdq]. */
984 is_typed_vecreg
= TRUE
;
986 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
988 /* The width is always variable; we don't allow an integer width
990 gas_assert (parsetype
.width
== 0);
991 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
993 else if (parsetype
.width
== 0)
994 /* Expect index. In the new scheme we cannot have
995 Vn.[bhsdq] represent a scalar. Therefore any
996 Vn.[bhsdq] should have an index following it.
997 Except in reglists of course. */
998 atype
.defined
|= NTA_HASINDEX
;
1000 atype
.defined
|= NTA_HASTYPE
;
1002 atype
.type
= parsetype
.type
;
1003 atype
.width
= parsetype
.width
;
1006 if (skip_past_char (&str
, '['))
1010 /* Reject Sn[index] syntax. */
1011 if (!is_typed_vecreg
)
1013 first_error (_("this type of register can't be indexed"));
1019 first_error (_("index not allowed inside register list"));
1023 atype
.defined
|= NTA_HASINDEX
;
1025 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1027 if (exp
.X_op
!= O_constant
)
1029 first_error (_("constant expression required"));
1033 if (! skip_past_char (&str
, ']'))
1036 atype
.index
= exp
.X_add_number
;
1038 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1040 /* Indexed vector register expected. */
1041 first_error (_("indexed vector register expected"));
1045 /* A vector reg Vn should be typed or indexed. */
1046 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1048 first_error (_("invalid use of vector register"));
1064 Return the register number on success; return PARSE_FAIL otherwise.
1066 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1067 the register (e.g. NEON double or quad reg when either has been requested).
1069 If this is a NEON vector register with additional type information, fill
1070 in the struct pointed to by VECTYPE (if non-NULL).
1072 This parser does not handle register list. */
1075 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1076 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1078 struct vector_type_el atype
;
1080 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1081 /*in_reg_list= */ FALSE
);
1083 if (reg
== PARSE_FAIL
)
1094 static inline bfd_boolean
1095 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1099 && e1
.defined
== e2
.defined
1100 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1103 /* This function parses a list of vector registers of type TYPE.
1104 On success, it returns the parsed register list information in the
1105 following encoded format:
1107 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1108 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1110 The information of the register shape and/or index is returned in
1113 It returns PARSE_FAIL if the register list is invalid.
1115 The list contains one to four registers.
1116 Each register can be one of:
1119 All <T> should be identical.
1120 All <index> should be identical.
1121 There are restrictions on <Vt> numbers which are checked later
1122 (by reg_list_valid_p). */
1125 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1126 struct vector_type_el
*vectype
)
1130 struct vector_type_el typeinfo
, typeinfo_first
;
1135 bfd_boolean error
= FALSE
;
1136 bfd_boolean expect_index
= FALSE
;
1140 set_syntax_error (_("expecting {"));
1146 typeinfo_first
.defined
= 0;
1147 typeinfo_first
.type
= NT_invtype
;
1148 typeinfo_first
.width
= -1;
1149 typeinfo_first
.index
= 0;
1158 str
++; /* skip over '-' */
1161 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1162 /*in_reg_list= */ TRUE
);
1163 if (val
== PARSE_FAIL
)
1165 set_first_syntax_error (_("invalid vector register in list"));
1169 /* reject [bhsd]n */
1170 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1172 set_first_syntax_error (_("invalid scalar register in list"));
1177 if (typeinfo
.defined
& NTA_HASINDEX
)
1178 expect_index
= TRUE
;
1182 if (val
< val_range
)
1184 set_first_syntax_error
1185 (_("invalid range in vector register list"));
1194 typeinfo_first
= typeinfo
;
1195 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1197 set_first_syntax_error
1198 (_("type mismatch in vector register list"));
1203 for (i
= val_range
; i
<= val
; i
++)
1205 ret_val
|= i
<< (5 * nb_regs
);
1210 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1212 skip_whitespace (str
);
1215 set_first_syntax_error (_("end of vector register list not found"));
1220 skip_whitespace (str
);
1224 if (skip_past_char (&str
, '['))
1228 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1229 if (exp
.X_op
!= O_constant
)
1231 set_first_syntax_error (_("constant expression required."));
1234 if (! skip_past_char (&str
, ']'))
1237 typeinfo_first
.index
= exp
.X_add_number
;
1241 set_first_syntax_error (_("expected index"));
1248 set_first_syntax_error (_("too many registers in vector register list"));
1251 else if (nb_regs
== 0)
1253 set_first_syntax_error (_("empty vector register list"));
1259 *vectype
= typeinfo_first
;
1261 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1264 /* Directives: register aliases. */
1267 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1272 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1275 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1278 /* Only warn about a redefinition if it's not defined as the
1280 else if (new->number
!= number
|| new->type
!= type
)
1281 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1286 name
= xstrdup (str
);
1287 new = XNEW (reg_entry
);
1290 new->number
= number
;
1292 new->builtin
= FALSE
;
1294 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1300 /* Look for the .req directive. This is of the form:
1302 new_register_name .req existing_register_name
1304 If we find one, or if it looks sufficiently like one that we want to
1305 handle any error here, return TRUE. Otherwise return FALSE. */
1308 create_register_alias (char *newname
, char *p
)
1310 const reg_entry
*old
;
1311 char *oldname
, *nbuf
;
1314 /* The input scrubber ensures that whitespace after the mnemonic is
1315 collapsed to single spaces. */
1317 if (strncmp (oldname
, " .req ", 6) != 0)
1321 if (*oldname
== '\0')
1324 old
= hash_find (aarch64_reg_hsh
, oldname
);
1327 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1331 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1332 the desired alias name, and p points to its end. If not, then
1333 the desired alias name is in the global original_case_string. */
1334 #ifdef TC_CASE_SENSITIVE
1337 newname
= original_case_string
;
1338 nlen
= strlen (newname
);
1341 nbuf
= xmemdup0 (newname
, nlen
);
1343 /* Create aliases under the new name as stated; an all-lowercase
1344 version of the new name; and an all-uppercase version of the new
1346 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1348 for (p
= nbuf
; *p
; p
++)
1351 if (strncmp (nbuf
, newname
, nlen
))
1353 /* If this attempt to create an additional alias fails, do not bother
1354 trying to create the all-lower case alias. We will fail and issue
1355 a second, duplicate error message. This situation arises when the
1356 programmer does something like:
1359 The second .req creates the "Foo" alias but then fails to create
1360 the artificial FOO alias because it has already been created by the
1362 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1373 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1380 /* Should never be called, as .req goes between the alias and the
1381 register name, not at the beginning of the line. */
1383 s_req (int a ATTRIBUTE_UNUSED
)
1385 as_bad (_("invalid syntax for .req directive"));
1388 /* The .unreq directive deletes an alias which was previously defined
1389 by .req. For example:
1395 s_unreq (int a ATTRIBUTE_UNUSED
)
1400 name
= input_line_pointer
;
1402 while (*input_line_pointer
!= 0
1403 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1404 ++input_line_pointer
;
1406 saved_char
= *input_line_pointer
;
1407 *input_line_pointer
= 0;
1410 as_bad (_("invalid syntax for .unreq directive"));
1413 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1416 as_bad (_("unknown register alias '%s'"), name
);
1417 else if (reg
->builtin
)
1418 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1425 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1426 free ((char *) reg
->name
);
1429 /* Also locate the all upper case and all lower case versions.
1430 Do not complain if we cannot find one or the other as it
1431 was probably deleted above. */
1433 nbuf
= strdup (name
);
1434 for (p
= nbuf
; *p
; p
++)
1436 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1439 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1440 free ((char *) reg
->name
);
1444 for (p
= nbuf
; *p
; p
++)
1446 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1449 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1450 free ((char *) reg
->name
);
1458 *input_line_pointer
= saved_char
;
1459 demand_empty_rest_of_line ();
1462 /* Directives: Instruction set selection. */
1465 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1466 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1467 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1468 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1470 /* Create a new mapping symbol for the transition to STATE. */
1473 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1476 const char *symname
;
1483 type
= BSF_NO_FLAGS
;
1487 type
= BSF_NO_FLAGS
;
1493 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1494 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1496 /* Save the mapping symbols for future reference. Also check that
1497 we do not place two mapping symbols at the same offset within a
1498 frag. We'll handle overlap between frags in
1499 check_mapping_symbols.
1501 If .fill or other data filling directive generates zero sized data,
1502 the mapping symbol for the following code will have the same value
1503 as the one generated for the data filling directive. In this case,
1504 we replace the old symbol with the new one at the same address. */
1507 if (frag
->tc_frag_data
.first_map
!= NULL
)
1509 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1510 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1513 frag
->tc_frag_data
.first_map
= symbolP
;
1515 if (frag
->tc_frag_data
.last_map
!= NULL
)
1517 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1518 S_GET_VALUE (symbolP
));
1519 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1520 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1523 frag
->tc_frag_data
.last_map
= symbolP
;
1526 /* We must sometimes convert a region marked as code to data during
1527 code alignment, if an odd number of bytes have to be padded. The
1528 code mapping symbol is pushed to an aligned address. */
1531 insert_data_mapping_symbol (enum mstate state
,
1532 valueT value
, fragS
* frag
, offsetT bytes
)
1534 /* If there was already a mapping symbol, remove it. */
1535 if (frag
->tc_frag_data
.last_map
!= NULL
1536 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1537 frag
->fr_address
+ value
)
1539 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1543 know (frag
->tc_frag_data
.first_map
== symp
);
1544 frag
->tc_frag_data
.first_map
= NULL
;
1546 frag
->tc_frag_data
.last_map
= NULL
;
1547 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1550 make_mapping_symbol (MAP_DATA
, value
, frag
);
1551 make_mapping_symbol (state
, value
+ bytes
, frag
);
1554 static void mapping_state_2 (enum mstate state
, int max_chars
);
1556 /* Set the mapping state to STATE. Only call this when about to
1557 emit some STATE bytes to the file. */
1560 mapping_state (enum mstate state
)
1562 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1564 if (state
== MAP_INSN
)
1565 /* AArch64 instructions require 4-byte alignment. When emitting
1566 instructions into any section, record the appropriate section
1568 record_alignment (now_seg
, 2);
1570 if (mapstate
== state
)
1571 /* The mapping symbol has already been emitted.
1572 There is nothing else to do. */
1575 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1576 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1577 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1578 evaluated later in the next else. */
1580 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1582 /* Only add the symbol if the offset is > 0:
1583 if we're at the first frag, check it's size > 0;
1584 if we're not at the first frag, then for sure
1585 the offset is > 0. */
1586 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1587 const int add_symbol
= (frag_now
!= frag_first
)
1588 || (frag_now_fix () > 0);
1591 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1595 mapping_state_2 (state
, 0);
1598 /* Same as mapping_state, but MAX_CHARS bytes have already been
1599 allocated. Put the mapping symbol that far back. */
1602 mapping_state_2 (enum mstate state
, int max_chars
)
1604 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1606 if (!SEG_NORMAL (now_seg
))
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1615 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1618 #define mapping_state(x) /* nothing */
1619 #define mapping_state_2(x, y) /* nothing */
1622 /* Directives: sectioning and alignment. */
1625 s_bss (int ignore ATTRIBUTE_UNUSED
)
1627 /* We don't support putting frags in the BSS segment, we fake it by
1628 marking in_bss, then looking at s_skip for clues. */
1629 subseg_set (bss_section
, 0);
1630 demand_empty_rest_of_line ();
1631 mapping_state (MAP_DATA
);
1635 s_even (int ignore ATTRIBUTE_UNUSED
)
1637 /* Never make frag if expect extra pass. */
1639 frag_align (1, 0, 0);
1641 record_alignment (now_seg
, 1);
1643 demand_empty_rest_of_line ();
1646 /* Directives: Literal pools. */
1648 static literal_pool
*
1649 find_literal_pool (int size
)
1653 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1655 if (pool
->section
== now_seg
1656 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1663 static literal_pool
*
1664 find_or_make_literal_pool (int size
)
1666 /* Next literal pool ID number. */
1667 static unsigned int latest_pool_num
= 1;
1670 pool
= find_literal_pool (size
);
1674 /* Create a new pool. */
1675 pool
= XNEW (literal_pool
);
1679 /* Currently we always put the literal pool in the current text
1680 section. If we were generating "small" model code where we
1681 knew that all code and initialised data was within 1MB then
1682 we could output literals to mergeable, read-only data
1685 pool
->next_free_entry
= 0;
1686 pool
->section
= now_seg
;
1687 pool
->sub_section
= now_subseg
;
1689 pool
->next
= list_of_pools
;
1690 pool
->symbol
= NULL
;
1692 /* Add it to the list. */
1693 list_of_pools
= pool
;
1696 /* New pools, and emptied pools, will have a NULL symbol. */
1697 if (pool
->symbol
== NULL
)
1699 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1700 (valueT
) 0, &zero_address_frag
);
1701 pool
->id
= latest_pool_num
++;
1708 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1709 Return TRUE on success, otherwise return FALSE. */
1711 add_to_lit_pool (expressionS
*exp
, int size
)
1716 pool
= find_or_make_literal_pool (size
);
1718 /* Check if this literal value is already in the pool. */
1719 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1721 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1723 if ((litexp
->X_op
== exp
->X_op
)
1724 && (exp
->X_op
== O_constant
)
1725 && (litexp
->X_add_number
== exp
->X_add_number
)
1726 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1729 if ((litexp
->X_op
== exp
->X_op
)
1730 && (exp
->X_op
== O_symbol
)
1731 && (litexp
->X_add_number
== exp
->X_add_number
)
1732 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1733 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1737 /* Do we need to create a new entry? */
1738 if (entry
== pool
->next_free_entry
)
1740 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1742 set_syntax_error (_("literal pool overflow"));
1746 pool
->literals
[entry
].exp
= *exp
;
1747 pool
->next_free_entry
+= 1;
1748 if (exp
->X_op
== O_big
)
1750 /* PR 16688: Bignums are held in a single global array. We must
1751 copy and preserve that value now, before it is overwritten. */
1752 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1754 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1755 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1758 pool
->literals
[entry
].bignum
= NULL
;
1761 exp
->X_op
= O_symbol
;
1762 exp
->X_add_number
= ((int) entry
) * size
;
1763 exp
->X_add_symbol
= pool
->symbol
;
1768 /* Can't use symbol_new here, so have to create a symbol and then at
1769 a later date assign it a value. That's what these functions do. */
1772 symbol_locate (symbolS
* symbolP
,
1773 const char *name
,/* It is copied, the caller can modify. */
1774 segT segment
, /* Segment identifier (SEG_<something>). */
1775 valueT valu
, /* Symbol value. */
1776 fragS
* frag
) /* Associated fragment. */
1779 char *preserved_copy_of_name
;
1781 name_length
= strlen (name
) + 1; /* +1 for \0. */
1782 obstack_grow (¬es
, name
, name_length
);
1783 preserved_copy_of_name
= obstack_finish (¬es
);
1785 #ifdef tc_canonicalize_symbol_name
1786 preserved_copy_of_name
=
1787 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1790 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1792 S_SET_SEGMENT (symbolP
, segment
);
1793 S_SET_VALUE (symbolP
, valu
);
1794 symbol_clear_list_pointers (symbolP
);
1796 symbol_set_frag (symbolP
, frag
);
1798 /* Link to end of symbol chain. */
1800 extern int symbol_table_frozen
;
1802 if (symbol_table_frozen
)
1806 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1808 obj_symbol_new_hook (symbolP
);
1810 #ifdef tc_symbol_new_hook
1811 tc_symbol_new_hook (symbolP
);
1815 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1816 #endif /* DEBUG_SYMS */
1821 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1828 for (align
= 2; align
<= 4; align
++)
1830 int size
= 1 << align
;
1832 pool
= find_literal_pool (size
);
1833 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1836 /* Align pool as you have word accesses.
1837 Only make a frag if we have to. */
1839 frag_align (align
, 0, 0);
1841 mapping_state (MAP_DATA
);
1843 record_alignment (now_seg
, align
);
1845 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1847 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1848 (valueT
) frag_now_fix (), frag_now
);
1849 symbol_table_insert (pool
->symbol
);
1851 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1853 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1855 if (exp
->X_op
== O_big
)
1857 /* PR 16688: Restore the global bignum value. */
1858 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1859 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1860 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1863 /* First output the expression in the instruction to the pool. */
1864 emit_expr (exp
, size
); /* .word|.xword */
1866 if (exp
->X_op
== O_big
)
1868 free (pool
->literals
[entry
].bignum
);
1869 pool
->literals
[entry
].bignum
= NULL
;
1873 /* Mark the pool as empty. */
1874 pool
->next_free_entry
= 0;
1875 pool
->symbol
= NULL
;
1880 /* Forward declarations for functions below, in the MD interface
1882 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1883 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1885 /* Directives: Data. */
1886 /* N.B. the support for relocation suffix in this directive needs to be
1887 implemented properly. */
1890 s_aarch64_elf_cons (int nbytes
)
1894 #ifdef md_flush_pending_output
1895 md_flush_pending_output ();
1898 if (is_it_end_of_statement ())
1900 demand_empty_rest_of_line ();
1904 #ifdef md_cons_align
1905 md_cons_align (nbytes
);
1908 mapping_state (MAP_DATA
);
1911 struct reloc_table_entry
*reloc
;
1915 if (exp
.X_op
!= O_symbol
)
1916 emit_expr (&exp
, (unsigned int) nbytes
);
1919 skip_past_char (&input_line_pointer
, '#');
1920 if (skip_past_char (&input_line_pointer
, ':'))
1922 reloc
= find_reloc_table_entry (&input_line_pointer
);
1924 as_bad (_("unrecognized relocation suffix"));
1926 as_bad (_("unimplemented relocation suffix"));
1927 ignore_rest_of_line ();
1931 emit_expr (&exp
, (unsigned int) nbytes
);
1934 while (*input_line_pointer
++ == ',');
1936 /* Put terminator back into stream. */
1937 input_line_pointer
--;
1938 demand_empty_rest_of_line ();
1941 #endif /* OBJ_ELF */
1943 /* Output a 32-bit word, but mark as an instruction. */
1946 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1950 #ifdef md_flush_pending_output
1951 md_flush_pending_output ();
1954 if (is_it_end_of_statement ())
1956 demand_empty_rest_of_line ();
1960 /* Sections are assumed to start aligned. In executable section, there is no
1961 MAP_DATA symbol pending. So we only align the address during
1962 MAP_DATA --> MAP_INSN transition.
1963 For other sections, this is not guaranteed. */
1964 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1965 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1966 frag_align_code (2, 0);
1969 mapping_state (MAP_INSN
);
1975 if (exp
.X_op
!= O_constant
)
1977 as_bad (_("constant expression required"));
1978 ignore_rest_of_line ();
1982 if (target_big_endian
)
1984 unsigned int val
= exp
.X_add_number
;
1985 exp
.X_add_number
= SWAP_32 (val
);
1987 emit_expr (&exp
, 4);
1989 while (*input_line_pointer
++ == ',');
1991 /* Put terminator back into stream. */
1992 input_line_pointer
--;
1993 demand_empty_rest_of_line ();
1997 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2000 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2006 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2007 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2009 demand_empty_rest_of_line ();
2012 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2015 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2019 /* Since we're just labelling the code, there's no need to define a
2022 /* Make sure there is enough room in this frag for the following
2023 blr. This trick only works if the blr follows immediately after
2024 the .tlsdesc directive. */
2026 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2027 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2029 demand_empty_rest_of_line ();
2032 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2035 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2041 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2042 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2044 demand_empty_rest_of_line ();
2046 #endif /* OBJ_ELF */
2048 static void s_aarch64_arch (int);
2049 static void s_aarch64_cpu (int);
2050 static void s_aarch64_arch_extension (int);
2052 /* This table describes all the machine specific pseudo-ops the assembler
2053 has to support. The fields are:
2054 pseudo-op name without dot
2055 function to call to execute this pseudo-op
2056 Integer arg to pass to the function. */
2058 const pseudo_typeS md_pseudo_table
[] = {
2059 /* Never called because '.req' does not start a line. */
2061 {"unreq", s_unreq
, 0},
2063 {"even", s_even
, 0},
2064 {"ltorg", s_ltorg
, 0},
2065 {"pool", s_ltorg
, 0},
2066 {"cpu", s_aarch64_cpu
, 0},
2067 {"arch", s_aarch64_arch
, 0},
2068 {"arch_extension", s_aarch64_arch_extension
, 0},
2069 {"inst", s_aarch64_inst
, 0},
2071 {"tlsdescadd", s_tlsdescadd
, 0},
2072 {"tlsdesccall", s_tlsdesccall
, 0},
2073 {"tlsdescldr", s_tlsdescldr
, 0},
2074 {"word", s_aarch64_elf_cons
, 4},
2075 {"long", s_aarch64_elf_cons
, 4},
2076 {"xword", s_aarch64_elf_cons
, 8},
2077 {"dword", s_aarch64_elf_cons
, 8},
2083 /* Check whether STR points to a register name followed by a comma or the
2084 end of line; REG_TYPE indicates which register types are checked
2085 against. Return TRUE if STR is such a register name; otherwise return
2086 FALSE. The function does not intend to produce any diagnostics, but since
2087 the register parser aarch64_reg_parse, which is called by this function,
2088 does produce diagnostics, we call clear_error to clear any diagnostics
2089 that may be generated by aarch64_reg_parse.
2090 Also, the function returns FALSE directly if there is any user error
2091 present at the function entry. This prevents the existing diagnostics
2092 state from being spoiled.
2093 The function currently serves parse_constant_immediate and
2094 parse_big_immediate only. */
2096 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2100 /* Prevent the diagnostics state from being spoiled. */
2104 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2106 /* Clear the parsing error that may be set by the reg parser. */
2109 if (reg
== PARSE_FAIL
)
2112 skip_whitespace (str
);
2113 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2119 /* Parser functions used exclusively in instruction operands. */
2121 /* Parse an immediate expression which may not be constant.
2123 To prevent the expression parser from pushing a register name
2124 into the symbol table as an undefined symbol, firstly a check is
2125 done to find out whether STR is a register of type REG_TYPE followed
2126 by a comma or the end of line. Return FALSE if STR is such a string. */
2129 parse_immediate_expression (char **str
, expressionS
*exp
,
2130 aarch64_reg_type reg_type
)
2132 if (reg_name_p (*str
, reg_type
))
2134 set_recoverable_error (_("immediate operand required"));
2138 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2140 if (exp
->X_op
== O_absent
)
2142 set_fatal_syntax_error (_("missing immediate expression"));
2149 /* Constant immediate-value read function for use in insn parsing.
2150 STR points to the beginning of the immediate (with the optional
2151 leading #); *VAL receives the value. REG_TYPE says which register
2152 names should be treated as registers rather than as symbolic immediates.
2154 Return TRUE on success; otherwise return FALSE. */
2157 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2161 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2164 if (exp
.X_op
!= O_constant
)
2166 set_syntax_error (_("constant expression required"));
2170 *val
= exp
.X_add_number
;
2175 encode_imm_float_bits (uint32_t imm
)
2177 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2178 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2181 /* Return TRUE if the single-precision floating-point value encoded in IMM
2182 can be expressed in the AArch64 8-bit signed floating-point format with
2183 3-bit exponent and normalized 4 bits of precision; in other words, the
2184 floating-point value must be expressable as
2185 (+/-) n / 16 * power (2, r)
2186 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2189 aarch64_imm_float_p (uint32_t imm
)
2191 /* If a single-precision floating-point value has the following bit
2192 pattern, it can be expressed in the AArch64 8-bit floating-point
2195 3 32222222 2221111111111
2196 1 09876543 21098765432109876543210
2197 n Eeeeeexx xxxx0000000000000000000
2199 where n, e and each x are either 0 or 1 independently, with
2204 /* Prepare the pattern for 'Eeeeee'. */
2205 if (((imm
>> 30) & 0x1) == 0)
2206 pattern
= 0x3e000000;
2208 pattern
= 0x40000000;
2210 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2211 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2214 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2215 as an IEEE float without any loss of precision. Store the value in
2219 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2221 /* If a double-precision floating-point value has the following bit
2222 pattern, it can be expressed in a float:
2224 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2225 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2226 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2228 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2229 if Eeee_eeee != 1111_1111
2231 where n, e, s and S are either 0 or 1 independently and where ~ is the
2235 uint32_t high32
= imm
>> 32;
2236 uint32_t low32
= imm
;
2238 /* Lower 29 bits need to be 0s. */
2239 if ((imm
& 0x1fffffff) != 0)
2242 /* Prepare the pattern for 'Eeeeeeeee'. */
2243 if (((high32
>> 30) & 0x1) == 0)
2244 pattern
= 0x38000000;
2246 pattern
= 0x40000000;
2249 if ((high32
& 0x78000000) != pattern
)
2252 /* Check Eeee_eeee != 1111_1111. */
2253 if ((high32
& 0x7ff00000) == 0x47f00000)
2256 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2257 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2258 | (low32
>> 29)); /* 3 S bits. */
2262 /* Return true if we should treat OPERAND as a double-precision
2263 floating-point operand rather than a single-precision one. */
2265 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2267 /* Check for unsuffixed SVE registers, which are allowed
2268 for LDR and STR but not in instructions that require an
2269 immediate. We get better error messages if we arbitrarily
2270 pick one size, parse the immediate normally, and then
2271 report the match failure in the normal way. */
2272 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2273 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2276 /* Parse a floating-point immediate. Return TRUE on success and return the
2277 value in *IMMED in the format of IEEE754 single-precision encoding.
2278 *CCP points to the start of the string; DP_P is TRUE when the immediate
2279 is expected to be in double-precision (N.B. this only matters when
2280 hexadecimal representation is involved). REG_TYPE says which register
2281 names should be treated as registers rather than as symbolic immediates.
2283 This routine accepts any IEEE float; it is up to the callers to reject
2287 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2288 aarch64_reg_type reg_type
)
2292 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2294 unsigned fpword
= 0;
2295 bfd_boolean hex_p
= FALSE
;
2297 skip_past_char (&str
, '#');
2300 skip_whitespace (fpnum
);
2302 if (strncmp (fpnum
, "0x", 2) == 0)
2304 /* Support the hexadecimal representation of the IEEE754 encoding.
2305 Double-precision is expected when DP_P is TRUE, otherwise the
2306 representation should be in single-precision. */
2307 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2312 if (!can_convert_double_to_float (val
, &fpword
))
2315 else if ((uint64_t) val
> 0xffffffff)
2322 else if (reg_name_p (str
, reg_type
))
2324 set_recoverable_error (_("immediate operand required"));
2332 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2335 /* Our FP word must be 32 bits (single-precision FP). */
2336 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2338 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2348 set_fatal_syntax_error (_("invalid floating-point constant"));
2352 /* Less-generic immediate-value read function with the possibility of loading
2353 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2356 To prevent the expression parser from pushing a register name into the
2357 symbol table as an undefined symbol, a check is firstly done to find
2358 out whether STR is a register of type REG_TYPE followed by a comma or
2359 the end of line. Return FALSE if STR is such a register. */
2362 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2366 if (reg_name_p (ptr
, reg_type
))
2368 set_syntax_error (_("immediate operand required"));
2372 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2374 if (inst
.reloc
.exp
.X_op
== O_constant
)
2375 *imm
= inst
.reloc
.exp
.X_add_number
;
2382 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2383 if NEED_LIBOPCODES is non-zero, the fixup will need
2384 assistance from the libopcodes. */
2387 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2388 const aarch64_opnd_info
*operand
,
2389 int need_libopcodes_p
)
2391 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2392 reloc
->opnd
= operand
->type
;
2393 if (need_libopcodes_p
)
2394 reloc
->need_libopcodes_p
= 1;
2397 /* Return TRUE if the instruction needs to be fixed up later internally by
2398 the GAS; otherwise return FALSE. */
2400 static inline bfd_boolean
2401 aarch64_gas_internal_fixup_p (void)
2403 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2406 /* Assign the immediate value to the relevant field in *OPERAND if
2407 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2408 needs an internal fixup in a later stage.
2409 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2410 IMM.VALUE that may get assigned with the constant. */
2412 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2413 aarch64_opnd_info
*operand
,
2415 int need_libopcodes_p
,
2418 if (reloc
->exp
.X_op
== O_constant
)
2421 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2423 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2424 reloc
->type
= BFD_RELOC_UNUSED
;
2428 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2429 /* Tell libopcodes to ignore this operand or not. This is helpful
2430 when one of the operands needs to be fixed up later but we need
2431 libopcodes to check the other operands. */
2432 operand
->skip
= skip_p
;
2436 /* Relocation modifiers. Each entry in the table contains the textual
2437 name for the relocation which may be placed before a symbol used as
2438 a load/store offset, or add immediate. It must be surrounded by a
2439 leading and trailing colon, for example:
2441 ldr x0, [x1, #:rello:varsym]
2442 add x0, x1, #:rello:varsym */
2444 struct reloc_table_entry
2448 bfd_reloc_code_real_type adr_type
;
2449 bfd_reloc_code_real_type adrp_type
;
2450 bfd_reloc_code_real_type movw_type
;
2451 bfd_reloc_code_real_type add_type
;
2452 bfd_reloc_code_real_type ldst_type
;
2453 bfd_reloc_code_real_type ld_literal_type
;
2456 static struct reloc_table_entry reloc_table
[] = {
2457 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2462 BFD_RELOC_AARCH64_ADD_LO12
,
2463 BFD_RELOC_AARCH64_LDST_LO12
,
2466 /* Higher 21 bits of pc-relative page offset: ADRP */
2469 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2475 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2478 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2484 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2488 BFD_RELOC_AARCH64_MOVW_G0
,
2493 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2497 BFD_RELOC_AARCH64_MOVW_G0_S
,
2502 /* Less significant bits 0-15 of address/value: MOVK, no check */
2506 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2511 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2515 BFD_RELOC_AARCH64_MOVW_G1
,
2520 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2524 BFD_RELOC_AARCH64_MOVW_G1_S
,
2529 /* Less significant bits 16-31 of address/value: MOVK, no check */
2533 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2538 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2542 BFD_RELOC_AARCH64_MOVW_G2
,
2547 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2551 BFD_RELOC_AARCH64_MOVW_G2_S
,
2556 /* Less significant bits 32-47 of address/value: MOVK, no check */
2560 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2565 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2569 BFD_RELOC_AARCH64_MOVW_G3
,
2574 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2578 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2583 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2587 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2592 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2596 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2601 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2605 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2610 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2614 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2619 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2623 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2628 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2632 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2637 /* Get to the page containing GOT entry for a symbol. */
2640 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2644 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2646 /* 12 bit offset into the page containing GOT entry for that symbol. */
2652 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2655 /* 0-15 bits of address/value: MOVk, no check. */
2659 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2664 /* Most significant bits 16-31 of address/value: MOVZ. */
2668 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2673 /* 15 bit offset into the page containing GOT entry for that symbol. */
2679 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2682 /* Get to the page containing GOT TLS entry for a symbol */
2683 {"gottprel_g0_nc", 0,
2686 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2691 /* Get to the page containing GOT TLS entry for a symbol */
2695 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2700 /* Get to the page containing GOT TLS entry for a symbol */
2702 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2703 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2709 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2714 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2718 /* Lower 16 bits address/value: MOVk. */
2722 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2727 /* Most significant bits 16-31 of address/value: MOVZ. */
2731 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2736 /* Get to the page containing GOT TLS entry for a symbol */
2738 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2739 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2743 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2745 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2750 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2751 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2754 /* Get to the page containing GOT TLS entry for a symbol.
2755 The same as GD, we allocate two consecutive GOT slots
2756 for module index and module offset, the only difference
2757 with GD is the module offset should be initialized to
2758 zero without any outstanding runtime relocation. */
2760 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2761 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2767 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2768 {"tlsldm_lo12_nc", 0,
2772 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2776 /* 12 bit offset into the module TLS base address. */
2781 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2782 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2785 /* Same as dtprel_lo12, no overflow check. */
2786 {"dtprel_lo12_nc", 0,
2790 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2791 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2794 /* bits[23:12] of offset to the module TLS base address. */
2799 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2803 /* bits[15:0] of offset to the module TLS base address. */
2807 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2812 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2816 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2821 /* bits[31:16] of offset to the module TLS base address. */
2825 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2830 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2834 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2839 /* bits[47:32] of offset to the module TLS base address. */
2843 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2848 /* Lower 16 bit offset into GOT entry for a symbol */
2849 {"tlsdesc_off_g0_nc", 0,
2852 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2857 /* Higher 16 bit offset into GOT entry for a symbol */
2858 {"tlsdesc_off_g1", 0,
2861 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2866 /* Get to the page containing GOT TLS entry for a symbol */
2869 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2873 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2875 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2876 {"gottprel_lo12", 0,
2881 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2884 /* Get tp offset for a symbol. */
2889 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2893 /* Get tp offset for a symbol. */
2898 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2899 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2902 /* Get tp offset for a symbol. */
2907 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2911 /* Get tp offset for a symbol. */
2912 {"tprel_lo12_nc", 0,
2916 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2917 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2920 /* Most significant bits 32-47 of address/value: MOVZ. */
2924 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2929 /* Most significant bits 16-31 of address/value: MOVZ. */
2933 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2938 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2942 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2947 /* Most significant bits 0-15 of address/value: MOVZ. */
2951 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2956 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2960 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2965 /* 15bit offset from got entry to base address of GOT table. */
2971 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2974 /* 14bit offset from got entry to base address of GOT table. */
2980 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2984 /* Given the address of a pointer pointing to the textual name of a
2985 relocation as may appear in assembler source, attempt to find its
2986 details in reloc_table. The pointer will be updated to the character
2987 after the trailing colon. On failure, NULL will be returned;
2988 otherwise return the reloc_table_entry. */
2990 static struct reloc_table_entry
*
2991 find_reloc_table_entry (char **str
)
2994 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2996 int length
= strlen (reloc_table
[i
].name
);
2998 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2999 && (*str
)[length
] == ':')
3001 *str
+= (length
+ 1);
3002 return &reloc_table
[i
];
3009 /* Mode argument to parse_shift and parser_shifter_operand. */
3010 enum parse_shift_mode
3012 SHIFTED_NONE
, /* no shifter allowed */
3013 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3015 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3017 SHIFTED_LSL
, /* bare "lsl #n" */
3018 SHIFTED_MUL
, /* bare "mul #n" */
3019 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3020 SHIFTED_MUL_VL
, /* "mul vl" */
3021 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3024 /* Parse a <shift> operator on an AArch64 data processing instruction.
3025 Return TRUE on success; otherwise return FALSE. */
3027 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3029 const struct aarch64_name_value_pair
*shift_op
;
3030 enum aarch64_modifier_kind kind
;
3036 for (p
= *str
; ISALPHA (*p
); p
++)
3041 set_syntax_error (_("shift expression expected"));
3045 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3047 if (shift_op
== NULL
)
3049 set_syntax_error (_("shift operator expected"));
3053 kind
= aarch64_get_operand_modifier (shift_op
);
3055 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3057 set_syntax_error (_("invalid use of 'MSL'"));
3061 if (kind
== AARCH64_MOD_MUL
3062 && mode
!= SHIFTED_MUL
3063 && mode
!= SHIFTED_MUL_VL
)
3065 set_syntax_error (_("invalid use of 'MUL'"));
3071 case SHIFTED_LOGIC_IMM
:
3072 if (aarch64_extend_operator_p (kind
))
3074 set_syntax_error (_("extending shift is not permitted"));
3079 case SHIFTED_ARITH_IMM
:
3080 if (kind
== AARCH64_MOD_ROR
)
3082 set_syntax_error (_("'ROR' shift is not permitted"));
3088 if (kind
!= AARCH64_MOD_LSL
)
3090 set_syntax_error (_("only 'LSL' shift is permitted"));
3096 if (kind
!= AARCH64_MOD_MUL
)
3098 set_syntax_error (_("only 'MUL' is permitted"));
3103 case SHIFTED_MUL_VL
:
3104 /* "MUL VL" consists of two separate tokens. Require the first
3105 token to be "MUL" and look for a following "VL". */
3106 if (kind
== AARCH64_MOD_MUL
)
3108 skip_whitespace (p
);
3109 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3112 kind
= AARCH64_MOD_MUL_VL
;
3116 set_syntax_error (_("only 'MUL VL' is permitted"));
3119 case SHIFTED_REG_OFFSET
:
3120 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3121 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3123 set_fatal_syntax_error
3124 (_("invalid shift for the register offset addressing mode"));
3129 case SHIFTED_LSL_MSL
:
3130 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3132 set_syntax_error (_("invalid shift operator"));
3141 /* Whitespace can appear here if the next thing is a bare digit. */
3142 skip_whitespace (p
);
3144 /* Parse shift amount. */
3146 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3147 exp
.X_op
= O_absent
;
3150 if (is_immediate_prefix (*p
))
3155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3157 if (kind
== AARCH64_MOD_MUL_VL
)
3158 /* For consistency, give MUL VL the same shift amount as an implicit
3160 operand
->shifter
.amount
= 1;
3161 else if (exp
.X_op
== O_absent
)
3163 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3165 set_syntax_error (_("missing shift amount"));
3168 operand
->shifter
.amount
= 0;
3170 else if (exp
.X_op
!= O_constant
)
3172 set_syntax_error (_("constant shift amount required"));
3175 /* For parsing purposes, MUL #n has no inherent range. The range
3176 depends on the operand and will be checked by operand-specific
3178 else if (kind
!= AARCH64_MOD_MUL
3179 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3181 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3186 operand
->shifter
.amount
= exp
.X_add_number
;
3187 operand
->shifter
.amount_present
= 1;
3190 operand
->shifter
.operator_present
= 1;
3191 operand
->shifter
.kind
= kind
;
3197 /* Parse a <shifter_operand> for a data processing instruction:
3200 #<immediate>, LSL #imm
3202 Validation of immediate operands is deferred to md_apply_fix.
3204 Return TRUE on success; otherwise return FALSE. */
3207 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3208 enum parse_shift_mode mode
)
3212 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3217 /* Accept an immediate expression. */
3218 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3221 /* Accept optional LSL for arithmetic immediate values. */
3222 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3223 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3226 /* Not accept any shifter for logical immediate values. */
3227 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3228 && parse_shift (&p
, operand
, mode
))
3230 set_syntax_error (_("unexpected shift operator"));
3238 /* Parse a <shifter_operand> for a data processing instruction:
3243 #<immediate>, LSL #imm
3245 where <shift> is handled by parse_shift above, and the last two
3246 cases are handled by the function above.
3248 Validation of immediate operands is deferred to md_apply_fix.
3250 Return TRUE on success; otherwise return FALSE. */
3253 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3254 enum parse_shift_mode mode
)
3256 const reg_entry
*reg
;
3257 aarch64_opnd_qualifier_t qualifier
;
3258 enum aarch64_operand_class opd_class
3259 = aarch64_get_operand_class (operand
->type
);
3261 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3264 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3266 set_syntax_error (_("unexpected register in the immediate operand"));
3270 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3272 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3276 operand
->reg
.regno
= reg
->number
;
3277 operand
->qualifier
= qualifier
;
3279 /* Accept optional shift operation on register. */
3280 if (! skip_past_comma (str
))
3283 if (! parse_shift (str
, operand
, mode
))
3288 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3291 (_("integer register expected in the extended/shifted operand "
3296 /* We have a shifted immediate variable. */
3297 return parse_shifter_operand_imm (str
, operand
, mode
);
3300 /* Return TRUE on success; return FALSE otherwise. */
3303 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3304 enum parse_shift_mode mode
)
3308 /* Determine if we have the sequence of characters #: or just :
3309 coming next. If we do, then we check for a :rello: relocation
3310 modifier. If we don't, punt the whole lot to
3311 parse_shifter_operand. */
3313 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3315 struct reloc_table_entry
*entry
;
3323 /* Try to parse a relocation. Anything else is an error. */
3324 if (!(entry
= find_reloc_table_entry (str
)))
3326 set_syntax_error (_("unknown relocation modifier"));
3330 if (entry
->add_type
== 0)
3333 (_("this relocation modifier is not allowed on this instruction"));
3337 /* Save str before we decompose it. */
3340 /* Next, we parse the expression. */
3341 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3344 /* Record the relocation type (use the ADD variant here). */
3345 inst
.reloc
.type
= entry
->add_type
;
3346 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3348 /* If str is empty, we've reached the end, stop here. */
3352 /* Otherwise, we have a shifted reloc modifier, so rewind to
3353 recover the variable name and continue parsing for the shifter. */
3355 return parse_shifter_operand_imm (str
, operand
, mode
);
3358 return parse_shifter_operand (str
, operand
, mode
);
3361 /* Parse all forms of an address expression. Information is written
3362 to *OPERAND and/or inst.reloc.
3364 The A64 instruction set has the following addressing modes:
3367 [base] // in SIMD ld/st structure
3368 [base{,#0}] // in ld/st exclusive
3370 [base,Xm{,LSL #imm}]
3371 [base,Xm,SXTX {#imm}]
3372 [base,Wm,(S|U)XTW {#imm}]
3375 [base]! // in ld/stgv
3378 [base],Xm // in SIMD ld/st structure
3379 PC-relative (literal)
3383 [base,Zm.D{,LSL #imm}]
3384 [base,Zm.S,(S|U)XTW {#imm}]
3385 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3388 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3389 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3390 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3392 (As a convenience, the notation "=immediate" is permitted in conjunction
3393 with the pc-relative literal load instructions to automatically place an
3394 immediate value or symbolic address in a nearby literal pool and generate
3395 a hidden label which references it.)
3397 Upon a successful parsing, the address structure in *OPERAND will be
3398 filled in the following way:
3400 .base_regno = <base>
3401 .offset.is_reg // 1 if the offset is a register
3403 .offset.regno = <Rm>
3405 For different addressing modes defined in the A64 ISA:
3408 .pcrel=0; .preind=1; .postind=0; .writeback=0
3410 .pcrel=0; .preind=1; .postind=0; .writeback=1
3412 .pcrel=0; .preind=0; .postind=1; .writeback=1
3413 PC-relative (literal)
3414 .pcrel=1; .preind=1; .postind=0; .writeback=0
3416 The shift/extension information, if any, will be stored in .shifter.
3417 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3418 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3419 corresponding register.
3421 BASE_TYPE says which types of base register should be accepted and
3422 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3423 is the type of shifter that is allowed for immediate offsets,
3424 or SHIFTED_NONE if none.
3426 In all other respects, it is the caller's responsibility to check
3427 for addressing modes not supported by the instruction, and to set
3431 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3432 aarch64_opnd_qualifier_t
*base_qualifier
,
3433 aarch64_opnd_qualifier_t
*offset_qualifier
,
3434 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3435 enum parse_shift_mode imm_shift_mode
)
3438 const reg_entry
*reg
;
3439 expressionS
*exp
= &inst
.reloc
.exp
;
3441 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3442 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3443 if (! skip_past_char (&p
, '['))
3445 /* =immediate or label. */
3446 operand
->addr
.pcrel
= 1;
3447 operand
->addr
.preind
= 1;
3449 /* #:<reloc_op>:<symbol> */
3450 skip_past_char (&p
, '#');
3451 if (skip_past_char (&p
, ':'))
3453 bfd_reloc_code_real_type ty
;
3454 struct reloc_table_entry
*entry
;
3456 /* Try to parse a relocation modifier. Anything else is
3458 entry
= find_reloc_table_entry (&p
);
3461 set_syntax_error (_("unknown relocation modifier"));
3465 switch (operand
->type
)
3467 case AARCH64_OPND_ADDR_PCREL21
:
3469 ty
= entry
->adr_type
;
3473 ty
= entry
->ld_literal_type
;
3480 (_("this relocation modifier is not allowed on this "
3486 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3488 set_syntax_error (_("invalid relocation expression"));
3492 /* #:<reloc_op>:<expr> */
3493 /* Record the relocation type. */
3494 inst
.reloc
.type
= ty
;
3495 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3500 if (skip_past_char (&p
, '='))
3501 /* =immediate; need to generate the literal in the literal pool. */
3502 inst
.gen_lit_pool
= 1;
3504 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3506 set_syntax_error (_("invalid address"));
3517 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3518 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3520 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3523 operand
->addr
.base_regno
= reg
->number
;
3526 if (skip_past_comma (&p
))
3529 operand
->addr
.preind
= 1;
3531 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3534 if (!aarch64_check_reg_type (reg
, offset_type
))
3536 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3541 operand
->addr
.offset
.regno
= reg
->number
;
3542 operand
->addr
.offset
.is_reg
= 1;
3543 /* Shifted index. */
3544 if (skip_past_comma (&p
))
3547 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3548 /* Use the diagnostics set in parse_shift, so not set new
3549 error message here. */
3553 [base,Xm{,LSL #imm}]
3554 [base,Xm,SXTX {#imm}]
3555 [base,Wm,(S|U)XTW {#imm}] */
3556 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3557 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3558 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3560 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3562 set_syntax_error (_("invalid use of 32-bit register offset"));
3565 if (aarch64_get_qualifier_esize (*base_qualifier
)
3566 != aarch64_get_qualifier_esize (*offset_qualifier
))
3568 set_syntax_error (_("offset has different size from base"));
3572 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3574 set_syntax_error (_("invalid use of 64-bit register offset"));
3580 /* [Xn,#:<reloc_op>:<symbol> */
3581 skip_past_char (&p
, '#');
3582 if (skip_past_char (&p
, ':'))
3584 struct reloc_table_entry
*entry
;
3586 /* Try to parse a relocation modifier. Anything else is
3588 if (!(entry
= find_reloc_table_entry (&p
)))
3590 set_syntax_error (_("unknown relocation modifier"));
3594 if (entry
->ldst_type
== 0)
3597 (_("this relocation modifier is not allowed on this "
3602 /* [Xn,#:<reloc_op>: */
3603 /* We now have the group relocation table entry corresponding to
3604 the name in the assembler source. Next, we parse the
3606 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3608 set_syntax_error (_("invalid relocation expression"));
3612 /* [Xn,#:<reloc_op>:<expr> */
3613 /* Record the load/store relocation type. */
3614 inst
.reloc
.type
= entry
->ldst_type
;
3615 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3619 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3621 set_syntax_error (_("invalid expression in the address"));
3625 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3626 /* [Xn,<expr>,<shifter> */
3627 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3633 if (! skip_past_char (&p
, ']'))
3635 set_syntax_error (_("']' expected"));
3639 if (skip_past_char (&p
, '!'))
3641 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3643 set_syntax_error (_("register offset not allowed in pre-indexed "
3644 "addressing mode"));
3648 operand
->addr
.writeback
= 1;
3650 else if (skip_past_comma (&p
))
3653 operand
->addr
.postind
= 1;
3654 operand
->addr
.writeback
= 1;
3656 if (operand
->addr
.preind
)
3658 set_syntax_error (_("cannot combine pre- and post-indexing"));
3662 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3666 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3668 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3672 operand
->addr
.offset
.regno
= reg
->number
;
3673 operand
->addr
.offset
.is_reg
= 1;
3675 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3678 set_syntax_error (_("invalid expression in the address"));
3683 /* If at this point neither .preind nor .postind is set, we have a
3684 bare [Rn]{!}; reject [Rn]! except for ld/stgv but accept [Rn]
3685 as a shorthand for [Rn,#0]. */
3686 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3688 if (operand
->type
!= AARCH64_OPND_ADDR_SIMPLE_2
&& operand
->addr
.writeback
)
3691 set_syntax_error (_("missing offset in the pre-indexed address"));
3695 operand
->addr
.preind
= 1;
3696 inst
.reloc
.exp
.X_op
= O_constant
;
3697 inst
.reloc
.exp
.X_add_number
= 0;
3704 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3707 parse_address (char **str
, aarch64_opnd_info
*operand
)
3709 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3710 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3711 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3714 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3715 The arguments have the same meaning as for parse_address_main.
3716 Return TRUE on success. */
3718 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3719 aarch64_opnd_qualifier_t
*base_qualifier
,
3720 aarch64_opnd_qualifier_t
*offset_qualifier
)
3722 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3723 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3727 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3728 Return TRUE on success; otherwise return FALSE. */
3730 parse_half (char **str
, int *internal_fixup_p
)
3734 skip_past_char (&p
, '#');
3736 gas_assert (internal_fixup_p
);
3737 *internal_fixup_p
= 0;
3741 struct reloc_table_entry
*entry
;
3743 /* Try to parse a relocation. Anything else is an error. */
3745 if (!(entry
= find_reloc_table_entry (&p
)))
3747 set_syntax_error (_("unknown relocation modifier"));
3751 if (entry
->movw_type
== 0)
3754 (_("this relocation modifier is not allowed on this instruction"));
3758 inst
.reloc
.type
= entry
->movw_type
;
3761 *internal_fixup_p
= 1;
3763 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3770 /* Parse an operand for an ADRP instruction:
3772 Return TRUE on success; otherwise return FALSE. */
3775 parse_adrp (char **str
)
3782 struct reloc_table_entry
*entry
;
3784 /* Try to parse a relocation. Anything else is an error. */
3786 if (!(entry
= find_reloc_table_entry (&p
)))
3788 set_syntax_error (_("unknown relocation modifier"));
3792 if (entry
->adrp_type
== 0)
3795 (_("this relocation modifier is not allowed on this instruction"));
3799 inst
.reloc
.type
= entry
->adrp_type
;
3802 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3804 inst
.reloc
.pc_rel
= 1;
3806 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3813 /* Miscellaneous. */
3815 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3816 of SIZE tokens in which index I gives the token for field value I,
3817 or is null if field value I is invalid. REG_TYPE says which register
3818 names should be treated as registers rather than as symbolic immediates.
3820 Return true on success, moving *STR past the operand and storing the
3821 field value in *VAL. */
3824 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3825 size_t size
, aarch64_reg_type reg_type
)
3831 /* Match C-like tokens. */
3833 while (ISALNUM (*q
))
3836 for (i
= 0; i
< size
; ++i
)
3838 && strncasecmp (array
[i
], p
, q
- p
) == 0
3839 && array
[i
][q
- p
] == 0)
3846 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3849 if (exp
.X_op
== O_constant
3850 && (uint64_t) exp
.X_add_number
< size
)
3852 *val
= exp
.X_add_number
;
3857 /* Use the default error for this operand. */
3861 /* Parse an option for a preload instruction. Returns the encoding for the
3862 option, or PARSE_FAIL. */
3865 parse_pldop (char **str
)
3868 const struct aarch64_name_value_pair
*o
;
3871 while (ISALNUM (*q
))
3874 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3882 /* Parse an option for a barrier instruction. Returns the encoding for the
3883 option, or PARSE_FAIL. */
3886 parse_barrier (char **str
)
3889 const asm_barrier_opt
*o
;
3892 while (ISALPHA (*q
))
3895 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3903 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3904 return 0 if successful. Otherwise return PARSE_FAIL. */
3907 parse_barrier_psb (char **str
,
3908 const struct aarch64_name_value_pair
** hint_opt
)
3911 const struct aarch64_name_value_pair
*o
;
3914 while (ISALPHA (*q
))
3917 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3920 set_fatal_syntax_error
3921 ( _("unknown or missing option to PSB"));
3925 if (o
->value
!= 0x11)
3927 /* PSB only accepts option name 'CSYNC'. */
3929 (_("the specified option is not accepted for PSB"));
3938 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3939 return 0 if successful. Otherwise return PARSE_FAIL. */
3942 parse_bti_operand (char **str
,
3943 const struct aarch64_name_value_pair
** hint_opt
)
3946 const struct aarch64_name_value_pair
*o
;
3949 while (ISALPHA (*q
))
3952 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3955 set_fatal_syntax_error
3956 ( _("unknown option to BTI"));
3962 /* Valid BTI operands. */
3970 (_("unknown option to BTI"));
3979 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3980 Returns the encoding for the option, or PARSE_FAIL.
3982 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3983 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3985 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3986 field, otherwise as a system register.
3990 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3991 int imple_defined_p
, int pstatefield_p
,
3996 const aarch64_sys_reg
*o
;
4000 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4002 *p
++ = TOLOWER (*q
);
4004 /* Assert that BUF be large enough. */
4005 gas_assert (p
- buf
== q
- *str
);
4007 o
= hash_find (sys_regs
, buf
);
4010 if (!imple_defined_p
)
4014 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4015 unsigned int op0
, op1
, cn
, cm
, op2
;
4017 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4020 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4022 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4029 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4030 as_bad (_("selected processor does not support PSTATE field "
4032 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4033 as_bad (_("selected processor does not support system register "
4035 if (aarch64_sys_reg_deprecated_p (o
))
4036 as_warn (_("system register name '%s' is deprecated and may be "
4037 "removed in a future release"), buf
);
4047 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4048 for the option, or NULL. */
4050 static const aarch64_sys_ins_reg
*
4051 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4055 const aarch64_sys_ins_reg
*o
;
4058 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4060 *p
++ = TOLOWER (*q
);
4063 o
= hash_find (sys_ins_regs
, buf
);
4067 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4068 as_bad (_("selected processor does not support system register "
4075 #define po_char_or_fail(chr) do { \
4076 if (! skip_past_char (&str, chr)) \
4080 #define po_reg_or_fail(regtype) do { \
4081 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4082 if (val == PARSE_FAIL) \
4084 set_default_error (); \
4089 #define po_int_reg_or_fail(reg_type) do { \
4090 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4091 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4093 set_default_error (); \
4096 info->reg.regno = reg->number; \
4097 info->qualifier = qualifier; \
4100 #define po_imm_nc_or_fail() do { \
4101 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4105 #define po_imm_or_fail(min, max) do { \
4106 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4108 if (val < min || val > max) \
4110 set_fatal_syntax_error (_("immediate value out of range "\
4111 #min " to "#max)); \
4116 #define po_enum_or_fail(array) do { \
4117 if (!parse_enum_string (&str, &val, array, \
4118 ARRAY_SIZE (array), imm_reg_type)) \
4122 #define po_misc_or_fail(expr) do { \
4127 /* encode the 12-bit imm field of Add/sub immediate */
4128 static inline uint32_t
4129 encode_addsub_imm (uint32_t imm
)
4134 /* encode the shift amount field of Add/sub immediate */
4135 static inline uint32_t
4136 encode_addsub_imm_shift_amount (uint32_t cnt
)
4142 /* encode the imm field of Adr instruction */
4143 static inline uint32_t
4144 encode_adr_imm (uint32_t imm
)
4146 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4147 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4150 /* encode the immediate field of Move wide immediate */
4151 static inline uint32_t
4152 encode_movw_imm (uint32_t imm
)
4157 /* encode the 26-bit offset of unconditional branch */
4158 static inline uint32_t
4159 encode_branch_ofs_26 (uint32_t ofs
)
4161 return ofs
& ((1 << 26) - 1);
4164 /* encode the 19-bit offset of conditional branch and compare & branch */
4165 static inline uint32_t
4166 encode_cond_branch_ofs_19 (uint32_t ofs
)
4168 return (ofs
& ((1 << 19) - 1)) << 5;
4171 /* encode the 19-bit offset of ld literal */
4172 static inline uint32_t
4173 encode_ld_lit_ofs_19 (uint32_t ofs
)
4175 return (ofs
& ((1 << 19) - 1)) << 5;
4178 /* Encode the 14-bit offset of test & branch. */
4179 static inline uint32_t
4180 encode_tst_branch_ofs_14 (uint32_t ofs
)
4182 return (ofs
& ((1 << 14) - 1)) << 5;
4185 /* Encode the 16-bit imm field of svc/hvc/smc. */
4186 static inline uint32_t
4187 encode_svc_imm (uint32_t imm
)
4192 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4193 static inline uint32_t
4194 reencode_addsub_switch_add_sub (uint32_t opcode
)
4196 return opcode
^ (1 << 30);
4199 static inline uint32_t
4200 reencode_movzn_to_movz (uint32_t opcode
)
4202 return opcode
| (1 << 30);
4205 static inline uint32_t
4206 reencode_movzn_to_movn (uint32_t opcode
)
4208 return opcode
& ~(1 << 30);
4211 /* Overall per-instruction processing. */
4213 /* We need to be able to fix up arbitrary expressions in some statements.
4214 This is so that we can handle symbols that are an arbitrary distance from
4215 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4216 which returns part of an address in a form which will be valid for
4217 a data instruction. We do this by pushing the expression into a symbol
4218 in the expr_section, and creating a fix for that. */
4221 fix_new_aarch64 (fragS
* frag
,
4223 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4233 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4237 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4244 /* Diagnostics on operands errors. */
4246 /* By default, output verbose error message.
4247 Disable the verbose error message by -mno-verbose-error. */
4248 static int verbose_error_p
= 1;
4250 #ifdef DEBUG_AARCH64
4251 /* N.B. this is only for the purpose of debugging. */
4252 const char* operand_mismatch_kind_names
[] =
4255 "AARCH64_OPDE_RECOVERABLE",
4256 "AARCH64_OPDE_SYNTAX_ERROR",
4257 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4258 "AARCH64_OPDE_INVALID_VARIANT",
4259 "AARCH64_OPDE_OUT_OF_RANGE",
4260 "AARCH64_OPDE_UNALIGNED",
4261 "AARCH64_OPDE_REG_LIST",
4262 "AARCH64_OPDE_OTHER_ERROR",
4264 #endif /* DEBUG_AARCH64 */
4266 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4268 When multiple errors of different kinds are found in the same assembly
4269 line, only the error of the highest severity will be picked up for
4270 issuing the diagnostics. */
4272 static inline bfd_boolean
4273 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4274 enum aarch64_operand_error_kind rhs
)
4276 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4277 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4278 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4279 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4280 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4281 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4282 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4283 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4287 /* Helper routine to get the mnemonic name from the assembly instruction
4288 line; should only be called for the diagnosis purpose, as there is
4289 string copy operation involved, which may affect the runtime
4290 performance if used in elsewhere. */
4293 get_mnemonic_name (const char *str
)
4295 static char mnemonic
[32];
4298 /* Get the first 15 bytes and assume that the full name is included. */
4299 strncpy (mnemonic
, str
, 31);
4300 mnemonic
[31] = '\0';
4302 /* Scan up to the end of the mnemonic, which must end in white space,
4303 '.', or end of string. */
4304 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4309 /* Append '...' to the truncated long name. */
4310 if (ptr
- mnemonic
== 31)
4311 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4317 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4319 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4320 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4323 /* Data structures storing one user error in the assembly code related to
4326 struct operand_error_record
4328 const aarch64_opcode
*opcode
;
4329 aarch64_operand_error detail
;
4330 struct operand_error_record
*next
;
4333 typedef struct operand_error_record operand_error_record
;
4335 struct operand_errors
4337 operand_error_record
*head
;
4338 operand_error_record
*tail
;
4341 typedef struct operand_errors operand_errors
;
4343 /* Top-level data structure reporting user errors for the current line of
4345 The way md_assemble works is that all opcodes sharing the same mnemonic
4346 name are iterated to find a match to the assembly line. In this data
4347 structure, each of the such opcodes will have one operand_error_record
4348 allocated and inserted. In other words, excessive errors related with
4349 a single opcode are disregarded. */
4350 operand_errors operand_error_report
;
4352 /* Free record nodes. */
4353 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4355 /* Initialize the data structure that stores the operand mismatch
4356 information on assembling one line of the assembly code. */
4358 init_operand_error_report (void)
4360 if (operand_error_report
.head
!= NULL
)
4362 gas_assert (operand_error_report
.tail
!= NULL
);
4363 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4364 free_opnd_error_record_nodes
= operand_error_report
.head
;
4365 operand_error_report
.head
= NULL
;
4366 operand_error_report
.tail
= NULL
;
4369 gas_assert (operand_error_report
.tail
== NULL
);
4372 /* Return TRUE if some operand error has been recorded during the
4373 parsing of the current assembly line using the opcode *OPCODE;
4374 otherwise return FALSE. */
4375 static inline bfd_boolean
4376 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4378 operand_error_record
*record
= operand_error_report
.head
;
4379 return record
&& record
->opcode
== opcode
;
4382 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4383 OPCODE field is initialized with OPCODE.
4384 N.B. only one record for each opcode, i.e. the maximum of one error is
4385 recorded for each instruction template. */
4388 add_operand_error_record (const operand_error_record
* new_record
)
4390 const aarch64_opcode
*opcode
= new_record
->opcode
;
4391 operand_error_record
* record
= operand_error_report
.head
;
4393 /* The record may have been created for this opcode. If not, we need
4395 if (! opcode_has_operand_error_p (opcode
))
4397 /* Get one empty record. */
4398 if (free_opnd_error_record_nodes
== NULL
)
4400 record
= XNEW (operand_error_record
);
4404 record
= free_opnd_error_record_nodes
;
4405 free_opnd_error_record_nodes
= record
->next
;
4407 record
->opcode
= opcode
;
4408 /* Insert at the head. */
4409 record
->next
= operand_error_report
.head
;
4410 operand_error_report
.head
= record
;
4411 if (operand_error_report
.tail
== NULL
)
4412 operand_error_report
.tail
= record
;
4414 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4415 && record
->detail
.index
<= new_record
->detail
.index
4416 && operand_error_higher_severity_p (record
->detail
.kind
,
4417 new_record
->detail
.kind
))
4419 /* In the case of multiple errors found on operands related with a
4420 single opcode, only record the error of the leftmost operand and
4421 only if the error is of higher severity. */
4422 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4423 " the existing error %s on operand %d",
4424 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4425 new_record
->detail
.index
,
4426 operand_mismatch_kind_names
[record
->detail
.kind
],
4427 record
->detail
.index
);
4431 record
->detail
= new_record
->detail
;
4435 record_operand_error_info (const aarch64_opcode
*opcode
,
4436 aarch64_operand_error
*error_info
)
4438 operand_error_record record
;
4439 record
.opcode
= opcode
;
4440 record
.detail
= *error_info
;
4441 add_operand_error_record (&record
);
4444 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4445 error message *ERROR, for operand IDX (count from 0). */
4448 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4449 enum aarch64_operand_error_kind kind
,
4452 aarch64_operand_error info
;
4453 memset(&info
, 0, sizeof (info
));
4457 info
.non_fatal
= FALSE
;
4458 record_operand_error_info (opcode
, &info
);
4462 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4463 enum aarch64_operand_error_kind kind
,
4464 const char* error
, const int *extra_data
)
4466 aarch64_operand_error info
;
4470 info
.data
[0] = extra_data
[0];
4471 info
.data
[1] = extra_data
[1];
4472 info
.data
[2] = extra_data
[2];
4473 info
.non_fatal
= FALSE
;
4474 record_operand_error_info (opcode
, &info
);
4478 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4479 const char* error
, int lower_bound
,
4482 int data
[3] = {lower_bound
, upper_bound
, 0};
4483 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4487 /* Remove the operand error record for *OPCODE. */
4488 static void ATTRIBUTE_UNUSED
4489 remove_operand_error_record (const aarch64_opcode
*opcode
)
4491 if (opcode_has_operand_error_p (opcode
))
4493 operand_error_record
* record
= operand_error_report
.head
;
4494 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4495 operand_error_report
.head
= record
->next
;
4496 record
->next
= free_opnd_error_record_nodes
;
4497 free_opnd_error_record_nodes
= record
;
4498 if (operand_error_report
.head
== NULL
)
4500 gas_assert (operand_error_report
.tail
== record
);
4501 operand_error_report
.tail
= NULL
;
4506 /* Given the instruction in *INSTR, return the index of the best matched
4507 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4509 Return -1 if there is no qualifier sequence; return the first match
4510 if there is multiple matches found. */
4513 find_best_match (const aarch64_inst
*instr
,
4514 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4516 int i
, num_opnds
, max_num_matched
, idx
;
4518 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4521 DEBUG_TRACE ("no operand");
4525 max_num_matched
= 0;
4528 /* For each pattern. */
4529 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4532 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4534 /* Most opcodes has much fewer patterns in the list. */
4535 if (empty_qualifier_sequence_p (qualifiers
))
4537 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4541 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4542 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4545 if (num_matched
> max_num_matched
)
4547 max_num_matched
= num_matched
;
4552 DEBUG_TRACE ("return with %d", idx
);
4556 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4557 corresponding operands in *INSTR. */
4560 assign_qualifier_sequence (aarch64_inst
*instr
,
4561 const aarch64_opnd_qualifier_t
*qualifiers
)
4564 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4565 gas_assert (num_opnds
);
4566 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4567 instr
->operands
[i
].qualifier
= *qualifiers
;
4570 /* Print operands for the diagnosis purpose. */
4573 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4574 const aarch64_opnd_info
*opnds
)
4578 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4582 /* We regard the opcode operand info more, however we also look into
4583 the inst->operands to support the disassembling of the optional
4585 The two operand code should be the same in all cases, apart from
4586 when the operand can be optional. */
4587 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4588 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4591 /* Generate the operand string in STR. */
4592 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4597 strcat (buf
, i
== 0 ? " " : ", ");
4599 /* Append the operand string. */
4604 /* Send to stderr a string as information. */
4607 output_info (const char *format
, ...)
4613 file
= as_where (&line
);
4617 fprintf (stderr
, "%s:%u: ", file
, line
);
4619 fprintf (stderr
, "%s: ", file
);
4621 fprintf (stderr
, _("Info: "));
4622 va_start (args
, format
);
4623 vfprintf (stderr
, format
, args
);
4625 (void) putc ('\n', stderr
);
4628 /* Output one operand error record. */
4631 output_operand_error_record (const operand_error_record
*record
, char *str
)
4633 const aarch64_operand_error
*detail
= &record
->detail
;
4634 int idx
= detail
->index
;
4635 const aarch64_opcode
*opcode
= record
->opcode
;
4636 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4637 : AARCH64_OPND_NIL
);
4639 typedef void (*handler_t
)(const char *format
, ...);
4640 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4642 switch (detail
->kind
)
4644 case AARCH64_OPDE_NIL
:
4647 case AARCH64_OPDE_SYNTAX_ERROR
:
4648 case AARCH64_OPDE_RECOVERABLE
:
4649 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4650 case AARCH64_OPDE_OTHER_ERROR
:
4651 /* Use the prepared error message if there is, otherwise use the
4652 operand description string to describe the error. */
4653 if (detail
->error
!= NULL
)
4656 handler (_("%s -- `%s'"), detail
->error
, str
);
4658 handler (_("%s at operand %d -- `%s'"),
4659 detail
->error
, idx
+ 1, str
);
4663 gas_assert (idx
>= 0);
4664 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4665 aarch64_get_operand_desc (opd_code
), str
);
4669 case AARCH64_OPDE_INVALID_VARIANT
:
4670 handler (_("operand mismatch -- `%s'"), str
);
4671 if (verbose_error_p
)
4673 /* We will try to correct the erroneous instruction and also provide
4674 more information e.g. all other valid variants.
4676 The string representation of the corrected instruction and other
4677 valid variants are generated by
4679 1) obtaining the intermediate representation of the erroneous
4681 2) manipulating the IR, e.g. replacing the operand qualifier;
4682 3) printing out the instruction by calling the printer functions
4683 shared with the disassembler.
4685 The limitation of this method is that the exact input assembly
4686 line cannot be accurately reproduced in some cases, for example an
4687 optional operand present in the actual assembly line will be
4688 omitted in the output; likewise for the optional syntax rules,
4689 e.g. the # before the immediate. Another limitation is that the
4690 assembly symbols and relocation operations in the assembly line
4691 currently cannot be printed out in the error report. Last but not
4692 least, when there is other error(s) co-exist with this error, the
4693 'corrected' instruction may be still incorrect, e.g. given
4694 'ldnp h0,h1,[x0,#6]!'
4695 this diagnosis will provide the version:
4696 'ldnp s0,s1,[x0,#6]!'
4697 which is still not right. */
4698 size_t len
= strlen (get_mnemonic_name (str
));
4702 aarch64_inst
*inst_base
= &inst
.base
;
4703 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4706 reset_aarch64_instruction (&inst
);
4707 inst_base
->opcode
= opcode
;
4709 /* Reset the error report so that there is no side effect on the
4710 following operand parsing. */
4711 init_operand_error_report ();
4714 result
= parse_operands (str
+ len
, opcode
)
4715 && programmer_friendly_fixup (&inst
);
4716 gas_assert (result
);
4717 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4718 NULL
, NULL
, insn_sequence
);
4719 gas_assert (!result
);
4721 /* Find the most matched qualifier sequence. */
4722 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4723 gas_assert (qlf_idx
> -1);
4725 /* Assign the qualifiers. */
4726 assign_qualifier_sequence (inst_base
,
4727 opcode
->qualifiers_list
[qlf_idx
]);
4729 /* Print the hint. */
4730 output_info (_(" did you mean this?"));
4731 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4732 print_operands (buf
, opcode
, inst_base
->operands
);
4733 output_info (_(" %s"), buf
);
4735 /* Print out other variant(s) if there is any. */
4737 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4738 output_info (_(" other valid variant(s):"));
4740 /* For each pattern. */
4741 qualifiers_list
= opcode
->qualifiers_list
;
4742 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4744 /* Most opcodes has much fewer patterns in the list.
4745 First NIL qualifier indicates the end in the list. */
4746 if (empty_qualifier_sequence_p (*qualifiers_list
))
4751 /* Mnemonics name. */
4752 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4754 /* Assign the qualifiers. */
4755 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4757 /* Print instruction. */
4758 print_operands (buf
, opcode
, inst_base
->operands
);
4760 output_info (_(" %s"), buf
);
4766 case AARCH64_OPDE_UNTIED_OPERAND
:
4767 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4768 detail
->index
+ 1, str
);
4771 case AARCH64_OPDE_OUT_OF_RANGE
:
4772 if (detail
->data
[0] != detail
->data
[1])
4773 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4774 detail
->error
? detail
->error
: _("immediate value"),
4775 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4777 handler (_("%s must be %d at operand %d -- `%s'"),
4778 detail
->error
? detail
->error
: _("immediate value"),
4779 detail
->data
[0], idx
+ 1, str
);
4782 case AARCH64_OPDE_REG_LIST
:
4783 if (detail
->data
[0] == 1)
4784 handler (_("invalid number of registers in the list; "
4785 "only 1 register is expected at operand %d -- `%s'"),
4788 handler (_("invalid number of registers in the list; "
4789 "%d registers are expected at operand %d -- `%s'"),
4790 detail
->data
[0], idx
+ 1, str
);
4793 case AARCH64_OPDE_UNALIGNED
:
4794 handler (_("immediate value must be a multiple of "
4795 "%d at operand %d -- `%s'"),
4796 detail
->data
[0], idx
+ 1, str
);
4805 /* Process and output the error message about the operand mismatching.
4807 When this function is called, the operand error information had
4808 been collected for an assembly line and there will be multiple
4809 errors in the case of multiple instruction templates; output the
4810 error message that most closely describes the problem.
4812 The errors to be printed can be filtered on printing all errors
4813 or only non-fatal errors. This distinction has to be made because
4814 the error buffer may already be filled with fatal errors we don't want to
4815 print due to the different instruction templates. */
4818 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4820 int largest_error_pos
;
4821 const char *msg
= NULL
;
4822 enum aarch64_operand_error_kind kind
;
4823 operand_error_record
*curr
;
4824 operand_error_record
*head
= operand_error_report
.head
;
4825 operand_error_record
*record
= NULL
;
4827 /* No error to report. */
4831 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4833 /* Only one error. */
4834 if (head
== operand_error_report
.tail
)
4836 /* If the only error is a non-fatal one and we don't want to print it,
4838 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4840 DEBUG_TRACE ("single opcode entry with error kind: %s",
4841 operand_mismatch_kind_names
[head
->detail
.kind
]);
4842 output_operand_error_record (head
, str
);
4847 /* Find the error kind of the highest severity. */
4848 DEBUG_TRACE ("multiple opcode entries with error kind");
4849 kind
= AARCH64_OPDE_NIL
;
4850 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4852 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4853 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4854 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4855 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4856 kind
= curr
->detail
.kind
;
4859 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4861 /* Pick up one of errors of KIND to report. */
4862 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4863 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4865 /* If we don't want to print non-fatal errors then don't consider them
4867 if (curr
->detail
.kind
!= kind
4868 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4870 /* If there are multiple errors, pick up the one with the highest
4871 mismatching operand index. In the case of multiple errors with
4872 the equally highest operand index, pick up the first one or the
4873 first one with non-NULL error message. */
4874 if (curr
->detail
.index
> largest_error_pos
4875 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4876 && curr
->detail
.error
!= NULL
))
4878 largest_error_pos
= curr
->detail
.index
;
4880 msg
= record
->detail
.error
;
4884 /* The way errors are collected in the back-end is a bit non-intuitive. But
4885 essentially, because each operand template is tried recursively you may
4886 always have errors collected from the previous tried OPND. These are
4887 usually skipped if there is one successful match. However now with the
4888 non-fatal errors we have to ignore those previously collected hard errors
4889 when we're only interested in printing the non-fatal ones. This condition
4890 prevents us from printing errors that are not appropriate, since we did
4891 match a condition, but it also has warnings that it wants to print. */
4892 if (non_fatal_only
&& !record
)
4895 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4896 DEBUG_TRACE ("Pick up error kind %s to report",
4897 operand_mismatch_kind_names
[record
->detail
.kind
]);
4900 output_operand_error_record (record
, str
);
4903 /* Write an AARCH64 instruction to buf - always little-endian. */
4905 put_aarch64_insn (char *buf
, uint32_t insn
)
4907 unsigned char *where
= (unsigned char *) buf
;
4909 where
[1] = insn
>> 8;
4910 where
[2] = insn
>> 16;
4911 where
[3] = insn
>> 24;
4915 get_aarch64_insn (char *buf
)
4917 unsigned char *where
= (unsigned char *) buf
;
4919 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4924 output_inst (struct aarch64_inst
*new_inst
)
4928 to
= frag_more (INSN_SIZE
);
4930 frag_now
->tc_frag_data
.recorded
= 1;
4932 put_aarch64_insn (to
, inst
.base
.value
);
4934 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4936 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4937 INSN_SIZE
, &inst
.reloc
.exp
,
4940 DEBUG_TRACE ("Prepared relocation fix up");
4941 /* Don't check the addend value against the instruction size,
4942 that's the job of our code in md_apply_fix(). */
4943 fixp
->fx_no_overflow
= 1;
4944 if (new_inst
!= NULL
)
4945 fixp
->tc_fix_data
.inst
= new_inst
;
4946 if (aarch64_gas_internal_fixup_p ())
4948 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4949 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4950 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4954 dwarf2_emit_insn (INSN_SIZE
);
4957 /* Link together opcodes of the same name. */
4961 aarch64_opcode
*opcode
;
4962 struct templates
*next
;
4965 typedef struct templates templates
;
4968 lookup_mnemonic (const char *start
, int len
)
4970 templates
*templ
= NULL
;
4972 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4976 /* Subroutine of md_assemble, responsible for looking up the primary
4977 opcode from the mnemonic the user wrote. STR points to the
4978 beginning of the mnemonic. */
4981 opcode_lookup (char **str
)
4983 char *end
, *base
, *dot
;
4984 const aarch64_cond
*cond
;
4988 /* Scan up to the end of the mnemonic, which must end in white space,
4989 '.', or end of string. */
4991 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4992 if (*end
== '.' && !dot
)
4995 if (end
== base
|| dot
== base
)
4998 inst
.cond
= COND_ALWAYS
;
5000 /* Handle a possible condition. */
5003 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5006 inst
.cond
= cond
->value
;
5022 if (inst
.cond
== COND_ALWAYS
)
5024 /* Look for unaffixed mnemonic. */
5025 return lookup_mnemonic (base
, len
);
5029 /* append ".c" to mnemonic if conditional */
5030 memcpy (condname
, base
, len
);
5031 memcpy (condname
+ len
, ".c", 2);
5034 return lookup_mnemonic (base
, len
);
5040 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5041 to a corresponding operand qualifier. */
5043 static inline aarch64_opnd_qualifier_t
5044 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5046 /* Element size in bytes indexed by vector_el_type. */
5047 const unsigned char ele_size
[5]
5049 const unsigned int ele_base
[5] =
5051 AARCH64_OPND_QLF_V_4B
,
5052 AARCH64_OPND_QLF_V_2H
,
5053 AARCH64_OPND_QLF_V_2S
,
5054 AARCH64_OPND_QLF_V_1D
,
5055 AARCH64_OPND_QLF_V_1Q
5058 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5059 goto vectype_conversion_fail
;
5061 if (vectype
->type
== NT_zero
)
5062 return AARCH64_OPND_QLF_P_Z
;
5063 if (vectype
->type
== NT_merge
)
5064 return AARCH64_OPND_QLF_P_M
;
5066 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5068 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5070 /* Special case S_4B. */
5071 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5072 return AARCH64_OPND_QLF_S_4B
;
5074 /* Vector element register. */
5075 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5079 /* Vector register. */
5080 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5083 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5084 goto vectype_conversion_fail
;
5086 /* The conversion is by calculating the offset from the base operand
5087 qualifier for the vector type. The operand qualifiers are regular
5088 enough that the offset can established by shifting the vector width by
5089 a vector-type dependent amount. */
5091 if (vectype
->type
== NT_b
)
5093 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5095 else if (vectype
->type
>= NT_d
)
5100 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5101 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5102 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5106 vectype_conversion_fail
:
5107 first_error (_("bad vector arrangement type"));
5108 return AARCH64_OPND_QLF_NIL
;
5111 /* Process an optional operand that is found omitted from the assembly line.
5112 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5113 instruction's opcode entry while IDX is the index of this omitted operand.
5117 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5118 int idx
, aarch64_opnd_info
*operand
)
5120 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5121 gas_assert (optional_operand_p (opcode
, idx
));
5122 gas_assert (!operand
->present
);
5126 case AARCH64_OPND_Rd
:
5127 case AARCH64_OPND_Rn
:
5128 case AARCH64_OPND_Rm
:
5129 case AARCH64_OPND_Rt
:
5130 case AARCH64_OPND_Rt2
:
5131 case AARCH64_OPND_Rs
:
5132 case AARCH64_OPND_Ra
:
5133 case AARCH64_OPND_Rt_SYS
:
5134 case AARCH64_OPND_Rd_SP
:
5135 case AARCH64_OPND_Rn_SP
:
5136 case AARCH64_OPND_Rm_SP
:
5137 case AARCH64_OPND_Fd
:
5138 case AARCH64_OPND_Fn
:
5139 case AARCH64_OPND_Fm
:
5140 case AARCH64_OPND_Fa
:
5141 case AARCH64_OPND_Ft
:
5142 case AARCH64_OPND_Ft2
:
5143 case AARCH64_OPND_Sd
:
5144 case AARCH64_OPND_Sn
:
5145 case AARCH64_OPND_Sm
:
5146 case AARCH64_OPND_Va
:
5147 case AARCH64_OPND_Vd
:
5148 case AARCH64_OPND_Vn
:
5149 case AARCH64_OPND_Vm
:
5150 case AARCH64_OPND_VdD1
:
5151 case AARCH64_OPND_VnD1
:
5152 operand
->reg
.regno
= default_value
;
5155 case AARCH64_OPND_Ed
:
5156 case AARCH64_OPND_En
:
5157 case AARCH64_OPND_Em
:
5158 case AARCH64_OPND_Em16
:
5159 case AARCH64_OPND_SM3_IMM2
:
5160 operand
->reglane
.regno
= default_value
;
5163 case AARCH64_OPND_IDX
:
5164 case AARCH64_OPND_BIT_NUM
:
5165 case AARCH64_OPND_IMMR
:
5166 case AARCH64_OPND_IMMS
:
5167 case AARCH64_OPND_SHLL_IMM
:
5168 case AARCH64_OPND_IMM_VLSL
:
5169 case AARCH64_OPND_IMM_VLSR
:
5170 case AARCH64_OPND_CCMP_IMM
:
5171 case AARCH64_OPND_FBITS
:
5172 case AARCH64_OPND_UIMM4
:
5173 case AARCH64_OPND_UIMM3_OP1
:
5174 case AARCH64_OPND_UIMM3_OP2
:
5175 case AARCH64_OPND_IMM
:
5176 case AARCH64_OPND_IMM_2
:
5177 case AARCH64_OPND_WIDTH
:
5178 case AARCH64_OPND_UIMM7
:
5179 case AARCH64_OPND_NZCV
:
5180 case AARCH64_OPND_SVE_PATTERN
:
5181 case AARCH64_OPND_SVE_PRFOP
:
5182 operand
->imm
.value
= default_value
;
5185 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5186 operand
->imm
.value
= default_value
;
5187 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5188 operand
->shifter
.amount
= 1;
5191 case AARCH64_OPND_EXCEPTION
:
5192 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5195 case AARCH64_OPND_BARRIER_ISB
:
5196 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5199 case AARCH64_OPND_BTI_TARGET
:
5200 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5208 /* Process the relocation type for move wide instructions.
5209 Return TRUE on success; otherwise return FALSE. */
5212 process_movw_reloc_info (void)
5217 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5219 if (inst
.base
.opcode
->op
== OP_MOVK
)
5220 switch (inst
.reloc
.type
)
5222 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5223 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5224 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5225 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5226 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5227 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5228 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5229 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5230 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5231 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5232 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5234 (_("the specified relocation type is not allowed for MOVK"));
5240 switch (inst
.reloc
.type
)
5242 case BFD_RELOC_AARCH64_MOVW_G0
:
5243 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5244 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5245 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5246 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5247 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5248 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5249 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5250 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5251 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5252 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5253 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5254 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5257 case BFD_RELOC_AARCH64_MOVW_G1
:
5258 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5259 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5260 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5261 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5262 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5263 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5264 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5265 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5266 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5267 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5268 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5269 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5272 case BFD_RELOC_AARCH64_MOVW_G2
:
5273 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5274 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5275 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5276 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5277 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5278 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5281 set_fatal_syntax_error
5282 (_("the specified relocation type is not allowed for 32-bit "
5288 case BFD_RELOC_AARCH64_MOVW_G3
:
5289 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5292 set_fatal_syntax_error
5293 (_("the specified relocation type is not allowed for 32-bit "
5300 /* More cases should be added when more MOVW-related relocation types
5301 are supported in GAS. */
5302 gas_assert (aarch64_gas_internal_fixup_p ());
5303 /* The shift amount should have already been set by the parser. */
5306 inst
.base
.operands
[1].shifter
.amount
= shift
;
5310 /* A primitive log calculator. */
5312 static inline unsigned int
5313 get_logsz (unsigned int size
)
5315 const unsigned char ls
[16] =
5316 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5322 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5323 return ls
[size
- 1];
5326 /* Determine and return the real reloc type code for an instruction
5327 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5329 static inline bfd_reloc_code_real_type
5330 ldst_lo12_determine_real_reloc_type (void)
5333 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5334 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5336 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5338 BFD_RELOC_AARCH64_LDST8_LO12
,
5339 BFD_RELOC_AARCH64_LDST16_LO12
,
5340 BFD_RELOC_AARCH64_LDST32_LO12
,
5341 BFD_RELOC_AARCH64_LDST64_LO12
,
5342 BFD_RELOC_AARCH64_LDST128_LO12
5345 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5346 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5347 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5348 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5349 BFD_RELOC_AARCH64_NONE
5352 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5353 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5354 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5355 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5356 BFD_RELOC_AARCH64_NONE
5359 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5360 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5361 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5362 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5363 BFD_RELOC_AARCH64_NONE
5366 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5367 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5368 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5369 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5370 BFD_RELOC_AARCH64_NONE
5374 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5375 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5377 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5379 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5381 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5382 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5384 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5386 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5388 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5390 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5391 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5392 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5393 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5394 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5395 gas_assert (logsz
<= 3);
5397 gas_assert (logsz
<= 4);
5399 /* In reloc.c, these pseudo relocation types should be defined in similar
5400 order as above reloc_ldst_lo12 array. Because the array index calculation
5401 below relies on this. */
5402 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5405 /* Check whether a register list REGINFO is valid. The registers must be
5406 numbered in increasing order (modulo 32), in increments of one or two.
5408 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5411 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5414 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5416 uint32_t i
, nb_regs
, prev_regno
, incr
;
5418 nb_regs
= 1 + (reginfo
& 0x3);
5420 prev_regno
= reginfo
& 0x1f;
5421 incr
= accept_alternate
? 2 : 1;
5423 for (i
= 1; i
< nb_regs
; ++i
)
5425 uint32_t curr_regno
;
5427 curr_regno
= reginfo
& 0x1f;
5428 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5430 prev_regno
= curr_regno
;
5436 /* Generic instruction operand parser. This does no encoding and no
5437 semantic validation; it merely squirrels values away in the inst
5438 structure. Returns TRUE or FALSE depending on whether the
5439 specified grammar matched. */
5442 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5445 char *backtrack_pos
= 0;
5446 const enum aarch64_opnd
*operands
= opcode
->operands
;
5447 aarch64_reg_type imm_reg_type
;
5450 skip_whitespace (str
);
5452 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5453 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5455 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5457 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5460 const reg_entry
*reg
;
5461 int comma_skipped_p
= 0;
5462 aarch64_reg_type rtype
;
5463 struct vector_type_el vectype
;
5464 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5465 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5466 aarch64_reg_type reg_type
;
5468 DEBUG_TRACE ("parse operand %d", i
);
5470 /* Assign the operand code. */
5471 info
->type
= operands
[i
];
5473 if (optional_operand_p (opcode
, i
))
5475 /* Remember where we are in case we need to backtrack. */
5476 gas_assert (!backtrack_pos
);
5477 backtrack_pos
= str
;
5480 /* Expect comma between operands; the backtrack mechanism will take
5481 care of cases of omitted optional operand. */
5482 if (i
> 0 && ! skip_past_char (&str
, ','))
5484 set_syntax_error (_("comma expected between operands"));
5488 comma_skipped_p
= 1;
5490 switch (operands
[i
])
5492 case AARCH64_OPND_Rd
:
5493 case AARCH64_OPND_Rn
:
5494 case AARCH64_OPND_Rm
:
5495 case AARCH64_OPND_Rt
:
5496 case AARCH64_OPND_Rt2
:
5497 case AARCH64_OPND_Rs
:
5498 case AARCH64_OPND_Ra
:
5499 case AARCH64_OPND_Rt_SYS
:
5500 case AARCH64_OPND_PAIRREG
:
5501 case AARCH64_OPND_SVE_Rm
:
5502 po_int_reg_or_fail (REG_TYPE_R_Z
);
5505 case AARCH64_OPND_Rd_SP
:
5506 case AARCH64_OPND_Rn_SP
:
5507 case AARCH64_OPND_SVE_Rn_SP
:
5508 case AARCH64_OPND_Rm_SP
:
5509 po_int_reg_or_fail (REG_TYPE_R_SP
);
5512 case AARCH64_OPND_Rm_EXT
:
5513 case AARCH64_OPND_Rm_SFT
:
5514 po_misc_or_fail (parse_shifter_operand
5515 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5517 : SHIFTED_LOGIC_IMM
)));
5518 if (!info
->shifter
.operator_present
)
5520 /* Default to LSL if not present. Libopcodes prefers shifter
5521 kind to be explicit. */
5522 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5523 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5524 /* For Rm_EXT, libopcodes will carry out further check on whether
5525 or not stack pointer is used in the instruction (Recall that
5526 "the extend operator is not optional unless at least one of
5527 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5531 case AARCH64_OPND_Fd
:
5532 case AARCH64_OPND_Fn
:
5533 case AARCH64_OPND_Fm
:
5534 case AARCH64_OPND_Fa
:
5535 case AARCH64_OPND_Ft
:
5536 case AARCH64_OPND_Ft2
:
5537 case AARCH64_OPND_Sd
:
5538 case AARCH64_OPND_Sn
:
5539 case AARCH64_OPND_Sm
:
5540 case AARCH64_OPND_SVE_VZn
:
5541 case AARCH64_OPND_SVE_Vd
:
5542 case AARCH64_OPND_SVE_Vm
:
5543 case AARCH64_OPND_SVE_Vn
:
5544 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5545 if (val
== PARSE_FAIL
)
5547 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5550 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5552 info
->reg
.regno
= val
;
5553 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5556 case AARCH64_OPND_SVE_Pd
:
5557 case AARCH64_OPND_SVE_Pg3
:
5558 case AARCH64_OPND_SVE_Pg4_5
:
5559 case AARCH64_OPND_SVE_Pg4_10
:
5560 case AARCH64_OPND_SVE_Pg4_16
:
5561 case AARCH64_OPND_SVE_Pm
:
5562 case AARCH64_OPND_SVE_Pn
:
5563 case AARCH64_OPND_SVE_Pt
:
5564 reg_type
= REG_TYPE_PN
;
5567 case AARCH64_OPND_SVE_Za_5
:
5568 case AARCH64_OPND_SVE_Za_16
:
5569 case AARCH64_OPND_SVE_Zd
:
5570 case AARCH64_OPND_SVE_Zm_5
:
5571 case AARCH64_OPND_SVE_Zm_16
:
5572 case AARCH64_OPND_SVE_Zn
:
5573 case AARCH64_OPND_SVE_Zt
:
5574 reg_type
= REG_TYPE_ZN
;
5577 case AARCH64_OPND_Va
:
5578 case AARCH64_OPND_Vd
:
5579 case AARCH64_OPND_Vn
:
5580 case AARCH64_OPND_Vm
:
5581 reg_type
= REG_TYPE_VN
;
5583 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5584 if (val
== PARSE_FAIL
)
5586 first_error (_(get_reg_expected_msg (reg_type
)));
5589 if (vectype
.defined
& NTA_HASINDEX
)
5592 info
->reg
.regno
= val
;
5593 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5594 && vectype
.type
== NT_invtype
)
5595 /* Unqualified Pn and Zn registers are allowed in certain
5596 contexts. Rely on F_STRICT qualifier checking to catch
5598 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5601 info
->qualifier
= vectype_to_qualifier (&vectype
);
5602 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5607 case AARCH64_OPND_VdD1
:
5608 case AARCH64_OPND_VnD1
:
5609 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5610 if (val
== PARSE_FAIL
)
5612 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5615 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5617 set_fatal_syntax_error
5618 (_("the top half of a 128-bit FP/SIMD register is expected"));
5621 info
->reg
.regno
= val
;
5622 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5623 here; it is correct for the purpose of encoding/decoding since
5624 only the register number is explicitly encoded in the related
5625 instructions, although this appears a bit hacky. */
5626 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5629 case AARCH64_OPND_SVE_Zm3_INDEX
:
5630 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5631 case AARCH64_OPND_SVE_Zm4_INDEX
:
5632 case AARCH64_OPND_SVE_Zn_INDEX
:
5633 reg_type
= REG_TYPE_ZN
;
5634 goto vector_reg_index
;
5636 case AARCH64_OPND_Ed
:
5637 case AARCH64_OPND_En
:
5638 case AARCH64_OPND_Em
:
5639 case AARCH64_OPND_Em16
:
5640 case AARCH64_OPND_SM3_IMM2
:
5641 reg_type
= REG_TYPE_VN
;
5643 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5644 if (val
== PARSE_FAIL
)
5646 first_error (_(get_reg_expected_msg (reg_type
)));
5649 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5652 info
->reglane
.regno
= val
;
5653 info
->reglane
.index
= vectype
.index
;
5654 info
->qualifier
= vectype_to_qualifier (&vectype
);
5655 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5659 case AARCH64_OPND_SVE_ZnxN
:
5660 case AARCH64_OPND_SVE_ZtxN
:
5661 reg_type
= REG_TYPE_ZN
;
5662 goto vector_reg_list
;
5664 case AARCH64_OPND_LVn
:
5665 case AARCH64_OPND_LVt
:
5666 case AARCH64_OPND_LVt_AL
:
5667 case AARCH64_OPND_LEt
:
5668 reg_type
= REG_TYPE_VN
;
5670 if (reg_type
== REG_TYPE_ZN
5671 && get_opcode_dependent_value (opcode
) == 1
5674 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5675 if (val
== PARSE_FAIL
)
5677 first_error (_(get_reg_expected_msg (reg_type
)));
5680 info
->reglist
.first_regno
= val
;
5681 info
->reglist
.num_regs
= 1;
5685 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5686 if (val
== PARSE_FAIL
)
5688 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5690 set_fatal_syntax_error (_("invalid register list"));
5693 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5694 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5696 if (operands
[i
] == AARCH64_OPND_LEt
)
5698 if (!(vectype
.defined
& NTA_HASINDEX
))
5700 info
->reglist
.has_index
= 1;
5701 info
->reglist
.index
= vectype
.index
;
5705 if (vectype
.defined
& NTA_HASINDEX
)
5707 if (!(vectype
.defined
& NTA_HASTYPE
))
5709 if (reg_type
== REG_TYPE_ZN
)
5710 set_fatal_syntax_error (_("missing type suffix"));
5714 info
->qualifier
= vectype_to_qualifier (&vectype
);
5715 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5719 case AARCH64_OPND_CRn
:
5720 case AARCH64_OPND_CRm
:
5722 char prefix
= *(str
++);
5723 if (prefix
!= 'c' && prefix
!= 'C')
5726 po_imm_nc_or_fail ();
5729 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5732 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5733 info
->imm
.value
= val
;
5737 case AARCH64_OPND_SHLL_IMM
:
5738 case AARCH64_OPND_IMM_VLSR
:
5739 po_imm_or_fail (1, 64);
5740 info
->imm
.value
= val
;
5743 case AARCH64_OPND_CCMP_IMM
:
5744 case AARCH64_OPND_SIMM5
:
5745 case AARCH64_OPND_FBITS
:
5746 case AARCH64_OPND_UIMM4
:
5747 case AARCH64_OPND_UIMM4_ADDG
:
5748 case AARCH64_OPND_UIMM10
:
5749 case AARCH64_OPND_UIMM3_OP1
:
5750 case AARCH64_OPND_UIMM3_OP2
:
5751 case AARCH64_OPND_IMM_VLSL
:
5752 case AARCH64_OPND_IMM
:
5753 case AARCH64_OPND_IMM_2
:
5754 case AARCH64_OPND_WIDTH
:
5755 case AARCH64_OPND_SVE_INV_LIMM
:
5756 case AARCH64_OPND_SVE_LIMM
:
5757 case AARCH64_OPND_SVE_LIMM_MOV
:
5758 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5759 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5760 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5761 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5762 case AARCH64_OPND_SVE_SIMM5
:
5763 case AARCH64_OPND_SVE_SIMM5B
:
5764 case AARCH64_OPND_SVE_SIMM6
:
5765 case AARCH64_OPND_SVE_SIMM8
:
5766 case AARCH64_OPND_SVE_UIMM3
:
5767 case AARCH64_OPND_SVE_UIMM7
:
5768 case AARCH64_OPND_SVE_UIMM8
:
5769 case AARCH64_OPND_SVE_UIMM8_53
:
5770 case AARCH64_OPND_IMM_ROT1
:
5771 case AARCH64_OPND_IMM_ROT2
:
5772 case AARCH64_OPND_IMM_ROT3
:
5773 case AARCH64_OPND_SVE_IMM_ROT1
:
5774 case AARCH64_OPND_SVE_IMM_ROT2
:
5775 po_imm_nc_or_fail ();
5776 info
->imm
.value
= val
;
5779 case AARCH64_OPND_SVE_AIMM
:
5780 case AARCH64_OPND_SVE_ASIMM
:
5781 po_imm_nc_or_fail ();
5782 info
->imm
.value
= val
;
5783 skip_whitespace (str
);
5784 if (skip_past_comma (&str
))
5785 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5787 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5790 case AARCH64_OPND_SVE_PATTERN
:
5791 po_enum_or_fail (aarch64_sve_pattern_array
);
5792 info
->imm
.value
= val
;
5795 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5796 po_enum_or_fail (aarch64_sve_pattern_array
);
5797 info
->imm
.value
= val
;
5798 if (skip_past_comma (&str
)
5799 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5801 if (!info
->shifter
.operator_present
)
5803 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5804 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5805 info
->shifter
.amount
= 1;
5809 case AARCH64_OPND_SVE_PRFOP
:
5810 po_enum_or_fail (aarch64_sve_prfop_array
);
5811 info
->imm
.value
= val
;
5814 case AARCH64_OPND_UIMM7
:
5815 po_imm_or_fail (0, 127);
5816 info
->imm
.value
= val
;
5819 case AARCH64_OPND_IDX
:
5820 case AARCH64_OPND_MASK
:
5821 case AARCH64_OPND_BIT_NUM
:
5822 case AARCH64_OPND_IMMR
:
5823 case AARCH64_OPND_IMMS
:
5824 po_imm_or_fail (0, 63);
5825 info
->imm
.value
= val
;
5828 case AARCH64_OPND_IMM0
:
5829 po_imm_nc_or_fail ();
5832 set_fatal_syntax_error (_("immediate zero expected"));
5835 info
->imm
.value
= 0;
5838 case AARCH64_OPND_FPIMM0
:
5841 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5842 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5843 it is probably not worth the effort to support it. */
5844 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5847 || !(res2
= parse_constant_immediate (&str
, &val
,
5850 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5852 info
->imm
.value
= 0;
5853 info
->imm
.is_fp
= 1;
5856 set_fatal_syntax_error (_("immediate zero expected"));
5860 case AARCH64_OPND_IMM_MOV
:
5863 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5864 reg_name_p (str
, REG_TYPE_VN
))
5867 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5869 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5870 later. fix_mov_imm_insn will try to determine a machine
5871 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5872 message if the immediate cannot be moved by a single
5874 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5875 inst
.base
.operands
[i
].skip
= 1;
5879 case AARCH64_OPND_SIMD_IMM
:
5880 case AARCH64_OPND_SIMD_IMM_SFT
:
5881 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5883 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5885 /* need_libopcodes_p */ 1,
5888 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5889 shift, we don't check it here; we leave the checking to
5890 the libopcodes (operand_general_constraint_met_p). By
5891 doing this, we achieve better diagnostics. */
5892 if (skip_past_comma (&str
)
5893 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5895 if (!info
->shifter
.operator_present
5896 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5898 /* Default to LSL if not present. Libopcodes prefers shifter
5899 kind to be explicit. */
5900 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5901 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5905 case AARCH64_OPND_FPIMM
:
5906 case AARCH64_OPND_SIMD_FPIMM
:
5907 case AARCH64_OPND_SVE_FPIMM8
:
5912 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5913 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5914 || !aarch64_imm_float_p (qfloat
))
5917 set_fatal_syntax_error (_("invalid floating-point"
5921 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5922 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5926 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5927 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5928 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5933 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5934 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5937 set_fatal_syntax_error (_("invalid floating-point"
5941 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5942 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5946 case AARCH64_OPND_LIMM
:
5947 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5948 SHIFTED_LOGIC_IMM
));
5949 if (info
->shifter
.operator_present
)
5951 set_fatal_syntax_error
5952 (_("shift not allowed for bitmask immediate"));
5955 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5957 /* need_libopcodes_p */ 1,
5961 case AARCH64_OPND_AIMM
:
5962 if (opcode
->op
== OP_ADD
)
5963 /* ADD may have relocation types. */
5964 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5965 SHIFTED_ARITH_IMM
));
5967 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5968 SHIFTED_ARITH_IMM
));
5969 switch (inst
.reloc
.type
)
5971 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5972 info
->shifter
.amount
= 12;
5974 case BFD_RELOC_UNUSED
:
5975 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5976 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5977 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5978 inst
.reloc
.pc_rel
= 0;
5983 info
->imm
.value
= 0;
5984 if (!info
->shifter
.operator_present
)
5986 /* Default to LSL if not present. Libopcodes prefers shifter
5987 kind to be explicit. */
5988 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5989 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5993 case AARCH64_OPND_HALF
:
5995 /* #<imm16> or relocation. */
5996 int internal_fixup_p
;
5997 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5998 if (internal_fixup_p
)
5999 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6000 skip_whitespace (str
);
6001 if (skip_past_comma (&str
))
6003 /* {, LSL #<shift>} */
6004 if (! aarch64_gas_internal_fixup_p ())
6006 set_fatal_syntax_error (_("can't mix relocation modifier "
6007 "with explicit shift"));
6010 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6013 inst
.base
.operands
[i
].shifter
.amount
= 0;
6014 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6015 inst
.base
.operands
[i
].imm
.value
= 0;
6016 if (! process_movw_reloc_info ())
6021 case AARCH64_OPND_EXCEPTION
:
6022 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6024 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6026 /* need_libopcodes_p */ 0,
6030 case AARCH64_OPND_NZCV
:
6032 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6036 info
->imm
.value
= nzcv
->value
;
6039 po_imm_or_fail (0, 15);
6040 info
->imm
.value
= val
;
6044 case AARCH64_OPND_COND
:
6045 case AARCH64_OPND_COND1
:
6050 while (ISALPHA (*str
));
6051 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6052 if (info
->cond
== NULL
)
6054 set_syntax_error (_("invalid condition"));
6057 else if (operands
[i
] == AARCH64_OPND_COND1
6058 && (info
->cond
->value
& 0xe) == 0xe)
6060 /* Do not allow AL or NV. */
6061 set_default_error ();
6067 case AARCH64_OPND_ADDR_ADRP
:
6068 po_misc_or_fail (parse_adrp (&str
));
6069 /* Clear the value as operand needs to be relocated. */
6070 info
->imm
.value
= 0;
6073 case AARCH64_OPND_ADDR_PCREL14
:
6074 case AARCH64_OPND_ADDR_PCREL19
:
6075 case AARCH64_OPND_ADDR_PCREL21
:
6076 case AARCH64_OPND_ADDR_PCREL26
:
6077 po_misc_or_fail (parse_address (&str
, info
));
6078 if (!info
->addr
.pcrel
)
6080 set_syntax_error (_("invalid pc-relative address"));
6083 if (inst
.gen_lit_pool
6084 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6086 /* Only permit "=value" in the literal load instructions.
6087 The literal will be generated by programmer_friendly_fixup. */
6088 set_syntax_error (_("invalid use of \"=immediate\""));
6091 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6093 set_syntax_error (_("unrecognized relocation suffix"));
6096 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6098 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6099 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6103 info
->imm
.value
= 0;
6104 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6105 switch (opcode
->iclass
)
6109 /* e.g. CBZ or B.COND */
6110 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6111 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6115 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6116 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6120 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6122 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6123 : BFD_RELOC_AARCH64_JUMP26
;
6126 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6127 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6130 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6131 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6137 inst
.reloc
.pc_rel
= 1;
6141 case AARCH64_OPND_ADDR_SIMPLE
:
6142 case AARCH64_OPND_ADDR_SIMPLE_2
:
6143 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6145 /* [<Xn|SP>{, #<simm>}] */
6147 /* First use the normal address-parsing routines, to get
6148 the usual syntax errors. */
6149 po_misc_or_fail (parse_address (&str
, info
));
6150 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6151 || !info
->addr
.preind
|| info
->addr
.postind
6152 || (info
->addr
.writeback
6153 && operands
[i
] != AARCH64_OPND_ADDR_SIMPLE_2
))
6155 set_syntax_error (_("invalid addressing mode"));
6159 /* Then retry, matching the specific syntax of these addresses. */
6161 po_char_or_fail ('[');
6162 po_reg_or_fail (REG_TYPE_R64_SP
);
6163 /* Accept optional ", #0". */
6164 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6165 && skip_past_char (&str
, ','))
6167 skip_past_char (&str
, '#');
6168 if (! skip_past_char (&str
, '0'))
6170 set_fatal_syntax_error
6171 (_("the optional immediate offset can only be 0"));
6175 po_char_or_fail (']');
6176 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE_2
)
6177 po_char_or_fail ('!');
6181 case AARCH64_OPND_ADDR_REGOFF
:
6182 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6183 po_misc_or_fail (parse_address (&str
, info
));
6185 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6186 || !info
->addr
.preind
|| info
->addr
.postind
6187 || info
->addr
.writeback
)
6189 set_syntax_error (_("invalid addressing mode"));
6192 if (!info
->shifter
.operator_present
)
6194 /* Default to LSL if not present. Libopcodes prefers shifter
6195 kind to be explicit. */
6196 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6197 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6199 /* Qualifier to be deduced by libopcodes. */
6202 case AARCH64_OPND_ADDR_SIMM7
:
6203 po_misc_or_fail (parse_address (&str
, info
));
6204 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6205 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6207 set_syntax_error (_("invalid addressing mode"));
6210 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6212 set_syntax_error (_("relocation not allowed"));
6215 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6217 /* need_libopcodes_p */ 1,
6221 case AARCH64_OPND_ADDR_SIMM9
:
6222 case AARCH64_OPND_ADDR_SIMM9_2
:
6223 case AARCH64_OPND_ADDR_SIMM11
:
6224 case AARCH64_OPND_ADDR_SIMM13
:
6225 po_misc_or_fail (parse_address (&str
, info
));
6226 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6227 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6228 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6229 && info
->addr
.writeback
))
6231 set_syntax_error (_("invalid addressing mode"));
6234 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6236 set_syntax_error (_("relocation not allowed"));
6239 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6241 /* need_libopcodes_p */ 1,
6245 case AARCH64_OPND_ADDR_SIMM10
:
6246 case AARCH64_OPND_ADDR_OFFSET
:
6247 po_misc_or_fail (parse_address (&str
, info
));
6248 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6249 || !info
->addr
.preind
|| info
->addr
.postind
)
6251 set_syntax_error (_("invalid addressing mode"));
6254 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6256 set_syntax_error (_("relocation not allowed"));
6259 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6261 /* need_libopcodes_p */ 1,
6265 case AARCH64_OPND_ADDR_UIMM12
:
6266 po_misc_or_fail (parse_address (&str
, info
));
6267 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6268 || !info
->addr
.preind
|| info
->addr
.writeback
)
6270 set_syntax_error (_("invalid addressing mode"));
6273 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6274 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6275 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6277 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6279 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6281 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6283 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6284 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6285 /* Leave qualifier to be determined by libopcodes. */
6288 case AARCH64_OPND_SIMD_ADDR_POST
:
6289 /* [<Xn|SP>], <Xm|#<amount>> */
6290 po_misc_or_fail (parse_address (&str
, info
));
6291 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6293 set_syntax_error (_("invalid addressing mode"));
6296 if (!info
->addr
.offset
.is_reg
)
6298 if (inst
.reloc
.exp
.X_op
== O_constant
)
6299 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6302 set_fatal_syntax_error
6303 (_("writeback value must be an immediate constant"));
6310 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6311 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6312 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6313 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6314 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6315 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6316 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6317 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6318 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6319 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6320 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6321 /* [X<n>{, #imm, MUL VL}]
6323 but recognizing SVE registers. */
6324 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6325 &offset_qualifier
));
6326 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6328 set_syntax_error (_("invalid addressing mode"));
6332 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6333 || !info
->addr
.preind
|| info
->addr
.writeback
)
6335 set_syntax_error (_("invalid addressing mode"));
6338 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6339 || inst
.reloc
.exp
.X_op
!= O_constant
)
6341 /* Make sure this has priority over
6342 "invalid addressing mode". */
6343 set_fatal_syntax_error (_("constant offset required"));
6346 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6349 case AARCH64_OPND_SVE_ADDR_R
:
6350 /* [<Xn|SP>{, <R><m>}]
6351 but recognizing SVE registers. */
6352 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6353 &offset_qualifier
));
6354 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6356 offset_qualifier
= AARCH64_OPND_QLF_X
;
6357 info
->addr
.offset
.is_reg
= 1;
6358 info
->addr
.offset
.regno
= 31;
6360 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6361 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6363 set_syntax_error (_("invalid addressing mode"));
6368 case AARCH64_OPND_SVE_ADDR_RR
:
6369 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6370 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6371 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6372 case AARCH64_OPND_SVE_ADDR_RX
:
6373 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6374 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6375 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6376 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6377 but recognizing SVE registers. */
6378 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6379 &offset_qualifier
));
6380 if (base_qualifier
!= AARCH64_OPND_QLF_X
6381 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6383 set_syntax_error (_("invalid addressing mode"));
6388 case AARCH64_OPND_SVE_ADDR_RZ
:
6389 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6390 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6391 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6392 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6393 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6394 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6395 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6396 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6397 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6398 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6399 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6400 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6401 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6402 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6403 &offset_qualifier
));
6404 if (base_qualifier
!= AARCH64_OPND_QLF_X
6405 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6406 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6408 set_syntax_error (_("invalid addressing mode"));
6411 info
->qualifier
= offset_qualifier
;
6414 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6415 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6416 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6417 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6418 /* [Z<n>.<T>{, #imm}] */
6419 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6420 &offset_qualifier
));
6421 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6422 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6424 set_syntax_error (_("invalid addressing mode"));
6427 info
->qualifier
= base_qualifier
;
6430 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6431 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6432 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6433 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6434 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6438 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6440 here since we get better error messages by leaving it to
6441 the qualifier checking routines. */
6442 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6443 &offset_qualifier
));
6444 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6445 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6446 || offset_qualifier
!= base_qualifier
)
6448 set_syntax_error (_("invalid addressing mode"));
6451 info
->qualifier
= base_qualifier
;
6454 case AARCH64_OPND_SYSREG
:
6456 uint32_t sysreg_flags
;
6457 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6458 &sysreg_flags
)) == PARSE_FAIL
)
6460 set_syntax_error (_("unknown or missing system register name"));
6463 inst
.base
.operands
[i
].sysreg
.value
= val
;
6464 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6468 case AARCH64_OPND_PSTATEFIELD
:
6469 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6472 set_syntax_error (_("unknown or missing PSTATE field name"));
6475 inst
.base
.operands
[i
].pstatefield
= val
;
6478 case AARCH64_OPND_SYSREG_IC
:
6479 inst
.base
.operands
[i
].sysins_op
=
6480 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6483 case AARCH64_OPND_SYSREG_DC
:
6484 inst
.base
.operands
[i
].sysins_op
=
6485 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6488 case AARCH64_OPND_SYSREG_AT
:
6489 inst
.base
.operands
[i
].sysins_op
=
6490 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6493 case AARCH64_OPND_SYSREG_SR
:
6494 inst
.base
.operands
[i
].sysins_op
=
6495 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6498 case AARCH64_OPND_SYSREG_TLBI
:
6499 inst
.base
.operands
[i
].sysins_op
=
6500 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6502 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6504 set_fatal_syntax_error ( _("unknown or missing operation name"));
6509 case AARCH64_OPND_BARRIER
:
6510 case AARCH64_OPND_BARRIER_ISB
:
6511 val
= parse_barrier (&str
);
6512 if (val
!= PARSE_FAIL
6513 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6515 /* ISB only accepts options name 'sy'. */
6517 (_("the specified option is not accepted in ISB"));
6518 /* Turn off backtrack as this optional operand is present. */
6522 /* This is an extension to accept a 0..15 immediate. */
6523 if (val
== PARSE_FAIL
)
6524 po_imm_or_fail (0, 15);
6525 info
->barrier
= aarch64_barrier_options
+ val
;
6528 case AARCH64_OPND_PRFOP
:
6529 val
= parse_pldop (&str
);
6530 /* This is an extension to accept a 0..31 immediate. */
6531 if (val
== PARSE_FAIL
)
6532 po_imm_or_fail (0, 31);
6533 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6536 case AARCH64_OPND_BARRIER_PSB
:
6537 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6538 if (val
== PARSE_FAIL
)
6542 case AARCH64_OPND_BTI_TARGET
:
6543 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6544 if (val
== PARSE_FAIL
)
6549 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6552 /* If we get here, this operand was successfully parsed. */
6553 inst
.base
.operands
[i
].present
= 1;
6557 /* The parse routine should already have set the error, but in case
6558 not, set a default one here. */
6560 set_default_error ();
6562 if (! backtrack_pos
)
6563 goto parse_operands_return
;
6566 /* We reach here because this operand is marked as optional, and
6567 either no operand was supplied or the operand was supplied but it
6568 was syntactically incorrect. In the latter case we report an
6569 error. In the former case we perform a few more checks before
6570 dropping through to the code to insert the default operand. */
6572 char *tmp
= backtrack_pos
;
6573 char endchar
= END_OF_INSN
;
6575 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6577 skip_past_char (&tmp
, ',');
6579 if (*tmp
!= endchar
)
6580 /* The user has supplied an operand in the wrong format. */
6581 goto parse_operands_return
;
6583 /* Make sure there is not a comma before the optional operand.
6584 For example the fifth operand of 'sys' is optional:
6586 sys #0,c0,c0,#0, <--- wrong
6587 sys #0,c0,c0,#0 <--- correct. */
6588 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6590 set_fatal_syntax_error
6591 (_("unexpected comma before the omitted optional operand"));
6592 goto parse_operands_return
;
6596 /* Reaching here means we are dealing with an optional operand that is
6597 omitted from the assembly line. */
6598 gas_assert (optional_operand_p (opcode
, i
));
6600 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6602 /* Try again, skipping the optional operand at backtrack_pos. */
6603 str
= backtrack_pos
;
6606 /* Clear any error record after the omitted optional operand has been
6607 successfully handled. */
6611 /* Check if we have parsed all the operands. */
6612 if (*str
!= '\0' && ! error_p ())
6614 /* Set I to the index of the last present operand; this is
6615 for the purpose of diagnostics. */
6616 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6618 set_fatal_syntax_error
6619 (_("unexpected characters following instruction"));
6622 parse_operands_return
:
6626 DEBUG_TRACE ("parsing FAIL: %s - %s",
6627 operand_mismatch_kind_names
[get_error_kind ()],
6628 get_error_message ());
6629 /* Record the operand error properly; this is useful when there
6630 are multiple instruction templates for a mnemonic name, so that
6631 later on, we can select the error that most closely describes
6633 record_operand_error (opcode
, i
, get_error_kind (),
6634 get_error_message ());
6639 DEBUG_TRACE ("parsing SUCCESS");
6644 /* It does some fix-up to provide some programmer friendly feature while
6645 keeping the libopcodes happy, i.e. libopcodes only accepts
6646 the preferred architectural syntax.
6647 Return FALSE if there is any failure; otherwise return TRUE. */
6650 programmer_friendly_fixup (aarch64_instruction
*instr
)
6652 aarch64_inst
*base
= &instr
->base
;
6653 const aarch64_opcode
*opcode
= base
->opcode
;
6654 enum aarch64_op op
= opcode
->op
;
6655 aarch64_opnd_info
*operands
= base
->operands
;
6657 DEBUG_TRACE ("enter");
6659 switch (opcode
->iclass
)
6662 /* TBNZ Xn|Wn, #uimm6, label
6663 Test and Branch Not Zero: conditionally jumps to label if bit number
6664 uimm6 in register Xn is not zero. The bit number implies the width of
6665 the register, which may be written and should be disassembled as Wn if
6666 uimm is less than 32. */
6667 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6669 if (operands
[1].imm
.value
>= 32)
6671 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6675 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6679 /* LDR Wt, label | =value
6680 As a convenience assemblers will typically permit the notation
6681 "=value" in conjunction with the pc-relative literal load instructions
6682 to automatically place an immediate value or symbolic address in a
6683 nearby literal pool and generate a hidden label which references it.
6684 ISREG has been set to 0 in the case of =value. */
6685 if (instr
->gen_lit_pool
6686 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6688 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6689 if (op
== OP_LDRSW_LIT
)
6691 if (instr
->reloc
.exp
.X_op
!= O_constant
6692 && instr
->reloc
.exp
.X_op
!= O_big
6693 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6695 record_operand_error (opcode
, 1,
6696 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6697 _("constant expression expected"));
6700 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6702 record_operand_error (opcode
, 1,
6703 AARCH64_OPDE_OTHER_ERROR
,
6704 _("literal pool insertion failed"));
6712 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6713 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6714 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6715 A programmer-friendly assembler should accept a destination Xd in
6716 place of Wd, however that is not the preferred form for disassembly.
6718 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6719 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6720 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6721 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6726 /* In the 64-bit form, the final register operand is written as Wm
6727 for all but the (possibly omitted) UXTX/LSL and SXTX
6729 As a programmer-friendly assembler, we accept e.g.
6730 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6731 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6732 int idx
= aarch64_operand_index (opcode
->operands
,
6733 AARCH64_OPND_Rm_EXT
);
6734 gas_assert (idx
== 1 || idx
== 2);
6735 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6736 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6737 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6738 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6739 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6740 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6748 DEBUG_TRACE ("exit with SUCCESS");
6752 /* Check for loads and stores that will cause unpredictable behavior. */
6755 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6757 aarch64_inst
*base
= &instr
->base
;
6758 const aarch64_opcode
*opcode
= base
->opcode
;
6759 const aarch64_opnd_info
*opnds
= base
->operands
;
6760 switch (opcode
->iclass
)
6767 /* Loading/storing the base register is unpredictable if writeback. */
6768 if ((aarch64_get_operand_class (opnds
[0].type
)
6769 == AARCH64_OPND_CLASS_INT_REG
)
6770 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6771 && opnds
[1].addr
.base_regno
!= REG_SP
6772 && opnds
[1].addr
.writeback
)
6773 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6776 case ldstgv_indexed
:
6777 /* Load operations must load different registers. */
6778 if ((opcode
->opcode
& (1 << 22))
6779 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
)
6780 as_warn (_("unpredictable load of register -- `%s'"), str
);
6784 case ldstnapair_offs
:
6785 case ldstpair_indexed
:
6786 /* Loading/storing the base register is unpredictable if writeback. */
6787 if ((aarch64_get_operand_class (opnds
[0].type
)
6788 == AARCH64_OPND_CLASS_INT_REG
)
6789 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6790 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6791 && opnds
[2].addr
.base_regno
!= REG_SP
6793 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6794 && opnds
[2].addr
.writeback
)
6795 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6796 /* Load operations must load different registers. */
6797 if ((opcode
->opcode
& (1 << 22))
6798 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6799 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6803 /* It is unpredictable if the destination and status registers are the
6805 if ((aarch64_get_operand_class (opnds
[0].type
)
6806 == AARCH64_OPND_CLASS_INT_REG
)
6807 && (aarch64_get_operand_class (opnds
[1].type
)
6808 == AARCH64_OPND_CLASS_INT_REG
)
6809 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6810 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6811 as_warn (_("unpredictable: identical transfer and status registers"
6823 force_automatic_sequence_close (void)
6825 if (now_instr_sequence
.instr
)
6827 as_warn (_("previous `%s' sequence has not been closed"),
6828 now_instr_sequence
.instr
->opcode
->name
);
6829 init_insn_sequence (NULL
, &now_instr_sequence
);
6833 /* A wrapper function to interface with libopcodes on encoding and
6834 record the error message if there is any.
6836 Return TRUE on success; otherwise return FALSE. */
6839 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6842 aarch64_operand_error error_info
;
6843 memset (&error_info
, '\0', sizeof (error_info
));
6844 error_info
.kind
= AARCH64_OPDE_NIL
;
6845 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6846 && !error_info
.non_fatal
)
6849 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6850 record_operand_error_info (opcode
, &error_info
);
6851 return error_info
.non_fatal
;
6854 #ifdef DEBUG_AARCH64
6856 dump_opcode_operands (const aarch64_opcode
*opcode
)
6859 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6861 aarch64_verbose ("\t\t opnd%d: %s", i
,
6862 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6863 ? aarch64_get_operand_name (opcode
->operands
[i
])
6864 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6868 #endif /* DEBUG_AARCH64 */
6870 /* This is the guts of the machine-dependent assembler. STR points to a
6871 machine dependent instruction. This function is supposed to emit
6872 the frags/bytes it assembles to. */
6875 md_assemble (char *str
)
6878 templates
*template;
6879 aarch64_opcode
*opcode
;
6880 aarch64_inst
*inst_base
;
6881 unsigned saved_cond
;
6883 /* Align the previous label if needed. */
6884 if (last_label_seen
!= NULL
)
6886 symbol_set_frag (last_label_seen
, frag_now
);
6887 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6888 S_SET_SEGMENT (last_label_seen
, now_seg
);
6891 /* Update the current insn_sequence from the segment. */
6892 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6894 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6896 DEBUG_TRACE ("\n\n");
6897 DEBUG_TRACE ("==============================");
6898 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6900 template = opcode_lookup (&p
);
6903 /* It wasn't an instruction, but it might be a register alias of
6904 the form alias .req reg directive. */
6905 if (!create_register_alias (str
, p
))
6906 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6911 skip_whitespace (p
);
6914 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6915 get_mnemonic_name (str
), str
);
6919 init_operand_error_report ();
6921 /* Sections are assumed to start aligned. In executable section, there is no
6922 MAP_DATA symbol pending. So we only align the address during
6923 MAP_DATA --> MAP_INSN transition.
6924 For other sections, this is not guaranteed. */
6925 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6926 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6927 frag_align_code (2, 0);
6929 saved_cond
= inst
.cond
;
6930 reset_aarch64_instruction (&inst
);
6931 inst
.cond
= saved_cond
;
6933 /* Iterate through all opcode entries with the same mnemonic name. */
6936 opcode
= template->opcode
;
6938 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6939 #ifdef DEBUG_AARCH64
6941 dump_opcode_operands (opcode
);
6942 #endif /* DEBUG_AARCH64 */
6944 mapping_state (MAP_INSN
);
6946 inst_base
= &inst
.base
;
6947 inst_base
->opcode
= opcode
;
6949 /* Truly conditionally executed instructions, e.g. b.cond. */
6950 if (opcode
->flags
& F_COND
)
6952 gas_assert (inst
.cond
!= COND_ALWAYS
);
6953 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6954 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6956 else if (inst
.cond
!= COND_ALWAYS
)
6958 /* It shouldn't arrive here, where the assembly looks like a
6959 conditional instruction but the found opcode is unconditional. */
6964 if (parse_operands (p
, opcode
)
6965 && programmer_friendly_fixup (&inst
)
6966 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6968 /* Check that this instruction is supported for this CPU. */
6969 if (!opcode
->avariant
6970 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6972 as_bad (_("selected processor does not support `%s'"), str
);
6976 warn_unpredictable_ldst (&inst
, str
);
6978 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6979 || !inst
.reloc
.need_libopcodes_p
)
6983 /* If there is relocation generated for the instruction,
6984 store the instruction information for the future fix-up. */
6985 struct aarch64_inst
*copy
;
6986 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6987 copy
= XNEW (struct aarch64_inst
);
6988 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6992 /* Issue non-fatal messages if any. */
6993 output_operand_error_report (str
, TRUE
);
6997 template = template->next
;
6998 if (template != NULL
)
7000 reset_aarch64_instruction (&inst
);
7001 inst
.cond
= saved_cond
;
7004 while (template != NULL
);
7006 /* Issue the error messages if any. */
7007 output_operand_error_report (str
, FALSE
);
7010 /* Various frobbings of labels and their addresses. */
7013 aarch64_start_line_hook (void)
7015 last_label_seen
= NULL
;
7019 aarch64_frob_label (symbolS
* sym
)
7021 last_label_seen
= sym
;
7023 dwarf2_emit_label (sym
);
7027 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7029 /* Check to see if we have a block to close. */
7030 force_automatic_sequence_close ();
7034 aarch64_data_in_code (void)
7036 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7038 *input_line_pointer
= '/';
7039 input_line_pointer
+= 5;
7040 *input_line_pointer
= 0;
7048 aarch64_canonicalize_symbol_name (char *name
)
7052 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7053 *(name
+ len
- 5) = 0;
7058 /* Table of all register names defined by default. The user can
7059 define additional names with .req. Note that all register names
7060 should appear in both upper and lowercase variants. Some registers
7061 also have mixed-case names. */
7063 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7064 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7065 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7066 #define REGSET16(p,t) \
7067 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7068 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7069 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7070 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7071 #define REGSET31(p,t) \
7073 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7074 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7075 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7076 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7077 #define REGSET(p,t) \
7078 REGSET31(p,t), REGNUM(p,31,t)
7080 /* These go into aarch64_reg_hsh hash-table. */
7081 static const reg_entry reg_names
[] = {
7082 /* Integer registers. */
7083 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7084 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7086 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7087 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7088 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7089 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7090 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7091 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7093 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7094 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7096 /* Floating-point single precision registers. */
7097 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7099 /* Floating-point double precision registers. */
7100 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7102 /* Floating-point half precision registers. */
7103 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7105 /* Floating-point byte precision registers. */
7106 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7108 /* Floating-point quad precision registers. */
7109 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7111 /* FP/SIMD registers. */
7112 REGSET (v
, VN
), REGSET (V
, VN
),
7114 /* SVE vector registers. */
7115 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7117 /* SVE predicate registers. */
7118 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7136 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7137 static const asm_nzcv nzcv_names
[] = {
7138 {"nzcv", B (n
, z
, c
, v
)},
7139 {"nzcV", B (n
, z
, c
, V
)},
7140 {"nzCv", B (n
, z
, C
, v
)},
7141 {"nzCV", B (n
, z
, C
, V
)},
7142 {"nZcv", B (n
, Z
, c
, v
)},
7143 {"nZcV", B (n
, Z
, c
, V
)},
7144 {"nZCv", B (n
, Z
, C
, v
)},
7145 {"nZCV", B (n
, Z
, C
, V
)},
7146 {"Nzcv", B (N
, z
, c
, v
)},
7147 {"NzcV", B (N
, z
, c
, V
)},
7148 {"NzCv", B (N
, z
, C
, v
)},
7149 {"NzCV", B (N
, z
, C
, V
)},
7150 {"NZcv", B (N
, Z
, c
, v
)},
7151 {"NZcV", B (N
, Z
, c
, V
)},
7152 {"NZCv", B (N
, Z
, C
, v
)},
7153 {"NZCV", B (N
, Z
, C
, V
)}
7166 /* MD interface: bits in the object file. */
7168 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7169 for use in the a.out file, and stores them in the array pointed to by buf.
7170 This knows about the endian-ness of the target machine and does
7171 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7172 2 (short) and 4 (long) Floating numbers are put out as a series of
7173 LITTLENUMS (shorts, here at least). */
7176 md_number_to_chars (char *buf
, valueT val
, int n
)
7178 if (target_big_endian
)
7179 number_to_chars_bigendian (buf
, val
, n
);
7181 number_to_chars_littleendian (buf
, val
, n
);
7184 /* MD interface: Sections. */
7186 /* Estimate the size of a frag before relaxing. Assume everything fits in
7190 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7196 /* Round up a section size to the appropriate boundary. */
7199 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7204 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7205 of an rs_align_code fragment.
7207 Here we fill the frag with the appropriate info for padding the
7208 output stream. The resulting frag will consist of a fixed (fr_fix)
7209 and of a repeating (fr_var) part.
7211 The fixed content is always emitted before the repeating content and
7212 these two parts are used as follows in constructing the output:
7213 - the fixed part will be used to align to a valid instruction word
7214 boundary, in case that we start at a misaligned address; as no
7215 executable instruction can live at the misaligned location, we
7216 simply fill with zeros;
7217 - the variable part will be used to cover the remaining padding and
7218 we fill using the AArch64 NOP instruction.
7220 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7221 enough storage space for up to 3 bytes for padding the back to a valid
7222 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7225 aarch64_handle_align (fragS
* fragP
)
7227 /* NOP = d503201f */
7228 /* AArch64 instructions are always little-endian. */
7229 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7231 int bytes
, fix
, noop_size
;
7234 if (fragP
->fr_type
!= rs_align_code
)
7237 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7238 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7241 gas_assert (fragP
->tc_frag_data
.recorded
);
7244 noop_size
= sizeof (aarch64_noop
);
7246 fix
= bytes
& (noop_size
- 1);
7250 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7254 fragP
->fr_fix
+= fix
;
7258 memcpy (p
, aarch64_noop
, noop_size
);
7259 fragP
->fr_var
= noop_size
;
7262 /* Perform target specific initialisation of a frag.
7263 Note - despite the name this initialisation is not done when the frag
7264 is created, but only when its type is assigned. A frag can be created
7265 and used a long time before its type is set, so beware of assuming that
7266 this initialisation is performed first. */
7270 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7271 int max_chars ATTRIBUTE_UNUSED
)
7275 #else /* OBJ_ELF is defined. */
7277 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7279 /* Record a mapping symbol for alignment frags. We will delete this
7280 later if the alignment ends up empty. */
7281 if (!fragP
->tc_frag_data
.recorded
)
7282 fragP
->tc_frag_data
.recorded
= 1;
7284 /* PR 21809: Do not set a mapping state for debug sections
7285 - it just confuses other tools. */
7286 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7289 switch (fragP
->fr_type
)
7293 mapping_state_2 (MAP_DATA
, max_chars
);
7296 /* PR 20364: We can get alignment frags in code sections,
7297 so do not just assume that we should use the MAP_DATA state. */
7298 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7301 mapping_state_2 (MAP_INSN
, max_chars
);
7308 /* Initialize the DWARF-2 unwind information for this procedure. */
7311 tc_aarch64_frame_initial_instructions (void)
7313 cfi_add_CFA_def_cfa (REG_SP
, 0);
7315 #endif /* OBJ_ELF */
7317 /* Convert REGNAME to a DWARF-2 register number. */
7320 tc_aarch64_regname_to_dw2regnum (char *regname
)
7322 const reg_entry
*reg
= parse_reg (®name
);
7328 case REG_TYPE_SP_32
:
7329 case REG_TYPE_SP_64
:
7339 return reg
->number
+ 64;
7347 /* Implement DWARF2_ADDR_SIZE. */
7350 aarch64_dwarf2_addr_size (void)
7352 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7356 return bfd_arch_bits_per_address (stdoutput
) / 8;
7359 /* MD interface: Symbol and relocation handling. */
7361 /* Return the address within the segment that a PC-relative fixup is
7362 relative to. For AArch64 PC-relative fixups applied to instructions
7363 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7366 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7368 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7370 /* If this is pc-relative and we are going to emit a relocation
7371 then we just want to put out any pipeline compensation that the linker
7372 will need. Otherwise we want to use the calculated base. */
7374 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7375 || aarch64_force_relocation (fixP
)))
7378 /* AArch64 should be consistent for all pc-relative relocations. */
7379 return base
+ AARCH64_PCREL_OFFSET
;
7382 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7383 Otherwise we have no need to default values of symbols. */
7386 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7389 if (name
[0] == '_' && name
[1] == 'G'
7390 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7394 if (symbol_find (name
))
7395 as_bad (_("GOT already in the symbol table"));
7397 GOT_symbol
= symbol_new (name
, undefined_section
,
7398 (valueT
) 0, &zero_address_frag
);
7408 /* Return non-zero if the indicated VALUE has overflowed the maximum
7409 range expressible by a unsigned number with the indicated number of
7413 unsigned_overflow (valueT value
, unsigned bits
)
7416 if (bits
>= sizeof (valueT
) * 8)
7418 lim
= (valueT
) 1 << bits
;
7419 return (value
>= lim
);
7423 /* Return non-zero if the indicated VALUE has overflowed the maximum
7424 range expressible by an signed number with the indicated number of
7428 signed_overflow (offsetT value
, unsigned bits
)
7431 if (bits
>= sizeof (offsetT
) * 8)
7433 lim
= (offsetT
) 1 << (bits
- 1);
7434 return (value
< -lim
|| value
>= lim
);
7437 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7438 unsigned immediate offset load/store instruction, try to encode it as
7439 an unscaled, 9-bit, signed immediate offset load/store instruction.
7440 Return TRUE if it is successful; otherwise return FALSE.
7442 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7443 in response to the standard LDR/STR mnemonics when the immediate offset is
7444 unambiguous, i.e. when it is negative or unaligned. */
7447 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7450 enum aarch64_op new_op
;
7451 const aarch64_opcode
*new_opcode
;
7453 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7455 switch (instr
->opcode
->op
)
7457 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7458 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7459 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7460 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7461 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7462 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7463 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7464 case OP_STR_POS
: new_op
= OP_STUR
; break;
7465 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7466 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7467 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7468 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7469 default: new_op
= OP_NIL
; break;
7472 if (new_op
== OP_NIL
)
7475 new_opcode
= aarch64_get_opcode (new_op
);
7476 gas_assert (new_opcode
!= NULL
);
7478 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7479 instr
->opcode
->op
, new_opcode
->op
);
7481 aarch64_replace_opcode (instr
, new_opcode
);
7483 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7484 qualifier matching may fail because the out-of-date qualifier will
7485 prevent the operand being updated with a new and correct qualifier. */
7486 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7487 AARCH64_OPND_ADDR_SIMM9
);
7488 gas_assert (idx
== 1);
7489 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7491 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7493 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7500 /* Called by fix_insn to fix a MOV immediate alias instruction.
7502 Operand for a generic move immediate instruction, which is an alias
7503 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7504 a 32-bit/64-bit immediate value into general register. An assembler error
7505 shall result if the immediate cannot be created by a single one of these
7506 instructions. If there is a choice, then to ensure reversability an
7507 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7510 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7512 const aarch64_opcode
*opcode
;
7514 /* Need to check if the destination is SP/ZR. The check has to be done
7515 before any aarch64_replace_opcode. */
7516 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7517 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7519 instr
->operands
[1].imm
.value
= value
;
7520 instr
->operands
[1].skip
= 0;
7524 /* Try the MOVZ alias. */
7525 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7526 aarch64_replace_opcode (instr
, opcode
);
7527 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7528 &instr
->value
, NULL
, NULL
, insn_sequence
))
7530 put_aarch64_insn (buf
, instr
->value
);
7533 /* Try the MOVK alias. */
7534 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7535 aarch64_replace_opcode (instr
, opcode
);
7536 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7537 &instr
->value
, NULL
, NULL
, insn_sequence
))
7539 put_aarch64_insn (buf
, instr
->value
);
7544 if (try_mov_bitmask_p
)
7546 /* Try the ORR alias. */
7547 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7548 aarch64_replace_opcode (instr
, opcode
);
7549 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7550 &instr
->value
, NULL
, NULL
, insn_sequence
))
7552 put_aarch64_insn (buf
, instr
->value
);
7557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7558 _("immediate cannot be moved by a single instruction"));
7561 /* An instruction operand which is immediate related may have symbol used
7562 in the assembly, e.g.
7565 .set u32, 0x00ffff00
7567 At the time when the assembly instruction is parsed, a referenced symbol,
7568 like 'u32' in the above example may not have been seen; a fixS is created
7569 in such a case and is handled here after symbols have been resolved.
7570 Instruction is fixed up with VALUE using the information in *FIXP plus
7571 extra information in FLAGS.
7573 This function is called by md_apply_fix to fix up instructions that need
7574 a fix-up described above but does not involve any linker-time relocation. */
7577 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7581 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7582 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7583 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7587 /* Now the instruction is about to be fixed-up, so the operand that
7588 was previously marked as 'ignored' needs to be unmarked in order
7589 to get the encoding done properly. */
7590 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7591 new_inst
->operands
[idx
].skip
= 0;
7594 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7598 case AARCH64_OPND_EXCEPTION
:
7599 if (unsigned_overflow (value
, 16))
7600 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7601 _("immediate out of range"));
7602 insn
= get_aarch64_insn (buf
);
7603 insn
|= encode_svc_imm (value
);
7604 put_aarch64_insn (buf
, insn
);
7607 case AARCH64_OPND_AIMM
:
7608 /* ADD or SUB with immediate.
7609 NOTE this assumes we come here with a add/sub shifted reg encoding
7610 3 322|2222|2 2 2 21111 111111
7611 1 098|7654|3 2 1 09876 543210 98765 43210
7612 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7613 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7614 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7615 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7617 3 322|2222|2 2 221111111111
7618 1 098|7654|3 2 109876543210 98765 43210
7619 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7620 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7621 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7622 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7623 Fields sf Rn Rd are already set. */
7624 insn
= get_aarch64_insn (buf
);
7628 insn
= reencode_addsub_switch_add_sub (insn
);
7632 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7633 && unsigned_overflow (value
, 12))
7635 /* Try to shift the value by 12 to make it fit. */
7636 if (((value
>> 12) << 12) == value
7637 && ! unsigned_overflow (value
, 12 + 12))
7640 insn
|= encode_addsub_imm_shift_amount (1);
7644 if (unsigned_overflow (value
, 12))
7645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7646 _("immediate out of range"));
7648 insn
|= encode_addsub_imm (value
);
7650 put_aarch64_insn (buf
, insn
);
7653 case AARCH64_OPND_SIMD_IMM
:
7654 case AARCH64_OPND_SIMD_IMM_SFT
:
7655 case AARCH64_OPND_LIMM
:
7656 /* Bit mask immediate. */
7657 gas_assert (new_inst
!= NULL
);
7658 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7659 new_inst
->operands
[idx
].imm
.value
= value
;
7660 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7661 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7662 put_aarch64_insn (buf
, new_inst
->value
);
7664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7665 _("invalid immediate"));
7668 case AARCH64_OPND_HALF
:
7669 /* 16-bit unsigned immediate. */
7670 if (unsigned_overflow (value
, 16))
7671 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7672 _("immediate out of range"));
7673 insn
= get_aarch64_insn (buf
);
7674 insn
|= encode_movw_imm (value
& 0xffff);
7675 put_aarch64_insn (buf
, insn
);
7678 case AARCH64_OPND_IMM_MOV
:
7679 /* Operand for a generic move immediate instruction, which is
7680 an alias instruction that generates a single MOVZ, MOVN or ORR
7681 instruction to loads a 32-bit/64-bit immediate value into general
7682 register. An assembler error shall result if the immediate cannot be
7683 created by a single one of these instructions. If there is a choice,
7684 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7685 and MOVZ or MOVN to ORR. */
7686 gas_assert (new_inst
!= NULL
);
7687 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7690 case AARCH64_OPND_ADDR_SIMM7
:
7691 case AARCH64_OPND_ADDR_SIMM9
:
7692 case AARCH64_OPND_ADDR_SIMM9_2
:
7693 case AARCH64_OPND_ADDR_SIMM10
:
7694 case AARCH64_OPND_ADDR_UIMM12
:
7695 case AARCH64_OPND_ADDR_SIMM11
:
7696 case AARCH64_OPND_ADDR_SIMM13
:
7697 /* Immediate offset in an address. */
7698 insn
= get_aarch64_insn (buf
);
7700 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7701 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7702 || new_inst
->opcode
->operands
[2] == opnd
);
7704 /* Get the index of the address operand. */
7705 if (new_inst
->opcode
->operands
[1] == opnd
)
7706 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7709 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7712 /* Update the resolved offset value. */
7713 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7715 /* Encode/fix-up. */
7716 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7717 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7719 put_aarch64_insn (buf
, new_inst
->value
);
7722 else if (new_inst
->opcode
->iclass
== ldst_pos
7723 && try_to_encode_as_unscaled_ldst (new_inst
))
7725 put_aarch64_insn (buf
, new_inst
->value
);
7729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7730 _("immediate offset out of range"));
7735 as_fatal (_("unhandled operand code %d"), opnd
);
7739 /* Apply a fixup (fixP) to segment data, once it has been determined
7740 by our caller that we have all the info we need to fix it up.
7742 Parameter valP is the pointer to the value of the bits. */
7745 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7747 offsetT value
= *valP
;
7749 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7751 unsigned flags
= fixP
->fx_addnumber
;
7753 DEBUG_TRACE ("\n\n");
7754 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7755 DEBUG_TRACE ("Enter md_apply_fix");
7757 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7759 /* Note whether this will delete the relocation. */
7761 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7764 /* Process the relocations. */
7765 switch (fixP
->fx_r_type
)
7767 case BFD_RELOC_NONE
:
7768 /* This will need to go in the object file. */
7773 case BFD_RELOC_8_PCREL
:
7774 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7775 md_number_to_chars (buf
, value
, 1);
7779 case BFD_RELOC_16_PCREL
:
7780 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7781 md_number_to_chars (buf
, value
, 2);
7785 case BFD_RELOC_32_PCREL
:
7786 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7787 md_number_to_chars (buf
, value
, 4);
7791 case BFD_RELOC_64_PCREL
:
7792 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7793 md_number_to_chars (buf
, value
, 8);
7796 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7797 /* We claim that these fixups have been processed here, even if
7798 in fact we generate an error because we do not have a reloc
7799 for them, so tc_gen_reloc() will reject them. */
7801 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7803 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7804 _("undefined symbol %s used as an immediate value"),
7805 S_GET_NAME (fixP
->fx_addsy
));
7806 goto apply_fix_return
;
7808 fix_insn (fixP
, flags
, value
);
7811 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7812 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7816 _("pc-relative load offset not word aligned"));
7817 if (signed_overflow (value
, 21))
7818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7819 _("pc-relative load offset out of range"));
7820 insn
= get_aarch64_insn (buf
);
7821 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7822 put_aarch64_insn (buf
, insn
);
7826 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7827 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7829 if (signed_overflow (value
, 21))
7830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7831 _("pc-relative address offset out of range"));
7832 insn
= get_aarch64_insn (buf
);
7833 insn
|= encode_adr_imm (value
);
7834 put_aarch64_insn (buf
, insn
);
7838 case BFD_RELOC_AARCH64_BRANCH19
:
7839 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7842 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7843 _("conditional branch target not word aligned"));
7844 if (signed_overflow (value
, 21))
7845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7846 _("conditional branch out of range"));
7847 insn
= get_aarch64_insn (buf
);
7848 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7849 put_aarch64_insn (buf
, insn
);
7853 case BFD_RELOC_AARCH64_TSTBR14
:
7854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7858 _("conditional branch target not word aligned"));
7859 if (signed_overflow (value
, 16))
7860 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7861 _("conditional branch out of range"));
7862 insn
= get_aarch64_insn (buf
);
7863 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7864 put_aarch64_insn (buf
, insn
);
7868 case BFD_RELOC_AARCH64_CALL26
:
7869 case BFD_RELOC_AARCH64_JUMP26
:
7870 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7873 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7874 _("branch target not word aligned"));
7875 if (signed_overflow (value
, 28))
7876 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7877 _("branch out of range"));
7878 insn
= get_aarch64_insn (buf
);
7879 insn
|= encode_branch_ofs_26 (value
>> 2);
7880 put_aarch64_insn (buf
, insn
);
7884 case BFD_RELOC_AARCH64_MOVW_G0
:
7885 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7886 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7887 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7888 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7889 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7892 case BFD_RELOC_AARCH64_MOVW_G1
:
7893 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7894 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7895 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7896 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7897 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7900 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7902 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7903 /* Should always be exported to object file, see
7904 aarch64_force_relocation(). */
7905 gas_assert (!fixP
->fx_done
);
7906 gas_assert (seg
->use_rela_p
);
7908 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7910 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7911 /* Should always be exported to object file, see
7912 aarch64_force_relocation(). */
7913 gas_assert (!fixP
->fx_done
);
7914 gas_assert (seg
->use_rela_p
);
7916 case BFD_RELOC_AARCH64_MOVW_G2
:
7917 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7918 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7919 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7920 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7923 case BFD_RELOC_AARCH64_MOVW_G3
:
7924 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7927 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7929 insn
= get_aarch64_insn (buf
);
7933 /* REL signed addend must fit in 16 bits */
7934 if (signed_overflow (value
, 16))
7935 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7936 _("offset out of range"));
7940 /* Check for overflow and scale. */
7941 switch (fixP
->fx_r_type
)
7943 case BFD_RELOC_AARCH64_MOVW_G0
:
7944 case BFD_RELOC_AARCH64_MOVW_G1
:
7945 case BFD_RELOC_AARCH64_MOVW_G2
:
7946 case BFD_RELOC_AARCH64_MOVW_G3
:
7947 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7948 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7949 if (unsigned_overflow (value
, scale
+ 16))
7950 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7951 _("unsigned value out of range"));
7953 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7954 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7955 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7956 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7957 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7958 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7959 /* NOTE: We can only come here with movz or movn. */
7960 if (signed_overflow (value
, scale
+ 16))
7961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7962 _("signed value out of range"));
7965 /* Force use of MOVN. */
7967 insn
= reencode_movzn_to_movn (insn
);
7971 /* Force use of MOVZ. */
7972 insn
= reencode_movzn_to_movz (insn
);
7976 /* Unchecked relocations. */
7982 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7983 insn
|= encode_movw_imm (value
& 0xffff);
7985 put_aarch64_insn (buf
, insn
);
7989 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7990 fixP
->fx_r_type
= (ilp32_p
7991 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7992 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7993 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7994 /* Should always be exported to object file, see
7995 aarch64_force_relocation(). */
7996 gas_assert (!fixP
->fx_done
);
7997 gas_assert (seg
->use_rela_p
);
8000 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8001 fixP
->fx_r_type
= (ilp32_p
8002 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8003 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8004 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8005 /* Should always be exported to object file, see
8006 aarch64_force_relocation(). */
8007 gas_assert (!fixP
->fx_done
);
8008 gas_assert (seg
->use_rela_p
);
8011 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8012 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8013 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8014 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8015 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8016 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8017 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8018 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8019 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8020 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8021 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8022 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8023 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8024 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8025 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8026 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8027 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8028 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8029 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8030 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8031 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8032 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8033 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8034 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8035 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8036 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8037 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8038 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8039 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8040 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8041 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8042 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8043 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8044 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8045 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8046 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8047 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8048 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8049 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8050 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8051 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8052 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8053 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8054 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8055 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8056 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8057 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8058 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8059 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8060 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8061 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8062 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8063 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8064 /* Should always be exported to object file, see
8065 aarch64_force_relocation(). */
8066 gas_assert (!fixP
->fx_done
);
8067 gas_assert (seg
->use_rela_p
);
8070 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8071 /* Should always be exported to object file, see
8072 aarch64_force_relocation(). */
8073 fixP
->fx_r_type
= (ilp32_p
8074 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8075 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8076 gas_assert (!fixP
->fx_done
);
8077 gas_assert (seg
->use_rela_p
);
8080 case BFD_RELOC_AARCH64_ADD_LO12
:
8081 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8082 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8083 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8084 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8085 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8086 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8087 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8088 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8089 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8090 case BFD_RELOC_AARCH64_LDST128_LO12
:
8091 case BFD_RELOC_AARCH64_LDST16_LO12
:
8092 case BFD_RELOC_AARCH64_LDST32_LO12
:
8093 case BFD_RELOC_AARCH64_LDST64_LO12
:
8094 case BFD_RELOC_AARCH64_LDST8_LO12
:
8095 /* Should always be exported to object file, see
8096 aarch64_force_relocation(). */
8097 gas_assert (!fixP
->fx_done
);
8098 gas_assert (seg
->use_rela_p
);
8101 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8102 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8103 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8106 case BFD_RELOC_UNUSED
:
8107 /* An error will already have been reported. */
8111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8112 _("unexpected %s fixup"),
8113 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8118 /* Free the allocated the struct aarch64_inst.
8119 N.B. currently there are very limited number of fix-up types actually use
8120 this field, so the impact on the performance should be minimal . */
8121 if (fixP
->tc_fix_data
.inst
!= NULL
)
8122 free (fixP
->tc_fix_data
.inst
);
8127 /* Translate internal representation of relocation info to BFD target
8131 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8134 bfd_reloc_code_real_type code
;
8136 reloc
= XNEW (arelent
);
8138 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8139 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8140 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8144 if (section
->use_rela_p
)
8145 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8147 fixp
->fx_offset
= reloc
->address
;
8149 reloc
->addend
= fixp
->fx_offset
;
8151 code
= fixp
->fx_r_type
;
8156 code
= BFD_RELOC_16_PCREL
;
8161 code
= BFD_RELOC_32_PCREL
;
8166 code
= BFD_RELOC_64_PCREL
;
8173 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8174 if (reloc
->howto
== NULL
)
8176 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8178 ("cannot represent %s relocation in this object file format"),
8179 bfd_get_reloc_code_name (code
));
8186 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8189 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8191 bfd_reloc_code_real_type type
;
8195 FIXME: @@ Should look at CPU word size. */
8202 type
= BFD_RELOC_16
;
8205 type
= BFD_RELOC_32
;
8208 type
= BFD_RELOC_64
;
8211 as_bad (_("cannot do %u-byte relocation"), size
);
8212 type
= BFD_RELOC_UNUSED
;
8216 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8220 aarch64_force_relocation (struct fix
*fixp
)
8222 switch (fixp
->fx_r_type
)
8224 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8225 /* Perform these "immediate" internal relocations
8226 even if the symbol is extern or weak. */
8229 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8230 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8231 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8232 /* Pseudo relocs that need to be fixed up according to
8236 case BFD_RELOC_AARCH64_ADD_LO12
:
8237 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8238 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8239 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8240 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8241 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8242 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8243 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8244 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8245 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8246 case BFD_RELOC_AARCH64_LDST128_LO12
:
8247 case BFD_RELOC_AARCH64_LDST16_LO12
:
8248 case BFD_RELOC_AARCH64_LDST32_LO12
:
8249 case BFD_RELOC_AARCH64_LDST64_LO12
:
8250 case BFD_RELOC_AARCH64_LDST8_LO12
:
8251 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8252 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8253 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8254 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8255 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8256 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8257 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8258 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8259 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8260 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8261 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8262 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8263 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8264 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8265 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8266 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8267 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8268 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8269 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8270 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8271 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8272 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8273 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8274 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8275 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8276 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8277 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8278 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8279 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8280 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8281 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8282 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8283 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8284 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8285 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8286 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8287 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8288 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8289 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8290 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8291 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8292 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8293 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8294 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8295 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8296 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8297 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8298 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8299 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8300 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8301 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8302 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8303 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8304 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8305 /* Always leave these relocations for the linker. */
8312 return generic_force_reloc (fixp
);
8317 /* Implement md_after_parse_args. This is the earliest time we need to decide
8318 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8321 aarch64_after_parse_args (void)
8323 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8326 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8327 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8328 aarch64_abi
= AARCH64_ABI_ILP32
;
8330 aarch64_abi
= AARCH64_ABI_LP64
;
8334 elf64_aarch64_target_format (void)
8336 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8338 /* FIXME: What to do for ilp32_p ? */
8339 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8341 if (target_big_endian
)
8342 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8344 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8348 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8350 elf_frob_symbol (symp
, puntp
);
8354 /* MD interface: Finalization. */
8356 /* A good place to do this, although this was probably not intended
8357 for this kind of use. We need to dump the literal pool before
8358 references are made to a null symbol pointer. */
8361 aarch64_cleanup (void)
8365 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8367 /* Put it at the end of the relevant section. */
8368 subseg_set (pool
->section
, pool
->sub_section
);
8374 /* Remove any excess mapping symbols generated for alignment frags in
8375 SEC. We may have created a mapping symbol before a zero byte
8376 alignment; remove it if there's a mapping symbol after the
8379 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8380 void *dummy ATTRIBUTE_UNUSED
)
8382 segment_info_type
*seginfo
= seg_info (sec
);
8385 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8388 for (fragp
= seginfo
->frchainP
->frch_root
;
8389 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8391 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8392 fragS
*next
= fragp
->fr_next
;
8394 /* Variable-sized frags have been converted to fixed size by
8395 this point. But if this was variable-sized to start with,
8396 there will be a fixed-size frag after it. So don't handle
8398 if (sym
== NULL
|| next
== NULL
)
8401 if (S_GET_VALUE (sym
) < next
->fr_address
)
8402 /* Not at the end of this frag. */
8404 know (S_GET_VALUE (sym
) == next
->fr_address
);
8408 if (next
->tc_frag_data
.first_map
!= NULL
)
8410 /* Next frag starts with a mapping symbol. Discard this
8412 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8416 if (next
->fr_next
== NULL
)
8418 /* This mapping symbol is at the end of the section. Discard
8420 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8421 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8425 /* As long as we have empty frags without any mapping symbols,
8427 /* If the next frag is non-empty and does not start with a
8428 mapping symbol, then this mapping symbol is required. */
8429 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8432 next
= next
->fr_next
;
8434 while (next
!= NULL
);
8439 /* Adjust the symbol table. */
8442 aarch64_adjust_symtab (void)
8445 /* Remove any overlapping mapping symbols generated by alignment frags. */
8446 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8447 /* Now do generic ELF adjustments. */
8448 elf_adjust_symtab ();
8453 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8455 const char *hash_err
;
8457 hash_err
= hash_insert (table
, key
, value
);
8459 printf ("Internal Error: Can't hash %s\n", key
);
8463 fill_instruction_hash_table (void)
8465 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8467 while (opcode
->name
!= NULL
)
8469 templates
*templ
, *new_templ
;
8470 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8472 new_templ
= XNEW (templates
);
8473 new_templ
->opcode
= opcode
;
8474 new_templ
->next
= NULL
;
8477 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8480 new_templ
->next
= templ
->next
;
8481 templ
->next
= new_templ
;
8488 convert_to_upper (char *dst
, const char *src
, size_t num
)
8491 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8492 *dst
= TOUPPER (*src
);
8496 /* Assume STR point to a lower-case string, allocate, convert and return
8497 the corresponding upper-case string. */
8498 static inline const char*
8499 get_upper_str (const char *str
)
8502 size_t len
= strlen (str
);
8503 ret
= XNEWVEC (char, len
+ 1);
8504 convert_to_upper (ret
, str
, len
);
8508 /* MD interface: Initialization. */
8516 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8517 || (aarch64_cond_hsh
= hash_new ()) == NULL
8518 || (aarch64_shift_hsh
= hash_new ()) == NULL
8519 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8520 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8521 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8522 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8523 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8524 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8525 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8526 || (aarch64_reg_hsh
= hash_new ()) == NULL
8527 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8528 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8529 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8530 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8531 as_fatal (_("virtual memory exhausted"));
8533 fill_instruction_hash_table ();
8535 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8536 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8537 (void *) (aarch64_sys_regs
+ i
));
8539 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8540 checked_hash_insert (aarch64_pstatefield_hsh
,
8541 aarch64_pstatefields
[i
].name
,
8542 (void *) (aarch64_pstatefields
+ i
));
8544 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8545 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8546 aarch64_sys_regs_ic
[i
].name
,
8547 (void *) (aarch64_sys_regs_ic
+ i
));
8549 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8550 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8551 aarch64_sys_regs_dc
[i
].name
,
8552 (void *) (aarch64_sys_regs_dc
+ i
));
8554 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8555 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8556 aarch64_sys_regs_at
[i
].name
,
8557 (void *) (aarch64_sys_regs_at
+ i
));
8559 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8560 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8561 aarch64_sys_regs_tlbi
[i
].name
,
8562 (void *) (aarch64_sys_regs_tlbi
+ i
));
8564 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8565 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8566 aarch64_sys_regs_sr
[i
].name
,
8567 (void *) (aarch64_sys_regs_sr
+ i
));
8569 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8570 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8571 (void *) (reg_names
+ i
));
8573 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8574 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8575 (void *) (nzcv_names
+ i
));
8577 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8579 const char *name
= aarch64_operand_modifiers
[i
].name
;
8580 checked_hash_insert (aarch64_shift_hsh
, name
,
8581 (void *) (aarch64_operand_modifiers
+ i
));
8582 /* Also hash the name in the upper case. */
8583 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8584 (void *) (aarch64_operand_modifiers
+ i
));
8587 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8590 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8591 the same condition code. */
8592 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8594 const char *name
= aarch64_conds
[i
].names
[j
];
8597 checked_hash_insert (aarch64_cond_hsh
, name
,
8598 (void *) (aarch64_conds
+ i
));
8599 /* Also hash the name in the upper case. */
8600 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8601 (void *) (aarch64_conds
+ i
));
8605 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8607 const char *name
= aarch64_barrier_options
[i
].name
;
8608 /* Skip xx00 - the unallocated values of option. */
8611 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8612 (void *) (aarch64_barrier_options
+ i
));
8613 /* Also hash the name in the upper case. */
8614 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8615 (void *) (aarch64_barrier_options
+ i
));
8618 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8620 const char* name
= aarch64_prfops
[i
].name
;
8621 /* Skip the unallocated hint encodings. */
8624 checked_hash_insert (aarch64_pldop_hsh
, name
,
8625 (void *) (aarch64_prfops
+ i
));
8626 /* Also hash the name in the upper case. */
8627 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8628 (void *) (aarch64_prfops
+ i
));
8631 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8633 const char* name
= aarch64_hint_options
[i
].name
;
8635 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8636 (void *) (aarch64_hint_options
+ i
));
8637 /* Also hash the name in the upper case. */
8638 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8639 (void *) (aarch64_hint_options
+ i
));
8642 /* Set the cpu variant based on the command-line options. */
8644 mcpu_cpu_opt
= march_cpu_opt
;
8647 mcpu_cpu_opt
= &cpu_default
;
8649 cpu_variant
= *mcpu_cpu_opt
;
8651 /* Record the CPU type. */
8652 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8654 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8657 /* Command line processing. */
8659 const char *md_shortopts
= "m:";
8661 #ifdef AARCH64_BI_ENDIAN
8662 #define OPTION_EB (OPTION_MD_BASE + 0)
8663 #define OPTION_EL (OPTION_MD_BASE + 1)
8665 #if TARGET_BYTES_BIG_ENDIAN
8666 #define OPTION_EB (OPTION_MD_BASE + 0)
8668 #define OPTION_EL (OPTION_MD_BASE + 1)
8672 struct option md_longopts
[] = {
8674 {"EB", no_argument
, NULL
, OPTION_EB
},
8677 {"EL", no_argument
, NULL
, OPTION_EL
},
8679 {NULL
, no_argument
, NULL
, 0}
8682 size_t md_longopts_size
= sizeof (md_longopts
);
8684 struct aarch64_option_table
8686 const char *option
; /* Option name to match. */
8687 const char *help
; /* Help information. */
8688 int *var
; /* Variable to change. */
8689 int value
; /* What to change it to. */
8690 char *deprecated
; /* If non-null, print this message. */
8693 static struct aarch64_option_table aarch64_opts
[] = {
8694 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8695 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8697 #ifdef DEBUG_AARCH64
8698 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8699 #endif /* DEBUG_AARCH64 */
8700 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8702 {"mno-verbose-error", N_("do not output verbose error messages"),
8703 &verbose_error_p
, 0, NULL
},
8704 {NULL
, NULL
, NULL
, 0, NULL
}
8707 struct aarch64_cpu_option_table
8710 const aarch64_feature_set value
;
8711 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8713 const char *canonical_name
;
8716 /* This list should, at a minimum, contain all the cpu names
8717 recognized by GCC. */
8718 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8719 {"all", AARCH64_ANY
, NULL
},
8720 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8721 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8722 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8723 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8724 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8725 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8726 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8727 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8728 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8729 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8730 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8731 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8733 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8734 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8736 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8737 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8739 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8740 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8741 "Samsung Exynos M1"},
8742 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8743 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8744 | AARCH64_FEATURE_RDMA
),
8746 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8747 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8748 | AARCH64_FEATURE_RDMA
),
8749 "Qualcomm QDF24XX"},
8750 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8751 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8752 "Qualcomm Saphira"},
8753 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8754 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8756 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8757 AARCH64_FEATURE_CRYPTO
),
8759 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8760 in earlier releases and is superseded by 'xgene1' in all
8762 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8763 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8764 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8765 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8766 {"generic", AARCH64_ARCH_V8
, NULL
},
8768 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8771 struct aarch64_arch_option_table
8774 const aarch64_feature_set value
;
8777 /* This list should, at a minimum, contain all the architecture names
8778 recognized by GCC. */
8779 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8780 {"all", AARCH64_ANY
},
8781 {"armv8-a", AARCH64_ARCH_V8
},
8782 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8783 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8784 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8785 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8786 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8787 {NULL
, AARCH64_ARCH_NONE
}
8790 /* ISA extensions. */
8791 struct aarch64_option_cpu_value_table
8794 const aarch64_feature_set value
;
8795 const aarch64_feature_set require
; /* Feature dependencies. */
8798 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8799 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8801 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8802 | AARCH64_FEATURE_AES
8803 | AARCH64_FEATURE_SHA2
, 0),
8804 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8805 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8807 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8809 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8810 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8811 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8813 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8815 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8817 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8818 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8819 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8820 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8821 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8822 AARCH64_FEATURE (AARCH64_FEATURE_FP
8823 | AARCH64_FEATURE_F16
, 0)},
8824 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8826 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8827 AARCH64_FEATURE (AARCH64_FEATURE_F16
8828 | AARCH64_FEATURE_SIMD
8829 | AARCH64_FEATURE_COMPNUM
, 0)},
8830 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8831 AARCH64_FEATURE (AARCH64_FEATURE_F16
8832 | AARCH64_FEATURE_SIMD
, 0)},
8833 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8835 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8837 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8839 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8841 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8843 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8845 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8847 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8848 | AARCH64_FEATURE_SHA3
, 0),
8850 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8852 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8854 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8856 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8859 struct aarch64_long_option_table
8861 const char *option
; /* Substring to match. */
8862 const char *help
; /* Help information. */
8863 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8864 char *deprecated
; /* If non-null, print this message. */
8867 /* Transitive closure of features depending on set. */
8868 static aarch64_feature_set
8869 aarch64_feature_disable_set (aarch64_feature_set set
)
8871 const struct aarch64_option_cpu_value_table
*opt
;
8872 aarch64_feature_set prev
= 0;
8874 while (prev
!= set
) {
8876 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8877 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8878 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8883 /* Transitive closure of dependencies of set. */
8884 static aarch64_feature_set
8885 aarch64_feature_enable_set (aarch64_feature_set set
)
8887 const struct aarch64_option_cpu_value_table
*opt
;
8888 aarch64_feature_set prev
= 0;
8890 while (prev
!= set
) {
8892 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8893 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8894 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8900 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8901 bfd_boolean ext_only
)
8903 /* We insist on extensions being added before being removed. We achieve
8904 this by using the ADDING_VALUE variable to indicate whether we are
8905 adding an extension (1) or removing it (0) and only allowing it to
8906 change in the order -1 -> 1 -> 0. */
8907 int adding_value
= -1;
8908 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8910 /* Copy the feature set, so that we can modify it. */
8914 while (str
!= NULL
&& *str
!= 0)
8916 const struct aarch64_option_cpu_value_table
*opt
;
8917 const char *ext
= NULL
;
8924 as_bad (_("invalid architectural extension"));
8928 ext
= strchr (++str
, '+');
8934 optlen
= strlen (str
);
8936 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8938 if (adding_value
!= 0)
8943 else if (optlen
> 0)
8945 if (adding_value
== -1)
8947 else if (adding_value
!= 1)
8949 as_bad (_("must specify extensions to add before specifying "
8950 "those to remove"));
8957 as_bad (_("missing architectural extension"));
8961 gas_assert (adding_value
!= -1);
8963 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8964 if (strncmp (opt
->name
, str
, optlen
) == 0)
8966 aarch64_feature_set set
;
8968 /* Add or remove the extension. */
8971 set
= aarch64_feature_enable_set (opt
->value
);
8972 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8976 set
= aarch64_feature_disable_set (opt
->value
);
8977 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8982 if (opt
->name
== NULL
)
8984 as_bad (_("unknown architectural extension `%s'"), str
);
8995 aarch64_parse_cpu (const char *str
)
8997 const struct aarch64_cpu_option_table
*opt
;
8998 const char *ext
= strchr (str
, '+');
9004 optlen
= strlen (str
);
9008 as_bad (_("missing cpu name `%s'"), str
);
9012 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9013 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9015 mcpu_cpu_opt
= &opt
->value
;
9017 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9022 as_bad (_("unknown cpu `%s'"), str
);
9027 aarch64_parse_arch (const char *str
)
9029 const struct aarch64_arch_option_table
*opt
;
9030 const char *ext
= strchr (str
, '+');
9036 optlen
= strlen (str
);
9040 as_bad (_("missing architecture name `%s'"), str
);
9044 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9045 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9047 march_cpu_opt
= &opt
->value
;
9049 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9054 as_bad (_("unknown architecture `%s'\n"), str
);
9059 struct aarch64_option_abi_value_table
9062 enum aarch64_abi_type value
;
9065 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9066 {"ilp32", AARCH64_ABI_ILP32
},
9067 {"lp64", AARCH64_ABI_LP64
},
9071 aarch64_parse_abi (const char *str
)
9077 as_bad (_("missing abi name `%s'"), str
);
9081 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9082 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9084 aarch64_abi
= aarch64_abis
[i
].value
;
9088 as_bad (_("unknown abi `%s'\n"), str
);
9092 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9094 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9095 aarch64_parse_abi
, NULL
},
9096 #endif /* OBJ_ELF */
9097 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9098 aarch64_parse_cpu
, NULL
},
9099 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9100 aarch64_parse_arch
, NULL
},
9101 {NULL
, NULL
, 0, NULL
}
9105 md_parse_option (int c
, const char *arg
)
9107 struct aarch64_option_table
*opt
;
9108 struct aarch64_long_option_table
*lopt
;
9114 target_big_endian
= 1;
9120 target_big_endian
= 0;
9125 /* Listing option. Just ignore these, we don't support additional
9130 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9132 if (c
== opt
->option
[0]
9133 && ((arg
== NULL
&& opt
->option
[1] == 0)
9134 || streq (arg
, opt
->option
+ 1)))
9136 /* If the option is deprecated, tell the user. */
9137 if (opt
->deprecated
!= NULL
)
9138 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9139 arg
? arg
: "", _(opt
->deprecated
));
9141 if (opt
->var
!= NULL
)
9142 *opt
->var
= opt
->value
;
9148 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9150 /* These options are expected to have an argument. */
9151 if (c
== lopt
->option
[0]
9153 && strncmp (arg
, lopt
->option
+ 1,
9154 strlen (lopt
->option
+ 1)) == 0)
9156 /* If the option is deprecated, tell the user. */
9157 if (lopt
->deprecated
!= NULL
)
9158 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9159 _(lopt
->deprecated
));
9161 /* Call the sup-option parser. */
9162 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9173 md_show_usage (FILE * fp
)
9175 struct aarch64_option_table
*opt
;
9176 struct aarch64_long_option_table
*lopt
;
9178 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9180 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9181 if (opt
->help
!= NULL
)
9182 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9184 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9185 if (lopt
->help
!= NULL
)
9186 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9190 -EB assemble code for a big-endian cpu\n"));
9195 -EL assemble code for a little-endian cpu\n"));
9199 /* Parse a .cpu directive. */
9202 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9204 const struct aarch64_cpu_option_table
*opt
;
9210 name
= input_line_pointer
;
9211 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9212 input_line_pointer
++;
9213 saved_char
= *input_line_pointer
;
9214 *input_line_pointer
= 0;
9216 ext
= strchr (name
, '+');
9219 optlen
= ext
- name
;
9221 optlen
= strlen (name
);
9223 /* Skip the first "all" entry. */
9224 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9225 if (strlen (opt
->name
) == optlen
9226 && strncmp (name
, opt
->name
, optlen
) == 0)
9228 mcpu_cpu_opt
= &opt
->value
;
9230 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9233 cpu_variant
= *mcpu_cpu_opt
;
9235 *input_line_pointer
= saved_char
;
9236 demand_empty_rest_of_line ();
9239 as_bad (_("unknown cpu `%s'"), name
);
9240 *input_line_pointer
= saved_char
;
9241 ignore_rest_of_line ();
9245 /* Parse a .arch directive. */
9248 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9250 const struct aarch64_arch_option_table
*opt
;
9256 name
= input_line_pointer
;
9257 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9258 input_line_pointer
++;
9259 saved_char
= *input_line_pointer
;
9260 *input_line_pointer
= 0;
9262 ext
= strchr (name
, '+');
9265 optlen
= ext
- name
;
9267 optlen
= strlen (name
);
9269 /* Skip the first "all" entry. */
9270 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9271 if (strlen (opt
->name
) == optlen
9272 && strncmp (name
, opt
->name
, optlen
) == 0)
9274 mcpu_cpu_opt
= &opt
->value
;
9276 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9279 cpu_variant
= *mcpu_cpu_opt
;
9281 *input_line_pointer
= saved_char
;
9282 demand_empty_rest_of_line ();
9286 as_bad (_("unknown architecture `%s'\n"), name
);
9287 *input_line_pointer
= saved_char
;
9288 ignore_rest_of_line ();
9291 /* Parse a .arch_extension directive. */
9294 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9297 char *ext
= input_line_pointer
;;
9299 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9300 input_line_pointer
++;
9301 saved_char
= *input_line_pointer
;
9302 *input_line_pointer
= 0;
9304 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9307 cpu_variant
= *mcpu_cpu_opt
;
9309 *input_line_pointer
= saved_char
;
9310 demand_empty_rest_of_line ();
9313 /* Copy symbol information. */
9316 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9318 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);