1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Return value for certain parsers when the parsing fails; those parsers
242 return the information of the parsed result, e.g. register number, on
244 #define PARSE_FAIL -1
246 /* This is an invalid condition code that means no conditional field is
248 #define COND_ALWAYS 0x10
252 const char *template;
258 const char *template;
265 bfd_reloc_code_real_type reloc
;
268 /* Macros to define the register types and masks for the purpose
271 #undef AARCH64_REG_TYPES
272 #define AARCH64_REG_TYPES \
273 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
274 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
275 BASIC_REG_TYPE(SP_32) /* wsp */ \
276 BASIC_REG_TYPE(SP_64) /* sp */ \
277 BASIC_REG_TYPE(Z_32) /* wzr */ \
278 BASIC_REG_TYPE(Z_64) /* xzr */ \
279 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
280 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
281 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
282 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
283 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
284 BASIC_REG_TYPE(VN) /* v[0-31] */ \
285 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
286 BASIC_REG_TYPE(PN) /* p[0-15] */ \
287 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
288 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
289 /* Typecheck: same, plus SVE registers. */ \
290 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
292 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
293 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Typecheck: same, plus SVE registers. */ \
296 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
299 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
300 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
301 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
302 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
303 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
305 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
306 /* Typecheck: any [BHSDQ]P FP. */ \
307 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
308 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
309 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
310 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
311 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
312 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
313 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
314 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
315 be used for SVE instructions, since Zn and Pn are valid symbols \
316 in other contexts. */ \
317 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
318 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
319 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
320 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
321 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
322 | REG_TYPE(ZN) | REG_TYPE(PN)) \
323 /* Any integer register; used for error messages only. */ \
324 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
325 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
326 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
327 /* Pseudo type to mark the end of the enumerator sequence. */ \
330 #undef BASIC_REG_TYPE
331 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
332 #undef MULTI_REG_TYPE
333 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
335 /* Register type enumerators. */
336 typedef enum aarch64_reg_type_
338 /* A list of REG_TYPE_*. */
342 #undef BASIC_REG_TYPE
343 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
345 #define REG_TYPE(T) (1 << REG_TYPE_##T)
346 #undef MULTI_REG_TYPE
347 #define MULTI_REG_TYPE(T,V) V,
349 /* Structure for a hash table entry for a register. */
353 unsigned char number
;
354 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
355 unsigned char builtin
;
358 /* Values indexed by aarch64_reg_type to assist the type checking. */
359 static const unsigned reg_type_masks
[] =
364 #undef BASIC_REG_TYPE
366 #undef MULTI_REG_TYPE
367 #undef AARCH64_REG_TYPES
369 /* Diagnostics used when we don't get a register of the expected type.
370 Note: this has to synchronized with aarch64_reg_type definitions
373 get_reg_expected_msg (aarch64_reg_type reg_type
)
380 msg
= N_("integer 32-bit register expected");
383 msg
= N_("integer 64-bit register expected");
386 msg
= N_("integer register expected");
388 case REG_TYPE_R64_SP
:
389 msg
= N_("64-bit integer or SP register expected");
391 case REG_TYPE_SVE_BASE
:
392 msg
= N_("base register expected");
395 msg
= N_("integer or zero register expected");
397 case REG_TYPE_SVE_OFFSET
:
398 msg
= N_("offset register expected");
401 msg
= N_("integer or SP register expected");
403 case REG_TYPE_R_Z_SP
:
404 msg
= N_("integer, zero or SP register expected");
407 msg
= N_("8-bit SIMD scalar register expected");
410 msg
= N_("16-bit SIMD scalar or floating-point half precision "
411 "register expected");
414 msg
= N_("32-bit SIMD scalar or floating-point single precision "
415 "register expected");
418 msg
= N_("64-bit SIMD scalar or floating-point double precision "
419 "register expected");
422 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
423 "register expected");
425 case REG_TYPE_R_Z_BHSDQ_V
:
426 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
427 msg
= N_("register expected");
429 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
430 msg
= N_("SIMD scalar or floating-point register expected");
432 case REG_TYPE_VN
: /* any V reg */
433 msg
= N_("vector register expected");
436 msg
= N_("SVE vector register expected");
439 msg
= N_("SVE predicate register expected");
442 as_fatal (_("invalid register type %d"), reg_type
);
447 /* Some well known registers that we refer to directly elsewhere. */
451 /* Instructions take 4 bytes in the object file. */
454 static struct hash_control
*aarch64_ops_hsh
;
455 static struct hash_control
*aarch64_cond_hsh
;
456 static struct hash_control
*aarch64_shift_hsh
;
457 static struct hash_control
*aarch64_sys_regs_hsh
;
458 static struct hash_control
*aarch64_pstatefield_hsh
;
459 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
460 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
461 static struct hash_control
*aarch64_sys_regs_at_hsh
;
462 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
463 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
464 static struct hash_control
*aarch64_reg_hsh
;
465 static struct hash_control
*aarch64_barrier_opt_hsh
;
466 static struct hash_control
*aarch64_nzcv_hsh
;
467 static struct hash_control
*aarch64_pldop_hsh
;
468 static struct hash_control
*aarch64_hint_opt_hsh
;
470 /* Stuff needed to resolve the label ambiguity
479 static symbolS
*last_label_seen
;
481 /* Literal pool structure. Held on a per-section
482 and per-sub-section basis. */
484 #define MAX_LITERAL_POOL_SIZE 1024
485 typedef struct literal_expression
488 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
489 LITTLENUM_TYPE
* bignum
;
490 } literal_expression
;
492 typedef struct literal_pool
494 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
495 unsigned int next_free_entry
;
501 struct literal_pool
*next
;
504 /* Pointer to a linked list of literal pools. */
505 static literal_pool
*list_of_pools
= NULL
;
509 /* This array holds the chars that always start a comment. If the
510 pre-processor is disabled, these aren't very useful. */
511 const char comment_chars
[] = "";
513 /* This array holds the chars that only start a comment at the beginning of
514 a line. If the line seems to have the form '# 123 filename'
515 .line and .file directives will appear in the pre-processed output. */
516 /* Note that input_file.c hand checks for '#' at the beginning of the
517 first line of the input file. This is because the compiler outputs
518 #NO_APP at the beginning of its output. */
519 /* Also note that comments like this one will always work. */
520 const char line_comment_chars
[] = "#";
522 const char line_separator_chars
[] = ";";
524 /* Chars that can be used to separate mant
525 from exp in floating point numbers. */
526 const char EXP_CHARS
[] = "eE";
528 /* Chars that mean this number is a floating point constant. */
532 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPhH";
534 /* Prefix character that indicates the start of an immediate value. */
535 #define is_immediate_prefix(C) ((C) == '#')
537 /* Separator character handling. */
539 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
541 static inline bfd_boolean
542 skip_past_char (char **str
, char c
)
553 #define skip_past_comma(str) skip_past_char (str, ',')
555 /* Arithmetic expressions (possibly involving symbols). */
557 static bfd_boolean in_my_get_expression_p
= FALSE
;
559 /* Third argument to my_get_expression. */
560 #define GE_NO_PREFIX 0
561 #define GE_OPT_PREFIX 1
563 /* Return TRUE if the string pointed by *STR is successfully parsed
564 as an valid expression; *EP will be filled with the information of
565 such an expression. Otherwise return FALSE. */
568 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
573 int prefix_present_p
= 0;
580 if (is_immediate_prefix (**str
))
583 prefix_present_p
= 1;
590 memset (ep
, 0, sizeof (expressionS
));
592 save_in
= input_line_pointer
;
593 input_line_pointer
= *str
;
594 in_my_get_expression_p
= TRUE
;
595 seg
= expression (ep
);
596 in_my_get_expression_p
= FALSE
;
598 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
600 /* We found a bad expression in md_operand(). */
601 *str
= input_line_pointer
;
602 input_line_pointer
= save_in
;
603 if (prefix_present_p
&& ! error_p ())
604 set_fatal_syntax_error (_("bad expression"));
606 set_first_syntax_error (_("bad expression"));
611 if (seg
!= absolute_section
612 && seg
!= text_section
613 && seg
!= data_section
614 && seg
!= bss_section
&& seg
!= undefined_section
)
616 set_syntax_error (_("bad segment"));
617 *str
= input_line_pointer
;
618 input_line_pointer
= save_in
;
625 *str
= input_line_pointer
;
626 input_line_pointer
= save_in
;
630 /* Turn a string in input_line_pointer into a floating point constant
631 of type TYPE, and store the appropriate bytes in *LITP. The number
632 of LITTLENUMS emitted is stored in *SIZEP. An error message is
633 returned, or NULL on OK. */
636 md_atof (int type
, char *litP
, int *sizeP
)
638 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
641 /* We handle all bad expressions here, so that we can report the faulty
642 instruction in the error message. */
644 md_operand (expressionS
* exp
)
646 if (in_my_get_expression_p
)
647 exp
->X_op
= O_illegal
;
650 /* Immediate values. */
652 /* Errors may be set multiple times during parsing or bit encoding
653 (particularly in the Neon bits), but usually the earliest error which is set
654 will be the most meaningful. Avoid overwriting it with later (cascading)
655 errors by calling this function. */
658 first_error (const char *error
)
661 set_syntax_error (error
);
664 /* Similar to first_error, but this function accepts formatted error
667 first_error_fmt (const char *format
, ...)
672 /* N.B. this single buffer will not cause error messages for different
673 instructions to pollute each other; this is because at the end of
674 processing of each assembly line, error message if any will be
675 collected by as_bad. */
676 static char buffer
[size
];
680 int ret ATTRIBUTE_UNUSED
;
681 va_start (args
, format
);
682 ret
= vsnprintf (buffer
, size
, format
, args
);
683 know (ret
<= size
- 1 && ret
>= 0);
685 set_syntax_error (buffer
);
689 /* Register parsing. */
691 /* Generic register parser which is called by other specialized
693 CCP points to what should be the beginning of a register name.
694 If it is indeed a valid register name, advance CCP over it and
695 return the reg_entry structure; otherwise return NULL.
696 It does not issue diagnostics. */
699 parse_reg (char **ccp
)
705 #ifdef REGISTER_PREFIX
706 if (*start
!= REGISTER_PREFIX
)
712 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
717 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
719 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
728 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
731 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
733 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
736 /* Try to parse a base or offset register. Allow SVE base and offset
737 registers if REG_TYPE includes SVE registers. Return the register
738 entry on success, setting *QUALIFIER to the register qualifier.
739 Return null otherwise.
741 Note that this function does not issue any diagnostics. */
743 static const reg_entry
*
744 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
745 aarch64_opnd_qualifier_t
*qualifier
)
748 const reg_entry
*reg
= parse_reg (&str
);
758 *qualifier
= AARCH64_OPND_QLF_W
;
764 *qualifier
= AARCH64_OPND_QLF_X
;
768 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
771 switch (TOLOWER (str
[1]))
774 *qualifier
= AARCH64_OPND_QLF_S_S
;
777 *qualifier
= AARCH64_OPND_QLF_S_D
;
794 /* Try to parse a base or offset register. Return the register entry
795 on success, setting *QUALIFIER to the register qualifier. Return null
798 Note that this function does not issue any diagnostics. */
800 static const reg_entry
*
801 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
803 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
806 /* Parse the qualifier of a vector register or vector element of type
807 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
808 succeeds; otherwise return FALSE.
810 Accept only one occurrence of:
811 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
814 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
815 struct vector_type_el
*parsed_type
, char **str
)
819 unsigned element_size
;
820 enum vector_el_type type
;
823 gas_assert (*ptr
== '.');
826 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
831 width
= strtoul (ptr
, &ptr
, 10);
832 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
834 first_error_fmt (_("bad size %d in vector width specifier"), width
);
839 switch (TOLOWER (*ptr
))
858 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
867 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
869 first_error (_("missing element size"));
872 if (width
!= 0 && width
* element_size
!= 64
873 && width
* element_size
!= 128
874 && !(width
== 2 && element_size
== 16)
875 && !(width
== 4 && element_size
== 8))
878 ("invalid element size %d and vector size combination %c"),
884 parsed_type
->type
= type
;
885 parsed_type
->width
= width
;
892 /* *STR contains an SVE zero/merge predication suffix. Parse it into
893 *PARSED_TYPE and point *STR at the end of the suffix. */
896 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
901 gas_assert (*ptr
== '/');
903 switch (TOLOWER (*ptr
))
906 parsed_type
->type
= NT_zero
;
909 parsed_type
->type
= NT_merge
;
912 if (*ptr
!= '\0' && *ptr
!= ',')
913 first_error_fmt (_("unexpected character `%c' in predication type"),
916 first_error (_("missing predication type"));
919 parsed_type
->width
= 0;
924 /* Parse a register of the type TYPE.
926 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
927 name or the parsed register is not of TYPE.
929 Otherwise return the register number, and optionally fill in the actual
930 type of the register in *RTYPE when multiple alternatives were given, and
931 return the register shape and element index information in *TYPEINFO.
933 IN_REG_LIST should be set with TRUE if the caller is parsing a register
937 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
938 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
941 const reg_entry
*reg
= parse_reg (&str
);
942 struct vector_type_el atype
;
943 struct vector_type_el parsetype
;
944 bfd_boolean is_typed_vecreg
= FALSE
;
947 atype
.type
= NT_invtype
;
955 set_default_error ();
959 if (! aarch64_check_reg_type (reg
, type
))
961 DEBUG_TRACE ("reg type check failed");
962 set_default_error ();
967 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
968 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
972 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
977 if (!parse_predication_for_operand (&parsetype
, &str
))
981 /* Register if of the form Vn.[bhsdq]. */
982 is_typed_vecreg
= TRUE
;
984 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
986 /* The width is always variable; we don't allow an integer width
988 gas_assert (parsetype
.width
== 0);
989 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
991 else if (parsetype
.width
== 0)
992 /* Expect index. In the new scheme we cannot have
993 Vn.[bhsdq] represent a scalar. Therefore any
994 Vn.[bhsdq] should have an index following it.
995 Except in reglists of course. */
996 atype
.defined
|= NTA_HASINDEX
;
998 atype
.defined
|= NTA_HASTYPE
;
1000 atype
.type
= parsetype
.type
;
1001 atype
.width
= parsetype
.width
;
1004 if (skip_past_char (&str
, '['))
1008 /* Reject Sn[index] syntax. */
1009 if (!is_typed_vecreg
)
1011 first_error (_("this type of register can't be indexed"));
1017 first_error (_("index not allowed inside register list"));
1021 atype
.defined
|= NTA_HASINDEX
;
1023 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1025 if (exp
.X_op
!= O_constant
)
1027 first_error (_("constant expression required"));
1031 if (! skip_past_char (&str
, ']'))
1034 atype
.index
= exp
.X_add_number
;
1036 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1038 /* Indexed vector register expected. */
1039 first_error (_("indexed vector register expected"));
1043 /* A vector reg Vn should be typed or indexed. */
1044 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1046 first_error (_("invalid use of vector register"));
1062 Return the register number on success; return PARSE_FAIL otherwise.
1064 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1065 the register (e.g. NEON double or quad reg when either has been requested).
1067 If this is a NEON vector register with additional type information, fill
1068 in the struct pointed to by VECTYPE (if non-NULL).
1070 This parser does not handle register list. */
1073 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1074 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1076 struct vector_type_el atype
;
1078 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1079 /*in_reg_list= */ FALSE
);
1081 if (reg
== PARSE_FAIL
)
1092 static inline bfd_boolean
1093 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1097 && e1
.defined
== e2
.defined
1098 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1101 /* This function parses a list of vector registers of type TYPE.
1102 On success, it returns the parsed register list information in the
1103 following encoded format:
1105 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1106 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1108 The information of the register shape and/or index is returned in
1111 It returns PARSE_FAIL if the register list is invalid.
1113 The list contains one to four registers.
1114 Each register can be one of:
1117 All <T> should be identical.
1118 All <index> should be identical.
1119 There are restrictions on <Vt> numbers which are checked later
1120 (by reg_list_valid_p). */
1123 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1124 struct vector_type_el
*vectype
)
1128 struct vector_type_el typeinfo
, typeinfo_first
;
1133 bfd_boolean error
= FALSE
;
1134 bfd_boolean expect_index
= FALSE
;
1138 set_syntax_error (_("expecting {"));
1144 typeinfo_first
.defined
= 0;
1145 typeinfo_first
.type
= NT_invtype
;
1146 typeinfo_first
.width
= -1;
1147 typeinfo_first
.index
= 0;
1156 str
++; /* skip over '-' */
1159 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1160 /*in_reg_list= */ TRUE
);
1161 if (val
== PARSE_FAIL
)
1163 set_first_syntax_error (_("invalid vector register in list"));
1167 /* reject [bhsd]n */
1168 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1170 set_first_syntax_error (_("invalid scalar register in list"));
1175 if (typeinfo
.defined
& NTA_HASINDEX
)
1176 expect_index
= TRUE
;
1180 if (val
< val_range
)
1182 set_first_syntax_error
1183 (_("invalid range in vector register list"));
1192 typeinfo_first
= typeinfo
;
1193 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1195 set_first_syntax_error
1196 (_("type mismatch in vector register list"));
1201 for (i
= val_range
; i
<= val
; i
++)
1203 ret_val
|= i
<< (5 * nb_regs
);
1208 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1210 skip_whitespace (str
);
1213 set_first_syntax_error (_("end of vector register list not found"));
1218 skip_whitespace (str
);
1222 if (skip_past_char (&str
, '['))
1226 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1227 if (exp
.X_op
!= O_constant
)
1229 set_first_syntax_error (_("constant expression required."));
1232 if (! skip_past_char (&str
, ']'))
1235 typeinfo_first
.index
= exp
.X_add_number
;
1239 set_first_syntax_error (_("expected index"));
1246 set_first_syntax_error (_("too many registers in vector register list"));
1249 else if (nb_regs
== 0)
1251 set_first_syntax_error (_("empty vector register list"));
1257 *vectype
= typeinfo_first
;
1259 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1262 /* Directives: register aliases. */
1265 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1270 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1273 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1276 /* Only warn about a redefinition if it's not defined as the
1278 else if (new->number
!= number
|| new->type
!= type
)
1279 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1284 name
= xstrdup (str
);
1285 new = XNEW (reg_entry
);
1288 new->number
= number
;
1290 new->builtin
= FALSE
;
1292 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1298 /* Look for the .req directive. This is of the form:
1300 new_register_name .req existing_register_name
1302 If we find one, or if it looks sufficiently like one that we want to
1303 handle any error here, return TRUE. Otherwise return FALSE. */
1306 create_register_alias (char *newname
, char *p
)
1308 const reg_entry
*old
;
1309 char *oldname
, *nbuf
;
1312 /* The input scrubber ensures that whitespace after the mnemonic is
1313 collapsed to single spaces. */
1315 if (strncmp (oldname
, " .req ", 6) != 0)
1319 if (*oldname
== '\0')
1322 old
= hash_find (aarch64_reg_hsh
, oldname
);
1325 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1329 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1330 the desired alias name, and p points to its end. If not, then
1331 the desired alias name is in the global original_case_string. */
1332 #ifdef TC_CASE_SENSITIVE
1335 newname
= original_case_string
;
1336 nlen
= strlen (newname
);
1339 nbuf
= xmemdup0 (newname
, nlen
);
1341 /* Create aliases under the new name as stated; an all-lowercase
1342 version of the new name; and an all-uppercase version of the new
1344 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1346 for (p
= nbuf
; *p
; p
++)
1349 if (strncmp (nbuf
, newname
, nlen
))
1351 /* If this attempt to create an additional alias fails, do not bother
1352 trying to create the all-lower case alias. We will fail and issue
1353 a second, duplicate error message. This situation arises when the
1354 programmer does something like:
1357 The second .req creates the "Foo" alias but then fails to create
1358 the artificial FOO alias because it has already been created by the
1360 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1367 for (p
= nbuf
; *p
; p
++)
1370 if (strncmp (nbuf
, newname
, nlen
))
1371 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1378 /* Should never be called, as .req goes between the alias and the
1379 register name, not at the beginning of the line. */
1381 s_req (int a ATTRIBUTE_UNUSED
)
1383 as_bad (_("invalid syntax for .req directive"));
1386 /* The .unreq directive deletes an alias which was previously defined
1387 by .req. For example:
1393 s_unreq (int a ATTRIBUTE_UNUSED
)
1398 name
= input_line_pointer
;
1400 while (*input_line_pointer
!= 0
1401 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1402 ++input_line_pointer
;
1404 saved_char
= *input_line_pointer
;
1405 *input_line_pointer
= 0;
1408 as_bad (_("invalid syntax for .unreq directive"));
1411 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1414 as_bad (_("unknown register alias '%s'"), name
);
1415 else if (reg
->builtin
)
1416 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1423 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1424 free ((char *) reg
->name
);
1427 /* Also locate the all upper case and all lower case versions.
1428 Do not complain if we cannot find one or the other as it
1429 was probably deleted above. */
1431 nbuf
= strdup (name
);
1432 for (p
= nbuf
; *p
; p
++)
1434 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1437 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1438 free ((char *) reg
->name
);
1442 for (p
= nbuf
; *p
; p
++)
1444 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1447 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1448 free ((char *) reg
->name
);
1456 *input_line_pointer
= saved_char
;
1457 demand_empty_rest_of_line ();
1460 /* Directives: Instruction set selection. */
1463 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1464 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1465 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1466 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1468 /* Create a new mapping symbol for the transition to STATE. */
1471 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1474 const char *symname
;
1481 type
= BSF_NO_FLAGS
;
1485 type
= BSF_NO_FLAGS
;
1491 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1492 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1494 /* Save the mapping symbols for future reference. Also check that
1495 we do not place two mapping symbols at the same offset within a
1496 frag. We'll handle overlap between frags in
1497 check_mapping_symbols.
1499 If .fill or other data filling directive generates zero sized data,
1500 the mapping symbol for the following code will have the same value
1501 as the one generated for the data filling directive. In this case,
1502 we replace the old symbol with the new one at the same address. */
1505 if (frag
->tc_frag_data
.first_map
!= NULL
)
1507 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1508 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1511 frag
->tc_frag_data
.first_map
= symbolP
;
1513 if (frag
->tc_frag_data
.last_map
!= NULL
)
1515 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1516 S_GET_VALUE (symbolP
));
1517 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1518 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1521 frag
->tc_frag_data
.last_map
= symbolP
;
1524 /* We must sometimes convert a region marked as code to data during
1525 code alignment, if an odd number of bytes have to be padded. The
1526 code mapping symbol is pushed to an aligned address. */
1529 insert_data_mapping_symbol (enum mstate state
,
1530 valueT value
, fragS
* frag
, offsetT bytes
)
1532 /* If there was already a mapping symbol, remove it. */
1533 if (frag
->tc_frag_data
.last_map
!= NULL
1534 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1535 frag
->fr_address
+ value
)
1537 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1541 know (frag
->tc_frag_data
.first_map
== symp
);
1542 frag
->tc_frag_data
.first_map
= NULL
;
1544 frag
->tc_frag_data
.last_map
= NULL
;
1545 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1548 make_mapping_symbol (MAP_DATA
, value
, frag
);
1549 make_mapping_symbol (state
, value
+ bytes
, frag
);
1552 static void mapping_state_2 (enum mstate state
, int max_chars
);
1554 /* Set the mapping state to STATE. Only call this when about to
1555 emit some STATE bytes to the file. */
1558 mapping_state (enum mstate state
)
1560 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1562 if (state
== MAP_INSN
)
1563 /* AArch64 instructions require 4-byte alignment. When emitting
1564 instructions into any section, record the appropriate section
1566 record_alignment (now_seg
, 2);
1568 if (mapstate
== state
)
1569 /* The mapping symbol has already been emitted.
1570 There is nothing else to do. */
1573 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1574 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1575 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1576 evaluated later in the next else. */
1578 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1580 /* Only add the symbol if the offset is > 0:
1581 if we're at the first frag, check it's size > 0;
1582 if we're not at the first frag, then for sure
1583 the offset is > 0. */
1584 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1585 const int add_symbol
= (frag_now
!= frag_first
)
1586 || (frag_now_fix () > 0);
1589 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1593 mapping_state_2 (state
, 0);
1596 /* Same as mapping_state, but MAX_CHARS bytes have already been
1597 allocated. Put the mapping symbol that far back. */
1600 mapping_state_2 (enum mstate state
, int max_chars
)
1602 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1604 if (!SEG_NORMAL (now_seg
))
1607 if (mapstate
== state
)
1608 /* The mapping symbol has already been emitted.
1609 There is nothing else to do. */
1612 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1613 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1616 #define mapping_state(x) /* nothing */
1617 #define mapping_state_2(x, y) /* nothing */
1620 /* Directives: sectioning and alignment. */
1623 s_bss (int ignore ATTRIBUTE_UNUSED
)
1625 /* We don't support putting frags in the BSS segment, we fake it by
1626 marking in_bss, then looking at s_skip for clues. */
1627 subseg_set (bss_section
, 0);
1628 demand_empty_rest_of_line ();
1629 mapping_state (MAP_DATA
);
1633 s_even (int ignore ATTRIBUTE_UNUSED
)
1635 /* Never make frag if expect extra pass. */
1637 frag_align (1, 0, 0);
1639 record_alignment (now_seg
, 1);
1641 demand_empty_rest_of_line ();
1644 /* Directives: Literal pools. */
1646 static literal_pool
*
1647 find_literal_pool (int size
)
1651 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1653 if (pool
->section
== now_seg
1654 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1661 static literal_pool
*
1662 find_or_make_literal_pool (int size
)
1664 /* Next literal pool ID number. */
1665 static unsigned int latest_pool_num
= 1;
1668 pool
= find_literal_pool (size
);
1672 /* Create a new pool. */
1673 pool
= XNEW (literal_pool
);
1677 /* Currently we always put the literal pool in the current text
1678 section. If we were generating "small" model code where we
1679 knew that all code and initialised data was within 1MB then
1680 we could output literals to mergeable, read-only data
1683 pool
->next_free_entry
= 0;
1684 pool
->section
= now_seg
;
1685 pool
->sub_section
= now_subseg
;
1687 pool
->next
= list_of_pools
;
1688 pool
->symbol
= NULL
;
1690 /* Add it to the list. */
1691 list_of_pools
= pool
;
1694 /* New pools, and emptied pools, will have a NULL symbol. */
1695 if (pool
->symbol
== NULL
)
1697 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1698 (valueT
) 0, &zero_address_frag
);
1699 pool
->id
= latest_pool_num
++;
1706 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1707 Return TRUE on success, otherwise return FALSE. */
1709 add_to_lit_pool (expressionS
*exp
, int size
)
1714 pool
= find_or_make_literal_pool (size
);
1716 /* Check if this literal value is already in the pool. */
1717 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1719 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1721 if ((litexp
->X_op
== exp
->X_op
)
1722 && (exp
->X_op
== O_constant
)
1723 && (litexp
->X_add_number
== exp
->X_add_number
)
1724 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1727 if ((litexp
->X_op
== exp
->X_op
)
1728 && (exp
->X_op
== O_symbol
)
1729 && (litexp
->X_add_number
== exp
->X_add_number
)
1730 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1731 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1735 /* Do we need to create a new entry? */
1736 if (entry
== pool
->next_free_entry
)
1738 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1740 set_syntax_error (_("literal pool overflow"));
1744 pool
->literals
[entry
].exp
= *exp
;
1745 pool
->next_free_entry
+= 1;
1746 if (exp
->X_op
== O_big
)
1748 /* PR 16688: Bignums are held in a single global array. We must
1749 copy and preserve that value now, before it is overwritten. */
1750 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1752 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1753 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1756 pool
->literals
[entry
].bignum
= NULL
;
1759 exp
->X_op
= O_symbol
;
1760 exp
->X_add_number
= ((int) entry
) * size
;
1761 exp
->X_add_symbol
= pool
->symbol
;
1766 /* Can't use symbol_new here, so have to create a symbol and then at
1767 a later date assign it a value. That's what these functions do. */
1770 symbol_locate (symbolS
* symbolP
,
1771 const char *name
,/* It is copied, the caller can modify. */
1772 segT segment
, /* Segment identifier (SEG_<something>). */
1773 valueT valu
, /* Symbol value. */
1774 fragS
* frag
) /* Associated fragment. */
1777 char *preserved_copy_of_name
;
1779 name_length
= strlen (name
) + 1; /* +1 for \0. */
1780 obstack_grow (¬es
, name
, name_length
);
1781 preserved_copy_of_name
= obstack_finish (¬es
);
1783 #ifdef tc_canonicalize_symbol_name
1784 preserved_copy_of_name
=
1785 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1788 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1790 S_SET_SEGMENT (symbolP
, segment
);
1791 S_SET_VALUE (symbolP
, valu
);
1792 symbol_clear_list_pointers (symbolP
);
1794 symbol_set_frag (symbolP
, frag
);
1796 /* Link to end of symbol chain. */
1798 extern int symbol_table_frozen
;
1800 if (symbol_table_frozen
)
1804 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1806 obj_symbol_new_hook (symbolP
);
1808 #ifdef tc_symbol_new_hook
1809 tc_symbol_new_hook (symbolP
);
1813 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1814 #endif /* DEBUG_SYMS */
1819 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1826 for (align
= 2; align
<= 4; align
++)
1828 int size
= 1 << align
;
1830 pool
= find_literal_pool (size
);
1831 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1834 /* Align pool as you have word accesses.
1835 Only make a frag if we have to. */
1837 frag_align (align
, 0, 0);
1839 mapping_state (MAP_DATA
);
1841 record_alignment (now_seg
, align
);
1843 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1845 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1846 (valueT
) frag_now_fix (), frag_now
);
1847 symbol_table_insert (pool
->symbol
);
1849 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1851 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1853 if (exp
->X_op
== O_big
)
1855 /* PR 16688: Restore the global bignum value. */
1856 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1857 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1858 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1861 /* First output the expression in the instruction to the pool. */
1862 emit_expr (exp
, size
); /* .word|.xword */
1864 if (exp
->X_op
== O_big
)
1866 free (pool
->literals
[entry
].bignum
);
1867 pool
->literals
[entry
].bignum
= NULL
;
1871 /* Mark the pool as empty. */
1872 pool
->next_free_entry
= 0;
1873 pool
->symbol
= NULL
;
1878 /* Forward declarations for functions below, in the MD interface
1880 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1881 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1883 /* Directives: Data. */
1884 /* N.B. the support for relocation suffix in this directive needs to be
1885 implemented properly. */
1888 s_aarch64_elf_cons (int nbytes
)
1892 #ifdef md_flush_pending_output
1893 md_flush_pending_output ();
1896 if (is_it_end_of_statement ())
1898 demand_empty_rest_of_line ();
1902 #ifdef md_cons_align
1903 md_cons_align (nbytes
);
1906 mapping_state (MAP_DATA
);
1909 struct reloc_table_entry
*reloc
;
1913 if (exp
.X_op
!= O_symbol
)
1914 emit_expr (&exp
, (unsigned int) nbytes
);
1917 skip_past_char (&input_line_pointer
, '#');
1918 if (skip_past_char (&input_line_pointer
, ':'))
1920 reloc
= find_reloc_table_entry (&input_line_pointer
);
1922 as_bad (_("unrecognized relocation suffix"));
1924 as_bad (_("unimplemented relocation suffix"));
1925 ignore_rest_of_line ();
1929 emit_expr (&exp
, (unsigned int) nbytes
);
1932 while (*input_line_pointer
++ == ',');
1934 /* Put terminator back into stream. */
1935 input_line_pointer
--;
1936 demand_empty_rest_of_line ();
1939 /* Mark symbol that it follows a variant PCS convention. */
1942 s_variant_pcs (int ignored ATTRIBUTE_UNUSED
)
1948 elf_symbol_type
*elfsym
;
1950 c
= get_symbol_name (&name
);
1952 as_bad (_("Missing symbol name in directive"));
1953 sym
= symbol_find_or_make (name
);
1954 restore_line_pointer (c
);
1955 demand_empty_rest_of_line ();
1956 bfdsym
= symbol_get_bfdsym (sym
);
1957 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
1958 gas_assert (elfsym
);
1959 elfsym
->internal_elf_sym
.st_other
|= STO_AARCH64_VARIANT_PCS
;
1961 #endif /* OBJ_ELF */
1963 /* Output a 32-bit word, but mark as an instruction. */
1966 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1970 #ifdef md_flush_pending_output
1971 md_flush_pending_output ();
1974 if (is_it_end_of_statement ())
1976 demand_empty_rest_of_line ();
1980 /* Sections are assumed to start aligned. In executable section, there is no
1981 MAP_DATA symbol pending. So we only align the address during
1982 MAP_DATA --> MAP_INSN transition.
1983 For other sections, this is not guaranteed. */
1984 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1985 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1986 frag_align_code (2, 0);
1989 mapping_state (MAP_INSN
);
1995 if (exp
.X_op
!= O_constant
)
1997 as_bad (_("constant expression required"));
1998 ignore_rest_of_line ();
2002 if (target_big_endian
)
2004 unsigned int val
= exp
.X_add_number
;
2005 exp
.X_add_number
= SWAP_32 (val
);
2007 emit_expr (&exp
, 4);
2009 while (*input_line_pointer
++ == ',');
2011 /* Put terminator back into stream. */
2012 input_line_pointer
--;
2013 demand_empty_rest_of_line ();
2017 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
2019 demand_empty_rest_of_line ();
2020 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2021 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2025 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2028 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2034 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2035 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2037 demand_empty_rest_of_line ();
2040 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2043 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2047 /* Since we're just labelling the code, there's no need to define a
2050 /* Make sure there is enough room in this frag for the following
2051 blr. This trick only works if the blr follows immediately after
2052 the .tlsdesc directive. */
2054 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2055 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2057 demand_empty_rest_of_line ();
2060 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2063 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2069 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2070 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2072 demand_empty_rest_of_line ();
2074 #endif /* OBJ_ELF */
2076 static void s_aarch64_arch (int);
2077 static void s_aarch64_cpu (int);
2078 static void s_aarch64_arch_extension (int);
2080 /* This table describes all the machine specific pseudo-ops the assembler
2081 has to support. The fields are:
2082 pseudo-op name without dot
2083 function to call to execute this pseudo-op
2084 Integer arg to pass to the function. */
2086 const pseudo_typeS md_pseudo_table
[] = {
2087 /* Never called because '.req' does not start a line. */
2089 {"unreq", s_unreq
, 0},
2091 {"even", s_even
, 0},
2092 {"ltorg", s_ltorg
, 0},
2093 {"pool", s_ltorg
, 0},
2094 {"cpu", s_aarch64_cpu
, 0},
2095 {"arch", s_aarch64_arch
, 0},
2096 {"arch_extension", s_aarch64_arch_extension
, 0},
2097 {"inst", s_aarch64_inst
, 0},
2098 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2100 {"tlsdescadd", s_tlsdescadd
, 0},
2101 {"tlsdesccall", s_tlsdesccall
, 0},
2102 {"tlsdescldr", s_tlsdescldr
, 0},
2103 {"word", s_aarch64_elf_cons
, 4},
2104 {"long", s_aarch64_elf_cons
, 4},
2105 {"xword", s_aarch64_elf_cons
, 8},
2106 {"dword", s_aarch64_elf_cons
, 8},
2107 {"variant_pcs", s_variant_pcs
, 0},
2109 {"float16", float_cons
, 'h'},
2114 /* Check whether STR points to a register name followed by a comma or the
2115 end of line; REG_TYPE indicates which register types are checked
2116 against. Return TRUE if STR is such a register name; otherwise return
2117 FALSE. The function does not intend to produce any diagnostics, but since
2118 the register parser aarch64_reg_parse, which is called by this function,
2119 does produce diagnostics, we call clear_error to clear any diagnostics
2120 that may be generated by aarch64_reg_parse.
2121 Also, the function returns FALSE directly if there is any user error
2122 present at the function entry. This prevents the existing diagnostics
2123 state from being spoiled.
2124 The function currently serves parse_constant_immediate and
2125 parse_big_immediate only. */
2127 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2131 /* Prevent the diagnostics state from being spoiled. */
2135 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2137 /* Clear the parsing error that may be set by the reg parser. */
2140 if (reg
== PARSE_FAIL
)
2143 skip_whitespace (str
);
2144 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2150 /* Parser functions used exclusively in instruction operands. */
2152 /* Parse an immediate expression which may not be constant.
2154 To prevent the expression parser from pushing a register name
2155 into the symbol table as an undefined symbol, firstly a check is
2156 done to find out whether STR is a register of type REG_TYPE followed
2157 by a comma or the end of line. Return FALSE if STR is such a string. */
2160 parse_immediate_expression (char **str
, expressionS
*exp
,
2161 aarch64_reg_type reg_type
)
2163 if (reg_name_p (*str
, reg_type
))
2165 set_recoverable_error (_("immediate operand required"));
2169 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2171 if (exp
->X_op
== O_absent
)
2173 set_fatal_syntax_error (_("missing immediate expression"));
2180 /* Constant immediate-value read function for use in insn parsing.
2181 STR points to the beginning of the immediate (with the optional
2182 leading #); *VAL receives the value. REG_TYPE says which register
2183 names should be treated as registers rather than as symbolic immediates.
2185 Return TRUE on success; otherwise return FALSE. */
2188 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2192 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2195 if (exp
.X_op
!= O_constant
)
2197 set_syntax_error (_("constant expression required"));
2201 *val
= exp
.X_add_number
;
2206 encode_imm_float_bits (uint32_t imm
)
2208 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2209 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2212 /* Return TRUE if the single-precision floating-point value encoded in IMM
2213 can be expressed in the AArch64 8-bit signed floating-point format with
2214 3-bit exponent and normalized 4 bits of precision; in other words, the
2215 floating-point value must be expressable as
2216 (+/-) n / 16 * power (2, r)
2217 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2220 aarch64_imm_float_p (uint32_t imm
)
2222 /* If a single-precision floating-point value has the following bit
2223 pattern, it can be expressed in the AArch64 8-bit floating-point
2226 3 32222222 2221111111111
2227 1 09876543 21098765432109876543210
2228 n Eeeeeexx xxxx0000000000000000000
2230 where n, e and each x are either 0 or 1 independently, with
2235 /* Prepare the pattern for 'Eeeeee'. */
2236 if (((imm
>> 30) & 0x1) == 0)
2237 pattern
= 0x3e000000;
2239 pattern
= 0x40000000;
2241 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2242 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2245 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2246 as an IEEE float without any loss of precision. Store the value in
2250 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2252 /* If a double-precision floating-point value has the following bit
2253 pattern, it can be expressed in a float:
2255 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2256 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2257 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2259 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2260 if Eeee_eeee != 1111_1111
2262 where n, e, s and S are either 0 or 1 independently and where ~ is the
2266 uint32_t high32
= imm
>> 32;
2267 uint32_t low32
= imm
;
2269 /* Lower 29 bits need to be 0s. */
2270 if ((imm
& 0x1fffffff) != 0)
2273 /* Prepare the pattern for 'Eeeeeeeee'. */
2274 if (((high32
>> 30) & 0x1) == 0)
2275 pattern
= 0x38000000;
2277 pattern
= 0x40000000;
2280 if ((high32
& 0x78000000) != pattern
)
2283 /* Check Eeee_eeee != 1111_1111. */
2284 if ((high32
& 0x7ff00000) == 0x47f00000)
2287 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2288 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2289 | (low32
>> 29)); /* 3 S bits. */
2293 /* Return true if we should treat OPERAND as a double-precision
2294 floating-point operand rather than a single-precision one. */
2296 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2298 /* Check for unsuffixed SVE registers, which are allowed
2299 for LDR and STR but not in instructions that require an
2300 immediate. We get better error messages if we arbitrarily
2301 pick one size, parse the immediate normally, and then
2302 report the match failure in the normal way. */
2303 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2304 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2307 /* Parse a floating-point immediate. Return TRUE on success and return the
2308 value in *IMMED in the format of IEEE754 single-precision encoding.
2309 *CCP points to the start of the string; DP_P is TRUE when the immediate
2310 is expected to be in double-precision (N.B. this only matters when
2311 hexadecimal representation is involved). REG_TYPE says which register
2312 names should be treated as registers rather than as symbolic immediates.
2314 This routine accepts any IEEE float; it is up to the callers to reject
2318 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2319 aarch64_reg_type reg_type
)
2323 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2325 unsigned fpword
= 0;
2326 bfd_boolean hex_p
= FALSE
;
2328 skip_past_char (&str
, '#');
2331 skip_whitespace (fpnum
);
2333 if (strncmp (fpnum
, "0x", 2) == 0)
2335 /* Support the hexadecimal representation of the IEEE754 encoding.
2336 Double-precision is expected when DP_P is TRUE, otherwise the
2337 representation should be in single-precision. */
2338 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2343 if (!can_convert_double_to_float (val
, &fpword
))
2346 else if ((uint64_t) val
> 0xffffffff)
2353 else if (reg_name_p (str
, reg_type
))
2355 set_recoverable_error (_("immediate operand required"));
2363 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2366 /* Our FP word must be 32 bits (single-precision FP). */
2367 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2369 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2379 set_fatal_syntax_error (_("invalid floating-point constant"));
2383 /* Less-generic immediate-value read function with the possibility of loading
2384 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2387 To prevent the expression parser from pushing a register name into the
2388 symbol table as an undefined symbol, a check is firstly done to find
2389 out whether STR is a register of type REG_TYPE followed by a comma or
2390 the end of line. Return FALSE if STR is such a register. */
2393 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2397 if (reg_name_p (ptr
, reg_type
))
2399 set_syntax_error (_("immediate operand required"));
2403 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2405 if (inst
.reloc
.exp
.X_op
== O_constant
)
2406 *imm
= inst
.reloc
.exp
.X_add_number
;
2413 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2414 if NEED_LIBOPCODES is non-zero, the fixup will need
2415 assistance from the libopcodes. */
2418 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2419 const aarch64_opnd_info
*operand
,
2420 int need_libopcodes_p
)
2422 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2423 reloc
->opnd
= operand
->type
;
2424 if (need_libopcodes_p
)
2425 reloc
->need_libopcodes_p
= 1;
2428 /* Return TRUE if the instruction needs to be fixed up later internally by
2429 the GAS; otherwise return FALSE. */
2431 static inline bfd_boolean
2432 aarch64_gas_internal_fixup_p (void)
2434 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2437 /* Assign the immediate value to the relevant field in *OPERAND if
2438 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2439 needs an internal fixup in a later stage.
2440 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2441 IMM.VALUE that may get assigned with the constant. */
2443 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2444 aarch64_opnd_info
*operand
,
2446 int need_libopcodes_p
,
2449 if (reloc
->exp
.X_op
== O_constant
)
2452 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2454 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2455 reloc
->type
= BFD_RELOC_UNUSED
;
2459 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2460 /* Tell libopcodes to ignore this operand or not. This is helpful
2461 when one of the operands needs to be fixed up later but we need
2462 libopcodes to check the other operands. */
2463 operand
->skip
= skip_p
;
2467 /* Relocation modifiers. Each entry in the table contains the textual
2468 name for the relocation which may be placed before a symbol used as
2469 a load/store offset, or add immediate. It must be surrounded by a
2470 leading and trailing colon, for example:
2472 ldr x0, [x1, #:rello:varsym]
2473 add x0, x1, #:rello:varsym */
2475 struct reloc_table_entry
2479 bfd_reloc_code_real_type adr_type
;
2480 bfd_reloc_code_real_type adrp_type
;
2481 bfd_reloc_code_real_type movw_type
;
2482 bfd_reloc_code_real_type add_type
;
2483 bfd_reloc_code_real_type ldst_type
;
2484 bfd_reloc_code_real_type ld_literal_type
;
2487 static struct reloc_table_entry reloc_table
[] = {
2488 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2493 BFD_RELOC_AARCH64_ADD_LO12
,
2494 BFD_RELOC_AARCH64_LDST_LO12
,
2497 /* Higher 21 bits of pc-relative page offset: ADRP */
2500 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2506 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2509 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2515 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2519 BFD_RELOC_AARCH64_MOVW_G0
,
2524 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2528 BFD_RELOC_AARCH64_MOVW_G0_S
,
2533 /* Less significant bits 0-15 of address/value: MOVK, no check */
2537 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2542 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2546 BFD_RELOC_AARCH64_MOVW_G1
,
2551 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2555 BFD_RELOC_AARCH64_MOVW_G1_S
,
2560 /* Less significant bits 16-31 of address/value: MOVK, no check */
2564 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2569 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2573 BFD_RELOC_AARCH64_MOVW_G2
,
2578 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2582 BFD_RELOC_AARCH64_MOVW_G2_S
,
2587 /* Less significant bits 32-47 of address/value: MOVK, no check */
2591 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2596 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2600 BFD_RELOC_AARCH64_MOVW_G3
,
2605 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2609 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2614 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2618 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2623 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2627 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2632 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2636 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2641 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2645 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2650 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2654 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2659 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2663 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2668 /* Get to the page containing GOT entry for a symbol. */
2671 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2675 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2677 /* 12 bit offset into the page containing GOT entry for that symbol. */
2683 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2686 /* 0-15 bits of address/value: MOVk, no check. */
2690 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2695 /* Most significant bits 16-31 of address/value: MOVZ. */
2699 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2704 /* 15 bit offset into the page containing GOT entry for that symbol. */
2710 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2713 /* Get to the page containing GOT TLS entry for a symbol */
2714 {"gottprel_g0_nc", 0,
2717 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2722 /* Get to the page containing GOT TLS entry for a symbol */
2726 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2731 /* Get to the page containing GOT TLS entry for a symbol */
2733 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2734 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2740 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2745 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2749 /* Lower 16 bits address/value: MOVk. */
2753 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2758 /* Most significant bits 16-31 of address/value: MOVZ. */
2762 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2767 /* Get to the page containing GOT TLS entry for a symbol */
2769 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2770 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2774 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2776 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2781 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2782 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2785 /* Get to the page containing GOT TLS entry for a symbol.
2786 The same as GD, we allocate two consecutive GOT slots
2787 for module index and module offset, the only difference
2788 with GD is the module offset should be initialized to
2789 zero without any outstanding runtime relocation. */
2791 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2792 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2798 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2799 {"tlsldm_lo12_nc", 0,
2803 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2807 /* 12 bit offset into the module TLS base address. */
2812 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2813 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2816 /* Same as dtprel_lo12, no overflow check. */
2817 {"dtprel_lo12_nc", 0,
2821 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2822 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2825 /* bits[23:12] of offset to the module TLS base address. */
2830 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2834 /* bits[15:0] of offset to the module TLS base address. */
2838 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2843 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2847 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2852 /* bits[31:16] of offset to the module TLS base address. */
2856 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2861 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2865 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2870 /* bits[47:32] of offset to the module TLS base address. */
2874 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2879 /* Lower 16 bit offset into GOT entry for a symbol */
2880 {"tlsdesc_off_g0_nc", 0,
2883 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2888 /* Higher 16 bit offset into GOT entry for a symbol */
2889 {"tlsdesc_off_g1", 0,
2892 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2897 /* Get to the page containing GOT TLS entry for a symbol */
2900 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2904 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2906 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2907 {"gottprel_lo12", 0,
2912 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2915 /* Get tp offset for a symbol. */
2920 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2924 /* Get tp offset for a symbol. */
2929 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2930 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2933 /* Get tp offset for a symbol. */
2938 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2942 /* Get tp offset for a symbol. */
2943 {"tprel_lo12_nc", 0,
2947 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2948 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2951 /* Most significant bits 32-47 of address/value: MOVZ. */
2955 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2960 /* Most significant bits 16-31 of address/value: MOVZ. */
2964 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2969 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2973 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2978 /* Most significant bits 0-15 of address/value: MOVZ. */
2982 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2987 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2991 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2996 /* 15bit offset from got entry to base address of GOT table. */
3002 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
3005 /* 14bit offset from got entry to base address of GOT table. */
3011 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
3015 /* Given the address of a pointer pointing to the textual name of a
3016 relocation as may appear in assembler source, attempt to find its
3017 details in reloc_table. The pointer will be updated to the character
3018 after the trailing colon. On failure, NULL will be returned;
3019 otherwise return the reloc_table_entry. */
3021 static struct reloc_table_entry
*
3022 find_reloc_table_entry (char **str
)
3025 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3027 int length
= strlen (reloc_table
[i
].name
);
3029 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3030 && (*str
)[length
] == ':')
3032 *str
+= (length
+ 1);
3033 return &reloc_table
[i
];
3040 /* Mode argument to parse_shift and parser_shifter_operand. */
3041 enum parse_shift_mode
3043 SHIFTED_NONE
, /* no shifter allowed */
3044 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3046 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3048 SHIFTED_LSL
, /* bare "lsl #n" */
3049 SHIFTED_MUL
, /* bare "mul #n" */
3050 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3051 SHIFTED_MUL_VL
, /* "mul vl" */
3052 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3055 /* Parse a <shift> operator on an AArch64 data processing instruction.
3056 Return TRUE on success; otherwise return FALSE. */
3058 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3060 const struct aarch64_name_value_pair
*shift_op
;
3061 enum aarch64_modifier_kind kind
;
3067 for (p
= *str
; ISALPHA (*p
); p
++)
3072 set_syntax_error (_("shift expression expected"));
3076 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3078 if (shift_op
== NULL
)
3080 set_syntax_error (_("shift operator expected"));
3084 kind
= aarch64_get_operand_modifier (shift_op
);
3086 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3088 set_syntax_error (_("invalid use of 'MSL'"));
3092 if (kind
== AARCH64_MOD_MUL
3093 && mode
!= SHIFTED_MUL
3094 && mode
!= SHIFTED_MUL_VL
)
3096 set_syntax_error (_("invalid use of 'MUL'"));
3102 case SHIFTED_LOGIC_IMM
:
3103 if (aarch64_extend_operator_p (kind
))
3105 set_syntax_error (_("extending shift is not permitted"));
3110 case SHIFTED_ARITH_IMM
:
3111 if (kind
== AARCH64_MOD_ROR
)
3113 set_syntax_error (_("'ROR' shift is not permitted"));
3119 if (kind
!= AARCH64_MOD_LSL
)
3121 set_syntax_error (_("only 'LSL' shift is permitted"));
3127 if (kind
!= AARCH64_MOD_MUL
)
3129 set_syntax_error (_("only 'MUL' is permitted"));
3134 case SHIFTED_MUL_VL
:
3135 /* "MUL VL" consists of two separate tokens. Require the first
3136 token to be "MUL" and look for a following "VL". */
3137 if (kind
== AARCH64_MOD_MUL
)
3139 skip_whitespace (p
);
3140 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3143 kind
= AARCH64_MOD_MUL_VL
;
3147 set_syntax_error (_("only 'MUL VL' is permitted"));
3150 case SHIFTED_REG_OFFSET
:
3151 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3152 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3154 set_fatal_syntax_error
3155 (_("invalid shift for the register offset addressing mode"));
3160 case SHIFTED_LSL_MSL
:
3161 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3163 set_syntax_error (_("invalid shift operator"));
3172 /* Whitespace can appear here if the next thing is a bare digit. */
3173 skip_whitespace (p
);
3175 /* Parse shift amount. */
3177 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3178 exp
.X_op
= O_absent
;
3181 if (is_immediate_prefix (*p
))
3186 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3188 if (kind
== AARCH64_MOD_MUL_VL
)
3189 /* For consistency, give MUL VL the same shift amount as an implicit
3191 operand
->shifter
.amount
= 1;
3192 else if (exp
.X_op
== O_absent
)
3194 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3196 set_syntax_error (_("missing shift amount"));
3199 operand
->shifter
.amount
= 0;
3201 else if (exp
.X_op
!= O_constant
)
3203 set_syntax_error (_("constant shift amount required"));
3206 /* For parsing purposes, MUL #n has no inherent range. The range
3207 depends on the operand and will be checked by operand-specific
3209 else if (kind
!= AARCH64_MOD_MUL
3210 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3212 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3217 operand
->shifter
.amount
= exp
.X_add_number
;
3218 operand
->shifter
.amount_present
= 1;
3221 operand
->shifter
.operator_present
= 1;
3222 operand
->shifter
.kind
= kind
;
3228 /* Parse a <shifter_operand> for a data processing instruction:
3231 #<immediate>, LSL #imm
3233 Validation of immediate operands is deferred to md_apply_fix.
3235 Return TRUE on success; otherwise return FALSE. */
3238 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3239 enum parse_shift_mode mode
)
3243 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3248 /* Accept an immediate expression. */
3249 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3252 /* Accept optional LSL for arithmetic immediate values. */
3253 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3254 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3257 /* Not accept any shifter for logical immediate values. */
3258 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3259 && parse_shift (&p
, operand
, mode
))
3261 set_syntax_error (_("unexpected shift operator"));
3269 /* Parse a <shifter_operand> for a data processing instruction:
3274 #<immediate>, LSL #imm
3276 where <shift> is handled by parse_shift above, and the last two
3277 cases are handled by the function above.
3279 Validation of immediate operands is deferred to md_apply_fix.
3281 Return TRUE on success; otherwise return FALSE. */
3284 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3285 enum parse_shift_mode mode
)
3287 const reg_entry
*reg
;
3288 aarch64_opnd_qualifier_t qualifier
;
3289 enum aarch64_operand_class opd_class
3290 = aarch64_get_operand_class (operand
->type
);
3292 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3295 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3297 set_syntax_error (_("unexpected register in the immediate operand"));
3301 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3303 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3307 operand
->reg
.regno
= reg
->number
;
3308 operand
->qualifier
= qualifier
;
3310 /* Accept optional shift operation on register. */
3311 if (! skip_past_comma (str
))
3314 if (! parse_shift (str
, operand
, mode
))
3319 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3322 (_("integer register expected in the extended/shifted operand "
3327 /* We have a shifted immediate variable. */
3328 return parse_shifter_operand_imm (str
, operand
, mode
);
3331 /* Return TRUE on success; return FALSE otherwise. */
3334 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3335 enum parse_shift_mode mode
)
3339 /* Determine if we have the sequence of characters #: or just :
3340 coming next. If we do, then we check for a :rello: relocation
3341 modifier. If we don't, punt the whole lot to
3342 parse_shifter_operand. */
3344 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3346 struct reloc_table_entry
*entry
;
3354 /* Try to parse a relocation. Anything else is an error. */
3355 if (!(entry
= find_reloc_table_entry (str
)))
3357 set_syntax_error (_("unknown relocation modifier"));
3361 if (entry
->add_type
== 0)
3364 (_("this relocation modifier is not allowed on this instruction"));
3368 /* Save str before we decompose it. */
3371 /* Next, we parse the expression. */
3372 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3375 /* Record the relocation type (use the ADD variant here). */
3376 inst
.reloc
.type
= entry
->add_type
;
3377 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3379 /* If str is empty, we've reached the end, stop here. */
3383 /* Otherwise, we have a shifted reloc modifier, so rewind to
3384 recover the variable name and continue parsing for the shifter. */
3386 return parse_shifter_operand_imm (str
, operand
, mode
);
3389 return parse_shifter_operand (str
, operand
, mode
);
3392 /* Parse all forms of an address expression. Information is written
3393 to *OPERAND and/or inst.reloc.
3395 The A64 instruction set has the following addressing modes:
3398 [base] // in SIMD ld/st structure
3399 [base{,#0}] // in ld/st exclusive
3401 [base,Xm{,LSL #imm}]
3402 [base,Xm,SXTX {#imm}]
3403 [base,Wm,(S|U)XTW {#imm}]
3408 [base],Xm // in SIMD ld/st structure
3409 PC-relative (literal)
3413 [base,Zm.D{,LSL #imm}]
3414 [base,Zm.S,(S|U)XTW {#imm}]
3415 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3419 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3420 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3421 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3423 (As a convenience, the notation "=immediate" is permitted in conjunction
3424 with the pc-relative literal load instructions to automatically place an
3425 immediate value or symbolic address in a nearby literal pool and generate
3426 a hidden label which references it.)
3428 Upon a successful parsing, the address structure in *OPERAND will be
3429 filled in the following way:
3431 .base_regno = <base>
3432 .offset.is_reg // 1 if the offset is a register
3434 .offset.regno = <Rm>
3436 For different addressing modes defined in the A64 ISA:
3439 .pcrel=0; .preind=1; .postind=0; .writeback=0
3441 .pcrel=0; .preind=1; .postind=0; .writeback=1
3443 .pcrel=0; .preind=0; .postind=1; .writeback=1
3444 PC-relative (literal)
3445 .pcrel=1; .preind=1; .postind=0; .writeback=0
3447 The shift/extension information, if any, will be stored in .shifter.
3448 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3449 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3450 corresponding register.
3452 BASE_TYPE says which types of base register should be accepted and
3453 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3454 is the type of shifter that is allowed for immediate offsets,
3455 or SHIFTED_NONE if none.
3457 In all other respects, it is the caller's responsibility to check
3458 for addressing modes not supported by the instruction, and to set
3462 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3463 aarch64_opnd_qualifier_t
*base_qualifier
,
3464 aarch64_opnd_qualifier_t
*offset_qualifier
,
3465 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3466 enum parse_shift_mode imm_shift_mode
)
3469 const reg_entry
*reg
;
3470 expressionS
*exp
= &inst
.reloc
.exp
;
3472 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3473 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3474 if (! skip_past_char (&p
, '['))
3476 /* =immediate or label. */
3477 operand
->addr
.pcrel
= 1;
3478 operand
->addr
.preind
= 1;
3480 /* #:<reloc_op>:<symbol> */
3481 skip_past_char (&p
, '#');
3482 if (skip_past_char (&p
, ':'))
3484 bfd_reloc_code_real_type ty
;
3485 struct reloc_table_entry
*entry
;
3487 /* Try to parse a relocation modifier. Anything else is
3489 entry
= find_reloc_table_entry (&p
);
3492 set_syntax_error (_("unknown relocation modifier"));
3496 switch (operand
->type
)
3498 case AARCH64_OPND_ADDR_PCREL21
:
3500 ty
= entry
->adr_type
;
3504 ty
= entry
->ld_literal_type
;
3511 (_("this relocation modifier is not allowed on this "
3517 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3519 set_syntax_error (_("invalid relocation expression"));
3523 /* #:<reloc_op>:<expr> */
3524 /* Record the relocation type. */
3525 inst
.reloc
.type
= ty
;
3526 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3531 if (skip_past_char (&p
, '='))
3532 /* =immediate; need to generate the literal in the literal pool. */
3533 inst
.gen_lit_pool
= 1;
3535 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3537 set_syntax_error (_("invalid address"));
3548 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3549 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3551 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3554 operand
->addr
.base_regno
= reg
->number
;
3557 if (skip_past_comma (&p
))
3560 operand
->addr
.preind
= 1;
3562 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3565 if (!aarch64_check_reg_type (reg
, offset_type
))
3567 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3572 operand
->addr
.offset
.regno
= reg
->number
;
3573 operand
->addr
.offset
.is_reg
= 1;
3574 /* Shifted index. */
3575 if (skip_past_comma (&p
))
3578 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3579 /* Use the diagnostics set in parse_shift, so not set new
3580 error message here. */
3584 [base,Xm] # For vector plus scalar SVE2 indexing.
3585 [base,Xm{,LSL #imm}]
3586 [base,Xm,SXTX {#imm}]
3587 [base,Wm,(S|U)XTW {#imm}] */
3588 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3589 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3590 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3592 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3594 set_syntax_error (_("invalid use of 32-bit register offset"));
3597 if (aarch64_get_qualifier_esize (*base_qualifier
)
3598 != aarch64_get_qualifier_esize (*offset_qualifier
)
3599 && (operand
->type
!= AARCH64_OPND_SVE_ADDR_ZX
3600 || *base_qualifier
!= AARCH64_OPND_QLF_S_S
3601 || *offset_qualifier
!= AARCH64_OPND_QLF_X
))
3603 set_syntax_error (_("offset has different size from base"));
3607 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3609 set_syntax_error (_("invalid use of 64-bit register offset"));
3615 /* [Xn,#:<reloc_op>:<symbol> */
3616 skip_past_char (&p
, '#');
3617 if (skip_past_char (&p
, ':'))
3619 struct reloc_table_entry
*entry
;
3621 /* Try to parse a relocation modifier. Anything else is
3623 if (!(entry
= find_reloc_table_entry (&p
)))
3625 set_syntax_error (_("unknown relocation modifier"));
3629 if (entry
->ldst_type
== 0)
3632 (_("this relocation modifier is not allowed on this "
3637 /* [Xn,#:<reloc_op>: */
3638 /* We now have the group relocation table entry corresponding to
3639 the name in the assembler source. Next, we parse the
3641 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3643 set_syntax_error (_("invalid relocation expression"));
3647 /* [Xn,#:<reloc_op>:<expr> */
3648 /* Record the load/store relocation type. */
3649 inst
.reloc
.type
= entry
->ldst_type
;
3650 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3654 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3656 set_syntax_error (_("invalid expression in the address"));
3660 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3661 /* [Xn,<expr>,<shifter> */
3662 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3668 if (! skip_past_char (&p
, ']'))
3670 set_syntax_error (_("']' expected"));
3674 if (skip_past_char (&p
, '!'))
3676 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3678 set_syntax_error (_("register offset not allowed in pre-indexed "
3679 "addressing mode"));
3683 operand
->addr
.writeback
= 1;
3685 else if (skip_past_comma (&p
))
3688 operand
->addr
.postind
= 1;
3689 operand
->addr
.writeback
= 1;
3691 if (operand
->addr
.preind
)
3693 set_syntax_error (_("cannot combine pre- and post-indexing"));
3697 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3701 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3703 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3707 operand
->addr
.offset
.regno
= reg
->number
;
3708 operand
->addr
.offset
.is_reg
= 1;
3710 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3713 set_syntax_error (_("invalid expression in the address"));
3718 /* If at this point neither .preind nor .postind is set, we have a
3719 bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0].
3720 For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
3722 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3724 if (operand
->addr
.writeback
)
3727 set_syntax_error (_("missing offset in the pre-indexed address"));
3731 operand
->addr
.preind
= 1;
3732 if (operand
->type
== AARCH64_OPND_SVE_ADDR_ZX
)
3734 operand
->addr
.offset
.is_reg
= 1;
3735 operand
->addr
.offset
.regno
= REG_ZR
;
3736 *offset_qualifier
= AARCH64_OPND_QLF_X
;
3740 inst
.reloc
.exp
.X_op
= O_constant
;
3741 inst
.reloc
.exp
.X_add_number
= 0;
3749 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3752 parse_address (char **str
, aarch64_opnd_info
*operand
)
3754 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3755 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3756 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3759 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3760 The arguments have the same meaning as for parse_address_main.
3761 Return TRUE on success. */
3763 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3764 aarch64_opnd_qualifier_t
*base_qualifier
,
3765 aarch64_opnd_qualifier_t
*offset_qualifier
)
3767 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3768 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3772 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3773 Return TRUE on success; otherwise return FALSE. */
3775 parse_half (char **str
, int *internal_fixup_p
)
3779 skip_past_char (&p
, '#');
3781 gas_assert (internal_fixup_p
);
3782 *internal_fixup_p
= 0;
3786 struct reloc_table_entry
*entry
;
3788 /* Try to parse a relocation. Anything else is an error. */
3790 if (!(entry
= find_reloc_table_entry (&p
)))
3792 set_syntax_error (_("unknown relocation modifier"));
3796 if (entry
->movw_type
== 0)
3799 (_("this relocation modifier is not allowed on this instruction"));
3803 inst
.reloc
.type
= entry
->movw_type
;
3806 *internal_fixup_p
= 1;
3808 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3815 /* Parse an operand for an ADRP instruction:
3817 Return TRUE on success; otherwise return FALSE. */
3820 parse_adrp (char **str
)
3827 struct reloc_table_entry
*entry
;
3829 /* Try to parse a relocation. Anything else is an error. */
3831 if (!(entry
= find_reloc_table_entry (&p
)))
3833 set_syntax_error (_("unknown relocation modifier"));
3837 if (entry
->adrp_type
== 0)
3840 (_("this relocation modifier is not allowed on this instruction"));
3844 inst
.reloc
.type
= entry
->adrp_type
;
3847 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3849 inst
.reloc
.pc_rel
= 1;
3851 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3858 /* Miscellaneous. */
3860 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3861 of SIZE tokens in which index I gives the token for field value I,
3862 or is null if field value I is invalid. REG_TYPE says which register
3863 names should be treated as registers rather than as symbolic immediates.
3865 Return true on success, moving *STR past the operand and storing the
3866 field value in *VAL. */
3869 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3870 size_t size
, aarch64_reg_type reg_type
)
3876 /* Match C-like tokens. */
3878 while (ISALNUM (*q
))
3881 for (i
= 0; i
< size
; ++i
)
3883 && strncasecmp (array
[i
], p
, q
- p
) == 0
3884 && array
[i
][q
- p
] == 0)
3891 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3894 if (exp
.X_op
== O_constant
3895 && (uint64_t) exp
.X_add_number
< size
)
3897 *val
= exp
.X_add_number
;
3902 /* Use the default error for this operand. */
3906 /* Parse an option for a preload instruction. Returns the encoding for the
3907 option, or PARSE_FAIL. */
3910 parse_pldop (char **str
)
3913 const struct aarch64_name_value_pair
*o
;
3916 while (ISALNUM (*q
))
3919 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3927 /* Parse an option for a barrier instruction. Returns the encoding for the
3928 option, or PARSE_FAIL. */
3931 parse_barrier (char **str
)
3934 const asm_barrier_opt
*o
;
3937 while (ISALPHA (*q
))
3940 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3948 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3949 return 0 if successful. Otherwise return PARSE_FAIL. */
3952 parse_barrier_psb (char **str
,
3953 const struct aarch64_name_value_pair
** hint_opt
)
3956 const struct aarch64_name_value_pair
*o
;
3959 while (ISALPHA (*q
))
3962 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3965 set_fatal_syntax_error
3966 ( _("unknown or missing option to PSB"));
3970 if (o
->value
!= 0x11)
3972 /* PSB only accepts option name 'CSYNC'. */
3974 (_("the specified option is not accepted for PSB"));
3983 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3984 return 0 if successful. Otherwise return PARSE_FAIL. */
3987 parse_bti_operand (char **str
,
3988 const struct aarch64_name_value_pair
** hint_opt
)
3991 const struct aarch64_name_value_pair
*o
;
3994 while (ISALPHA (*q
))
3997 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
4000 set_fatal_syntax_error
4001 ( _("unknown option to BTI"));
4007 /* Valid BTI operands. */
4015 (_("unknown option to BTI"));
4024 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
4025 Returns the encoding for the option, or PARSE_FAIL.
4027 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
4028 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
4030 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
4031 field, otherwise as a system register.
4035 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
4036 int imple_defined_p
, int pstatefield_p
,
4041 const aarch64_sys_reg
*o
;
4045 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4047 *p
++ = TOLOWER (*q
);
4049 /* Assert that BUF be large enough. */
4050 gas_assert (p
- buf
== q
- *str
);
4052 o
= hash_find (sys_regs
, buf
);
4055 if (!imple_defined_p
)
4059 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4060 unsigned int op0
, op1
, cn
, cm
, op2
;
4062 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4065 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4067 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4074 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4075 as_bad (_("selected processor does not support PSTATE field "
4077 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4078 as_bad (_("selected processor does not support system register "
4080 if (aarch64_sys_reg_deprecated_p (o
))
4081 as_warn (_("system register name '%s' is deprecated and may be "
4082 "removed in a future release"), buf
);
4092 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4093 for the option, or NULL. */
4095 static const aarch64_sys_ins_reg
*
4096 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4100 const aarch64_sys_ins_reg
*o
;
4103 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4105 *p
++ = TOLOWER (*q
);
4108 o
= hash_find (sys_ins_regs
, buf
);
4112 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4113 as_bad (_("selected processor does not support system register "
4120 #define po_char_or_fail(chr) do { \
4121 if (! skip_past_char (&str, chr)) \
4125 #define po_reg_or_fail(regtype) do { \
4126 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4127 if (val == PARSE_FAIL) \
4129 set_default_error (); \
4134 #define po_int_reg_or_fail(reg_type) do { \
4135 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4136 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4138 set_default_error (); \
4141 info->reg.regno = reg->number; \
4142 info->qualifier = qualifier; \
4145 #define po_imm_nc_or_fail() do { \
4146 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4150 #define po_imm_or_fail(min, max) do { \
4151 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4153 if (val < min || val > max) \
4155 set_fatal_syntax_error (_("immediate value out of range "\
4156 #min " to "#max)); \
4161 #define po_enum_or_fail(array) do { \
4162 if (!parse_enum_string (&str, &val, array, \
4163 ARRAY_SIZE (array), imm_reg_type)) \
4167 #define po_misc_or_fail(expr) do { \
4172 /* encode the 12-bit imm field of Add/sub immediate */
4173 static inline uint32_t
4174 encode_addsub_imm (uint32_t imm
)
4179 /* encode the shift amount field of Add/sub immediate */
4180 static inline uint32_t
4181 encode_addsub_imm_shift_amount (uint32_t cnt
)
4187 /* encode the imm field of Adr instruction */
4188 static inline uint32_t
4189 encode_adr_imm (uint32_t imm
)
4191 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4192 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4195 /* encode the immediate field of Move wide immediate */
4196 static inline uint32_t
4197 encode_movw_imm (uint32_t imm
)
4202 /* encode the 26-bit offset of unconditional branch */
4203 static inline uint32_t
4204 encode_branch_ofs_26 (uint32_t ofs
)
4206 return ofs
& ((1 << 26) - 1);
4209 /* encode the 19-bit offset of conditional branch and compare & branch */
4210 static inline uint32_t
4211 encode_cond_branch_ofs_19 (uint32_t ofs
)
4213 return (ofs
& ((1 << 19) - 1)) << 5;
4216 /* encode the 19-bit offset of ld literal */
4217 static inline uint32_t
4218 encode_ld_lit_ofs_19 (uint32_t ofs
)
4220 return (ofs
& ((1 << 19) - 1)) << 5;
4223 /* Encode the 14-bit offset of test & branch. */
4224 static inline uint32_t
4225 encode_tst_branch_ofs_14 (uint32_t ofs
)
4227 return (ofs
& ((1 << 14) - 1)) << 5;
4230 /* Encode the 16-bit imm field of svc/hvc/smc. */
4231 static inline uint32_t
4232 encode_svc_imm (uint32_t imm
)
4237 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4238 static inline uint32_t
4239 reencode_addsub_switch_add_sub (uint32_t opcode
)
4241 return opcode
^ (1 << 30);
4244 static inline uint32_t
4245 reencode_movzn_to_movz (uint32_t opcode
)
4247 return opcode
| (1 << 30);
4250 static inline uint32_t
4251 reencode_movzn_to_movn (uint32_t opcode
)
4253 return opcode
& ~(1 << 30);
4256 /* Overall per-instruction processing. */
4258 /* We need to be able to fix up arbitrary expressions in some statements.
4259 This is so that we can handle symbols that are an arbitrary distance from
4260 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4261 which returns part of an address in a form which will be valid for
4262 a data instruction. We do this by pushing the expression into a symbol
4263 in the expr_section, and creating a fix for that. */
4266 fix_new_aarch64 (fragS
* frag
,
4268 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4278 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4282 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4289 /* Diagnostics on operands errors. */
4291 /* By default, output verbose error message.
4292 Disable the verbose error message by -mno-verbose-error. */
4293 static int verbose_error_p
= 1;
4295 #ifdef DEBUG_AARCH64
4296 /* N.B. this is only for the purpose of debugging. */
4297 const char* operand_mismatch_kind_names
[] =
4300 "AARCH64_OPDE_RECOVERABLE",
4301 "AARCH64_OPDE_SYNTAX_ERROR",
4302 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4303 "AARCH64_OPDE_INVALID_VARIANT",
4304 "AARCH64_OPDE_OUT_OF_RANGE",
4305 "AARCH64_OPDE_UNALIGNED",
4306 "AARCH64_OPDE_REG_LIST",
4307 "AARCH64_OPDE_OTHER_ERROR",
4309 #endif /* DEBUG_AARCH64 */
4311 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4313 When multiple errors of different kinds are found in the same assembly
4314 line, only the error of the highest severity will be picked up for
4315 issuing the diagnostics. */
4317 static inline bfd_boolean
4318 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4319 enum aarch64_operand_error_kind rhs
)
4321 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4322 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4323 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4324 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4325 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4326 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4327 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4328 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4332 /* Helper routine to get the mnemonic name from the assembly instruction
4333 line; should only be called for the diagnosis purpose, as there is
4334 string copy operation involved, which may affect the runtime
4335 performance if used in elsewhere. */
4338 get_mnemonic_name (const char *str
)
4340 static char mnemonic
[32];
4343 /* Get the first 15 bytes and assume that the full name is included. */
4344 strncpy (mnemonic
, str
, 31);
4345 mnemonic
[31] = '\0';
4347 /* Scan up to the end of the mnemonic, which must end in white space,
4348 '.', or end of string. */
4349 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4354 /* Append '...' to the truncated long name. */
4355 if (ptr
- mnemonic
== 31)
4356 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4362 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4364 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4365 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4368 /* Data structures storing one user error in the assembly code related to
4371 struct operand_error_record
4373 const aarch64_opcode
*opcode
;
4374 aarch64_operand_error detail
;
4375 struct operand_error_record
*next
;
4378 typedef struct operand_error_record operand_error_record
;
4380 struct operand_errors
4382 operand_error_record
*head
;
4383 operand_error_record
*tail
;
4386 typedef struct operand_errors operand_errors
;
4388 /* Top-level data structure reporting user errors for the current line of
4390 The way md_assemble works is that all opcodes sharing the same mnemonic
4391 name are iterated to find a match to the assembly line. In this data
4392 structure, each of the such opcodes will have one operand_error_record
4393 allocated and inserted. In other words, excessive errors related with
4394 a single opcode are disregarded. */
4395 operand_errors operand_error_report
;
4397 /* Free record nodes. */
4398 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4400 /* Initialize the data structure that stores the operand mismatch
4401 information on assembling one line of the assembly code. */
4403 init_operand_error_report (void)
4405 if (operand_error_report
.head
!= NULL
)
4407 gas_assert (operand_error_report
.tail
!= NULL
);
4408 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4409 free_opnd_error_record_nodes
= operand_error_report
.head
;
4410 operand_error_report
.head
= NULL
;
4411 operand_error_report
.tail
= NULL
;
4414 gas_assert (operand_error_report
.tail
== NULL
);
4417 /* Return TRUE if some operand error has been recorded during the
4418 parsing of the current assembly line using the opcode *OPCODE;
4419 otherwise return FALSE. */
4420 static inline bfd_boolean
4421 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4423 operand_error_record
*record
= operand_error_report
.head
;
4424 return record
&& record
->opcode
== opcode
;
4427 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4428 OPCODE field is initialized with OPCODE.
4429 N.B. only one record for each opcode, i.e. the maximum of one error is
4430 recorded for each instruction template. */
4433 add_operand_error_record (const operand_error_record
* new_record
)
4435 const aarch64_opcode
*opcode
= new_record
->opcode
;
4436 operand_error_record
* record
= operand_error_report
.head
;
4438 /* The record may have been created for this opcode. If not, we need
4440 if (! opcode_has_operand_error_p (opcode
))
4442 /* Get one empty record. */
4443 if (free_opnd_error_record_nodes
== NULL
)
4445 record
= XNEW (operand_error_record
);
4449 record
= free_opnd_error_record_nodes
;
4450 free_opnd_error_record_nodes
= record
->next
;
4452 record
->opcode
= opcode
;
4453 /* Insert at the head. */
4454 record
->next
= operand_error_report
.head
;
4455 operand_error_report
.head
= record
;
4456 if (operand_error_report
.tail
== NULL
)
4457 operand_error_report
.tail
= record
;
4459 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4460 && record
->detail
.index
<= new_record
->detail
.index
4461 && operand_error_higher_severity_p (record
->detail
.kind
,
4462 new_record
->detail
.kind
))
4464 /* In the case of multiple errors found on operands related with a
4465 single opcode, only record the error of the leftmost operand and
4466 only if the error is of higher severity. */
4467 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4468 " the existing error %s on operand %d",
4469 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4470 new_record
->detail
.index
,
4471 operand_mismatch_kind_names
[record
->detail
.kind
],
4472 record
->detail
.index
);
4476 record
->detail
= new_record
->detail
;
4480 record_operand_error_info (const aarch64_opcode
*opcode
,
4481 aarch64_operand_error
*error_info
)
4483 operand_error_record record
;
4484 record
.opcode
= opcode
;
4485 record
.detail
= *error_info
;
4486 add_operand_error_record (&record
);
4489 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4490 error message *ERROR, for operand IDX (count from 0). */
4493 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4494 enum aarch64_operand_error_kind kind
,
4497 aarch64_operand_error info
;
4498 memset(&info
, 0, sizeof (info
));
4502 info
.non_fatal
= FALSE
;
4503 record_operand_error_info (opcode
, &info
);
4507 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4508 enum aarch64_operand_error_kind kind
,
4509 const char* error
, const int *extra_data
)
4511 aarch64_operand_error info
;
4515 info
.data
[0] = extra_data
[0];
4516 info
.data
[1] = extra_data
[1];
4517 info
.data
[2] = extra_data
[2];
4518 info
.non_fatal
= FALSE
;
4519 record_operand_error_info (opcode
, &info
);
4523 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4524 const char* error
, int lower_bound
,
4527 int data
[3] = {lower_bound
, upper_bound
, 0};
4528 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4532 /* Remove the operand error record for *OPCODE. */
4533 static void ATTRIBUTE_UNUSED
4534 remove_operand_error_record (const aarch64_opcode
*opcode
)
4536 if (opcode_has_operand_error_p (opcode
))
4538 operand_error_record
* record
= operand_error_report
.head
;
4539 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4540 operand_error_report
.head
= record
->next
;
4541 record
->next
= free_opnd_error_record_nodes
;
4542 free_opnd_error_record_nodes
= record
;
4543 if (operand_error_report
.head
== NULL
)
4545 gas_assert (operand_error_report
.tail
== record
);
4546 operand_error_report
.tail
= NULL
;
4551 /* Given the instruction in *INSTR, return the index of the best matched
4552 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4554 Return -1 if there is no qualifier sequence; return the first match
4555 if there is multiple matches found. */
4558 find_best_match (const aarch64_inst
*instr
,
4559 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4561 int i
, num_opnds
, max_num_matched
, idx
;
4563 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4566 DEBUG_TRACE ("no operand");
4570 max_num_matched
= 0;
4573 /* For each pattern. */
4574 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4577 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4579 /* Most opcodes has much fewer patterns in the list. */
4580 if (empty_qualifier_sequence_p (qualifiers
))
4582 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4586 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4587 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4590 if (num_matched
> max_num_matched
)
4592 max_num_matched
= num_matched
;
4597 DEBUG_TRACE ("return with %d", idx
);
4601 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4602 corresponding operands in *INSTR. */
4605 assign_qualifier_sequence (aarch64_inst
*instr
,
4606 const aarch64_opnd_qualifier_t
*qualifiers
)
4609 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4610 gas_assert (num_opnds
);
4611 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4612 instr
->operands
[i
].qualifier
= *qualifiers
;
4615 /* Print operands for the diagnosis purpose. */
4618 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4619 const aarch64_opnd_info
*opnds
)
4623 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4627 /* We regard the opcode operand info more, however we also look into
4628 the inst->operands to support the disassembling of the optional
4630 The two operand code should be the same in all cases, apart from
4631 when the operand can be optional. */
4632 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4633 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4636 /* Generate the operand string in STR. */
4637 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4642 strcat (buf
, i
== 0 ? " " : ", ");
4644 /* Append the operand string. */
4649 /* Send to stderr a string as information. */
4652 output_info (const char *format
, ...)
4658 file
= as_where (&line
);
4662 fprintf (stderr
, "%s:%u: ", file
, line
);
4664 fprintf (stderr
, "%s: ", file
);
4666 fprintf (stderr
, _("Info: "));
4667 va_start (args
, format
);
4668 vfprintf (stderr
, format
, args
);
4670 (void) putc ('\n', stderr
);
4673 /* Output one operand error record. */
4676 output_operand_error_record (const operand_error_record
*record
, char *str
)
4678 const aarch64_operand_error
*detail
= &record
->detail
;
4679 int idx
= detail
->index
;
4680 const aarch64_opcode
*opcode
= record
->opcode
;
4681 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4682 : AARCH64_OPND_NIL
);
4684 typedef void (*handler_t
)(const char *format
, ...);
4685 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4687 switch (detail
->kind
)
4689 case AARCH64_OPDE_NIL
:
4692 case AARCH64_OPDE_SYNTAX_ERROR
:
4693 case AARCH64_OPDE_RECOVERABLE
:
4694 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4695 case AARCH64_OPDE_OTHER_ERROR
:
4696 /* Use the prepared error message if there is, otherwise use the
4697 operand description string to describe the error. */
4698 if (detail
->error
!= NULL
)
4701 handler (_("%s -- `%s'"), detail
->error
, str
);
4703 handler (_("%s at operand %d -- `%s'"),
4704 detail
->error
, idx
+ 1, str
);
4708 gas_assert (idx
>= 0);
4709 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4710 aarch64_get_operand_desc (opd_code
), str
);
4714 case AARCH64_OPDE_INVALID_VARIANT
:
4715 handler (_("operand mismatch -- `%s'"), str
);
4716 if (verbose_error_p
)
4718 /* We will try to correct the erroneous instruction and also provide
4719 more information e.g. all other valid variants.
4721 The string representation of the corrected instruction and other
4722 valid variants are generated by
4724 1) obtaining the intermediate representation of the erroneous
4726 2) manipulating the IR, e.g. replacing the operand qualifier;
4727 3) printing out the instruction by calling the printer functions
4728 shared with the disassembler.
4730 The limitation of this method is that the exact input assembly
4731 line cannot be accurately reproduced in some cases, for example an
4732 optional operand present in the actual assembly line will be
4733 omitted in the output; likewise for the optional syntax rules,
4734 e.g. the # before the immediate. Another limitation is that the
4735 assembly symbols and relocation operations in the assembly line
4736 currently cannot be printed out in the error report. Last but not
4737 least, when there is other error(s) co-exist with this error, the
4738 'corrected' instruction may be still incorrect, e.g. given
4739 'ldnp h0,h1,[x0,#6]!'
4740 this diagnosis will provide the version:
4741 'ldnp s0,s1,[x0,#6]!'
4742 which is still not right. */
4743 size_t len
= strlen (get_mnemonic_name (str
));
4747 aarch64_inst
*inst_base
= &inst
.base
;
4748 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4751 reset_aarch64_instruction (&inst
);
4752 inst_base
->opcode
= opcode
;
4754 /* Reset the error report so that there is no side effect on the
4755 following operand parsing. */
4756 init_operand_error_report ();
4759 result
= parse_operands (str
+ len
, opcode
)
4760 && programmer_friendly_fixup (&inst
);
4761 gas_assert (result
);
4762 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4763 NULL
, NULL
, insn_sequence
);
4764 gas_assert (!result
);
4766 /* Find the most matched qualifier sequence. */
4767 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4768 gas_assert (qlf_idx
> -1);
4770 /* Assign the qualifiers. */
4771 assign_qualifier_sequence (inst_base
,
4772 opcode
->qualifiers_list
[qlf_idx
]);
4774 /* Print the hint. */
4775 output_info (_(" did you mean this?"));
4776 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4777 print_operands (buf
, opcode
, inst_base
->operands
);
4778 output_info (_(" %s"), buf
);
4780 /* Print out other variant(s) if there is any. */
4782 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4783 output_info (_(" other valid variant(s):"));
4785 /* For each pattern. */
4786 qualifiers_list
= opcode
->qualifiers_list
;
4787 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4789 /* Most opcodes has much fewer patterns in the list.
4790 First NIL qualifier indicates the end in the list. */
4791 if (empty_qualifier_sequence_p (*qualifiers_list
))
4796 /* Mnemonics name. */
4797 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4799 /* Assign the qualifiers. */
4800 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4802 /* Print instruction. */
4803 print_operands (buf
, opcode
, inst_base
->operands
);
4805 output_info (_(" %s"), buf
);
4811 case AARCH64_OPDE_UNTIED_OPERAND
:
4812 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4813 detail
->index
+ 1, str
);
4816 case AARCH64_OPDE_OUT_OF_RANGE
:
4817 if (detail
->data
[0] != detail
->data
[1])
4818 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4819 detail
->error
? detail
->error
: _("immediate value"),
4820 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4822 handler (_("%s must be %d at operand %d -- `%s'"),
4823 detail
->error
? detail
->error
: _("immediate value"),
4824 detail
->data
[0], idx
+ 1, str
);
4827 case AARCH64_OPDE_REG_LIST
:
4828 if (detail
->data
[0] == 1)
4829 handler (_("invalid number of registers in the list; "
4830 "only 1 register is expected at operand %d -- `%s'"),
4833 handler (_("invalid number of registers in the list; "
4834 "%d registers are expected at operand %d -- `%s'"),
4835 detail
->data
[0], idx
+ 1, str
);
4838 case AARCH64_OPDE_UNALIGNED
:
4839 handler (_("immediate value must be a multiple of "
4840 "%d at operand %d -- `%s'"),
4841 detail
->data
[0], idx
+ 1, str
);
4850 /* Process and output the error message about the operand mismatching.
4852 When this function is called, the operand error information had
4853 been collected for an assembly line and there will be multiple
4854 errors in the case of multiple instruction templates; output the
4855 error message that most closely describes the problem.
4857 The errors to be printed can be filtered on printing all errors
4858 or only non-fatal errors. This distinction has to be made because
4859 the error buffer may already be filled with fatal errors we don't want to
4860 print due to the different instruction templates. */
4863 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4865 int largest_error_pos
;
4866 const char *msg
= NULL
;
4867 enum aarch64_operand_error_kind kind
;
4868 operand_error_record
*curr
;
4869 operand_error_record
*head
= operand_error_report
.head
;
4870 operand_error_record
*record
= NULL
;
4872 /* No error to report. */
4876 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4878 /* Only one error. */
4879 if (head
== operand_error_report
.tail
)
4881 /* If the only error is a non-fatal one and we don't want to print it,
4883 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4885 DEBUG_TRACE ("single opcode entry with error kind: %s",
4886 operand_mismatch_kind_names
[head
->detail
.kind
]);
4887 output_operand_error_record (head
, str
);
4892 /* Find the error kind of the highest severity. */
4893 DEBUG_TRACE ("multiple opcode entries with error kind");
4894 kind
= AARCH64_OPDE_NIL
;
4895 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4897 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4898 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4899 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4900 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4901 kind
= curr
->detail
.kind
;
4904 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4906 /* Pick up one of errors of KIND to report. */
4907 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4908 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4910 /* If we don't want to print non-fatal errors then don't consider them
4912 if (curr
->detail
.kind
!= kind
4913 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4915 /* If there are multiple errors, pick up the one with the highest
4916 mismatching operand index. In the case of multiple errors with
4917 the equally highest operand index, pick up the first one or the
4918 first one with non-NULL error message. */
4919 if (curr
->detail
.index
> largest_error_pos
4920 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4921 && curr
->detail
.error
!= NULL
))
4923 largest_error_pos
= curr
->detail
.index
;
4925 msg
= record
->detail
.error
;
4929 /* The way errors are collected in the back-end is a bit non-intuitive. But
4930 essentially, because each operand template is tried recursively you may
4931 always have errors collected from the previous tried OPND. These are
4932 usually skipped if there is one successful match. However now with the
4933 non-fatal errors we have to ignore those previously collected hard errors
4934 when we're only interested in printing the non-fatal ones. This condition
4935 prevents us from printing errors that are not appropriate, since we did
4936 match a condition, but it also has warnings that it wants to print. */
4937 if (non_fatal_only
&& !record
)
4940 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4941 DEBUG_TRACE ("Pick up error kind %s to report",
4942 operand_mismatch_kind_names
[record
->detail
.kind
]);
4945 output_operand_error_record (record
, str
);
4948 /* Write an AARCH64 instruction to buf - always little-endian. */
4950 put_aarch64_insn (char *buf
, uint32_t insn
)
4952 unsigned char *where
= (unsigned char *) buf
;
4954 where
[1] = insn
>> 8;
4955 where
[2] = insn
>> 16;
4956 where
[3] = insn
>> 24;
4960 get_aarch64_insn (char *buf
)
4962 unsigned char *where
= (unsigned char *) buf
;
4964 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4969 output_inst (struct aarch64_inst
*new_inst
)
4973 to
= frag_more (INSN_SIZE
);
4975 frag_now
->tc_frag_data
.recorded
= 1;
4977 put_aarch64_insn (to
, inst
.base
.value
);
4979 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4981 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4982 INSN_SIZE
, &inst
.reloc
.exp
,
4985 DEBUG_TRACE ("Prepared relocation fix up");
4986 /* Don't check the addend value against the instruction size,
4987 that's the job of our code in md_apply_fix(). */
4988 fixp
->fx_no_overflow
= 1;
4989 if (new_inst
!= NULL
)
4990 fixp
->tc_fix_data
.inst
= new_inst
;
4991 if (aarch64_gas_internal_fixup_p ())
4993 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4994 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4995 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4999 dwarf2_emit_insn (INSN_SIZE
);
5002 /* Link together opcodes of the same name. */
5006 aarch64_opcode
*opcode
;
5007 struct templates
*next
;
5010 typedef struct templates templates
;
5013 lookup_mnemonic (const char *start
, int len
)
5015 templates
*templ
= NULL
;
5017 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
5021 /* Subroutine of md_assemble, responsible for looking up the primary
5022 opcode from the mnemonic the user wrote. STR points to the
5023 beginning of the mnemonic. */
5026 opcode_lookup (char **str
)
5028 char *end
, *base
, *dot
;
5029 const aarch64_cond
*cond
;
5033 /* Scan up to the end of the mnemonic, which must end in white space,
5034 '.', or end of string. */
5036 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
5037 if (*end
== '.' && !dot
)
5040 if (end
== base
|| dot
== base
)
5043 inst
.cond
= COND_ALWAYS
;
5045 /* Handle a possible condition. */
5048 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5051 inst
.cond
= cond
->value
;
5067 if (inst
.cond
== COND_ALWAYS
)
5069 /* Look for unaffixed mnemonic. */
5070 return lookup_mnemonic (base
, len
);
5074 /* append ".c" to mnemonic if conditional */
5075 memcpy (condname
, base
, len
);
5076 memcpy (condname
+ len
, ".c", 2);
5079 return lookup_mnemonic (base
, len
);
5085 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5086 to a corresponding operand qualifier. */
5088 static inline aarch64_opnd_qualifier_t
5089 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5091 /* Element size in bytes indexed by vector_el_type. */
5092 const unsigned char ele_size
[5]
5094 const unsigned int ele_base
[5] =
5096 AARCH64_OPND_QLF_V_4B
,
5097 AARCH64_OPND_QLF_V_2H
,
5098 AARCH64_OPND_QLF_V_2S
,
5099 AARCH64_OPND_QLF_V_1D
,
5100 AARCH64_OPND_QLF_V_1Q
5103 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5104 goto vectype_conversion_fail
;
5106 if (vectype
->type
== NT_zero
)
5107 return AARCH64_OPND_QLF_P_Z
;
5108 if (vectype
->type
== NT_merge
)
5109 return AARCH64_OPND_QLF_P_M
;
5111 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5113 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5115 /* Special case S_4B. */
5116 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5117 return AARCH64_OPND_QLF_S_4B
;
5119 /* Vector element register. */
5120 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5124 /* Vector register. */
5125 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5128 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5129 goto vectype_conversion_fail
;
5131 /* The conversion is by calculating the offset from the base operand
5132 qualifier for the vector type. The operand qualifiers are regular
5133 enough that the offset can established by shifting the vector width by
5134 a vector-type dependent amount. */
5136 if (vectype
->type
== NT_b
)
5138 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5140 else if (vectype
->type
>= NT_d
)
5145 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5146 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5147 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5151 vectype_conversion_fail
:
5152 first_error (_("bad vector arrangement type"));
5153 return AARCH64_OPND_QLF_NIL
;
5156 /* Process an optional operand that is found omitted from the assembly line.
5157 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5158 instruction's opcode entry while IDX is the index of this omitted operand.
5162 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5163 int idx
, aarch64_opnd_info
*operand
)
5165 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5166 gas_assert (optional_operand_p (opcode
, idx
));
5167 gas_assert (!operand
->present
);
5171 case AARCH64_OPND_Rd
:
5172 case AARCH64_OPND_Rn
:
5173 case AARCH64_OPND_Rm
:
5174 case AARCH64_OPND_Rt
:
5175 case AARCH64_OPND_Rt2
:
5176 case AARCH64_OPND_Rt_SP
:
5177 case AARCH64_OPND_Rs
:
5178 case AARCH64_OPND_Ra
:
5179 case AARCH64_OPND_Rt_SYS
:
5180 case AARCH64_OPND_Rd_SP
:
5181 case AARCH64_OPND_Rn_SP
:
5182 case AARCH64_OPND_Rm_SP
:
5183 case AARCH64_OPND_Fd
:
5184 case AARCH64_OPND_Fn
:
5185 case AARCH64_OPND_Fm
:
5186 case AARCH64_OPND_Fa
:
5187 case AARCH64_OPND_Ft
:
5188 case AARCH64_OPND_Ft2
:
5189 case AARCH64_OPND_Sd
:
5190 case AARCH64_OPND_Sn
:
5191 case AARCH64_OPND_Sm
:
5192 case AARCH64_OPND_Va
:
5193 case AARCH64_OPND_Vd
:
5194 case AARCH64_OPND_Vn
:
5195 case AARCH64_OPND_Vm
:
5196 case AARCH64_OPND_VdD1
:
5197 case AARCH64_OPND_VnD1
:
5198 operand
->reg
.regno
= default_value
;
5201 case AARCH64_OPND_Ed
:
5202 case AARCH64_OPND_En
:
5203 case AARCH64_OPND_Em
:
5204 case AARCH64_OPND_Em16
:
5205 case AARCH64_OPND_SM3_IMM2
:
5206 operand
->reglane
.regno
= default_value
;
5209 case AARCH64_OPND_IDX
:
5210 case AARCH64_OPND_BIT_NUM
:
5211 case AARCH64_OPND_IMMR
:
5212 case AARCH64_OPND_IMMS
:
5213 case AARCH64_OPND_SHLL_IMM
:
5214 case AARCH64_OPND_IMM_VLSL
:
5215 case AARCH64_OPND_IMM_VLSR
:
5216 case AARCH64_OPND_CCMP_IMM
:
5217 case AARCH64_OPND_FBITS
:
5218 case AARCH64_OPND_UIMM4
:
5219 case AARCH64_OPND_UIMM3_OP1
:
5220 case AARCH64_OPND_UIMM3_OP2
:
5221 case AARCH64_OPND_IMM
:
5222 case AARCH64_OPND_IMM_2
:
5223 case AARCH64_OPND_WIDTH
:
5224 case AARCH64_OPND_UIMM7
:
5225 case AARCH64_OPND_NZCV
:
5226 case AARCH64_OPND_SVE_PATTERN
:
5227 case AARCH64_OPND_SVE_PRFOP
:
5228 operand
->imm
.value
= default_value
;
5231 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5232 operand
->imm
.value
= default_value
;
5233 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5234 operand
->shifter
.amount
= 1;
5237 case AARCH64_OPND_EXCEPTION
:
5238 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5241 case AARCH64_OPND_BARRIER_ISB
:
5242 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5245 case AARCH64_OPND_BTI_TARGET
:
5246 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5254 /* Process the relocation type for move wide instructions.
5255 Return TRUE on success; otherwise return FALSE. */
5258 process_movw_reloc_info (void)
5263 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5265 if (inst
.base
.opcode
->op
== OP_MOVK
)
5266 switch (inst
.reloc
.type
)
5268 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5269 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5270 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5271 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5272 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5273 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5274 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5275 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5277 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5278 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5280 (_("the specified relocation type is not allowed for MOVK"));
5286 switch (inst
.reloc
.type
)
5288 case BFD_RELOC_AARCH64_MOVW_G0
:
5289 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5290 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5291 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5292 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5293 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5294 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5295 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5296 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5297 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5298 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5299 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5300 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5303 case BFD_RELOC_AARCH64_MOVW_G1
:
5304 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5305 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5306 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5307 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5308 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5309 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5310 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5311 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5312 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5313 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5314 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5315 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5318 case BFD_RELOC_AARCH64_MOVW_G2
:
5319 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5320 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5321 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5322 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5323 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5324 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5327 set_fatal_syntax_error
5328 (_("the specified relocation type is not allowed for 32-bit "
5334 case BFD_RELOC_AARCH64_MOVW_G3
:
5335 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5338 set_fatal_syntax_error
5339 (_("the specified relocation type is not allowed for 32-bit "
5346 /* More cases should be added when more MOVW-related relocation types
5347 are supported in GAS. */
5348 gas_assert (aarch64_gas_internal_fixup_p ());
5349 /* The shift amount should have already been set by the parser. */
5352 inst
.base
.operands
[1].shifter
.amount
= shift
;
5356 /* A primitive log calculator. */
5358 static inline unsigned int
5359 get_logsz (unsigned int size
)
5361 const unsigned char ls
[16] =
5362 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5368 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5369 return ls
[size
- 1];
5372 /* Determine and return the real reloc type code for an instruction
5373 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5375 static inline bfd_reloc_code_real_type
5376 ldst_lo12_determine_real_reloc_type (void)
5379 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5380 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5382 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5384 BFD_RELOC_AARCH64_LDST8_LO12
,
5385 BFD_RELOC_AARCH64_LDST16_LO12
,
5386 BFD_RELOC_AARCH64_LDST32_LO12
,
5387 BFD_RELOC_AARCH64_LDST64_LO12
,
5388 BFD_RELOC_AARCH64_LDST128_LO12
5391 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5392 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5393 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5394 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5395 BFD_RELOC_AARCH64_NONE
5398 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5399 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5400 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5401 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5402 BFD_RELOC_AARCH64_NONE
5405 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5406 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5407 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5408 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5409 BFD_RELOC_AARCH64_NONE
5412 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5413 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5414 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5415 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5416 BFD_RELOC_AARCH64_NONE
5420 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5421 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5423 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5425 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5427 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5428 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5430 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5432 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5434 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5436 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5437 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5438 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5439 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5440 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5441 gas_assert (logsz
<= 3);
5443 gas_assert (logsz
<= 4);
5445 /* In reloc.c, these pseudo relocation types should be defined in similar
5446 order as above reloc_ldst_lo12 array. Because the array index calculation
5447 below relies on this. */
5448 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5451 /* Check whether a register list REGINFO is valid. The registers must be
5452 numbered in increasing order (modulo 32), in increments of one or two.
5454 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5457 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5460 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5462 uint32_t i
, nb_regs
, prev_regno
, incr
;
5464 nb_regs
= 1 + (reginfo
& 0x3);
5466 prev_regno
= reginfo
& 0x1f;
5467 incr
= accept_alternate
? 2 : 1;
5469 for (i
= 1; i
< nb_regs
; ++i
)
5471 uint32_t curr_regno
;
5473 curr_regno
= reginfo
& 0x1f;
5474 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5476 prev_regno
= curr_regno
;
5482 /* Generic instruction operand parser. This does no encoding and no
5483 semantic validation; it merely squirrels values away in the inst
5484 structure. Returns TRUE or FALSE depending on whether the
5485 specified grammar matched. */
5488 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5491 char *backtrack_pos
= 0;
5492 const enum aarch64_opnd
*operands
= opcode
->operands
;
5493 aarch64_reg_type imm_reg_type
;
5496 skip_whitespace (str
);
5498 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5499 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5501 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5503 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5506 const reg_entry
*reg
;
5507 int comma_skipped_p
= 0;
5508 aarch64_reg_type rtype
;
5509 struct vector_type_el vectype
;
5510 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5511 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5512 aarch64_reg_type reg_type
;
5514 DEBUG_TRACE ("parse operand %d", i
);
5516 /* Assign the operand code. */
5517 info
->type
= operands
[i
];
5519 if (optional_operand_p (opcode
, i
))
5521 /* Remember where we are in case we need to backtrack. */
5522 gas_assert (!backtrack_pos
);
5523 backtrack_pos
= str
;
5526 /* Expect comma between operands; the backtrack mechanism will take
5527 care of cases of omitted optional operand. */
5528 if (i
> 0 && ! skip_past_char (&str
, ','))
5530 set_syntax_error (_("comma expected between operands"));
5534 comma_skipped_p
= 1;
5536 switch (operands
[i
])
5538 case AARCH64_OPND_Rd
:
5539 case AARCH64_OPND_Rn
:
5540 case AARCH64_OPND_Rm
:
5541 case AARCH64_OPND_Rt
:
5542 case AARCH64_OPND_Rt2
:
5543 case AARCH64_OPND_Rs
:
5544 case AARCH64_OPND_Ra
:
5545 case AARCH64_OPND_Rt_SYS
:
5546 case AARCH64_OPND_PAIRREG
:
5547 case AARCH64_OPND_SVE_Rm
:
5548 po_int_reg_or_fail (REG_TYPE_R_Z
);
5551 case AARCH64_OPND_Rd_SP
:
5552 case AARCH64_OPND_Rn_SP
:
5553 case AARCH64_OPND_Rt_SP
:
5554 case AARCH64_OPND_SVE_Rn_SP
:
5555 case AARCH64_OPND_Rm_SP
:
5556 po_int_reg_or_fail (REG_TYPE_R_SP
);
5559 case AARCH64_OPND_Rm_EXT
:
5560 case AARCH64_OPND_Rm_SFT
:
5561 po_misc_or_fail (parse_shifter_operand
5562 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5564 : SHIFTED_LOGIC_IMM
)));
5565 if (!info
->shifter
.operator_present
)
5567 /* Default to LSL if not present. Libopcodes prefers shifter
5568 kind to be explicit. */
5569 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5570 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5571 /* For Rm_EXT, libopcodes will carry out further check on whether
5572 or not stack pointer is used in the instruction (Recall that
5573 "the extend operator is not optional unless at least one of
5574 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5578 case AARCH64_OPND_Fd
:
5579 case AARCH64_OPND_Fn
:
5580 case AARCH64_OPND_Fm
:
5581 case AARCH64_OPND_Fa
:
5582 case AARCH64_OPND_Ft
:
5583 case AARCH64_OPND_Ft2
:
5584 case AARCH64_OPND_Sd
:
5585 case AARCH64_OPND_Sn
:
5586 case AARCH64_OPND_Sm
:
5587 case AARCH64_OPND_SVE_VZn
:
5588 case AARCH64_OPND_SVE_Vd
:
5589 case AARCH64_OPND_SVE_Vm
:
5590 case AARCH64_OPND_SVE_Vn
:
5591 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5592 if (val
== PARSE_FAIL
)
5594 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5597 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5599 info
->reg
.regno
= val
;
5600 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5603 case AARCH64_OPND_SVE_Pd
:
5604 case AARCH64_OPND_SVE_Pg3
:
5605 case AARCH64_OPND_SVE_Pg4_5
:
5606 case AARCH64_OPND_SVE_Pg4_10
:
5607 case AARCH64_OPND_SVE_Pg4_16
:
5608 case AARCH64_OPND_SVE_Pm
:
5609 case AARCH64_OPND_SVE_Pn
:
5610 case AARCH64_OPND_SVE_Pt
:
5611 reg_type
= REG_TYPE_PN
;
5614 case AARCH64_OPND_SVE_Za_5
:
5615 case AARCH64_OPND_SVE_Za_16
:
5616 case AARCH64_OPND_SVE_Zd
:
5617 case AARCH64_OPND_SVE_Zm_5
:
5618 case AARCH64_OPND_SVE_Zm_16
:
5619 case AARCH64_OPND_SVE_Zn
:
5620 case AARCH64_OPND_SVE_Zt
:
5621 reg_type
= REG_TYPE_ZN
;
5624 case AARCH64_OPND_Va
:
5625 case AARCH64_OPND_Vd
:
5626 case AARCH64_OPND_Vn
:
5627 case AARCH64_OPND_Vm
:
5628 reg_type
= REG_TYPE_VN
;
5630 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5631 if (val
== PARSE_FAIL
)
5633 first_error (_(get_reg_expected_msg (reg_type
)));
5636 if (vectype
.defined
& NTA_HASINDEX
)
5639 info
->reg
.regno
= val
;
5640 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5641 && vectype
.type
== NT_invtype
)
5642 /* Unqualified Pn and Zn registers are allowed in certain
5643 contexts. Rely on F_STRICT qualifier checking to catch
5645 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5648 info
->qualifier
= vectype_to_qualifier (&vectype
);
5649 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5654 case AARCH64_OPND_VdD1
:
5655 case AARCH64_OPND_VnD1
:
5656 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5657 if (val
== PARSE_FAIL
)
5659 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5662 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5664 set_fatal_syntax_error
5665 (_("the top half of a 128-bit FP/SIMD register is expected"));
5668 info
->reg
.regno
= val
;
5669 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5670 here; it is correct for the purpose of encoding/decoding since
5671 only the register number is explicitly encoded in the related
5672 instructions, although this appears a bit hacky. */
5673 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5676 case AARCH64_OPND_SVE_Zm3_INDEX
:
5677 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5678 case AARCH64_OPND_SVE_Zm3_11_INDEX
:
5679 case AARCH64_OPND_SVE_Zm4_11_INDEX
:
5680 case AARCH64_OPND_SVE_Zm4_INDEX
:
5681 case AARCH64_OPND_SVE_Zn_INDEX
:
5682 reg_type
= REG_TYPE_ZN
;
5683 goto vector_reg_index
;
5685 case AARCH64_OPND_Ed
:
5686 case AARCH64_OPND_En
:
5687 case AARCH64_OPND_Em
:
5688 case AARCH64_OPND_Em16
:
5689 case AARCH64_OPND_SM3_IMM2
:
5690 reg_type
= REG_TYPE_VN
;
5692 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5693 if (val
== PARSE_FAIL
)
5695 first_error (_(get_reg_expected_msg (reg_type
)));
5698 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5701 info
->reglane
.regno
= val
;
5702 info
->reglane
.index
= vectype
.index
;
5703 info
->qualifier
= vectype_to_qualifier (&vectype
);
5704 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5708 case AARCH64_OPND_SVE_ZnxN
:
5709 case AARCH64_OPND_SVE_ZtxN
:
5710 reg_type
= REG_TYPE_ZN
;
5711 goto vector_reg_list
;
5713 case AARCH64_OPND_LVn
:
5714 case AARCH64_OPND_LVt
:
5715 case AARCH64_OPND_LVt_AL
:
5716 case AARCH64_OPND_LEt
:
5717 reg_type
= REG_TYPE_VN
;
5719 if (reg_type
== REG_TYPE_ZN
5720 && get_opcode_dependent_value (opcode
) == 1
5723 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5724 if (val
== PARSE_FAIL
)
5726 first_error (_(get_reg_expected_msg (reg_type
)));
5729 info
->reglist
.first_regno
= val
;
5730 info
->reglist
.num_regs
= 1;
5734 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5735 if (val
== PARSE_FAIL
)
5738 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5740 set_fatal_syntax_error (_("invalid register list"));
5744 if (vectype
.width
!= 0 && *str
!= ',')
5746 set_fatal_syntax_error
5747 (_("expected element type rather than vector type"));
5751 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5752 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5754 if (operands
[i
] == AARCH64_OPND_LEt
)
5756 if (!(vectype
.defined
& NTA_HASINDEX
))
5758 info
->reglist
.has_index
= 1;
5759 info
->reglist
.index
= vectype
.index
;
5763 if (vectype
.defined
& NTA_HASINDEX
)
5765 if (!(vectype
.defined
& NTA_HASTYPE
))
5767 if (reg_type
== REG_TYPE_ZN
)
5768 set_fatal_syntax_error (_("missing type suffix"));
5772 info
->qualifier
= vectype_to_qualifier (&vectype
);
5773 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5777 case AARCH64_OPND_CRn
:
5778 case AARCH64_OPND_CRm
:
5780 char prefix
= *(str
++);
5781 if (prefix
!= 'c' && prefix
!= 'C')
5784 po_imm_nc_or_fail ();
5787 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5790 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5791 info
->imm
.value
= val
;
5795 case AARCH64_OPND_SHLL_IMM
:
5796 case AARCH64_OPND_IMM_VLSR
:
5797 po_imm_or_fail (1, 64);
5798 info
->imm
.value
= val
;
5801 case AARCH64_OPND_CCMP_IMM
:
5802 case AARCH64_OPND_SIMM5
:
5803 case AARCH64_OPND_FBITS
:
5804 case AARCH64_OPND_TME_UIMM16
:
5805 case AARCH64_OPND_UIMM4
:
5806 case AARCH64_OPND_UIMM4_ADDG
:
5807 case AARCH64_OPND_UIMM10
:
5808 case AARCH64_OPND_UIMM3_OP1
:
5809 case AARCH64_OPND_UIMM3_OP2
:
5810 case AARCH64_OPND_IMM_VLSL
:
5811 case AARCH64_OPND_IMM
:
5812 case AARCH64_OPND_IMM_2
:
5813 case AARCH64_OPND_WIDTH
:
5814 case AARCH64_OPND_SVE_INV_LIMM
:
5815 case AARCH64_OPND_SVE_LIMM
:
5816 case AARCH64_OPND_SVE_LIMM_MOV
:
5817 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5818 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5819 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22
:
5820 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5821 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5822 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22
:
5823 case AARCH64_OPND_SVE_SIMM5
:
5824 case AARCH64_OPND_SVE_SIMM5B
:
5825 case AARCH64_OPND_SVE_SIMM6
:
5826 case AARCH64_OPND_SVE_SIMM8
:
5827 case AARCH64_OPND_SVE_UIMM3
:
5828 case AARCH64_OPND_SVE_UIMM7
:
5829 case AARCH64_OPND_SVE_UIMM8
:
5830 case AARCH64_OPND_SVE_UIMM8_53
:
5831 case AARCH64_OPND_IMM_ROT1
:
5832 case AARCH64_OPND_IMM_ROT2
:
5833 case AARCH64_OPND_IMM_ROT3
:
5834 case AARCH64_OPND_SVE_IMM_ROT1
:
5835 case AARCH64_OPND_SVE_IMM_ROT2
:
5836 case AARCH64_OPND_SVE_IMM_ROT3
:
5837 po_imm_nc_or_fail ();
5838 info
->imm
.value
= val
;
5841 case AARCH64_OPND_SVE_AIMM
:
5842 case AARCH64_OPND_SVE_ASIMM
:
5843 po_imm_nc_or_fail ();
5844 info
->imm
.value
= val
;
5845 skip_whitespace (str
);
5846 if (skip_past_comma (&str
))
5847 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5849 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5852 case AARCH64_OPND_SVE_PATTERN
:
5853 po_enum_or_fail (aarch64_sve_pattern_array
);
5854 info
->imm
.value
= val
;
5857 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5858 po_enum_or_fail (aarch64_sve_pattern_array
);
5859 info
->imm
.value
= val
;
5860 if (skip_past_comma (&str
)
5861 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5863 if (!info
->shifter
.operator_present
)
5865 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5866 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5867 info
->shifter
.amount
= 1;
5871 case AARCH64_OPND_SVE_PRFOP
:
5872 po_enum_or_fail (aarch64_sve_prfop_array
);
5873 info
->imm
.value
= val
;
5876 case AARCH64_OPND_UIMM7
:
5877 po_imm_or_fail (0, 127);
5878 info
->imm
.value
= val
;
5881 case AARCH64_OPND_IDX
:
5882 case AARCH64_OPND_MASK
:
5883 case AARCH64_OPND_BIT_NUM
:
5884 case AARCH64_OPND_IMMR
:
5885 case AARCH64_OPND_IMMS
:
5886 po_imm_or_fail (0, 63);
5887 info
->imm
.value
= val
;
5890 case AARCH64_OPND_IMM0
:
5891 po_imm_nc_or_fail ();
5894 set_fatal_syntax_error (_("immediate zero expected"));
5897 info
->imm
.value
= 0;
5900 case AARCH64_OPND_FPIMM0
:
5903 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5904 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5905 it is probably not worth the effort to support it. */
5906 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5909 || !(res2
= parse_constant_immediate (&str
, &val
,
5912 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5914 info
->imm
.value
= 0;
5915 info
->imm
.is_fp
= 1;
5918 set_fatal_syntax_error (_("immediate zero expected"));
5922 case AARCH64_OPND_IMM_MOV
:
5925 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5926 reg_name_p (str
, REG_TYPE_VN
))
5929 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5931 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5932 later. fix_mov_imm_insn will try to determine a machine
5933 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5934 message if the immediate cannot be moved by a single
5936 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5937 inst
.base
.operands
[i
].skip
= 1;
5941 case AARCH64_OPND_SIMD_IMM
:
5942 case AARCH64_OPND_SIMD_IMM_SFT
:
5943 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5945 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5947 /* need_libopcodes_p */ 1,
5950 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5951 shift, we don't check it here; we leave the checking to
5952 the libopcodes (operand_general_constraint_met_p). By
5953 doing this, we achieve better diagnostics. */
5954 if (skip_past_comma (&str
)
5955 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5957 if (!info
->shifter
.operator_present
5958 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5960 /* Default to LSL if not present. Libopcodes prefers shifter
5961 kind to be explicit. */
5962 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5963 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5967 case AARCH64_OPND_FPIMM
:
5968 case AARCH64_OPND_SIMD_FPIMM
:
5969 case AARCH64_OPND_SVE_FPIMM8
:
5974 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5975 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5976 || !aarch64_imm_float_p (qfloat
))
5979 set_fatal_syntax_error (_("invalid floating-point"
5983 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5984 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5988 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5989 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5990 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5995 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5996 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5999 set_fatal_syntax_error (_("invalid floating-point"
6003 inst
.base
.operands
[i
].imm
.value
= qfloat
;
6004 inst
.base
.operands
[i
].imm
.is_fp
= 1;
6008 case AARCH64_OPND_LIMM
:
6009 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6010 SHIFTED_LOGIC_IMM
));
6011 if (info
->shifter
.operator_present
)
6013 set_fatal_syntax_error
6014 (_("shift not allowed for bitmask immediate"));
6017 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6019 /* need_libopcodes_p */ 1,
6023 case AARCH64_OPND_AIMM
:
6024 if (opcode
->op
== OP_ADD
)
6025 /* ADD may have relocation types. */
6026 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
6027 SHIFTED_ARITH_IMM
));
6029 po_misc_or_fail (parse_shifter_operand (&str
, info
,
6030 SHIFTED_ARITH_IMM
));
6031 switch (inst
.reloc
.type
)
6033 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
6034 info
->shifter
.amount
= 12;
6036 case BFD_RELOC_UNUSED
:
6037 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6038 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
6039 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
6040 inst
.reloc
.pc_rel
= 0;
6045 info
->imm
.value
= 0;
6046 if (!info
->shifter
.operator_present
)
6048 /* Default to LSL if not present. Libopcodes prefers shifter
6049 kind to be explicit. */
6050 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6051 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6055 case AARCH64_OPND_HALF
:
6057 /* #<imm16> or relocation. */
6058 int internal_fixup_p
;
6059 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6060 if (internal_fixup_p
)
6061 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6062 skip_whitespace (str
);
6063 if (skip_past_comma (&str
))
6065 /* {, LSL #<shift>} */
6066 if (! aarch64_gas_internal_fixup_p ())
6068 set_fatal_syntax_error (_("can't mix relocation modifier "
6069 "with explicit shift"));
6072 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6075 inst
.base
.operands
[i
].shifter
.amount
= 0;
6076 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6077 inst
.base
.operands
[i
].imm
.value
= 0;
6078 if (! process_movw_reloc_info ())
6083 case AARCH64_OPND_EXCEPTION
:
6084 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6086 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6088 /* need_libopcodes_p */ 0,
6092 case AARCH64_OPND_NZCV
:
6094 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6098 info
->imm
.value
= nzcv
->value
;
6101 po_imm_or_fail (0, 15);
6102 info
->imm
.value
= val
;
6106 case AARCH64_OPND_COND
:
6107 case AARCH64_OPND_COND1
:
6112 while (ISALPHA (*str
));
6113 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6114 if (info
->cond
== NULL
)
6116 set_syntax_error (_("invalid condition"));
6119 else if (operands
[i
] == AARCH64_OPND_COND1
6120 && (info
->cond
->value
& 0xe) == 0xe)
6122 /* Do not allow AL or NV. */
6123 set_default_error ();
6129 case AARCH64_OPND_ADDR_ADRP
:
6130 po_misc_or_fail (parse_adrp (&str
));
6131 /* Clear the value as operand needs to be relocated. */
6132 info
->imm
.value
= 0;
6135 case AARCH64_OPND_ADDR_PCREL14
:
6136 case AARCH64_OPND_ADDR_PCREL19
:
6137 case AARCH64_OPND_ADDR_PCREL21
:
6138 case AARCH64_OPND_ADDR_PCREL26
:
6139 po_misc_or_fail (parse_address (&str
, info
));
6140 if (!info
->addr
.pcrel
)
6142 set_syntax_error (_("invalid pc-relative address"));
6145 if (inst
.gen_lit_pool
6146 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6148 /* Only permit "=value" in the literal load instructions.
6149 The literal will be generated by programmer_friendly_fixup. */
6150 set_syntax_error (_("invalid use of \"=immediate\""));
6153 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6155 set_syntax_error (_("unrecognized relocation suffix"));
6158 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6160 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6161 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6165 info
->imm
.value
= 0;
6166 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6167 switch (opcode
->iclass
)
6171 /* e.g. CBZ or B.COND */
6172 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6173 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6177 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6178 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6182 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6184 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6185 : BFD_RELOC_AARCH64_JUMP26
;
6188 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6189 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6192 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6193 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6199 inst
.reloc
.pc_rel
= 1;
6203 case AARCH64_OPND_ADDR_SIMPLE
:
6204 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6206 /* [<Xn|SP>{, #<simm>}] */
6208 /* First use the normal address-parsing routines, to get
6209 the usual syntax errors. */
6210 po_misc_or_fail (parse_address (&str
, info
));
6211 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6212 || !info
->addr
.preind
|| info
->addr
.postind
6213 || info
->addr
.writeback
)
6215 set_syntax_error (_("invalid addressing mode"));
6219 /* Then retry, matching the specific syntax of these addresses. */
6221 po_char_or_fail ('[');
6222 po_reg_or_fail (REG_TYPE_R64_SP
);
6223 /* Accept optional ", #0". */
6224 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6225 && skip_past_char (&str
, ','))
6227 skip_past_char (&str
, '#');
6228 if (! skip_past_char (&str
, '0'))
6230 set_fatal_syntax_error
6231 (_("the optional immediate offset can only be 0"));
6235 po_char_or_fail (']');
6239 case AARCH64_OPND_ADDR_REGOFF
:
6240 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6241 po_misc_or_fail (parse_address (&str
, info
));
6243 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6244 || !info
->addr
.preind
|| info
->addr
.postind
6245 || info
->addr
.writeback
)
6247 set_syntax_error (_("invalid addressing mode"));
6250 if (!info
->shifter
.operator_present
)
6252 /* Default to LSL if not present. Libopcodes prefers shifter
6253 kind to be explicit. */
6254 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6255 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6257 /* Qualifier to be deduced by libopcodes. */
6260 case AARCH64_OPND_ADDR_SIMM7
:
6261 po_misc_or_fail (parse_address (&str
, info
));
6262 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6263 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6265 set_syntax_error (_("invalid addressing mode"));
6268 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6270 set_syntax_error (_("relocation not allowed"));
6273 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6275 /* need_libopcodes_p */ 1,
6279 case AARCH64_OPND_ADDR_SIMM9
:
6280 case AARCH64_OPND_ADDR_SIMM9_2
:
6281 case AARCH64_OPND_ADDR_SIMM11
:
6282 case AARCH64_OPND_ADDR_SIMM13
:
6283 po_misc_or_fail (parse_address (&str
, info
));
6284 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6285 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6286 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6287 && info
->addr
.writeback
))
6289 set_syntax_error (_("invalid addressing mode"));
6292 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6294 set_syntax_error (_("relocation not allowed"));
6297 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6299 /* need_libopcodes_p */ 1,
6303 case AARCH64_OPND_ADDR_SIMM10
:
6304 case AARCH64_OPND_ADDR_OFFSET
:
6305 po_misc_or_fail (parse_address (&str
, info
));
6306 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6307 || !info
->addr
.preind
|| info
->addr
.postind
)
6309 set_syntax_error (_("invalid addressing mode"));
6312 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6314 set_syntax_error (_("relocation not allowed"));
6317 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6319 /* need_libopcodes_p */ 1,
6323 case AARCH64_OPND_ADDR_UIMM12
:
6324 po_misc_or_fail (parse_address (&str
, info
));
6325 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6326 || !info
->addr
.preind
|| info
->addr
.writeback
)
6328 set_syntax_error (_("invalid addressing mode"));
6331 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6332 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6333 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6335 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6337 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6339 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6341 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6342 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6343 /* Leave qualifier to be determined by libopcodes. */
6346 case AARCH64_OPND_SIMD_ADDR_POST
:
6347 /* [<Xn|SP>], <Xm|#<amount>> */
6348 po_misc_or_fail (parse_address (&str
, info
));
6349 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6351 set_syntax_error (_("invalid addressing mode"));
6354 if (!info
->addr
.offset
.is_reg
)
6356 if (inst
.reloc
.exp
.X_op
== O_constant
)
6357 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6360 set_fatal_syntax_error
6361 (_("writeback value must be an immediate constant"));
6368 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6369 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6370 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6371 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6372 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6373 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6374 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6375 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6376 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6377 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6378 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6379 /* [X<n>{, #imm, MUL VL}]
6381 but recognizing SVE registers. */
6382 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6383 &offset_qualifier
));
6384 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6386 set_syntax_error (_("invalid addressing mode"));
6390 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6391 || !info
->addr
.preind
|| info
->addr
.writeback
)
6393 set_syntax_error (_("invalid addressing mode"));
6396 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6397 || inst
.reloc
.exp
.X_op
!= O_constant
)
6399 /* Make sure this has priority over
6400 "invalid addressing mode". */
6401 set_fatal_syntax_error (_("constant offset required"));
6404 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6407 case AARCH64_OPND_SVE_ADDR_R
:
6408 /* [<Xn|SP>{, <R><m>}]
6409 but recognizing SVE registers. */
6410 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6411 &offset_qualifier
));
6412 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6414 offset_qualifier
= AARCH64_OPND_QLF_X
;
6415 info
->addr
.offset
.is_reg
= 1;
6416 info
->addr
.offset
.regno
= 31;
6418 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6419 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6421 set_syntax_error (_("invalid addressing mode"));
6426 case AARCH64_OPND_SVE_ADDR_RR
:
6427 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6428 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6429 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6430 case AARCH64_OPND_SVE_ADDR_RX
:
6431 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6432 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6433 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6434 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6435 but recognizing SVE registers. */
6436 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6437 &offset_qualifier
));
6438 if (base_qualifier
!= AARCH64_OPND_QLF_X
6439 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6441 set_syntax_error (_("invalid addressing mode"));
6446 case AARCH64_OPND_SVE_ADDR_RZ
:
6447 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6448 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6449 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6450 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6451 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6452 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6453 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6454 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6455 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6456 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6457 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6458 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6459 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6460 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6461 &offset_qualifier
));
6462 if (base_qualifier
!= AARCH64_OPND_QLF_X
6463 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6464 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6466 set_syntax_error (_("invalid addressing mode"));
6469 info
->qualifier
= offset_qualifier
;
6472 case AARCH64_OPND_SVE_ADDR_ZX
:
6473 /* [Zn.<T>{, <Xm>}]. */
6474 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6475 &offset_qualifier
));
6477 base_qualifier either S_S or S_D
6478 offset_qualifier must be X
6480 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6481 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6482 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6484 set_syntax_error (_("invalid addressing mode"));
6487 info
->qualifier
= base_qualifier
;
6488 if (!info
->addr
.offset
.is_reg
|| info
->addr
.pcrel
6489 || !info
->addr
.preind
|| info
->addr
.writeback
6490 || info
->shifter
.operator_present
!= 0)
6492 set_syntax_error (_("invalid addressing mode"));
6495 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6499 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6500 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6501 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6502 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6503 /* [Z<n>.<T>{, #imm}] */
6504 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6505 &offset_qualifier
));
6506 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6507 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6509 set_syntax_error (_("invalid addressing mode"));
6512 info
->qualifier
= base_qualifier
;
6515 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6516 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6517 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6518 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6519 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6523 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6525 here since we get better error messages by leaving it to
6526 the qualifier checking routines. */
6527 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6528 &offset_qualifier
));
6529 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6530 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6531 || offset_qualifier
!= base_qualifier
)
6533 set_syntax_error (_("invalid addressing mode"));
6536 info
->qualifier
= base_qualifier
;
6539 case AARCH64_OPND_SYSREG
:
6541 uint32_t sysreg_flags
;
6542 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6543 &sysreg_flags
)) == PARSE_FAIL
)
6545 set_syntax_error (_("unknown or missing system register name"));
6548 inst
.base
.operands
[i
].sysreg
.value
= val
;
6549 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6553 case AARCH64_OPND_PSTATEFIELD
:
6554 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6557 set_syntax_error (_("unknown or missing PSTATE field name"));
6560 inst
.base
.operands
[i
].pstatefield
= val
;
6563 case AARCH64_OPND_SYSREG_IC
:
6564 inst
.base
.operands
[i
].sysins_op
=
6565 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6568 case AARCH64_OPND_SYSREG_DC
:
6569 inst
.base
.operands
[i
].sysins_op
=
6570 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6573 case AARCH64_OPND_SYSREG_AT
:
6574 inst
.base
.operands
[i
].sysins_op
=
6575 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6578 case AARCH64_OPND_SYSREG_SR
:
6579 inst
.base
.operands
[i
].sysins_op
=
6580 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6583 case AARCH64_OPND_SYSREG_TLBI
:
6584 inst
.base
.operands
[i
].sysins_op
=
6585 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6587 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6589 set_fatal_syntax_error ( _("unknown or missing operation name"));
6594 case AARCH64_OPND_BARRIER
:
6595 case AARCH64_OPND_BARRIER_ISB
:
6596 val
= parse_barrier (&str
);
6597 if (val
!= PARSE_FAIL
6598 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6600 /* ISB only accepts options name 'sy'. */
6602 (_("the specified option is not accepted in ISB"));
6603 /* Turn off backtrack as this optional operand is present. */
6607 /* This is an extension to accept a 0..15 immediate. */
6608 if (val
== PARSE_FAIL
)
6609 po_imm_or_fail (0, 15);
6610 info
->barrier
= aarch64_barrier_options
+ val
;
6613 case AARCH64_OPND_PRFOP
:
6614 val
= parse_pldop (&str
);
6615 /* This is an extension to accept a 0..31 immediate. */
6616 if (val
== PARSE_FAIL
)
6617 po_imm_or_fail (0, 31);
6618 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6621 case AARCH64_OPND_BARRIER_PSB
:
6622 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6623 if (val
== PARSE_FAIL
)
6627 case AARCH64_OPND_BTI_TARGET
:
6628 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6629 if (val
== PARSE_FAIL
)
6634 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6637 /* If we get here, this operand was successfully parsed. */
6638 inst
.base
.operands
[i
].present
= 1;
6642 /* The parse routine should already have set the error, but in case
6643 not, set a default one here. */
6645 set_default_error ();
6647 if (! backtrack_pos
)
6648 goto parse_operands_return
;
6651 /* We reach here because this operand is marked as optional, and
6652 either no operand was supplied or the operand was supplied but it
6653 was syntactically incorrect. In the latter case we report an
6654 error. In the former case we perform a few more checks before
6655 dropping through to the code to insert the default operand. */
6657 char *tmp
= backtrack_pos
;
6658 char endchar
= END_OF_INSN
;
6660 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6662 skip_past_char (&tmp
, ',');
6664 if (*tmp
!= endchar
)
6665 /* The user has supplied an operand in the wrong format. */
6666 goto parse_operands_return
;
6668 /* Make sure there is not a comma before the optional operand.
6669 For example the fifth operand of 'sys' is optional:
6671 sys #0,c0,c0,#0, <--- wrong
6672 sys #0,c0,c0,#0 <--- correct. */
6673 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6675 set_fatal_syntax_error
6676 (_("unexpected comma before the omitted optional operand"));
6677 goto parse_operands_return
;
6681 /* Reaching here means we are dealing with an optional operand that is
6682 omitted from the assembly line. */
6683 gas_assert (optional_operand_p (opcode
, i
));
6685 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6687 /* Try again, skipping the optional operand at backtrack_pos. */
6688 str
= backtrack_pos
;
6691 /* Clear any error record after the omitted optional operand has been
6692 successfully handled. */
6696 /* Check if we have parsed all the operands. */
6697 if (*str
!= '\0' && ! error_p ())
6699 /* Set I to the index of the last present operand; this is
6700 for the purpose of diagnostics. */
6701 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6703 set_fatal_syntax_error
6704 (_("unexpected characters following instruction"));
6707 parse_operands_return
:
6711 DEBUG_TRACE ("parsing FAIL: %s - %s",
6712 operand_mismatch_kind_names
[get_error_kind ()],
6713 get_error_message ());
6714 /* Record the operand error properly; this is useful when there
6715 are multiple instruction templates for a mnemonic name, so that
6716 later on, we can select the error that most closely describes
6718 record_operand_error (opcode
, i
, get_error_kind (),
6719 get_error_message ());
6724 DEBUG_TRACE ("parsing SUCCESS");
6729 /* It does some fix-up to provide some programmer friendly feature while
6730 keeping the libopcodes happy, i.e. libopcodes only accepts
6731 the preferred architectural syntax.
6732 Return FALSE if there is any failure; otherwise return TRUE. */
6735 programmer_friendly_fixup (aarch64_instruction
*instr
)
6737 aarch64_inst
*base
= &instr
->base
;
6738 const aarch64_opcode
*opcode
= base
->opcode
;
6739 enum aarch64_op op
= opcode
->op
;
6740 aarch64_opnd_info
*operands
= base
->operands
;
6742 DEBUG_TRACE ("enter");
6744 switch (opcode
->iclass
)
6747 /* TBNZ Xn|Wn, #uimm6, label
6748 Test and Branch Not Zero: conditionally jumps to label if bit number
6749 uimm6 in register Xn is not zero. The bit number implies the width of
6750 the register, which may be written and should be disassembled as Wn if
6751 uimm is less than 32. */
6752 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6754 if (operands
[1].imm
.value
>= 32)
6756 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6760 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6764 /* LDR Wt, label | =value
6765 As a convenience assemblers will typically permit the notation
6766 "=value" in conjunction with the pc-relative literal load instructions
6767 to automatically place an immediate value or symbolic address in a
6768 nearby literal pool and generate a hidden label which references it.
6769 ISREG has been set to 0 in the case of =value. */
6770 if (instr
->gen_lit_pool
6771 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6773 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6774 if (op
== OP_LDRSW_LIT
)
6776 if (instr
->reloc
.exp
.X_op
!= O_constant
6777 && instr
->reloc
.exp
.X_op
!= O_big
6778 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6780 record_operand_error (opcode
, 1,
6781 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6782 _("constant expression expected"));
6785 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6787 record_operand_error (opcode
, 1,
6788 AARCH64_OPDE_OTHER_ERROR
,
6789 _("literal pool insertion failed"));
6797 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6798 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6799 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6800 A programmer-friendly assembler should accept a destination Xd in
6801 place of Wd, however that is not the preferred form for disassembly.
6803 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6804 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6805 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6806 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6811 /* In the 64-bit form, the final register operand is written as Wm
6812 for all but the (possibly omitted) UXTX/LSL and SXTX
6814 As a programmer-friendly assembler, we accept e.g.
6815 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6816 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6817 int idx
= aarch64_operand_index (opcode
->operands
,
6818 AARCH64_OPND_Rm_EXT
);
6819 gas_assert (idx
== 1 || idx
== 2);
6820 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6821 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6822 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6823 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6824 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6825 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6833 DEBUG_TRACE ("exit with SUCCESS");
6837 /* Check for loads and stores that will cause unpredictable behavior. */
6840 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6842 aarch64_inst
*base
= &instr
->base
;
6843 const aarch64_opcode
*opcode
= base
->opcode
;
6844 const aarch64_opnd_info
*opnds
= base
->operands
;
6845 switch (opcode
->iclass
)
6852 /* Loading/storing the base register is unpredictable if writeback. */
6853 if ((aarch64_get_operand_class (opnds
[0].type
)
6854 == AARCH64_OPND_CLASS_INT_REG
)
6855 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6856 && opnds
[1].addr
.base_regno
!= REG_SP
6857 /* Exempt STG/STZG/ST2G/STZ2G. */
6858 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6859 && opnds
[1].addr
.writeback
)
6860 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6864 case ldstnapair_offs
:
6865 case ldstpair_indexed
:
6866 /* Loading/storing the base register is unpredictable if writeback. */
6867 if ((aarch64_get_operand_class (opnds
[0].type
)
6868 == AARCH64_OPND_CLASS_INT_REG
)
6869 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6870 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6871 && opnds
[2].addr
.base_regno
!= REG_SP
6873 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6874 && opnds
[2].addr
.writeback
)
6875 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6876 /* Load operations must load different registers. */
6877 if ((opcode
->opcode
& (1 << 22))
6878 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6879 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6883 /* It is unpredictable if the destination and status registers are the
6885 if ((aarch64_get_operand_class (opnds
[0].type
)
6886 == AARCH64_OPND_CLASS_INT_REG
)
6887 && (aarch64_get_operand_class (opnds
[1].type
)
6888 == AARCH64_OPND_CLASS_INT_REG
)
6889 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6890 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6891 as_warn (_("unpredictable: identical transfer and status registers"
6903 force_automatic_sequence_close (void)
6905 if (now_instr_sequence
.instr
)
6907 as_warn (_("previous `%s' sequence has not been closed"),
6908 now_instr_sequence
.instr
->opcode
->name
);
6909 init_insn_sequence (NULL
, &now_instr_sequence
);
6913 /* A wrapper function to interface with libopcodes on encoding and
6914 record the error message if there is any.
6916 Return TRUE on success; otherwise return FALSE. */
6919 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6922 aarch64_operand_error error_info
;
6923 memset (&error_info
, '\0', sizeof (error_info
));
6924 error_info
.kind
= AARCH64_OPDE_NIL
;
6925 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6926 && !error_info
.non_fatal
)
6929 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6930 record_operand_error_info (opcode
, &error_info
);
6931 return error_info
.non_fatal
;
6934 #ifdef DEBUG_AARCH64
6936 dump_opcode_operands (const aarch64_opcode
*opcode
)
6939 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6941 aarch64_verbose ("\t\t opnd%d: %s", i
,
6942 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6943 ? aarch64_get_operand_name (opcode
->operands
[i
])
6944 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6948 #endif /* DEBUG_AARCH64 */
6950 /* This is the guts of the machine-dependent assembler. STR points to a
6951 machine dependent instruction. This function is supposed to emit
6952 the frags/bytes it assembles to. */
6955 md_assemble (char *str
)
6958 templates
*template;
6959 aarch64_opcode
*opcode
;
6960 aarch64_inst
*inst_base
;
6961 unsigned saved_cond
;
6963 /* Align the previous label if needed. */
6964 if (last_label_seen
!= NULL
)
6966 symbol_set_frag (last_label_seen
, frag_now
);
6967 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6968 S_SET_SEGMENT (last_label_seen
, now_seg
);
6971 /* Update the current insn_sequence from the segment. */
6972 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6974 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6976 DEBUG_TRACE ("\n\n");
6977 DEBUG_TRACE ("==============================");
6978 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6980 template = opcode_lookup (&p
);
6983 /* It wasn't an instruction, but it might be a register alias of
6984 the form alias .req reg directive. */
6985 if (!create_register_alias (str
, p
))
6986 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6991 skip_whitespace (p
);
6994 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6995 get_mnemonic_name (str
), str
);
6999 init_operand_error_report ();
7001 /* Sections are assumed to start aligned. In executable section, there is no
7002 MAP_DATA symbol pending. So we only align the address during
7003 MAP_DATA --> MAP_INSN transition.
7004 For other sections, this is not guaranteed. */
7005 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
7006 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
7007 frag_align_code (2, 0);
7009 saved_cond
= inst
.cond
;
7010 reset_aarch64_instruction (&inst
);
7011 inst
.cond
= saved_cond
;
7013 /* Iterate through all opcode entries with the same mnemonic name. */
7016 opcode
= template->opcode
;
7018 DEBUG_TRACE ("opcode %s found", opcode
->name
);
7019 #ifdef DEBUG_AARCH64
7021 dump_opcode_operands (opcode
);
7022 #endif /* DEBUG_AARCH64 */
7024 mapping_state (MAP_INSN
);
7026 inst_base
= &inst
.base
;
7027 inst_base
->opcode
= opcode
;
7029 /* Truly conditionally executed instructions, e.g. b.cond. */
7030 if (opcode
->flags
& F_COND
)
7032 gas_assert (inst
.cond
!= COND_ALWAYS
);
7033 inst_base
->cond
= get_cond_from_value (inst
.cond
);
7034 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
7036 else if (inst
.cond
!= COND_ALWAYS
)
7038 /* It shouldn't arrive here, where the assembly looks like a
7039 conditional instruction but the found opcode is unconditional. */
7044 if (parse_operands (p
, opcode
)
7045 && programmer_friendly_fixup (&inst
)
7046 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
7048 /* Check that this instruction is supported for this CPU. */
7049 if (!opcode
->avariant
7050 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
7052 as_bad (_("selected processor does not support `%s'"), str
);
7056 warn_unpredictable_ldst (&inst
, str
);
7058 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
7059 || !inst
.reloc
.need_libopcodes_p
)
7063 /* If there is relocation generated for the instruction,
7064 store the instruction information for the future fix-up. */
7065 struct aarch64_inst
*copy
;
7066 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
7067 copy
= XNEW (struct aarch64_inst
);
7068 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
7072 /* Issue non-fatal messages if any. */
7073 output_operand_error_report (str
, TRUE
);
7077 template = template->next
;
7078 if (template != NULL
)
7080 reset_aarch64_instruction (&inst
);
7081 inst
.cond
= saved_cond
;
7084 while (template != NULL
);
7086 /* Issue the error messages if any. */
7087 output_operand_error_report (str
, FALSE
);
7090 /* Various frobbings of labels and their addresses. */
7093 aarch64_start_line_hook (void)
7095 last_label_seen
= NULL
;
7099 aarch64_frob_label (symbolS
* sym
)
7101 last_label_seen
= sym
;
7103 dwarf2_emit_label (sym
);
7107 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7109 /* Check to see if we have a block to close. */
7110 force_automatic_sequence_close ();
7114 aarch64_data_in_code (void)
7116 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7118 *input_line_pointer
= '/';
7119 input_line_pointer
+= 5;
7120 *input_line_pointer
= 0;
7128 aarch64_canonicalize_symbol_name (char *name
)
7132 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7133 *(name
+ len
- 5) = 0;
7138 /* Table of all register names defined by default. The user can
7139 define additional names with .req. Note that all register names
7140 should appear in both upper and lowercase variants. Some registers
7141 also have mixed-case names. */
7143 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7144 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7145 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7146 #define REGSET16(p,t) \
7147 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7148 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7149 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7150 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7151 #define REGSET31(p,t) \
7153 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7154 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7155 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7156 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7157 #define REGSET(p,t) \
7158 REGSET31(p,t), REGNUM(p,31,t)
7160 /* These go into aarch64_reg_hsh hash-table. */
7161 static const reg_entry reg_names
[] = {
7162 /* Integer registers. */
7163 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7164 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7166 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7167 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7168 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7169 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7170 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7171 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7173 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7174 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7176 /* Floating-point single precision registers. */
7177 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7179 /* Floating-point double precision registers. */
7180 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7182 /* Floating-point half precision registers. */
7183 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7185 /* Floating-point byte precision registers. */
7186 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7188 /* Floating-point quad precision registers. */
7189 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7191 /* FP/SIMD registers. */
7192 REGSET (v
, VN
), REGSET (V
, VN
),
7194 /* SVE vector registers. */
7195 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7197 /* SVE predicate registers. */
7198 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7216 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7217 static const asm_nzcv nzcv_names
[] = {
7218 {"nzcv", B (n
, z
, c
, v
)},
7219 {"nzcV", B (n
, z
, c
, V
)},
7220 {"nzCv", B (n
, z
, C
, v
)},
7221 {"nzCV", B (n
, z
, C
, V
)},
7222 {"nZcv", B (n
, Z
, c
, v
)},
7223 {"nZcV", B (n
, Z
, c
, V
)},
7224 {"nZCv", B (n
, Z
, C
, v
)},
7225 {"nZCV", B (n
, Z
, C
, V
)},
7226 {"Nzcv", B (N
, z
, c
, v
)},
7227 {"NzcV", B (N
, z
, c
, V
)},
7228 {"NzCv", B (N
, z
, C
, v
)},
7229 {"NzCV", B (N
, z
, C
, V
)},
7230 {"NZcv", B (N
, Z
, c
, v
)},
7231 {"NZcV", B (N
, Z
, c
, V
)},
7232 {"NZCv", B (N
, Z
, C
, v
)},
7233 {"NZCV", B (N
, Z
, C
, V
)}
7246 /* MD interface: bits in the object file. */
7248 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7249 for use in the a.out file, and stores them in the array pointed to by buf.
7250 This knows about the endian-ness of the target machine and does
7251 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7252 2 (short) and 4 (long) Floating numbers are put out as a series of
7253 LITTLENUMS (shorts, here at least). */
7256 md_number_to_chars (char *buf
, valueT val
, int n
)
7258 if (target_big_endian
)
7259 number_to_chars_bigendian (buf
, val
, n
);
7261 number_to_chars_littleendian (buf
, val
, n
);
7264 /* MD interface: Sections. */
7266 /* Estimate the size of a frag before relaxing. Assume everything fits in
7270 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7276 /* Round up a section size to the appropriate boundary. */
7279 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7284 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7285 of an rs_align_code fragment.
7287 Here we fill the frag with the appropriate info for padding the
7288 output stream. The resulting frag will consist of a fixed (fr_fix)
7289 and of a repeating (fr_var) part.
7291 The fixed content is always emitted before the repeating content and
7292 these two parts are used as follows in constructing the output:
7293 - the fixed part will be used to align to a valid instruction word
7294 boundary, in case that we start at a misaligned address; as no
7295 executable instruction can live at the misaligned location, we
7296 simply fill with zeros;
7297 - the variable part will be used to cover the remaining padding and
7298 we fill using the AArch64 NOP instruction.
7300 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7301 enough storage space for up to 3 bytes for padding the back to a valid
7302 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7305 aarch64_handle_align (fragS
* fragP
)
7307 /* NOP = d503201f */
7308 /* AArch64 instructions are always little-endian. */
7309 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7311 int bytes
, fix
, noop_size
;
7314 if (fragP
->fr_type
!= rs_align_code
)
7317 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7318 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7321 gas_assert (fragP
->tc_frag_data
.recorded
);
7324 noop_size
= sizeof (aarch64_noop
);
7326 fix
= bytes
& (noop_size
- 1);
7330 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7334 fragP
->fr_fix
+= fix
;
7338 memcpy (p
, aarch64_noop
, noop_size
);
7339 fragP
->fr_var
= noop_size
;
7342 /* Perform target specific initialisation of a frag.
7343 Note - despite the name this initialisation is not done when the frag
7344 is created, but only when its type is assigned. A frag can be created
7345 and used a long time before its type is set, so beware of assuming that
7346 this initialisation is performed first. */
7350 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7351 int max_chars ATTRIBUTE_UNUSED
)
7355 #else /* OBJ_ELF is defined. */
7357 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7359 /* Record a mapping symbol for alignment frags. We will delete this
7360 later if the alignment ends up empty. */
7361 if (!fragP
->tc_frag_data
.recorded
)
7362 fragP
->tc_frag_data
.recorded
= 1;
7364 /* PR 21809: Do not set a mapping state for debug sections
7365 - it just confuses other tools. */
7366 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
7369 switch (fragP
->fr_type
)
7373 mapping_state_2 (MAP_DATA
, max_chars
);
7376 /* PR 20364: We can get alignment frags in code sections,
7377 so do not just assume that we should use the MAP_DATA state. */
7378 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7381 mapping_state_2 (MAP_INSN
, max_chars
);
7388 /* Initialize the DWARF-2 unwind information for this procedure. */
7391 tc_aarch64_frame_initial_instructions (void)
7393 cfi_add_CFA_def_cfa (REG_SP
, 0);
7395 #endif /* OBJ_ELF */
7397 /* Convert REGNAME to a DWARF-2 register number. */
7400 tc_aarch64_regname_to_dw2regnum (char *regname
)
7402 const reg_entry
*reg
= parse_reg (®name
);
7408 case REG_TYPE_SP_32
:
7409 case REG_TYPE_SP_64
:
7419 return reg
->number
+ 64;
7427 /* Implement DWARF2_ADDR_SIZE. */
7430 aarch64_dwarf2_addr_size (void)
7432 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7436 return bfd_arch_bits_per_address (stdoutput
) / 8;
7439 /* MD interface: Symbol and relocation handling. */
7441 /* Return the address within the segment that a PC-relative fixup is
7442 relative to. For AArch64 PC-relative fixups applied to instructions
7443 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7446 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7448 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7450 /* If this is pc-relative and we are going to emit a relocation
7451 then we just want to put out any pipeline compensation that the linker
7452 will need. Otherwise we want to use the calculated base. */
7454 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7455 || aarch64_force_relocation (fixP
)))
7458 /* AArch64 should be consistent for all pc-relative relocations. */
7459 return base
+ AARCH64_PCREL_OFFSET
;
7462 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7463 Otherwise we have no need to default values of symbols. */
7466 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7469 if (name
[0] == '_' && name
[1] == 'G'
7470 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7474 if (symbol_find (name
))
7475 as_bad (_("GOT already in the symbol table"));
7477 GOT_symbol
= symbol_new (name
, undefined_section
,
7478 (valueT
) 0, &zero_address_frag
);
7488 /* Return non-zero if the indicated VALUE has overflowed the maximum
7489 range expressible by a unsigned number with the indicated number of
7493 unsigned_overflow (valueT value
, unsigned bits
)
7496 if (bits
>= sizeof (valueT
) * 8)
7498 lim
= (valueT
) 1 << bits
;
7499 return (value
>= lim
);
7503 /* Return non-zero if the indicated VALUE has overflowed the maximum
7504 range expressible by an signed number with the indicated number of
7508 signed_overflow (offsetT value
, unsigned bits
)
7511 if (bits
>= sizeof (offsetT
) * 8)
7513 lim
= (offsetT
) 1 << (bits
- 1);
7514 return (value
< -lim
|| value
>= lim
);
7517 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7518 unsigned immediate offset load/store instruction, try to encode it as
7519 an unscaled, 9-bit, signed immediate offset load/store instruction.
7520 Return TRUE if it is successful; otherwise return FALSE.
7522 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7523 in response to the standard LDR/STR mnemonics when the immediate offset is
7524 unambiguous, i.e. when it is negative or unaligned. */
7527 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7530 enum aarch64_op new_op
;
7531 const aarch64_opcode
*new_opcode
;
7533 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7535 switch (instr
->opcode
->op
)
7537 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7538 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7539 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7540 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7541 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7542 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7543 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7544 case OP_STR_POS
: new_op
= OP_STUR
; break;
7545 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7546 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7547 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7548 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7549 default: new_op
= OP_NIL
; break;
7552 if (new_op
== OP_NIL
)
7555 new_opcode
= aarch64_get_opcode (new_op
);
7556 gas_assert (new_opcode
!= NULL
);
7558 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7559 instr
->opcode
->op
, new_opcode
->op
);
7561 aarch64_replace_opcode (instr
, new_opcode
);
7563 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7564 qualifier matching may fail because the out-of-date qualifier will
7565 prevent the operand being updated with a new and correct qualifier. */
7566 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7567 AARCH64_OPND_ADDR_SIMM9
);
7568 gas_assert (idx
== 1);
7569 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7571 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7573 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7580 /* Called by fix_insn to fix a MOV immediate alias instruction.
7582 Operand for a generic move immediate instruction, which is an alias
7583 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7584 a 32-bit/64-bit immediate value into general register. An assembler error
7585 shall result if the immediate cannot be created by a single one of these
7586 instructions. If there is a choice, then to ensure reversability an
7587 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7590 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7592 const aarch64_opcode
*opcode
;
7594 /* Need to check if the destination is SP/ZR. The check has to be done
7595 before any aarch64_replace_opcode. */
7596 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7597 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7599 instr
->operands
[1].imm
.value
= value
;
7600 instr
->operands
[1].skip
= 0;
7604 /* Try the MOVZ alias. */
7605 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7606 aarch64_replace_opcode (instr
, opcode
);
7607 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7608 &instr
->value
, NULL
, NULL
, insn_sequence
))
7610 put_aarch64_insn (buf
, instr
->value
);
7613 /* Try the MOVK alias. */
7614 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7615 aarch64_replace_opcode (instr
, opcode
);
7616 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7617 &instr
->value
, NULL
, NULL
, insn_sequence
))
7619 put_aarch64_insn (buf
, instr
->value
);
7624 if (try_mov_bitmask_p
)
7626 /* Try the ORR alias. */
7627 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7628 aarch64_replace_opcode (instr
, opcode
);
7629 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7630 &instr
->value
, NULL
, NULL
, insn_sequence
))
7632 put_aarch64_insn (buf
, instr
->value
);
7637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7638 _("immediate cannot be moved by a single instruction"));
7641 /* An instruction operand which is immediate related may have symbol used
7642 in the assembly, e.g.
7645 .set u32, 0x00ffff00
7647 At the time when the assembly instruction is parsed, a referenced symbol,
7648 like 'u32' in the above example may not have been seen; a fixS is created
7649 in such a case and is handled here after symbols have been resolved.
7650 Instruction is fixed up with VALUE using the information in *FIXP plus
7651 extra information in FLAGS.
7653 This function is called by md_apply_fix to fix up instructions that need
7654 a fix-up described above but does not involve any linker-time relocation. */
7657 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7661 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7662 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7663 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7667 /* Now the instruction is about to be fixed-up, so the operand that
7668 was previously marked as 'ignored' needs to be unmarked in order
7669 to get the encoding done properly. */
7670 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7671 new_inst
->operands
[idx
].skip
= 0;
7674 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7678 case AARCH64_OPND_EXCEPTION
:
7679 if (unsigned_overflow (value
, 16))
7680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7681 _("immediate out of range"));
7682 insn
= get_aarch64_insn (buf
);
7683 insn
|= encode_svc_imm (value
);
7684 put_aarch64_insn (buf
, insn
);
7687 case AARCH64_OPND_AIMM
:
7688 /* ADD or SUB with immediate.
7689 NOTE this assumes we come here with a add/sub shifted reg encoding
7690 3 322|2222|2 2 2 21111 111111
7691 1 098|7654|3 2 1 09876 543210 98765 43210
7692 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7693 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7694 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7695 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7697 3 322|2222|2 2 221111111111
7698 1 098|7654|3 2 109876543210 98765 43210
7699 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7700 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7701 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7702 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7703 Fields sf Rn Rd are already set. */
7704 insn
= get_aarch64_insn (buf
);
7708 insn
= reencode_addsub_switch_add_sub (insn
);
7712 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7713 && unsigned_overflow (value
, 12))
7715 /* Try to shift the value by 12 to make it fit. */
7716 if (((value
>> 12) << 12) == value
7717 && ! unsigned_overflow (value
, 12 + 12))
7720 insn
|= encode_addsub_imm_shift_amount (1);
7724 if (unsigned_overflow (value
, 12))
7725 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7726 _("immediate out of range"));
7728 insn
|= encode_addsub_imm (value
);
7730 put_aarch64_insn (buf
, insn
);
7733 case AARCH64_OPND_SIMD_IMM
:
7734 case AARCH64_OPND_SIMD_IMM_SFT
:
7735 case AARCH64_OPND_LIMM
:
7736 /* Bit mask immediate. */
7737 gas_assert (new_inst
!= NULL
);
7738 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7739 new_inst
->operands
[idx
].imm
.value
= value
;
7740 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7741 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7742 put_aarch64_insn (buf
, new_inst
->value
);
7744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7745 _("invalid immediate"));
7748 case AARCH64_OPND_HALF
:
7749 /* 16-bit unsigned immediate. */
7750 if (unsigned_overflow (value
, 16))
7751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7752 _("immediate out of range"));
7753 insn
= get_aarch64_insn (buf
);
7754 insn
|= encode_movw_imm (value
& 0xffff);
7755 put_aarch64_insn (buf
, insn
);
7758 case AARCH64_OPND_IMM_MOV
:
7759 /* Operand for a generic move immediate instruction, which is
7760 an alias instruction that generates a single MOVZ, MOVN or ORR
7761 instruction to loads a 32-bit/64-bit immediate value into general
7762 register. An assembler error shall result if the immediate cannot be
7763 created by a single one of these instructions. If there is a choice,
7764 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7765 and MOVZ or MOVN to ORR. */
7766 gas_assert (new_inst
!= NULL
);
7767 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7770 case AARCH64_OPND_ADDR_SIMM7
:
7771 case AARCH64_OPND_ADDR_SIMM9
:
7772 case AARCH64_OPND_ADDR_SIMM9_2
:
7773 case AARCH64_OPND_ADDR_SIMM10
:
7774 case AARCH64_OPND_ADDR_UIMM12
:
7775 case AARCH64_OPND_ADDR_SIMM11
:
7776 case AARCH64_OPND_ADDR_SIMM13
:
7777 /* Immediate offset in an address. */
7778 insn
= get_aarch64_insn (buf
);
7780 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7781 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7782 || new_inst
->opcode
->operands
[2] == opnd
);
7784 /* Get the index of the address operand. */
7785 if (new_inst
->opcode
->operands
[1] == opnd
)
7786 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7789 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7792 /* Update the resolved offset value. */
7793 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7795 /* Encode/fix-up. */
7796 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7797 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7799 put_aarch64_insn (buf
, new_inst
->value
);
7802 else if (new_inst
->opcode
->iclass
== ldst_pos
7803 && try_to_encode_as_unscaled_ldst (new_inst
))
7805 put_aarch64_insn (buf
, new_inst
->value
);
7809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7810 _("immediate offset out of range"));
7815 as_fatal (_("unhandled operand code %d"), opnd
);
7819 /* Apply a fixup (fixP) to segment data, once it has been determined
7820 by our caller that we have all the info we need to fix it up.
7822 Parameter valP is the pointer to the value of the bits. */
7825 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7827 offsetT value
= *valP
;
7829 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7831 unsigned flags
= fixP
->fx_addnumber
;
7833 DEBUG_TRACE ("\n\n");
7834 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7835 DEBUG_TRACE ("Enter md_apply_fix");
7837 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7839 /* Note whether this will delete the relocation. */
7841 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7844 /* Process the relocations. */
7845 switch (fixP
->fx_r_type
)
7847 case BFD_RELOC_NONE
:
7848 /* This will need to go in the object file. */
7853 case BFD_RELOC_8_PCREL
:
7854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7855 md_number_to_chars (buf
, value
, 1);
7859 case BFD_RELOC_16_PCREL
:
7860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7861 md_number_to_chars (buf
, value
, 2);
7865 case BFD_RELOC_32_PCREL
:
7866 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7867 md_number_to_chars (buf
, value
, 4);
7871 case BFD_RELOC_64_PCREL
:
7872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7873 md_number_to_chars (buf
, value
, 8);
7876 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7877 /* We claim that these fixups have been processed here, even if
7878 in fact we generate an error because we do not have a reloc
7879 for them, so tc_gen_reloc() will reject them. */
7881 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7884 _("undefined symbol %s used as an immediate value"),
7885 S_GET_NAME (fixP
->fx_addsy
));
7886 goto apply_fix_return
;
7888 fix_insn (fixP
, flags
, value
);
7891 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7892 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7896 _("pc-relative load offset not word aligned"));
7897 if (signed_overflow (value
, 21))
7898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7899 _("pc-relative load offset out of range"));
7900 insn
= get_aarch64_insn (buf
);
7901 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7902 put_aarch64_insn (buf
, insn
);
7906 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7909 if (signed_overflow (value
, 21))
7910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7911 _("pc-relative address offset out of range"));
7912 insn
= get_aarch64_insn (buf
);
7913 insn
|= encode_adr_imm (value
);
7914 put_aarch64_insn (buf
, insn
);
7918 case BFD_RELOC_AARCH64_BRANCH19
:
7919 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7923 _("conditional branch target not word aligned"));
7924 if (signed_overflow (value
, 21))
7925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7926 _("conditional branch out of range"));
7927 insn
= get_aarch64_insn (buf
);
7928 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7929 put_aarch64_insn (buf
, insn
);
7933 case BFD_RELOC_AARCH64_TSTBR14
:
7934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7938 _("conditional branch target not word aligned"));
7939 if (signed_overflow (value
, 16))
7940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7941 _("conditional branch out of range"));
7942 insn
= get_aarch64_insn (buf
);
7943 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7944 put_aarch64_insn (buf
, insn
);
7948 case BFD_RELOC_AARCH64_CALL26
:
7949 case BFD_RELOC_AARCH64_JUMP26
:
7950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7954 _("branch target not word aligned"));
7955 if (signed_overflow (value
, 28))
7956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7957 _("branch out of range"));
7958 insn
= get_aarch64_insn (buf
);
7959 insn
|= encode_branch_ofs_26 (value
>> 2);
7960 put_aarch64_insn (buf
, insn
);
7964 case BFD_RELOC_AARCH64_MOVW_G0
:
7965 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7966 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7967 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7968 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7969 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7972 case BFD_RELOC_AARCH64_MOVW_G1
:
7973 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7974 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7975 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7976 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7977 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7980 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7982 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7983 /* Should always be exported to object file, see
7984 aarch64_force_relocation(). */
7985 gas_assert (!fixP
->fx_done
);
7986 gas_assert (seg
->use_rela_p
);
7988 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7990 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7991 /* Should always be exported to object file, see
7992 aarch64_force_relocation(). */
7993 gas_assert (!fixP
->fx_done
);
7994 gas_assert (seg
->use_rela_p
);
7996 case BFD_RELOC_AARCH64_MOVW_G2
:
7997 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7998 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7999 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8000 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
8003 case BFD_RELOC_AARCH64_MOVW_G3
:
8004 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
8007 if (fixP
->fx_done
|| !seg
->use_rela_p
)
8009 insn
= get_aarch64_insn (buf
);
8013 /* REL signed addend must fit in 16 bits */
8014 if (signed_overflow (value
, 16))
8015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8016 _("offset out of range"));
8020 /* Check for overflow and scale. */
8021 switch (fixP
->fx_r_type
)
8023 case BFD_RELOC_AARCH64_MOVW_G0
:
8024 case BFD_RELOC_AARCH64_MOVW_G1
:
8025 case BFD_RELOC_AARCH64_MOVW_G2
:
8026 case BFD_RELOC_AARCH64_MOVW_G3
:
8027 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
8028 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8029 if (unsigned_overflow (value
, scale
+ 16))
8030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8031 _("unsigned value out of range"));
8033 case BFD_RELOC_AARCH64_MOVW_G0_S
:
8034 case BFD_RELOC_AARCH64_MOVW_G1_S
:
8035 case BFD_RELOC_AARCH64_MOVW_G2_S
:
8036 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
8037 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
8038 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
8039 /* NOTE: We can only come here with movz or movn. */
8040 if (signed_overflow (value
, scale
+ 16))
8041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8042 _("signed value out of range"));
8045 /* Force use of MOVN. */
8047 insn
= reencode_movzn_to_movn (insn
);
8051 /* Force use of MOVZ. */
8052 insn
= reencode_movzn_to_movz (insn
);
8056 /* Unchecked relocations. */
8062 /* Insert value into MOVN/MOVZ/MOVK instruction. */
8063 insn
|= encode_movw_imm (value
& 0xffff);
8065 put_aarch64_insn (buf
, insn
);
8069 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8070 fixP
->fx_r_type
= (ilp32_p
8071 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
8072 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
8073 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8074 /* Should always be exported to object file, see
8075 aarch64_force_relocation(). */
8076 gas_assert (!fixP
->fx_done
);
8077 gas_assert (seg
->use_rela_p
);
8080 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8081 fixP
->fx_r_type
= (ilp32_p
8082 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8083 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8084 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8085 /* Should always be exported to object file, see
8086 aarch64_force_relocation(). */
8087 gas_assert (!fixP
->fx_done
);
8088 gas_assert (seg
->use_rela_p
);
8091 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8092 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8093 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8094 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8095 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8096 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8097 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8098 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8099 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8100 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8101 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8102 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8103 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8104 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8105 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8106 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8107 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8108 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8109 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8110 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8111 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8112 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8113 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8114 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8115 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8116 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8117 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8118 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8119 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8120 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8121 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8122 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8123 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8124 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8125 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8126 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8127 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8128 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8129 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8130 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8131 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8132 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8133 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8134 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8135 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8136 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8137 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8138 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8139 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8140 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8141 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8142 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8143 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8144 /* Should always be exported to object file, see
8145 aarch64_force_relocation(). */
8146 gas_assert (!fixP
->fx_done
);
8147 gas_assert (seg
->use_rela_p
);
8150 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8151 /* Should always be exported to object file, see
8152 aarch64_force_relocation(). */
8153 fixP
->fx_r_type
= (ilp32_p
8154 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8155 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8156 gas_assert (!fixP
->fx_done
);
8157 gas_assert (seg
->use_rela_p
);
8160 case BFD_RELOC_AARCH64_ADD_LO12
:
8161 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8162 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8163 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8164 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8165 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8166 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8167 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8168 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8169 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8170 case BFD_RELOC_AARCH64_LDST128_LO12
:
8171 case BFD_RELOC_AARCH64_LDST16_LO12
:
8172 case BFD_RELOC_AARCH64_LDST32_LO12
:
8173 case BFD_RELOC_AARCH64_LDST64_LO12
:
8174 case BFD_RELOC_AARCH64_LDST8_LO12
:
8175 /* Should always be exported to object file, see
8176 aarch64_force_relocation(). */
8177 gas_assert (!fixP
->fx_done
);
8178 gas_assert (seg
->use_rela_p
);
8181 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8182 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8183 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8186 case BFD_RELOC_UNUSED
:
8187 /* An error will already have been reported. */
8191 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8192 _("unexpected %s fixup"),
8193 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8198 /* Free the allocated the struct aarch64_inst.
8199 N.B. currently there are very limited number of fix-up types actually use
8200 this field, so the impact on the performance should be minimal . */
8201 if (fixP
->tc_fix_data
.inst
!= NULL
)
8202 free (fixP
->tc_fix_data
.inst
);
8207 /* Translate internal representation of relocation info to BFD target
8211 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8214 bfd_reloc_code_real_type code
;
8216 reloc
= XNEW (arelent
);
8218 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8219 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8220 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8224 if (section
->use_rela_p
)
8225 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8227 fixp
->fx_offset
= reloc
->address
;
8229 reloc
->addend
= fixp
->fx_offset
;
8231 code
= fixp
->fx_r_type
;
8236 code
= BFD_RELOC_16_PCREL
;
8241 code
= BFD_RELOC_32_PCREL
;
8246 code
= BFD_RELOC_64_PCREL
;
8253 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8254 if (reloc
->howto
== NULL
)
8256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8258 ("cannot represent %s relocation in this object file format"),
8259 bfd_get_reloc_code_name (code
));
8266 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8269 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8271 bfd_reloc_code_real_type type
;
8275 FIXME: @@ Should look at CPU word size. */
8282 type
= BFD_RELOC_16
;
8285 type
= BFD_RELOC_32
;
8288 type
= BFD_RELOC_64
;
8291 as_bad (_("cannot do %u-byte relocation"), size
);
8292 type
= BFD_RELOC_UNUSED
;
8296 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8300 aarch64_force_relocation (struct fix
*fixp
)
8302 switch (fixp
->fx_r_type
)
8304 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8305 /* Perform these "immediate" internal relocations
8306 even if the symbol is extern or weak. */
8309 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8310 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8311 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8312 /* Pseudo relocs that need to be fixed up according to
8316 case BFD_RELOC_AARCH64_ADD_LO12
:
8317 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8318 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8319 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8320 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8321 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8322 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8323 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8324 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8325 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8326 case BFD_RELOC_AARCH64_LDST128_LO12
:
8327 case BFD_RELOC_AARCH64_LDST16_LO12
:
8328 case BFD_RELOC_AARCH64_LDST32_LO12
:
8329 case BFD_RELOC_AARCH64_LDST64_LO12
:
8330 case BFD_RELOC_AARCH64_LDST8_LO12
:
8331 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8332 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8333 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8334 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8335 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8336 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8337 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8338 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8339 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8340 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8341 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8342 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8343 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8344 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8345 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8346 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8347 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8348 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8349 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8350 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8351 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8352 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8353 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8354 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8355 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8356 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8357 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8358 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8359 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8360 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8361 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8362 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8363 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8364 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8365 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8366 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8367 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8368 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8369 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8370 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8371 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8372 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8373 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8374 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8375 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8376 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8377 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8378 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8379 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8380 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8381 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8382 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8383 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8384 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8385 /* Always leave these relocations for the linker. */
8392 return generic_force_reloc (fixp
);
8397 /* Implement md_after_parse_args. This is the earliest time we need to decide
8398 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8401 aarch64_after_parse_args (void)
8403 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8406 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8407 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8408 aarch64_abi
= AARCH64_ABI_ILP32
;
8410 aarch64_abi
= AARCH64_ABI_LP64
;
8414 elf64_aarch64_target_format (void)
8417 /* FIXME: What to do for ilp32_p ? */
8418 if (target_big_endian
)
8419 return "elf64-bigaarch64-cloudabi";
8421 return "elf64-littleaarch64-cloudabi";
8423 if (target_big_endian
)
8424 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8426 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8431 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8433 elf_frob_symbol (symp
, puntp
);
8437 /* MD interface: Finalization. */
8439 /* A good place to do this, although this was probably not intended
8440 for this kind of use. We need to dump the literal pool before
8441 references are made to a null symbol pointer. */
8444 aarch64_cleanup (void)
8448 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8450 /* Put it at the end of the relevant section. */
8451 subseg_set (pool
->section
, pool
->sub_section
);
8457 /* Remove any excess mapping symbols generated for alignment frags in
8458 SEC. We may have created a mapping symbol before a zero byte
8459 alignment; remove it if there's a mapping symbol after the
8462 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8463 void *dummy ATTRIBUTE_UNUSED
)
8465 segment_info_type
*seginfo
= seg_info (sec
);
8468 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8471 for (fragp
= seginfo
->frchainP
->frch_root
;
8472 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8474 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8475 fragS
*next
= fragp
->fr_next
;
8477 /* Variable-sized frags have been converted to fixed size by
8478 this point. But if this was variable-sized to start with,
8479 there will be a fixed-size frag after it. So don't handle
8481 if (sym
== NULL
|| next
== NULL
)
8484 if (S_GET_VALUE (sym
) < next
->fr_address
)
8485 /* Not at the end of this frag. */
8487 know (S_GET_VALUE (sym
) == next
->fr_address
);
8491 if (next
->tc_frag_data
.first_map
!= NULL
)
8493 /* Next frag starts with a mapping symbol. Discard this
8495 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8499 if (next
->fr_next
== NULL
)
8501 /* This mapping symbol is at the end of the section. Discard
8503 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8504 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8508 /* As long as we have empty frags without any mapping symbols,
8510 /* If the next frag is non-empty and does not start with a
8511 mapping symbol, then this mapping symbol is required. */
8512 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8515 next
= next
->fr_next
;
8517 while (next
!= NULL
);
8522 /* Adjust the symbol table. */
8525 aarch64_adjust_symtab (void)
8528 /* Remove any overlapping mapping symbols generated by alignment frags. */
8529 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8530 /* Now do generic ELF adjustments. */
8531 elf_adjust_symtab ();
8536 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8538 const char *hash_err
;
8540 hash_err
= hash_insert (table
, key
, value
);
8542 printf ("Internal Error: Can't hash %s\n", key
);
8546 fill_instruction_hash_table (void)
8548 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8550 while (opcode
->name
!= NULL
)
8552 templates
*templ
, *new_templ
;
8553 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8555 new_templ
= XNEW (templates
);
8556 new_templ
->opcode
= opcode
;
8557 new_templ
->next
= NULL
;
8560 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8563 new_templ
->next
= templ
->next
;
8564 templ
->next
= new_templ
;
8571 convert_to_upper (char *dst
, const char *src
, size_t num
)
8574 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8575 *dst
= TOUPPER (*src
);
8579 /* Assume STR point to a lower-case string, allocate, convert and return
8580 the corresponding upper-case string. */
8581 static inline const char*
8582 get_upper_str (const char *str
)
8585 size_t len
= strlen (str
);
8586 ret
= XNEWVEC (char, len
+ 1);
8587 convert_to_upper (ret
, str
, len
);
8591 /* MD interface: Initialization. */
8599 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8600 || (aarch64_cond_hsh
= hash_new ()) == NULL
8601 || (aarch64_shift_hsh
= hash_new ()) == NULL
8602 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8603 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8604 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8605 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8606 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8607 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8608 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8609 || (aarch64_reg_hsh
= hash_new ()) == NULL
8610 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8611 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8612 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8613 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8614 as_fatal (_("virtual memory exhausted"));
8616 fill_instruction_hash_table ();
8618 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8619 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8620 (void *) (aarch64_sys_regs
+ i
));
8622 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8623 checked_hash_insert (aarch64_pstatefield_hsh
,
8624 aarch64_pstatefields
[i
].name
,
8625 (void *) (aarch64_pstatefields
+ i
));
8627 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8628 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8629 aarch64_sys_regs_ic
[i
].name
,
8630 (void *) (aarch64_sys_regs_ic
+ i
));
8632 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8633 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8634 aarch64_sys_regs_dc
[i
].name
,
8635 (void *) (aarch64_sys_regs_dc
+ i
));
8637 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8638 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8639 aarch64_sys_regs_at
[i
].name
,
8640 (void *) (aarch64_sys_regs_at
+ i
));
8642 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8643 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8644 aarch64_sys_regs_tlbi
[i
].name
,
8645 (void *) (aarch64_sys_regs_tlbi
+ i
));
8647 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8648 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8649 aarch64_sys_regs_sr
[i
].name
,
8650 (void *) (aarch64_sys_regs_sr
+ i
));
8652 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8653 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8654 (void *) (reg_names
+ i
));
8656 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8657 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8658 (void *) (nzcv_names
+ i
));
8660 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8662 const char *name
= aarch64_operand_modifiers
[i
].name
;
8663 checked_hash_insert (aarch64_shift_hsh
, name
,
8664 (void *) (aarch64_operand_modifiers
+ i
));
8665 /* Also hash the name in the upper case. */
8666 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8667 (void *) (aarch64_operand_modifiers
+ i
));
8670 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8673 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8674 the same condition code. */
8675 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8677 const char *name
= aarch64_conds
[i
].names
[j
];
8680 checked_hash_insert (aarch64_cond_hsh
, name
,
8681 (void *) (aarch64_conds
+ i
));
8682 /* Also hash the name in the upper case. */
8683 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8684 (void *) (aarch64_conds
+ i
));
8688 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8690 const char *name
= aarch64_barrier_options
[i
].name
;
8691 /* Skip xx00 - the unallocated values of option. */
8694 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8695 (void *) (aarch64_barrier_options
+ i
));
8696 /* Also hash the name in the upper case. */
8697 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8698 (void *) (aarch64_barrier_options
+ i
));
8701 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8703 const char* name
= aarch64_prfops
[i
].name
;
8704 /* Skip the unallocated hint encodings. */
8707 checked_hash_insert (aarch64_pldop_hsh
, name
,
8708 (void *) (aarch64_prfops
+ i
));
8709 /* Also hash the name in the upper case. */
8710 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8711 (void *) (aarch64_prfops
+ i
));
8714 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8716 const char* name
= aarch64_hint_options
[i
].name
;
8718 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8719 (void *) (aarch64_hint_options
+ i
));
8720 /* Also hash the name in the upper case. */
8721 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8722 (void *) (aarch64_hint_options
+ i
));
8725 /* Set the cpu variant based on the command-line options. */
8727 mcpu_cpu_opt
= march_cpu_opt
;
8730 mcpu_cpu_opt
= &cpu_default
;
8732 cpu_variant
= *mcpu_cpu_opt
;
8734 /* Record the CPU type. */
8735 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8737 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8740 /* Command line processing. */
8742 const char *md_shortopts
= "m:";
8744 #ifdef AARCH64_BI_ENDIAN
8745 #define OPTION_EB (OPTION_MD_BASE + 0)
8746 #define OPTION_EL (OPTION_MD_BASE + 1)
8748 #if TARGET_BYTES_BIG_ENDIAN
8749 #define OPTION_EB (OPTION_MD_BASE + 0)
8751 #define OPTION_EL (OPTION_MD_BASE + 1)
8755 struct option md_longopts
[] = {
8757 {"EB", no_argument
, NULL
, OPTION_EB
},
8760 {"EL", no_argument
, NULL
, OPTION_EL
},
8762 {NULL
, no_argument
, NULL
, 0}
8765 size_t md_longopts_size
= sizeof (md_longopts
);
8767 struct aarch64_option_table
8769 const char *option
; /* Option name to match. */
8770 const char *help
; /* Help information. */
8771 int *var
; /* Variable to change. */
8772 int value
; /* What to change it to. */
8773 char *deprecated
; /* If non-null, print this message. */
8776 static struct aarch64_option_table aarch64_opts
[] = {
8777 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8778 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8780 #ifdef DEBUG_AARCH64
8781 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8782 #endif /* DEBUG_AARCH64 */
8783 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8785 {"mno-verbose-error", N_("do not output verbose error messages"),
8786 &verbose_error_p
, 0, NULL
},
8787 {NULL
, NULL
, NULL
, 0, NULL
}
8790 struct aarch64_cpu_option_table
8793 const aarch64_feature_set value
;
8794 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8796 const char *canonical_name
;
8799 /* This list should, at a minimum, contain all the cpu names
8800 recognized by GCC. */
8801 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8802 {"all", AARCH64_ANY
, NULL
},
8803 {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8804 AARCH64_FEATURE_CRC
), "Cortex-A34"},
8805 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8806 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8807 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8808 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8809 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8810 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8811 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8812 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8813 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8814 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8815 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8816 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8818 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8819 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8821 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8822 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8824 {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8825 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8826 | AARCH64_FEATURE_DOTPROD
8827 | AARCH64_FEATURE_SSBS
),
8829 {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8830 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8831 | AARCH64_FEATURE_DOTPROD
8832 | AARCH64_FEATURE_SSBS
),
8834 {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8835 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8836 | AARCH64_FEATURE_DOTPROD
8837 | AARCH64_FEATURE_SSBS
),
8839 {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8840 AARCH64_FEATURE_F16
| AARCH64_FEATURE_RCPC
8841 | AARCH64_FEATURE_DOTPROD
8842 | AARCH64_FEATURE_SSBS
),
8844 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8845 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8846 | AARCH64_FEATURE_DOTPROD
8847 | AARCH64_FEATURE_PROFILE
),
8849 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8850 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8851 "Samsung Exynos M1"},
8852 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8853 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8854 | AARCH64_FEATURE_RDMA
),
8856 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8857 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8858 | AARCH64_FEATURE_DOTPROD
8859 | AARCH64_FEATURE_SSBS
),
8861 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8862 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8863 | AARCH64_FEATURE_DOTPROD
8864 | AARCH64_FEATURE_PROFILE
),
8866 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8867 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8868 | AARCH64_FEATURE_RDMA
),
8869 "Qualcomm QDF24XX"},
8870 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8871 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8872 "Qualcomm Saphira"},
8873 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8874 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8876 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8877 AARCH64_FEATURE_CRYPTO
),
8879 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8880 in earlier releases and is superseded by 'xgene1' in all
8882 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8883 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8884 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8885 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8886 {"generic", AARCH64_ARCH_V8
, NULL
},
8888 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8891 struct aarch64_arch_option_table
8894 const aarch64_feature_set value
;
8897 /* This list should, at a minimum, contain all the architecture names
8898 recognized by GCC. */
8899 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8900 {"all", AARCH64_ANY
},
8901 {"armv8-a", AARCH64_ARCH_V8
},
8902 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8903 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8904 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8905 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8906 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8907 {NULL
, AARCH64_ARCH_NONE
}
8910 /* ISA extensions. */
8911 struct aarch64_option_cpu_value_table
8914 const aarch64_feature_set value
;
8915 const aarch64_feature_set require
; /* Feature dependencies. */
8918 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8919 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8921 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8922 | AARCH64_FEATURE_AES
8923 | AARCH64_FEATURE_SHA2
, 0),
8924 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8925 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8927 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8929 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8930 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8931 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8933 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8935 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8937 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8938 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8939 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8940 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8941 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8942 AARCH64_FEATURE (AARCH64_FEATURE_FP
8943 | AARCH64_FEATURE_F16
, 0)},
8944 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8946 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8947 AARCH64_FEATURE (AARCH64_FEATURE_F16
8948 | AARCH64_FEATURE_SIMD
8949 | AARCH64_FEATURE_COMPNUM
, 0)},
8950 {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME
, 0),
8952 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8953 AARCH64_FEATURE (AARCH64_FEATURE_F16
8954 | AARCH64_FEATURE_SIMD
, 0)},
8955 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8957 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8959 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8961 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8963 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8965 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8967 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8969 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8970 | AARCH64_FEATURE_SHA3
, 0),
8972 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8974 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8976 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8978 {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0),
8979 AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0)},
8980 {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4
, 0),
8981 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8982 | AARCH64_FEATURE_SM4
, 0)},
8983 {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES
, 0),
8984 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8985 | AARCH64_FEATURE_AES
, 0)},
8986 {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3
, 0),
8987 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
8988 | AARCH64_FEATURE_SHA3
, 0)},
8989 {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM
, 0),
8990 AARCH64_FEATURE (AARCH64_FEATURE_SVE2
, 0)},
8991 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8994 struct aarch64_long_option_table
8996 const char *option
; /* Substring to match. */
8997 const char *help
; /* Help information. */
8998 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8999 char *deprecated
; /* If non-null, print this message. */
9002 /* Transitive closure of features depending on set. */
9003 static aarch64_feature_set
9004 aarch64_feature_disable_set (aarch64_feature_set set
)
9006 const struct aarch64_option_cpu_value_table
*opt
;
9007 aarch64_feature_set prev
= 0;
9009 while (prev
!= set
) {
9011 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9012 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
9013 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
9018 /* Transitive closure of dependencies of set. */
9019 static aarch64_feature_set
9020 aarch64_feature_enable_set (aarch64_feature_set set
)
9022 const struct aarch64_option_cpu_value_table
*opt
;
9023 aarch64_feature_set prev
= 0;
9025 while (prev
!= set
) {
9027 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9028 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
9029 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
9035 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
9036 bfd_boolean ext_only
)
9038 /* We insist on extensions being added before being removed. We achieve
9039 this by using the ADDING_VALUE variable to indicate whether we are
9040 adding an extension (1) or removing it (0) and only allowing it to
9041 change in the order -1 -> 1 -> 0. */
9042 int adding_value
= -1;
9043 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
9045 /* Copy the feature set, so that we can modify it. */
9049 while (str
!= NULL
&& *str
!= 0)
9051 const struct aarch64_option_cpu_value_table
*opt
;
9052 const char *ext
= NULL
;
9059 as_bad (_("invalid architectural extension"));
9063 ext
= strchr (++str
, '+');
9069 optlen
= strlen (str
);
9071 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
9073 if (adding_value
!= 0)
9078 else if (optlen
> 0)
9080 if (adding_value
== -1)
9082 else if (adding_value
!= 1)
9084 as_bad (_("must specify extensions to add before specifying "
9085 "those to remove"));
9092 as_bad (_("missing architectural extension"));
9096 gas_assert (adding_value
!= -1);
9098 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
9099 if (strncmp (opt
->name
, str
, optlen
) == 0)
9101 aarch64_feature_set set
;
9103 /* Add or remove the extension. */
9106 set
= aarch64_feature_enable_set (opt
->value
);
9107 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
9111 set
= aarch64_feature_disable_set (opt
->value
);
9112 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
9117 if (opt
->name
== NULL
)
9119 as_bad (_("unknown architectural extension `%s'"), str
);
9130 aarch64_parse_cpu (const char *str
)
9132 const struct aarch64_cpu_option_table
*opt
;
9133 const char *ext
= strchr (str
, '+');
9139 optlen
= strlen (str
);
9143 as_bad (_("missing cpu name `%s'"), str
);
9147 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9148 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9150 mcpu_cpu_opt
= &opt
->value
;
9152 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9157 as_bad (_("unknown cpu `%s'"), str
);
9162 aarch64_parse_arch (const char *str
)
9164 const struct aarch64_arch_option_table
*opt
;
9165 const char *ext
= strchr (str
, '+');
9171 optlen
= strlen (str
);
9175 as_bad (_("missing architecture name `%s'"), str
);
9179 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9180 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9182 march_cpu_opt
= &opt
->value
;
9184 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9189 as_bad (_("unknown architecture `%s'\n"), str
);
9194 struct aarch64_option_abi_value_table
9197 enum aarch64_abi_type value
;
9200 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9201 {"ilp32", AARCH64_ABI_ILP32
},
9202 {"lp64", AARCH64_ABI_LP64
},
9206 aarch64_parse_abi (const char *str
)
9212 as_bad (_("missing abi name `%s'"), str
);
9216 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9217 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9219 aarch64_abi
= aarch64_abis
[i
].value
;
9223 as_bad (_("unknown abi `%s'\n"), str
);
9227 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9229 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9230 aarch64_parse_abi
, NULL
},
9231 #endif /* OBJ_ELF */
9232 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9233 aarch64_parse_cpu
, NULL
},
9234 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9235 aarch64_parse_arch
, NULL
},
9236 {NULL
, NULL
, 0, NULL
}
9240 md_parse_option (int c
, const char *arg
)
9242 struct aarch64_option_table
*opt
;
9243 struct aarch64_long_option_table
*lopt
;
9249 target_big_endian
= 1;
9255 target_big_endian
= 0;
9260 /* Listing option. Just ignore these, we don't support additional
9265 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9267 if (c
== opt
->option
[0]
9268 && ((arg
== NULL
&& opt
->option
[1] == 0)
9269 || streq (arg
, opt
->option
+ 1)))
9271 /* If the option is deprecated, tell the user. */
9272 if (opt
->deprecated
!= NULL
)
9273 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9274 arg
? arg
: "", _(opt
->deprecated
));
9276 if (opt
->var
!= NULL
)
9277 *opt
->var
= opt
->value
;
9283 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9285 /* These options are expected to have an argument. */
9286 if (c
== lopt
->option
[0]
9288 && strncmp (arg
, lopt
->option
+ 1,
9289 strlen (lopt
->option
+ 1)) == 0)
9291 /* If the option is deprecated, tell the user. */
9292 if (lopt
->deprecated
!= NULL
)
9293 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9294 _(lopt
->deprecated
));
9296 /* Call the sup-option parser. */
9297 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9308 md_show_usage (FILE * fp
)
9310 struct aarch64_option_table
*opt
;
9311 struct aarch64_long_option_table
*lopt
;
9313 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9315 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9316 if (opt
->help
!= NULL
)
9317 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9319 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9320 if (lopt
->help
!= NULL
)
9321 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9325 -EB assemble code for a big-endian cpu\n"));
9330 -EL assemble code for a little-endian cpu\n"));
9334 /* Parse a .cpu directive. */
9337 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9339 const struct aarch64_cpu_option_table
*opt
;
9345 name
= input_line_pointer
;
9346 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9347 input_line_pointer
++;
9348 saved_char
= *input_line_pointer
;
9349 *input_line_pointer
= 0;
9351 ext
= strchr (name
, '+');
9354 optlen
= ext
- name
;
9356 optlen
= strlen (name
);
9358 /* Skip the first "all" entry. */
9359 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9360 if (strlen (opt
->name
) == optlen
9361 && strncmp (name
, opt
->name
, optlen
) == 0)
9363 mcpu_cpu_opt
= &opt
->value
;
9365 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9368 cpu_variant
= *mcpu_cpu_opt
;
9370 *input_line_pointer
= saved_char
;
9371 demand_empty_rest_of_line ();
9374 as_bad (_("unknown cpu `%s'"), name
);
9375 *input_line_pointer
= saved_char
;
9376 ignore_rest_of_line ();
9380 /* Parse a .arch directive. */
9383 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9385 const struct aarch64_arch_option_table
*opt
;
9391 name
= input_line_pointer
;
9392 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9393 input_line_pointer
++;
9394 saved_char
= *input_line_pointer
;
9395 *input_line_pointer
= 0;
9397 ext
= strchr (name
, '+');
9400 optlen
= ext
- name
;
9402 optlen
= strlen (name
);
9404 /* Skip the first "all" entry. */
9405 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9406 if (strlen (opt
->name
) == optlen
9407 && strncmp (name
, opt
->name
, optlen
) == 0)
9409 mcpu_cpu_opt
= &opt
->value
;
9411 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9414 cpu_variant
= *mcpu_cpu_opt
;
9416 *input_line_pointer
= saved_char
;
9417 demand_empty_rest_of_line ();
9421 as_bad (_("unknown architecture `%s'\n"), name
);
9422 *input_line_pointer
= saved_char
;
9423 ignore_rest_of_line ();
9426 /* Parse a .arch_extension directive. */
9429 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9432 char *ext
= input_line_pointer
;;
9434 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9435 input_line_pointer
++;
9436 saved_char
= *input_line_pointer
;
9437 *input_line_pointer
= 0;
9439 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9442 cpu_variant
= *mcpu_cpu_opt
;
9444 *input_line_pointer
= saved_char
;
9445 demand_empty_rest_of_line ();
9448 /* Copy symbol information. */
9451 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9453 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);
9457 /* Same as elf_copy_symbol_attributes, but without copying st_other.
9458 This is needed so AArch64 specific st_other values can be independently
9459 specified for an IFUNC resolver (that is called by the dynamic linker)
9460 and the symbol it resolves (aliased to the resolver). In particular,
9461 if a function symbol has special st_other value set via directives,
9462 then attaching an IFUNC resolver to that symbol should not override
9463 the st_other setting. Requiring the directive on the IFUNC resolver
9464 symbol would be unexpected and problematic in C code, where the two
9465 symbols appear as two independent function declarations. */
9468 aarch64_elf_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
9470 struct elf_obj_sy
*srcelf
= symbol_get_obj (src
);
9471 struct elf_obj_sy
*destelf
= symbol_get_obj (dest
);
9474 if (destelf
->size
== NULL
)
9475 destelf
->size
= XNEW (expressionS
);
9476 *destelf
->size
= *srcelf
->size
;
9480 if (destelf
->size
!= NULL
)
9481 free (destelf
->size
);
9482 destelf
->size
= NULL
;
9484 S_SET_SIZE (dest
, S_GET_SIZE (src
));