1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum neon_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a single type, e.g. ".8b", leading period included.
825 Only applicable to Vn registers.
827 Return TRUE on success; otherwise return FALSE. */
829 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
835 if (! parse_neon_type_for_operand (vectype
, &str
))
837 first_error (_("vector type expected"));
849 /* Parse a register of the type TYPE.
851 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
852 name or the parsed register is not of TYPE.
854 Otherwise return the register number, and optionally fill in the actual
855 type of the register in *RTYPE when multiple alternatives were given, and
856 return the register shape and element index information in *TYPEINFO.
858 IN_REG_LIST should be set with TRUE if the caller is parsing a register
862 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
863 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
866 const reg_entry
*reg
= parse_reg (&str
);
867 struct neon_type_el atype
;
868 struct neon_type_el parsetype
;
869 bfd_boolean is_typed_vecreg
= FALSE
;
872 atype
.type
= NT_invtype
;
880 set_default_error ();
884 if (! aarch64_check_reg_type (reg
, type
))
886 DEBUG_TRACE ("reg type check failed");
887 set_default_error ();
892 if (type
== REG_TYPE_VN
893 && parse_neon_operand_type (&parsetype
, &str
))
895 /* Register if of the form Vn.[bhsdq]. */
896 is_typed_vecreg
= TRUE
;
898 if (parsetype
.width
== 0)
899 /* Expect index. In the new scheme we cannot have
900 Vn.[bhsdq] represent a scalar. Therefore any
901 Vn.[bhsdq] should have an index following it.
902 Except in reglists ofcourse. */
903 atype
.defined
|= NTA_HASINDEX
;
905 atype
.defined
|= NTA_HASTYPE
;
907 atype
.type
= parsetype
.type
;
908 atype
.width
= parsetype
.width
;
911 if (skip_past_char (&str
, '['))
915 /* Reject Sn[index] syntax. */
916 if (!is_typed_vecreg
)
918 first_error (_("this type of register can't be indexed"));
922 if (in_reg_list
== TRUE
)
924 first_error (_("index not allowed inside register list"));
928 atype
.defined
|= NTA_HASINDEX
;
930 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
932 if (exp
.X_op
!= O_constant
)
934 first_error (_("constant expression required"));
938 if (! skip_past_char (&str
, ']'))
941 atype
.index
= exp
.X_add_number
;
943 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
945 /* Indexed vector register expected. */
946 first_error (_("indexed vector register expected"));
950 /* A vector reg Vn should be typed or indexed. */
951 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
953 first_error (_("invalid use of vector register"));
969 Return the register number on success; return PARSE_FAIL otherwise.
971 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
972 the register (e.g. NEON double or quad reg when either has been requested).
974 If this is a NEON vector register with additional type information, fill
975 in the struct pointed to by VECTYPE (if non-NULL).
977 This parser does not handle register list. */
980 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
981 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
983 struct neon_type_el atype
;
985 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
986 /*in_reg_list= */ FALSE
);
988 if (reg
== PARSE_FAIL
)
999 static inline bfd_boolean
1000 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1004 && e1
.defined
== e2
.defined
1005 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1008 /* This function parses the NEON register list. On success, it returns
1009 the parsed register list information in the following encoded format:
1011 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1012 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1014 The information of the register shape and/or index is returned in
1017 It returns PARSE_FAIL if the register list is invalid.
1019 The list contains one to four registers.
1020 Each register can be one of:
1023 All <T> should be identical.
1024 All <index> should be identical.
1025 There are restrictions on <Vt> numbers which are checked later
1026 (by reg_list_valid_p). */
1029 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1033 struct neon_type_el typeinfo
, typeinfo_first
;
1038 bfd_boolean error
= FALSE
;
1039 bfd_boolean expect_index
= FALSE
;
1043 set_syntax_error (_("expecting {"));
1049 typeinfo_first
.defined
= 0;
1050 typeinfo_first
.type
= NT_invtype
;
1051 typeinfo_first
.width
= -1;
1052 typeinfo_first
.index
= 0;
1061 str
++; /* skip over '-' */
1064 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1065 /*in_reg_list= */ TRUE
);
1066 if (val
== PARSE_FAIL
)
1068 set_first_syntax_error (_("invalid vector register in list"));
1072 /* reject [bhsd]n */
1073 if (typeinfo
.defined
== 0)
1075 set_first_syntax_error (_("invalid scalar register in list"));
1080 if (typeinfo
.defined
& NTA_HASINDEX
)
1081 expect_index
= TRUE
;
1085 if (val
< val_range
)
1087 set_first_syntax_error
1088 (_("invalid range in vector register list"));
1097 typeinfo_first
= typeinfo
;
1098 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1100 set_first_syntax_error
1101 (_("type mismatch in vector register list"));
1106 for (i
= val_range
; i
<= val
; i
++)
1108 ret_val
|= i
<< (5 * nb_regs
);
1113 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1115 skip_whitespace (str
);
1118 set_first_syntax_error (_("end of vector register list not found"));
1123 skip_whitespace (str
);
1127 if (skip_past_char (&str
, '['))
1131 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1132 if (exp
.X_op
!= O_constant
)
1134 set_first_syntax_error (_("constant expression required."));
1137 if (! skip_past_char (&str
, ']'))
1140 typeinfo_first
.index
= exp
.X_add_number
;
1144 set_first_syntax_error (_("expected index"));
1151 set_first_syntax_error (_("too many registers in vector register list"));
1154 else if (nb_regs
== 0)
1156 set_first_syntax_error (_("empty vector register list"));
1162 *vectype
= typeinfo_first
;
1164 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1167 /* Directives: register aliases. */
1170 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1175 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1178 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1181 /* Only warn about a redefinition if it's not defined as the
1183 else if (new->number
!= number
|| new->type
!= type
)
1184 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1189 name
= xstrdup (str
);
1190 new = xmalloc (sizeof (reg_entry
));
1193 new->number
= number
;
1195 new->builtin
= FALSE
;
1197 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1203 /* Look for the .req directive. This is of the form:
1205 new_register_name .req existing_register_name
1207 If we find one, or if it looks sufficiently like one that we want to
1208 handle any error here, return TRUE. Otherwise return FALSE. */
1211 create_register_alias (char *newname
, char *p
)
1213 const reg_entry
*old
;
1214 char *oldname
, *nbuf
;
1217 /* The input scrubber ensures that whitespace after the mnemonic is
1218 collapsed to single spaces. */
1220 if (strncmp (oldname
, " .req ", 6) != 0)
1224 if (*oldname
== '\0')
1227 old
= hash_find (aarch64_reg_hsh
, oldname
);
1230 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1234 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1235 the desired alias name, and p points to its end. If not, then
1236 the desired alias name is in the global original_case_string. */
1237 #ifdef TC_CASE_SENSITIVE
1240 newname
= original_case_string
;
1241 nlen
= strlen (newname
);
1244 nbuf
= alloca (nlen
+ 1);
1245 memcpy (nbuf
, newname
, nlen
);
1248 /* Create aliases under the new name as stated; an all-lowercase
1249 version of the new name; and an all-uppercase version of the new
1251 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1253 for (p
= nbuf
; *p
; p
++)
1256 if (strncmp (nbuf
, newname
, nlen
))
1258 /* If this attempt to create an additional alias fails, do not bother
1259 trying to create the all-lower case alias. We will fail and issue
1260 a second, duplicate error message. This situation arises when the
1261 programmer does something like:
1264 The second .req creates the "Foo" alias but then fails to create
1265 the artificial FOO alias because it has already been created by the
1267 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1271 for (p
= nbuf
; *p
; p
++)
1274 if (strncmp (nbuf
, newname
, nlen
))
1275 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1281 /* Should never be called, as .req goes between the alias and the
1282 register name, not at the beginning of the line. */
1284 s_req (int a ATTRIBUTE_UNUSED
)
1286 as_bad (_("invalid syntax for .req directive"));
1289 /* The .unreq directive deletes an alias which was previously defined
1290 by .req. For example:
1296 s_unreq (int a ATTRIBUTE_UNUSED
)
1301 name
= input_line_pointer
;
1303 while (*input_line_pointer
!= 0
1304 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1305 ++input_line_pointer
;
1307 saved_char
= *input_line_pointer
;
1308 *input_line_pointer
= 0;
1311 as_bad (_("invalid syntax for .unreq directive"));
1314 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1317 as_bad (_("unknown register alias '%s'"), name
);
1318 else if (reg
->builtin
)
1319 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1326 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1327 free ((char *) reg
->name
);
1330 /* Also locate the all upper case and all lower case versions.
1331 Do not complain if we cannot find one or the other as it
1332 was probably deleted above. */
1334 nbuf
= strdup (name
);
1335 for (p
= nbuf
; *p
; p
++)
1337 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1340 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1341 free ((char *) reg
->name
);
1345 for (p
= nbuf
; *p
; p
++)
1347 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1350 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1351 free ((char *) reg
->name
);
1359 *input_line_pointer
= saved_char
;
1360 demand_empty_rest_of_line ();
1363 /* Directives: Instruction set selection. */
1366 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1367 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1368 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1369 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1371 /* Create a new mapping symbol for the transition to STATE. */
1374 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1377 const char *symname
;
1384 type
= BSF_NO_FLAGS
;
1388 type
= BSF_NO_FLAGS
;
1394 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1395 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1397 /* Save the mapping symbols for future reference. Also check that
1398 we do not place two mapping symbols at the same offset within a
1399 frag. We'll handle overlap between frags in
1400 check_mapping_symbols.
1402 If .fill or other data filling directive generates zero sized data,
1403 the mapping symbol for the following code will have the same value
1404 as the one generated for the data filling directive. In this case,
1405 we replace the old symbol with the new one at the same address. */
1408 if (frag
->tc_frag_data
.first_map
!= NULL
)
1410 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1411 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1414 frag
->tc_frag_data
.first_map
= symbolP
;
1416 if (frag
->tc_frag_data
.last_map
!= NULL
)
1418 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1419 S_GET_VALUE (symbolP
));
1420 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1421 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1424 frag
->tc_frag_data
.last_map
= symbolP
;
1427 /* We must sometimes convert a region marked as code to data during
1428 code alignment, if an odd number of bytes have to be padded. The
1429 code mapping symbol is pushed to an aligned address. */
1432 insert_data_mapping_symbol (enum mstate state
,
1433 valueT value
, fragS
* frag
, offsetT bytes
)
1435 /* If there was already a mapping symbol, remove it. */
1436 if (frag
->tc_frag_data
.last_map
!= NULL
1437 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1438 frag
->fr_address
+ value
)
1440 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1444 know (frag
->tc_frag_data
.first_map
== symp
);
1445 frag
->tc_frag_data
.first_map
= NULL
;
1447 frag
->tc_frag_data
.last_map
= NULL
;
1448 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1451 make_mapping_symbol (MAP_DATA
, value
, frag
);
1452 make_mapping_symbol (state
, value
+ bytes
, frag
);
1455 static void mapping_state_2 (enum mstate state
, int max_chars
);
1457 /* Set the mapping state to STATE. Only call this when about to
1458 emit some STATE bytes to the file. */
1461 mapping_state (enum mstate state
)
1463 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1465 if (state
== MAP_INSN
)
1466 /* AArch64 instructions require 4-byte alignment. When emitting
1467 instructions into any section, record the appropriate section
1469 record_alignment (now_seg
, 2);
1471 if (mapstate
== state
)
1472 /* The mapping symbol has already been emitted.
1473 There is nothing else to do. */
1476 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1477 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1478 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1479 evaluated later in the next else. */
1481 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1483 /* Only add the symbol if the offset is > 0:
1484 if we're at the first frag, check it's size > 0;
1485 if we're not at the first frag, then for sure
1486 the offset is > 0. */
1487 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1488 const int add_symbol
= (frag_now
!= frag_first
)
1489 || (frag_now_fix () > 0);
1492 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1496 mapping_state_2 (state
, 0);
1499 /* Same as mapping_state, but MAX_CHARS bytes have already been
1500 allocated. Put the mapping symbol that far back. */
1503 mapping_state_2 (enum mstate state
, int max_chars
)
1505 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1507 if (!SEG_NORMAL (now_seg
))
1510 if (mapstate
== state
)
1511 /* The mapping symbol has already been emitted.
1512 There is nothing else to do. */
1515 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1516 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1519 #define mapping_state(x) /* nothing */
1520 #define mapping_state_2(x, y) /* nothing */
1523 /* Directives: sectioning and alignment. */
1526 s_bss (int ignore ATTRIBUTE_UNUSED
)
1528 /* We don't support putting frags in the BSS segment, we fake it by
1529 marking in_bss, then looking at s_skip for clues. */
1530 subseg_set (bss_section
, 0);
1531 demand_empty_rest_of_line ();
1532 mapping_state (MAP_DATA
);
1536 s_even (int ignore ATTRIBUTE_UNUSED
)
1538 /* Never make frag if expect extra pass. */
1540 frag_align (1, 0, 0);
1542 record_alignment (now_seg
, 1);
1544 demand_empty_rest_of_line ();
1547 /* Directives: Literal pools. */
1549 static literal_pool
*
1550 find_literal_pool (int size
)
1554 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1556 if (pool
->section
== now_seg
1557 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1564 static literal_pool
*
1565 find_or_make_literal_pool (int size
)
1567 /* Next literal pool ID number. */
1568 static unsigned int latest_pool_num
= 1;
1571 pool
= find_literal_pool (size
);
1575 /* Create a new pool. */
1576 pool
= xmalloc (sizeof (*pool
));
1580 /* Currently we always put the literal pool in the current text
1581 section. If we were generating "small" model code where we
1582 knew that all code and initialised data was within 1MB then
1583 we could output literals to mergeable, read-only data
1586 pool
->next_free_entry
= 0;
1587 pool
->section
= now_seg
;
1588 pool
->sub_section
= now_subseg
;
1590 pool
->next
= list_of_pools
;
1591 pool
->symbol
= NULL
;
1593 /* Add it to the list. */
1594 list_of_pools
= pool
;
1597 /* New pools, and emptied pools, will have a NULL symbol. */
1598 if (pool
->symbol
== NULL
)
1600 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1601 (valueT
) 0, &zero_address_frag
);
1602 pool
->id
= latest_pool_num
++;
1609 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1610 Return TRUE on success, otherwise return FALSE. */
1612 add_to_lit_pool (expressionS
*exp
, int size
)
1617 pool
= find_or_make_literal_pool (size
);
1619 /* Check if this literal value is already in the pool. */
1620 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1622 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1624 if ((litexp
->X_op
== exp
->X_op
)
1625 && (exp
->X_op
== O_constant
)
1626 && (litexp
->X_add_number
== exp
->X_add_number
)
1627 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1630 if ((litexp
->X_op
== exp
->X_op
)
1631 && (exp
->X_op
== O_symbol
)
1632 && (litexp
->X_add_number
== exp
->X_add_number
)
1633 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1634 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1638 /* Do we need to create a new entry? */
1639 if (entry
== pool
->next_free_entry
)
1641 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1643 set_syntax_error (_("literal pool overflow"));
1647 pool
->literals
[entry
].exp
= *exp
;
1648 pool
->next_free_entry
+= 1;
1649 if (exp
->X_op
== O_big
)
1651 /* PR 16688: Bignums are held in a single global array. We must
1652 copy and preserve that value now, before it is overwritten. */
1653 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1654 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1655 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1658 pool
->literals
[entry
].bignum
= NULL
;
1661 exp
->X_op
= O_symbol
;
1662 exp
->X_add_number
= ((int) entry
) * size
;
1663 exp
->X_add_symbol
= pool
->symbol
;
1668 /* Can't use symbol_new here, so have to create a symbol and then at
1669 a later date assign it a value. Thats what these functions do. */
1672 symbol_locate (symbolS
* symbolP
,
1673 const char *name
,/* It is copied, the caller can modify. */
1674 segT segment
, /* Segment identifier (SEG_<something>). */
1675 valueT valu
, /* Symbol value. */
1676 fragS
* frag
) /* Associated fragment. */
1679 char *preserved_copy_of_name
;
1681 name_length
= strlen (name
) + 1; /* +1 for \0. */
1682 obstack_grow (¬es
, name
, name_length
);
1683 preserved_copy_of_name
= obstack_finish (¬es
);
1685 #ifdef tc_canonicalize_symbol_name
1686 preserved_copy_of_name
=
1687 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1690 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1692 S_SET_SEGMENT (symbolP
, segment
);
1693 S_SET_VALUE (symbolP
, valu
);
1694 symbol_clear_list_pointers (symbolP
);
1696 symbol_set_frag (symbolP
, frag
);
1698 /* Link to end of symbol chain. */
1700 extern int symbol_table_frozen
;
1702 if (symbol_table_frozen
)
1706 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1708 obj_symbol_new_hook (symbolP
);
1710 #ifdef tc_symbol_new_hook
1711 tc_symbol_new_hook (symbolP
);
1715 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1716 #endif /* DEBUG_SYMS */
1721 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1728 for (align
= 2; align
<= 4; align
++)
1730 int size
= 1 << align
;
1732 pool
= find_literal_pool (size
);
1733 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1736 mapping_state (MAP_DATA
);
1738 /* Align pool as you have word accesses.
1739 Only make a frag if we have to. */
1741 frag_align (align
, 0, 0);
1743 record_alignment (now_seg
, align
);
1745 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1747 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1748 (valueT
) frag_now_fix (), frag_now
);
1749 symbol_table_insert (pool
->symbol
);
1751 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1753 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1755 if (exp
->X_op
== O_big
)
1757 /* PR 16688: Restore the global bignum value. */
1758 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1759 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1760 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1763 /* First output the expression in the instruction to the pool. */
1764 emit_expr (exp
, size
); /* .word|.xword */
1766 if (exp
->X_op
== O_big
)
1768 free (pool
->literals
[entry
].bignum
);
1769 pool
->literals
[entry
].bignum
= NULL
;
1773 /* Mark the pool as empty. */
1774 pool
->next_free_entry
= 0;
1775 pool
->symbol
= NULL
;
1780 /* Forward declarations for functions below, in the MD interface
1782 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1783 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1785 /* Directives: Data. */
1786 /* N.B. the support for relocation suffix in this directive needs to be
1787 implemented properly. */
1790 s_aarch64_elf_cons (int nbytes
)
1794 #ifdef md_flush_pending_output
1795 md_flush_pending_output ();
1798 if (is_it_end_of_statement ())
1800 demand_empty_rest_of_line ();
1804 #ifdef md_cons_align
1805 md_cons_align (nbytes
);
1808 mapping_state (MAP_DATA
);
1811 struct reloc_table_entry
*reloc
;
1815 if (exp
.X_op
!= O_symbol
)
1816 emit_expr (&exp
, (unsigned int) nbytes
);
1819 skip_past_char (&input_line_pointer
, '#');
1820 if (skip_past_char (&input_line_pointer
, ':'))
1822 reloc
= find_reloc_table_entry (&input_line_pointer
);
1824 as_bad (_("unrecognized relocation suffix"));
1826 as_bad (_("unimplemented relocation suffix"));
1827 ignore_rest_of_line ();
1831 emit_expr (&exp
, (unsigned int) nbytes
);
1834 while (*input_line_pointer
++ == ',');
1836 /* Put terminator back into stream. */
1837 input_line_pointer
--;
1838 demand_empty_rest_of_line ();
1841 #endif /* OBJ_ELF */
1843 /* Output a 32-bit word, but mark as an instruction. */
1846 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1850 #ifdef md_flush_pending_output
1851 md_flush_pending_output ();
1854 if (is_it_end_of_statement ())
1856 demand_empty_rest_of_line ();
1860 /* Sections are assumed to start aligned. In executable section, there is no
1861 MAP_DATA symbol pending. So we only align the address during
1862 MAP_DATA --> MAP_INSN transition.
1863 For other sections, this is not guaranteed. */
1864 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1865 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1866 frag_align_code (2, 0);
1869 mapping_state (MAP_INSN
);
1875 if (exp
.X_op
!= O_constant
)
1877 as_bad (_("constant expression required"));
1878 ignore_rest_of_line ();
1882 if (target_big_endian
)
1884 unsigned int val
= exp
.X_add_number
;
1885 exp
.X_add_number
= SWAP_32 (val
);
1887 emit_expr (&exp
, 4);
1889 while (*input_line_pointer
++ == ',');
1891 /* Put terminator back into stream. */
1892 input_line_pointer
--;
1893 demand_empty_rest_of_line ();
1897 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1900 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1906 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1907 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1909 demand_empty_rest_of_line ();
1912 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1915 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1919 /* Since we're just labelling the code, there's no need to define a
1922 /* Make sure there is enough room in this frag for the following
1923 blr. This trick only works if the blr follows immediately after
1924 the .tlsdesc directive. */
1926 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1927 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1929 demand_empty_rest_of_line ();
1932 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1935 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1941 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1942 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1944 demand_empty_rest_of_line ();
1946 #endif /* OBJ_ELF */
1948 static void s_aarch64_arch (int);
1949 static void s_aarch64_cpu (int);
1950 static void s_aarch64_arch_extension (int);
1952 /* This table describes all the machine specific pseudo-ops the assembler
1953 has to support. The fields are:
1954 pseudo-op name without dot
1955 function to call to execute this pseudo-op
1956 Integer arg to pass to the function. */
1958 const pseudo_typeS md_pseudo_table
[] = {
1959 /* Never called because '.req' does not start a line. */
1961 {"unreq", s_unreq
, 0},
1963 {"even", s_even
, 0},
1964 {"ltorg", s_ltorg
, 0},
1965 {"pool", s_ltorg
, 0},
1966 {"cpu", s_aarch64_cpu
, 0},
1967 {"arch", s_aarch64_arch
, 0},
1968 {"arch_extension", s_aarch64_arch_extension
, 0},
1969 {"inst", s_aarch64_inst
, 0},
1971 {"tlsdescadd", s_tlsdescadd
, 0},
1972 {"tlsdesccall", s_tlsdesccall
, 0},
1973 {"tlsdescldr", s_tlsdescldr
, 0},
1974 {"word", s_aarch64_elf_cons
, 4},
1975 {"long", s_aarch64_elf_cons
, 4},
1976 {"xword", s_aarch64_elf_cons
, 8},
1977 {"dword", s_aarch64_elf_cons
, 8},
1983 /* Check whether STR points to a register name followed by a comma or the
1984 end of line; REG_TYPE indicates which register types are checked
1985 against. Return TRUE if STR is such a register name; otherwise return
1986 FALSE. The function does not intend to produce any diagnostics, but since
1987 the register parser aarch64_reg_parse, which is called by this function,
1988 does produce diagnostics, we call clear_error to clear any diagnostics
1989 that may be generated by aarch64_reg_parse.
1990 Also, the function returns FALSE directly if there is any user error
1991 present at the function entry. This prevents the existing diagnostics
1992 state from being spoiled.
1993 The function currently serves parse_constant_immediate and
1994 parse_big_immediate only. */
1996 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2000 /* Prevent the diagnostics state from being spoiled. */
2004 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2006 /* Clear the parsing error that may be set by the reg parser. */
2009 if (reg
== PARSE_FAIL
)
2012 skip_whitespace (str
);
2013 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2019 /* Parser functions used exclusively in instruction operands. */
2021 /* Parse an immediate expression which may not be constant.
2023 To prevent the expression parser from pushing a register name
2024 into the symbol table as an undefined symbol, firstly a check is
2025 done to find out whether STR is a valid register name followed
2026 by a comma or the end of line. Return FALSE if STR is such a
2030 parse_immediate_expression (char **str
, expressionS
*exp
)
2032 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2034 set_recoverable_error (_("immediate operand required"));
2038 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2040 if (exp
->X_op
== O_absent
)
2042 set_fatal_syntax_error (_("missing immediate expression"));
2049 /* Constant immediate-value read function for use in insn parsing.
2050 STR points to the beginning of the immediate (with the optional
2051 leading #); *VAL receives the value.
2053 Return TRUE on success; otherwise return FALSE. */
2056 parse_constant_immediate (char **str
, int64_t * val
)
2060 if (! parse_immediate_expression (str
, &exp
))
2063 if (exp
.X_op
!= O_constant
)
2065 set_syntax_error (_("constant expression required"));
2069 *val
= exp
.X_add_number
;
2074 encode_imm_float_bits (uint32_t imm
)
2076 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2077 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2080 /* Return TRUE if the single-precision floating-point value encoded in IMM
2081 can be expressed in the AArch64 8-bit signed floating-point format with
2082 3-bit exponent and normalized 4 bits of precision; in other words, the
2083 floating-point value must be expressable as
2084 (+/-) n / 16 * power (2, r)
2085 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2088 aarch64_imm_float_p (uint32_t imm
)
2090 /* If a single-precision floating-point value has the following bit
2091 pattern, it can be expressed in the AArch64 8-bit floating-point
2094 3 32222222 2221111111111
2095 1 09876543 21098765432109876543210
2096 n Eeeeeexx xxxx0000000000000000000
2098 where n, e and each x are either 0 or 1 independently, with
2103 /* Prepare the pattern for 'Eeeeee'. */
2104 if (((imm
>> 30) & 0x1) == 0)
2105 pattern
= 0x3e000000;
2107 pattern
= 0x40000000;
2109 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2110 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2113 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2115 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2116 8-bit signed floating-point format with 3-bit exponent and normalized 4
2117 bits of precision (i.e. can be used in an FMOV instruction); return the
2118 equivalent single-precision encoding in *FPWORD.
2120 Otherwise return FALSE. */
2123 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2125 /* If a double-precision floating-point value has the following bit
2126 pattern, it can be expressed in the AArch64 8-bit floating-point
2129 6 66655555555 554444444...21111111111
2130 3 21098765432 109876543...098765432109876543210
2131 n Eeeeeeeeexx xxxx00000...000000000000000000000
2133 where n, e and each x are either 0 or 1 independently, with
2137 uint32_t high32
= imm
>> 32;
2139 /* Lower 32 bits need to be 0s. */
2140 if ((imm
& 0xffffffff) != 0)
2143 /* Prepare the pattern for 'Eeeeeeeee'. */
2144 if (((high32
>> 30) & 0x1) == 0)
2145 pattern
= 0x3fc00000;
2147 pattern
= 0x40000000;
2149 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2150 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2152 /* Convert to the single-precision encoding.
2154 n Eeeeeeeeexx xxxx00000...000000000000000000000
2156 n Eeeeeexx xxxx0000000000000000000. */
2157 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2158 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2165 /* Parse a floating-point immediate. Return TRUE on success and return the
2166 value in *IMMED in the format of IEEE754 single-precision encoding.
2167 *CCP points to the start of the string; DP_P is TRUE when the immediate
2168 is expected to be in double-precision (N.B. this only matters when
2169 hexadecimal representation is involved).
2171 N.B. 0.0 is accepted by this function. */
2174 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2178 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2179 int found_fpchar
= 0;
2181 unsigned fpword
= 0;
2182 bfd_boolean hex_p
= FALSE
;
2184 skip_past_char (&str
, '#');
2187 skip_whitespace (fpnum
);
2189 if (strncmp (fpnum
, "0x", 2) == 0)
2191 /* Support the hexadecimal representation of the IEEE754 encoding.
2192 Double-precision is expected when DP_P is TRUE, otherwise the
2193 representation should be in single-precision. */
2194 if (! parse_constant_immediate (&str
, &val
))
2199 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2202 else if ((uint64_t) val
> 0xffffffff)
2211 /* We must not accidentally parse an integer as a floating-point number.
2212 Make sure that the value we parse is not an integer by checking for
2213 special characters '.' or 'e'. */
2214 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2215 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2229 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2232 /* Our FP word must be 32 bits (single-precision FP). */
2233 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2235 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2240 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2248 set_fatal_syntax_error (_("invalid floating-point constant"));
2252 /* Less-generic immediate-value read function with the possibility of loading
2253 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2256 To prevent the expression parser from pushing a register name into the
2257 symbol table as an undefined symbol, a check is firstly done to find
2258 out whether STR is a valid register name followed by a comma or the end
2259 of line. Return FALSE if STR is such a register. */
2262 parse_big_immediate (char **str
, int64_t *imm
)
2266 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2268 set_syntax_error (_("immediate operand required"));
2272 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2274 if (inst
.reloc
.exp
.X_op
== O_constant
)
2275 *imm
= inst
.reloc
.exp
.X_add_number
;
2282 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2283 if NEED_LIBOPCODES is non-zero, the fixup will need
2284 assistance from the libopcodes. */
2287 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2288 const aarch64_opnd_info
*operand
,
2289 int need_libopcodes_p
)
2291 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2292 reloc
->opnd
= operand
->type
;
2293 if (need_libopcodes_p
)
2294 reloc
->need_libopcodes_p
= 1;
2297 /* Return TRUE if the instruction needs to be fixed up later internally by
2298 the GAS; otherwise return FALSE. */
2300 static inline bfd_boolean
2301 aarch64_gas_internal_fixup_p (void)
2303 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2306 /* Assign the immediate value to the relavant field in *OPERAND if
2307 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2308 needs an internal fixup in a later stage.
2309 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2310 IMM.VALUE that may get assigned with the constant. */
2312 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2313 aarch64_opnd_info
*operand
,
2315 int need_libopcodes_p
,
2318 if (reloc
->exp
.X_op
== O_constant
)
2321 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2323 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2324 reloc
->type
= BFD_RELOC_UNUSED
;
2328 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2329 /* Tell libopcodes to ignore this operand or not. This is helpful
2330 when one of the operands needs to be fixed up later but we need
2331 libopcodes to check the other operands. */
2332 operand
->skip
= skip_p
;
2336 /* Relocation modifiers. Each entry in the table contains the textual
2337 name for the relocation which may be placed before a symbol used as
2338 a load/store offset, or add immediate. It must be surrounded by a
2339 leading and trailing colon, for example:
2341 ldr x0, [x1, #:rello:varsym]
2342 add x0, x1, #:rello:varsym */
2344 struct reloc_table_entry
2348 bfd_reloc_code_real_type adr_type
;
2349 bfd_reloc_code_real_type adrp_type
;
2350 bfd_reloc_code_real_type movw_type
;
2351 bfd_reloc_code_real_type add_type
;
2352 bfd_reloc_code_real_type ldst_type
;
2353 bfd_reloc_code_real_type ld_literal_type
;
2356 static struct reloc_table_entry reloc_table
[] = {
2357 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2362 BFD_RELOC_AARCH64_ADD_LO12
,
2363 BFD_RELOC_AARCH64_LDST_LO12
,
2366 /* Higher 21 bits of pc-relative page offset: ADRP */
2369 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2375 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2378 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2384 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2388 BFD_RELOC_AARCH64_MOVW_G0
,
2393 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2397 BFD_RELOC_AARCH64_MOVW_G0_S
,
2402 /* Less significant bits 0-15 of address/value: MOVK, no check */
2406 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2411 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2415 BFD_RELOC_AARCH64_MOVW_G1
,
2420 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2424 BFD_RELOC_AARCH64_MOVW_G1_S
,
2429 /* Less significant bits 16-31 of address/value: MOVK, no check */
2433 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2438 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2442 BFD_RELOC_AARCH64_MOVW_G2
,
2447 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2451 BFD_RELOC_AARCH64_MOVW_G2_S
,
2456 /* Less significant bits 32-47 of address/value: MOVK, no check */
2460 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2465 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2469 BFD_RELOC_AARCH64_MOVW_G3
,
2474 /* Get to the page containing GOT entry for a symbol. */
2477 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2481 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2483 /* 12 bit offset into the page containing GOT entry for that symbol. */
2489 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2492 /* 0-15 bits of address/value: MOVk, no check. */
2496 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2501 /* Most significant bits 16-31 of address/value: MOVZ. */
2505 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2510 /* 15 bit offset into the page containing GOT entry for that symbol. */
2516 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2519 /* Get to the page containing GOT TLS entry for a symbol */
2520 {"gottprel_g0_nc", 0,
2523 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2528 /* Get to the page containing GOT TLS entry for a symbol */
2532 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2537 /* Get to the page containing GOT TLS entry for a symbol */
2539 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2540 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2546 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2551 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2555 /* Lower 16 bits address/value: MOVk. */
2559 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2564 /* Most significant bits 16-31 of address/value: MOVZ. */
2568 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2573 /* Get to the page containing GOT TLS entry for a symbol */
2575 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2576 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2580 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2582 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2587 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2588 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2591 /* Get to the page containing GOT TLS entry for a symbol.
2592 The same as GD, we allocate two consecutive GOT slots
2593 for module index and module offset, the only difference
2594 with GD is the module offset should be intialized to
2595 zero without any outstanding runtime relocation. */
2597 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2598 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2604 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2605 {"tlsldm_lo12_nc", 0,
2609 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2613 /* 12 bit offset into the module TLS base address. */
2618 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2619 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2622 /* Same as dtprel_lo12, no overflow check. */
2623 {"dtprel_lo12_nc", 0,
2627 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2628 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2631 /* bits[23:12] of offset to the module TLS base address. */
2636 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2640 /* bits[15:0] of offset to the module TLS base address. */
2644 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2649 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2653 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2658 /* bits[31:16] of offset to the module TLS base address. */
2662 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2667 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2671 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2676 /* bits[47:32] of offset to the module TLS base address. */
2680 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2685 /* Lower 16 bit offset into GOT entry for a symbol */
2686 {"tlsdesc_off_g0_nc", 0,
2689 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2694 /* Higher 16 bit offset into GOT entry for a symbol */
2695 {"tlsdesc_off_g1", 0,
2698 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2703 /* Get to the page containing GOT TLS entry for a symbol */
2706 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2710 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2712 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2713 {"gottprel_lo12", 0,
2718 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2721 /* Get tp offset for a symbol. */
2726 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2730 /* Get tp offset for a symbol. */
2735 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2739 /* Get tp offset for a symbol. */
2744 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2748 /* Get tp offset for a symbol. */
2749 {"tprel_lo12_nc", 0,
2753 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2757 /* Most significant bits 32-47 of address/value: MOVZ. */
2761 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2766 /* Most significant bits 16-31 of address/value: MOVZ. */
2770 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2775 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2779 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2784 /* Most significant bits 0-15 of address/value: MOVZ. */
2788 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2793 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2797 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2802 /* 15bit offset from got entry to base address of GOT table. */
2808 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2811 /* 14bit offset from got entry to base address of GOT table. */
2817 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2821 /* Given the address of a pointer pointing to the textual name of a
2822 relocation as may appear in assembler source, attempt to find its
2823 details in reloc_table. The pointer will be updated to the character
2824 after the trailing colon. On failure, NULL will be returned;
2825 otherwise return the reloc_table_entry. */
2827 static struct reloc_table_entry
*
2828 find_reloc_table_entry (char **str
)
2831 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2833 int length
= strlen (reloc_table
[i
].name
);
2835 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2836 && (*str
)[length
] == ':')
2838 *str
+= (length
+ 1);
2839 return &reloc_table
[i
];
2846 /* Mode argument to parse_shift and parser_shifter_operand. */
2847 enum parse_shift_mode
2849 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2851 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2853 SHIFTED_LSL
, /* bare "lsl #n" */
2854 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2855 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2858 /* Parse a <shift> operator on an AArch64 data processing instruction.
2859 Return TRUE on success; otherwise return FALSE. */
2861 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2863 const struct aarch64_name_value_pair
*shift_op
;
2864 enum aarch64_modifier_kind kind
;
2870 for (p
= *str
; ISALPHA (*p
); p
++)
2875 set_syntax_error (_("shift expression expected"));
2879 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2881 if (shift_op
== NULL
)
2883 set_syntax_error (_("shift operator expected"));
2887 kind
= aarch64_get_operand_modifier (shift_op
);
2889 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2891 set_syntax_error (_("invalid use of 'MSL'"));
2897 case SHIFTED_LOGIC_IMM
:
2898 if (aarch64_extend_operator_p (kind
) == TRUE
)
2900 set_syntax_error (_("extending shift is not permitted"));
2905 case SHIFTED_ARITH_IMM
:
2906 if (kind
== AARCH64_MOD_ROR
)
2908 set_syntax_error (_("'ROR' shift is not permitted"));
2914 if (kind
!= AARCH64_MOD_LSL
)
2916 set_syntax_error (_("only 'LSL' shift is permitted"));
2921 case SHIFTED_REG_OFFSET
:
2922 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2923 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2925 set_fatal_syntax_error
2926 (_("invalid shift for the register offset addressing mode"));
2931 case SHIFTED_LSL_MSL
:
2932 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2934 set_syntax_error (_("invalid shift operator"));
2943 /* Whitespace can appear here if the next thing is a bare digit. */
2944 skip_whitespace (p
);
2946 /* Parse shift amount. */
2948 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2949 exp
.X_op
= O_absent
;
2952 if (is_immediate_prefix (*p
))
2957 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2959 if (exp
.X_op
== O_absent
)
2961 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2963 set_syntax_error (_("missing shift amount"));
2966 operand
->shifter
.amount
= 0;
2968 else if (exp
.X_op
!= O_constant
)
2970 set_syntax_error (_("constant shift amount required"));
2973 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2975 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2980 operand
->shifter
.amount
= exp
.X_add_number
;
2981 operand
->shifter
.amount_present
= 1;
2984 operand
->shifter
.operator_present
= 1;
2985 operand
->shifter
.kind
= kind
;
2991 /* Parse a <shifter_operand> for a data processing instruction:
2994 #<immediate>, LSL #imm
2996 Validation of immediate operands is deferred to md_apply_fix.
2998 Return TRUE on success; otherwise return FALSE. */
3001 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3002 enum parse_shift_mode mode
)
3006 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3011 /* Accept an immediate expression. */
3012 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3015 /* Accept optional LSL for arithmetic immediate values. */
3016 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3017 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3020 /* Not accept any shifter for logical immediate values. */
3021 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3022 && parse_shift (&p
, operand
, mode
))
3024 set_syntax_error (_("unexpected shift operator"));
3032 /* Parse a <shifter_operand> for a data processing instruction:
3037 #<immediate>, LSL #imm
3039 where <shift> is handled by parse_shift above, and the last two
3040 cases are handled by the function above.
3042 Validation of immediate operands is deferred to md_apply_fix.
3044 Return TRUE on success; otherwise return FALSE. */
3047 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3048 enum parse_shift_mode mode
)
3051 int isreg32
, isregzero
;
3052 enum aarch64_operand_class opd_class
3053 = aarch64_get_operand_class (operand
->type
);
3056 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3058 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3060 set_syntax_error (_("unexpected register in the immediate operand"));
3064 if (!isregzero
&& reg
== REG_SP
)
3066 set_syntax_error (BAD_SP
);
3070 operand
->reg
.regno
= reg
;
3071 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3073 /* Accept optional shift operation on register. */
3074 if (! skip_past_comma (str
))
3077 if (! parse_shift (str
, operand
, mode
))
3082 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3085 (_("integer register expected in the extended/shifted operand "
3090 /* We have a shifted immediate variable. */
3091 return parse_shifter_operand_imm (str
, operand
, mode
);
3094 /* Return TRUE on success; return FALSE otherwise. */
3097 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3098 enum parse_shift_mode mode
)
3102 /* Determine if we have the sequence of characters #: or just :
3103 coming next. If we do, then we check for a :rello: relocation
3104 modifier. If we don't, punt the whole lot to
3105 parse_shifter_operand. */
3107 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3109 struct reloc_table_entry
*entry
;
3117 /* Try to parse a relocation. Anything else is an error. */
3118 if (!(entry
= find_reloc_table_entry (str
)))
3120 set_syntax_error (_("unknown relocation modifier"));
3124 if (entry
->add_type
== 0)
3127 (_("this relocation modifier is not allowed on this instruction"));
3131 /* Save str before we decompose it. */
3134 /* Next, we parse the expression. */
3135 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3138 /* Record the relocation type (use the ADD variant here). */
3139 inst
.reloc
.type
= entry
->add_type
;
3140 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3142 /* If str is empty, we've reached the end, stop here. */
3146 /* Otherwise, we have a shifted reloc modifier, so rewind to
3147 recover the variable name and continue parsing for the shifter. */
3149 return parse_shifter_operand_imm (str
, operand
, mode
);
3152 return parse_shifter_operand (str
, operand
, mode
);
3155 /* Parse all forms of an address expression. Information is written
3156 to *OPERAND and/or inst.reloc.
3158 The A64 instruction set has the following addressing modes:
3161 [base] // in SIMD ld/st structure
3162 [base{,#0}] // in ld/st exclusive
3164 [base,Xm{,LSL #imm}]
3165 [base,Xm,SXTX {#imm}]
3166 [base,Wm,(S|U)XTW {#imm}]
3171 [base],Xm // in SIMD ld/st structure
3172 PC-relative (literal)
3176 (As a convenience, the notation "=immediate" is permitted in conjunction
3177 with the pc-relative literal load instructions to automatically place an
3178 immediate value or symbolic address in a nearby literal pool and generate
3179 a hidden label which references it.)
3181 Upon a successful parsing, the address structure in *OPERAND will be
3182 filled in the following way:
3184 .base_regno = <base>
3185 .offset.is_reg // 1 if the offset is a register
3187 .offset.regno = <Rm>
3189 For different addressing modes defined in the A64 ISA:
3192 .pcrel=0; .preind=1; .postind=0; .writeback=0
3194 .pcrel=0; .preind=1; .postind=0; .writeback=1
3196 .pcrel=0; .preind=0; .postind=1; .writeback=1
3197 PC-relative (literal)
3198 .pcrel=1; .preind=1; .postind=0; .writeback=0
3200 The shift/extension information, if any, will be stored in .shifter.
3202 It is the caller's responsibility to check for addressing modes not
3203 supported by the instruction, and to set inst.reloc.type. */
3206 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3207 int accept_reg_post_index
)
3211 int isreg32
, isregzero
;
3212 expressionS
*exp
= &inst
.reloc
.exp
;
3214 if (! skip_past_char (&p
, '['))
3216 /* =immediate or label. */
3217 operand
->addr
.pcrel
= 1;
3218 operand
->addr
.preind
= 1;
3220 /* #:<reloc_op>:<symbol> */
3221 skip_past_char (&p
, '#');
3222 if (reloc
&& skip_past_char (&p
, ':'))
3224 bfd_reloc_code_real_type ty
;
3225 struct reloc_table_entry
*entry
;
3227 /* Try to parse a relocation modifier. Anything else is
3229 entry
= find_reloc_table_entry (&p
);
3232 set_syntax_error (_("unknown relocation modifier"));
3236 switch (operand
->type
)
3238 case AARCH64_OPND_ADDR_PCREL21
:
3240 ty
= entry
->adr_type
;
3244 ty
= entry
->ld_literal_type
;
3251 (_("this relocation modifier is not allowed on this "
3257 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3259 set_syntax_error (_("invalid relocation expression"));
3263 /* #:<reloc_op>:<expr> */
3264 /* Record the relocation type. */
3265 inst
.reloc
.type
= ty
;
3266 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3271 if (skip_past_char (&p
, '='))
3272 /* =immediate; need to generate the literal in the literal pool. */
3273 inst
.gen_lit_pool
= 1;
3275 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3277 set_syntax_error (_("invalid address"));
3288 /* Accept SP and reject ZR */
3289 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3290 if (reg
== PARSE_FAIL
|| isreg32
)
3292 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3295 operand
->addr
.base_regno
= reg
;
3298 if (skip_past_comma (&p
))
3301 operand
->addr
.preind
= 1;
3303 /* Reject SP and accept ZR */
3304 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3305 if (reg
!= PARSE_FAIL
)
3308 operand
->addr
.offset
.regno
= reg
;
3309 operand
->addr
.offset
.is_reg
= 1;
3310 /* Shifted index. */
3311 if (skip_past_comma (&p
))
3314 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3315 /* Use the diagnostics set in parse_shift, so not set new
3316 error message here. */
3320 [base,Xm{,LSL #imm}]
3321 [base,Xm,SXTX {#imm}]
3322 [base,Wm,(S|U)XTW {#imm}] */
3323 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3324 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3325 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3329 set_syntax_error (_("invalid use of 32-bit register offset"));
3335 set_syntax_error (_("invalid use of 64-bit register offset"));
3341 /* [Xn,#:<reloc_op>:<symbol> */
3342 skip_past_char (&p
, '#');
3343 if (reloc
&& skip_past_char (&p
, ':'))
3345 struct reloc_table_entry
*entry
;
3347 /* Try to parse a relocation modifier. Anything else is
3349 if (!(entry
= find_reloc_table_entry (&p
)))
3351 set_syntax_error (_("unknown relocation modifier"));
3355 if (entry
->ldst_type
== 0)
3358 (_("this relocation modifier is not allowed on this "
3363 /* [Xn,#:<reloc_op>: */
3364 /* We now have the group relocation table entry corresponding to
3365 the name in the assembler source. Next, we parse the
3367 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3369 set_syntax_error (_("invalid relocation expression"));
3373 /* [Xn,#:<reloc_op>:<expr> */
3374 /* Record the load/store relocation type. */
3375 inst
.reloc
.type
= entry
->ldst_type
;
3376 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3378 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3380 set_syntax_error (_("invalid expression in the address"));
3387 if (! skip_past_char (&p
, ']'))
3389 set_syntax_error (_("']' expected"));
3393 if (skip_past_char (&p
, '!'))
3395 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3397 set_syntax_error (_("register offset not allowed in pre-indexed "
3398 "addressing mode"));
3402 operand
->addr
.writeback
= 1;
3404 else if (skip_past_comma (&p
))
3407 operand
->addr
.postind
= 1;
3408 operand
->addr
.writeback
= 1;
3410 if (operand
->addr
.preind
)
3412 set_syntax_error (_("cannot combine pre- and post-indexing"));
3416 if (accept_reg_post_index
3417 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3418 &isregzero
)) != PARSE_FAIL
)
3423 set_syntax_error (_("invalid 32-bit register offset"));
3426 operand
->addr
.offset
.regno
= reg
;
3427 operand
->addr
.offset
.is_reg
= 1;
3429 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3432 set_syntax_error (_("invalid expression in the address"));
3437 /* If at this point neither .preind nor .postind is set, we have a
3438 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3439 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3441 if (operand
->addr
.writeback
)
3444 set_syntax_error (_("missing offset in the pre-indexed address"));
3447 operand
->addr
.preind
= 1;
3448 inst
.reloc
.exp
.X_op
= O_constant
;
3449 inst
.reloc
.exp
.X_add_number
= 0;
3456 /* Return TRUE on success; otherwise return FALSE. */
3458 parse_address (char **str
, aarch64_opnd_info
*operand
,
3459 int accept_reg_post_index
)
3461 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3464 /* Return TRUE on success; otherwise return FALSE. */
3466 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3468 return parse_address_main (str
, operand
, 1, 0);
3471 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3472 Return TRUE on success; otherwise return FALSE. */
3474 parse_half (char **str
, int *internal_fixup_p
)
3480 skip_past_char (&p
, '#');
3482 gas_assert (internal_fixup_p
);
3483 *internal_fixup_p
= 0;
3487 struct reloc_table_entry
*entry
;
3489 /* Try to parse a relocation. Anything else is an error. */
3491 if (!(entry
= find_reloc_table_entry (&p
)))
3493 set_syntax_error (_("unknown relocation modifier"));
3497 if (entry
->movw_type
== 0)
3500 (_("this relocation modifier is not allowed on this instruction"));
3504 inst
.reloc
.type
= entry
->movw_type
;
3507 *internal_fixup_p
= 1;
3509 /* Avoid parsing a register as a general symbol. */
3511 if (aarch64_reg_parse_32_64 (&p
, 0, 0, &dummy
, &dummy
) != PARSE_FAIL
)
3515 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3522 /* Parse an operand for an ADRP instruction:
3524 Return TRUE on success; otherwise return FALSE. */
3527 parse_adrp (char **str
)
3534 struct reloc_table_entry
*entry
;
3536 /* Try to parse a relocation. Anything else is an error. */
3538 if (!(entry
= find_reloc_table_entry (&p
)))
3540 set_syntax_error (_("unknown relocation modifier"));
3544 if (entry
->adrp_type
== 0)
3547 (_("this relocation modifier is not allowed on this instruction"));
3551 inst
.reloc
.type
= entry
->adrp_type
;
3554 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3556 inst
.reloc
.pc_rel
= 1;
3558 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3565 /* Miscellaneous. */
3567 /* Parse an option for a preload instruction. Returns the encoding for the
3568 option, or PARSE_FAIL. */
3571 parse_pldop (char **str
)
3574 const struct aarch64_name_value_pair
*o
;
3577 while (ISALNUM (*q
))
3580 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3588 /* Parse an option for a barrier instruction. Returns the encoding for the
3589 option, or PARSE_FAIL. */
3592 parse_barrier (char **str
)
3595 const asm_barrier_opt
*o
;
3598 while (ISALPHA (*q
))
3601 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3609 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3610 return 0 if successful. Otherwise return PARSE_FAIL. */
3613 parse_barrier_psb (char **str
,
3614 const struct aarch64_name_value_pair
** hint_opt
)
3617 const struct aarch64_name_value_pair
*o
;
3620 while (ISALPHA (*q
))
3623 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3626 set_fatal_syntax_error
3627 ( _("unknown or missing option to PSB"));
3631 if (o
->value
!= 0x11)
3633 /* PSB only accepts option name 'CSYNC'. */
3635 (_("the specified option is not accepted for PSB"));
3644 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3645 Returns the encoding for the option, or PARSE_FAIL.
3647 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3648 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3650 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3651 field, otherwise as a system register.
3655 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3656 int imple_defined_p
, int pstatefield_p
)
3660 const aarch64_sys_reg
*o
;
3664 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3666 *p
++ = TOLOWER (*q
);
3668 /* Assert that BUF be large enough. */
3669 gas_assert (p
- buf
== q
- *str
);
3671 o
= hash_find (sys_regs
, buf
);
3674 if (!imple_defined_p
)
3678 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3679 unsigned int op0
, op1
, cn
, cm
, op2
;
3681 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3684 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3686 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3691 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3692 as_bad (_("selected processor does not support PSTATE field "
3694 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3695 as_bad (_("selected processor does not support system register "
3697 if (aarch64_sys_reg_deprecated_p (o
))
3698 as_warn (_("system register name '%s' is deprecated and may be "
3699 "removed in a future release"), buf
);
3707 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3708 for the option, or NULL. */
3710 static const aarch64_sys_ins_reg
*
3711 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3715 const aarch64_sys_ins_reg
*o
;
3718 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3720 *p
++ = TOLOWER (*q
);
3723 o
= hash_find (sys_ins_regs
, buf
);
3727 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3728 as_bad (_("selected processor does not support system register "
3735 #define po_char_or_fail(chr) do { \
3736 if (! skip_past_char (&str, chr)) \
3740 #define po_reg_or_fail(regtype) do { \
3741 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3742 if (val == PARSE_FAIL) \
3744 set_default_error (); \
3749 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3750 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3751 &isreg32, &isregzero); \
3752 if (val == PARSE_FAIL) \
3754 set_default_error (); \
3757 info->reg.regno = val; \
3759 info->qualifier = AARCH64_OPND_QLF_W; \
3761 info->qualifier = AARCH64_OPND_QLF_X; \
3764 #define po_imm_nc_or_fail() do { \
3765 if (! parse_constant_immediate (&str, &val)) \
3769 #define po_imm_or_fail(min, max) do { \
3770 if (! parse_constant_immediate (&str, &val)) \
3772 if (val < min || val > max) \
3774 set_fatal_syntax_error (_("immediate value out of range "\
3775 #min " to "#max)); \
3780 #define po_misc_or_fail(expr) do { \
3785 /* encode the 12-bit imm field of Add/sub immediate */
3786 static inline uint32_t
3787 encode_addsub_imm (uint32_t imm
)
3792 /* encode the shift amount field of Add/sub immediate */
3793 static inline uint32_t
3794 encode_addsub_imm_shift_amount (uint32_t cnt
)
3800 /* encode the imm field of Adr instruction */
3801 static inline uint32_t
3802 encode_adr_imm (uint32_t imm
)
3804 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3805 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3808 /* encode the immediate field of Move wide immediate */
3809 static inline uint32_t
3810 encode_movw_imm (uint32_t imm
)
3815 /* encode the 26-bit offset of unconditional branch */
3816 static inline uint32_t
3817 encode_branch_ofs_26 (uint32_t ofs
)
3819 return ofs
& ((1 << 26) - 1);
3822 /* encode the 19-bit offset of conditional branch and compare & branch */
3823 static inline uint32_t
3824 encode_cond_branch_ofs_19 (uint32_t ofs
)
3826 return (ofs
& ((1 << 19) - 1)) << 5;
3829 /* encode the 19-bit offset of ld literal */
3830 static inline uint32_t
3831 encode_ld_lit_ofs_19 (uint32_t ofs
)
3833 return (ofs
& ((1 << 19) - 1)) << 5;
3836 /* Encode the 14-bit offset of test & branch. */
3837 static inline uint32_t
3838 encode_tst_branch_ofs_14 (uint32_t ofs
)
3840 return (ofs
& ((1 << 14) - 1)) << 5;
3843 /* Encode the 16-bit imm field of svc/hvc/smc. */
3844 static inline uint32_t
3845 encode_svc_imm (uint32_t imm
)
3850 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3851 static inline uint32_t
3852 reencode_addsub_switch_add_sub (uint32_t opcode
)
3854 return opcode
^ (1 << 30);
3857 static inline uint32_t
3858 reencode_movzn_to_movz (uint32_t opcode
)
3860 return opcode
| (1 << 30);
3863 static inline uint32_t
3864 reencode_movzn_to_movn (uint32_t opcode
)
3866 return opcode
& ~(1 << 30);
3869 /* Overall per-instruction processing. */
3871 /* We need to be able to fix up arbitrary expressions in some statements.
3872 This is so that we can handle symbols that are an arbitrary distance from
3873 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3874 which returns part of an address in a form which will be valid for
3875 a data instruction. We do this by pushing the expression into a symbol
3876 in the expr_section, and creating a fix for that. */
3879 fix_new_aarch64 (fragS
* frag
,
3881 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3891 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3895 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3902 /* Diagnostics on operands errors. */
3904 /* By default, output verbose error message.
3905 Disable the verbose error message by -mno-verbose-error. */
3906 static int verbose_error_p
= 1;
3908 #ifdef DEBUG_AARCH64
3909 /* N.B. this is only for the purpose of debugging. */
3910 const char* operand_mismatch_kind_names
[] =
3913 "AARCH64_OPDE_RECOVERABLE",
3914 "AARCH64_OPDE_SYNTAX_ERROR",
3915 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3916 "AARCH64_OPDE_INVALID_VARIANT",
3917 "AARCH64_OPDE_OUT_OF_RANGE",
3918 "AARCH64_OPDE_UNALIGNED",
3919 "AARCH64_OPDE_REG_LIST",
3920 "AARCH64_OPDE_OTHER_ERROR",
3922 #endif /* DEBUG_AARCH64 */
3924 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3926 When multiple errors of different kinds are found in the same assembly
3927 line, only the error of the highest severity will be picked up for
3928 issuing the diagnostics. */
3930 static inline bfd_boolean
3931 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3932 enum aarch64_operand_error_kind rhs
)
3934 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3935 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3936 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3937 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3938 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3939 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3940 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3941 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3945 /* Helper routine to get the mnemonic name from the assembly instruction
3946 line; should only be called for the diagnosis purpose, as there is
3947 string copy operation involved, which may affect the runtime
3948 performance if used in elsewhere. */
3951 get_mnemonic_name (const char *str
)
3953 static char mnemonic
[32];
3956 /* Get the first 15 bytes and assume that the full name is included. */
3957 strncpy (mnemonic
, str
, 31);
3958 mnemonic
[31] = '\0';
3960 /* Scan up to the end of the mnemonic, which must end in white space,
3961 '.', or end of string. */
3962 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3967 /* Append '...' to the truncated long name. */
3968 if (ptr
- mnemonic
== 31)
3969 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3975 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3977 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3978 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3981 /* Data strutures storing one user error in the assembly code related to
3984 struct operand_error_record
3986 const aarch64_opcode
*opcode
;
3987 aarch64_operand_error detail
;
3988 struct operand_error_record
*next
;
3991 typedef struct operand_error_record operand_error_record
;
3993 struct operand_errors
3995 operand_error_record
*head
;
3996 operand_error_record
*tail
;
3999 typedef struct operand_errors operand_errors
;
4001 /* Top-level data structure reporting user errors for the current line of
4003 The way md_assemble works is that all opcodes sharing the same mnemonic
4004 name are iterated to find a match to the assembly line. In this data
4005 structure, each of the such opcodes will have one operand_error_record
4006 allocated and inserted. In other words, excessive errors related with
4007 a single opcode are disregarded. */
4008 operand_errors operand_error_report
;
4010 /* Free record nodes. */
4011 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4013 /* Initialize the data structure that stores the operand mismatch
4014 information on assembling one line of the assembly code. */
4016 init_operand_error_report (void)
4018 if (operand_error_report
.head
!= NULL
)
4020 gas_assert (operand_error_report
.tail
!= NULL
);
4021 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4022 free_opnd_error_record_nodes
= operand_error_report
.head
;
4023 operand_error_report
.head
= NULL
;
4024 operand_error_report
.tail
= NULL
;
4027 gas_assert (operand_error_report
.tail
== NULL
);
4030 /* Return TRUE if some operand error has been recorded during the
4031 parsing of the current assembly line using the opcode *OPCODE;
4032 otherwise return FALSE. */
4033 static inline bfd_boolean
4034 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4036 operand_error_record
*record
= operand_error_report
.head
;
4037 return record
&& record
->opcode
== opcode
;
4040 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4041 OPCODE field is initialized with OPCODE.
4042 N.B. only one record for each opcode, i.e. the maximum of one error is
4043 recorded for each instruction template. */
4046 add_operand_error_record (const operand_error_record
* new_record
)
4048 const aarch64_opcode
*opcode
= new_record
->opcode
;
4049 operand_error_record
* record
= operand_error_report
.head
;
4051 /* The record may have been created for this opcode. If not, we need
4053 if (! opcode_has_operand_error_p (opcode
))
4055 /* Get one empty record. */
4056 if (free_opnd_error_record_nodes
== NULL
)
4058 record
= xmalloc (sizeof (operand_error_record
));
4064 record
= free_opnd_error_record_nodes
;
4065 free_opnd_error_record_nodes
= record
->next
;
4067 record
->opcode
= opcode
;
4068 /* Insert at the head. */
4069 record
->next
= operand_error_report
.head
;
4070 operand_error_report
.head
= record
;
4071 if (operand_error_report
.tail
== NULL
)
4072 operand_error_report
.tail
= record
;
4074 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4075 && record
->detail
.index
<= new_record
->detail
.index
4076 && operand_error_higher_severity_p (record
->detail
.kind
,
4077 new_record
->detail
.kind
))
4079 /* In the case of multiple errors found on operands related with a
4080 single opcode, only record the error of the leftmost operand and
4081 only if the error is of higher severity. */
4082 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4083 " the existing error %s on operand %d",
4084 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4085 new_record
->detail
.index
,
4086 operand_mismatch_kind_names
[record
->detail
.kind
],
4087 record
->detail
.index
);
4091 record
->detail
= new_record
->detail
;
4095 record_operand_error_info (const aarch64_opcode
*opcode
,
4096 aarch64_operand_error
*error_info
)
4098 operand_error_record record
;
4099 record
.opcode
= opcode
;
4100 record
.detail
= *error_info
;
4101 add_operand_error_record (&record
);
4104 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4105 error message *ERROR, for operand IDX (count from 0). */
4108 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4109 enum aarch64_operand_error_kind kind
,
4112 aarch64_operand_error info
;
4113 memset(&info
, 0, sizeof (info
));
4117 record_operand_error_info (opcode
, &info
);
4121 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4122 enum aarch64_operand_error_kind kind
,
4123 const char* error
, const int *extra_data
)
4125 aarch64_operand_error info
;
4129 info
.data
[0] = extra_data
[0];
4130 info
.data
[1] = extra_data
[1];
4131 info
.data
[2] = extra_data
[2];
4132 record_operand_error_info (opcode
, &info
);
4136 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4137 const char* error
, int lower_bound
,
4140 int data
[3] = {lower_bound
, upper_bound
, 0};
4141 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4145 /* Remove the operand error record for *OPCODE. */
4146 static void ATTRIBUTE_UNUSED
4147 remove_operand_error_record (const aarch64_opcode
*opcode
)
4149 if (opcode_has_operand_error_p (opcode
))
4151 operand_error_record
* record
= operand_error_report
.head
;
4152 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4153 operand_error_report
.head
= record
->next
;
4154 record
->next
= free_opnd_error_record_nodes
;
4155 free_opnd_error_record_nodes
= record
;
4156 if (operand_error_report
.head
== NULL
)
4158 gas_assert (operand_error_report
.tail
== record
);
4159 operand_error_report
.tail
= NULL
;
4164 /* Given the instruction in *INSTR, return the index of the best matched
4165 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4167 Return -1 if there is no qualifier sequence; return the first match
4168 if there is multiple matches found. */
4171 find_best_match (const aarch64_inst
*instr
,
4172 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4174 int i
, num_opnds
, max_num_matched
, idx
;
4176 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4179 DEBUG_TRACE ("no operand");
4183 max_num_matched
= 0;
4186 /* For each pattern. */
4187 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4190 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4192 /* Most opcodes has much fewer patterns in the list. */
4193 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4195 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4196 if (i
!= 0 && idx
== -1)
4197 /* If nothing has been matched, return the 1st sequence. */
4202 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4203 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4206 if (num_matched
> max_num_matched
)
4208 max_num_matched
= num_matched
;
4213 DEBUG_TRACE ("return with %d", idx
);
4217 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4218 corresponding operands in *INSTR. */
4221 assign_qualifier_sequence (aarch64_inst
*instr
,
4222 const aarch64_opnd_qualifier_t
*qualifiers
)
4225 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4226 gas_assert (num_opnds
);
4227 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4228 instr
->operands
[i
].qualifier
= *qualifiers
;
4231 /* Print operands for the diagnosis purpose. */
4234 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4235 const aarch64_opnd_info
*opnds
)
4239 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4241 const size_t size
= 128;
4244 /* We regard the opcode operand info more, however we also look into
4245 the inst->operands to support the disassembling of the optional
4247 The two operand code should be the same in all cases, apart from
4248 when the operand can be optional. */
4249 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4250 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4253 /* Generate the operand string in STR. */
4254 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4258 strcat (buf
, i
== 0 ? " " : ",");
4260 /* Append the operand string. */
4265 /* Send to stderr a string as information. */
4268 output_info (const char *format
, ...)
4274 as_where (&file
, &line
);
4278 fprintf (stderr
, "%s:%u: ", file
, line
);
4280 fprintf (stderr
, "%s: ", file
);
4282 fprintf (stderr
, _("Info: "));
4283 va_start (args
, format
);
4284 vfprintf (stderr
, format
, args
);
4286 (void) putc ('\n', stderr
);
4289 /* Output one operand error record. */
4292 output_operand_error_record (const operand_error_record
*record
, char *str
)
4294 const aarch64_operand_error
*detail
= &record
->detail
;
4295 int idx
= detail
->index
;
4296 const aarch64_opcode
*opcode
= record
->opcode
;
4297 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4298 : AARCH64_OPND_NIL
);
4300 switch (detail
->kind
)
4302 case AARCH64_OPDE_NIL
:
4306 case AARCH64_OPDE_SYNTAX_ERROR
:
4307 case AARCH64_OPDE_RECOVERABLE
:
4308 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4309 case AARCH64_OPDE_OTHER_ERROR
:
4310 /* Use the prepared error message if there is, otherwise use the
4311 operand description string to describe the error. */
4312 if (detail
->error
!= NULL
)
4315 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4317 as_bad (_("%s at operand %d -- `%s'"),
4318 detail
->error
, idx
+ 1, str
);
4322 gas_assert (idx
>= 0);
4323 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4324 aarch64_get_operand_desc (opd_code
), str
);
4328 case AARCH64_OPDE_INVALID_VARIANT
:
4329 as_bad (_("operand mismatch -- `%s'"), str
);
4330 if (verbose_error_p
)
4332 /* We will try to correct the erroneous instruction and also provide
4333 more information e.g. all other valid variants.
4335 The string representation of the corrected instruction and other
4336 valid variants are generated by
4338 1) obtaining the intermediate representation of the erroneous
4340 2) manipulating the IR, e.g. replacing the operand qualifier;
4341 3) printing out the instruction by calling the printer functions
4342 shared with the disassembler.
4344 The limitation of this method is that the exact input assembly
4345 line cannot be accurately reproduced in some cases, for example an
4346 optional operand present in the actual assembly line will be
4347 omitted in the output; likewise for the optional syntax rules,
4348 e.g. the # before the immediate. Another limitation is that the
4349 assembly symbols and relocation operations in the assembly line
4350 currently cannot be printed out in the error report. Last but not
4351 least, when there is other error(s) co-exist with this error, the
4352 'corrected' instruction may be still incorrect, e.g. given
4353 'ldnp h0,h1,[x0,#6]!'
4354 this diagnosis will provide the version:
4355 'ldnp s0,s1,[x0,#6]!'
4356 which is still not right. */
4357 size_t len
= strlen (get_mnemonic_name (str
));
4360 const size_t size
= 2048;
4362 aarch64_inst
*inst_base
= &inst
.base
;
4363 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4366 reset_aarch64_instruction (&inst
);
4367 inst_base
->opcode
= opcode
;
4369 /* Reset the error report so that there is no side effect on the
4370 following operand parsing. */
4371 init_operand_error_report ();
4374 result
= parse_operands (str
+ len
, opcode
)
4375 && programmer_friendly_fixup (&inst
);
4376 gas_assert (result
);
4377 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4379 gas_assert (!result
);
4381 /* Find the most matched qualifier sequence. */
4382 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4383 gas_assert (qlf_idx
> -1);
4385 /* Assign the qualifiers. */
4386 assign_qualifier_sequence (inst_base
,
4387 opcode
->qualifiers_list
[qlf_idx
]);
4389 /* Print the hint. */
4390 output_info (_(" did you mean this?"));
4391 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4392 print_operands (buf
, opcode
, inst_base
->operands
);
4393 output_info (_(" %s"), buf
);
4395 /* Print out other variant(s) if there is any. */
4397 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4398 output_info (_(" other valid variant(s):"));
4400 /* For each pattern. */
4401 qualifiers_list
= opcode
->qualifiers_list
;
4402 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4404 /* Most opcodes has much fewer patterns in the list.
4405 First NIL qualifier indicates the end in the list. */
4406 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4411 /* Mnemonics name. */
4412 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4414 /* Assign the qualifiers. */
4415 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4417 /* Print instruction. */
4418 print_operands (buf
, opcode
, inst_base
->operands
);
4420 output_info (_(" %s"), buf
);
4426 case AARCH64_OPDE_OUT_OF_RANGE
:
4427 if (detail
->data
[0] != detail
->data
[1])
4428 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4429 detail
->error
? detail
->error
: _("immediate value"),
4430 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4432 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4433 detail
->error
? detail
->error
: _("immediate value"),
4434 detail
->data
[0], idx
+ 1, str
);
4437 case AARCH64_OPDE_REG_LIST
:
4438 if (detail
->data
[0] == 1)
4439 as_bad (_("invalid number of registers in the list; "
4440 "only 1 register is expected at operand %d -- `%s'"),
4443 as_bad (_("invalid number of registers in the list; "
4444 "%d registers are expected at operand %d -- `%s'"),
4445 detail
->data
[0], idx
+ 1, str
);
4448 case AARCH64_OPDE_UNALIGNED
:
4449 as_bad (_("immediate value should be a multiple of "
4450 "%d at operand %d -- `%s'"),
4451 detail
->data
[0], idx
+ 1, str
);
4460 /* Process and output the error message about the operand mismatching.
4462 When this function is called, the operand error information had
4463 been collected for an assembly line and there will be multiple
4464 errors in the case of mulitple instruction templates; output the
4465 error message that most closely describes the problem. */
4468 output_operand_error_report (char *str
)
4470 int largest_error_pos
;
4471 const char *msg
= NULL
;
4472 enum aarch64_operand_error_kind kind
;
4473 operand_error_record
*curr
;
4474 operand_error_record
*head
= operand_error_report
.head
;
4475 operand_error_record
*record
= NULL
;
4477 /* No error to report. */
4481 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4483 /* Only one error. */
4484 if (head
== operand_error_report
.tail
)
4486 DEBUG_TRACE ("single opcode entry with error kind: %s",
4487 operand_mismatch_kind_names
[head
->detail
.kind
]);
4488 output_operand_error_record (head
, str
);
4492 /* Find the error kind of the highest severity. */
4493 DEBUG_TRACE ("multiple opcode entres with error kind");
4494 kind
= AARCH64_OPDE_NIL
;
4495 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4497 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4498 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4499 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4500 kind
= curr
->detail
.kind
;
4502 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4504 /* Pick up one of errors of KIND to report. */
4505 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4506 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4508 if (curr
->detail
.kind
!= kind
)
4510 /* If there are multiple errors, pick up the one with the highest
4511 mismatching operand index. In the case of multiple errors with
4512 the equally highest operand index, pick up the first one or the
4513 first one with non-NULL error message. */
4514 if (curr
->detail
.index
> largest_error_pos
4515 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4516 && curr
->detail
.error
!= NULL
))
4518 largest_error_pos
= curr
->detail
.index
;
4520 msg
= record
->detail
.error
;
4524 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4525 DEBUG_TRACE ("Pick up error kind %s to report",
4526 operand_mismatch_kind_names
[record
->detail
.kind
]);
4529 output_operand_error_record (record
, str
);
4532 /* Write an AARCH64 instruction to buf - always little-endian. */
4534 put_aarch64_insn (char *buf
, uint32_t insn
)
4536 unsigned char *where
= (unsigned char *) buf
;
4538 where
[1] = insn
>> 8;
4539 where
[2] = insn
>> 16;
4540 where
[3] = insn
>> 24;
4544 get_aarch64_insn (char *buf
)
4546 unsigned char *where
= (unsigned char *) buf
;
4548 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4553 output_inst (struct aarch64_inst
*new_inst
)
4557 to
= frag_more (INSN_SIZE
);
4559 frag_now
->tc_frag_data
.recorded
= 1;
4561 put_aarch64_insn (to
, inst
.base
.value
);
4563 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4565 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4566 INSN_SIZE
, &inst
.reloc
.exp
,
4569 DEBUG_TRACE ("Prepared relocation fix up");
4570 /* Don't check the addend value against the instruction size,
4571 that's the job of our code in md_apply_fix(). */
4572 fixp
->fx_no_overflow
= 1;
4573 if (new_inst
!= NULL
)
4574 fixp
->tc_fix_data
.inst
= new_inst
;
4575 if (aarch64_gas_internal_fixup_p ())
4577 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4578 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4579 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4583 dwarf2_emit_insn (INSN_SIZE
);
4586 /* Link together opcodes of the same name. */
4590 aarch64_opcode
*opcode
;
4591 struct templates
*next
;
4594 typedef struct templates templates
;
4597 lookup_mnemonic (const char *start
, int len
)
4599 templates
*templ
= NULL
;
4601 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4605 /* Subroutine of md_assemble, responsible for looking up the primary
4606 opcode from the mnemonic the user wrote. STR points to the
4607 beginning of the mnemonic. */
4610 opcode_lookup (char **str
)
4613 const aarch64_cond
*cond
;
4617 /* Scan up to the end of the mnemonic, which must end in white space,
4618 '.', or end of string. */
4619 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4626 inst
.cond
= COND_ALWAYS
;
4628 /* Handle a possible condition. */
4631 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4634 inst
.cond
= cond
->value
;
4648 if (inst
.cond
== COND_ALWAYS
)
4650 /* Look for unaffixed mnemonic. */
4651 return lookup_mnemonic (base
, len
);
4655 /* append ".c" to mnemonic if conditional */
4656 memcpy (condname
, base
, len
);
4657 memcpy (condname
+ len
, ".c", 2);
4660 return lookup_mnemonic (base
, len
);
4666 /* Internal helper routine converting a vector neon_type_el structure
4667 *VECTYPE to a corresponding operand qualifier. */
4669 static inline aarch64_opnd_qualifier_t
4670 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4672 /* Element size in bytes indexed by neon_el_type. */
4673 const unsigned char ele_size
[5]
4675 const unsigned int ele_base
[5] =
4677 AARCH64_OPND_QLF_V_8B
,
4678 AARCH64_OPND_QLF_V_2H
,
4679 AARCH64_OPND_QLF_V_2S
,
4680 AARCH64_OPND_QLF_V_1D
,
4681 AARCH64_OPND_QLF_V_1Q
4684 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4685 goto vectype_conversion_fail
;
4687 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4689 if (vectype
->defined
& NTA_HASINDEX
)
4690 /* Vector element register. */
4691 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4694 /* Vector register. */
4695 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4698 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4699 goto vectype_conversion_fail
;
4701 /* The conversion is by calculating the offset from the base operand
4702 qualifier for the vector type. The operand qualifiers are regular
4703 enough that the offset can established by shifting the vector width by
4704 a vector-type dependent amount. */
4706 if (vectype
->type
== NT_b
)
4708 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4710 else if (vectype
->type
>= NT_d
)
4715 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4716 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4717 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4721 vectype_conversion_fail
:
4722 first_error (_("bad vector arrangement type"));
4723 return AARCH64_OPND_QLF_NIL
;
4726 /* Process an optional operand that is found omitted from the assembly line.
4727 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4728 instruction's opcode entry while IDX is the index of this omitted operand.
4732 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4733 int idx
, aarch64_opnd_info
*operand
)
4735 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4736 gas_assert (optional_operand_p (opcode
, idx
));
4737 gas_assert (!operand
->present
);
4741 case AARCH64_OPND_Rd
:
4742 case AARCH64_OPND_Rn
:
4743 case AARCH64_OPND_Rm
:
4744 case AARCH64_OPND_Rt
:
4745 case AARCH64_OPND_Rt2
:
4746 case AARCH64_OPND_Rs
:
4747 case AARCH64_OPND_Ra
:
4748 case AARCH64_OPND_Rt_SYS
:
4749 case AARCH64_OPND_Rd_SP
:
4750 case AARCH64_OPND_Rn_SP
:
4751 case AARCH64_OPND_Fd
:
4752 case AARCH64_OPND_Fn
:
4753 case AARCH64_OPND_Fm
:
4754 case AARCH64_OPND_Fa
:
4755 case AARCH64_OPND_Ft
:
4756 case AARCH64_OPND_Ft2
:
4757 case AARCH64_OPND_Sd
:
4758 case AARCH64_OPND_Sn
:
4759 case AARCH64_OPND_Sm
:
4760 case AARCH64_OPND_Vd
:
4761 case AARCH64_OPND_Vn
:
4762 case AARCH64_OPND_Vm
:
4763 case AARCH64_OPND_VdD1
:
4764 case AARCH64_OPND_VnD1
:
4765 operand
->reg
.regno
= default_value
;
4768 case AARCH64_OPND_Ed
:
4769 case AARCH64_OPND_En
:
4770 case AARCH64_OPND_Em
:
4771 operand
->reglane
.regno
= default_value
;
4774 case AARCH64_OPND_IDX
:
4775 case AARCH64_OPND_BIT_NUM
:
4776 case AARCH64_OPND_IMMR
:
4777 case AARCH64_OPND_IMMS
:
4778 case AARCH64_OPND_SHLL_IMM
:
4779 case AARCH64_OPND_IMM_VLSL
:
4780 case AARCH64_OPND_IMM_VLSR
:
4781 case AARCH64_OPND_CCMP_IMM
:
4782 case AARCH64_OPND_FBITS
:
4783 case AARCH64_OPND_UIMM4
:
4784 case AARCH64_OPND_UIMM3_OP1
:
4785 case AARCH64_OPND_UIMM3_OP2
:
4786 case AARCH64_OPND_IMM
:
4787 case AARCH64_OPND_WIDTH
:
4788 case AARCH64_OPND_UIMM7
:
4789 case AARCH64_OPND_NZCV
:
4790 operand
->imm
.value
= default_value
;
4793 case AARCH64_OPND_EXCEPTION
:
4794 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4797 case AARCH64_OPND_BARRIER_ISB
:
4798 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4805 /* Process the relocation type for move wide instructions.
4806 Return TRUE on success; otherwise return FALSE. */
4809 process_movw_reloc_info (void)
4814 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4816 if (inst
.base
.opcode
->op
== OP_MOVK
)
4817 switch (inst
.reloc
.type
)
4819 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4820 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4821 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4822 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4823 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4824 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4825 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4827 (_("the specified relocation type is not allowed for MOVK"));
4833 switch (inst
.reloc
.type
)
4835 case BFD_RELOC_AARCH64_MOVW_G0
:
4836 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4837 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4838 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4839 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4840 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4841 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4842 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4843 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4844 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4845 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4848 case BFD_RELOC_AARCH64_MOVW_G1
:
4849 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4850 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4851 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4852 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4853 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4854 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4855 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4856 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4857 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4858 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4861 case BFD_RELOC_AARCH64_MOVW_G2
:
4862 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4863 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4864 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4865 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4868 set_fatal_syntax_error
4869 (_("the specified relocation type is not allowed for 32-bit "
4875 case BFD_RELOC_AARCH64_MOVW_G3
:
4878 set_fatal_syntax_error
4879 (_("the specified relocation type is not allowed for 32-bit "
4886 /* More cases should be added when more MOVW-related relocation types
4887 are supported in GAS. */
4888 gas_assert (aarch64_gas_internal_fixup_p ());
4889 /* The shift amount should have already been set by the parser. */
4892 inst
.base
.operands
[1].shifter
.amount
= shift
;
4896 /* A primitive log caculator. */
4898 static inline unsigned int
4899 get_logsz (unsigned int size
)
4901 const unsigned char ls
[16] =
4902 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4908 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4909 return ls
[size
- 1];
4912 /* Determine and return the real reloc type code for an instruction
4913 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4915 static inline bfd_reloc_code_real_type
4916 ldst_lo12_determine_real_reloc_type (void)
4919 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4920 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4922 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4924 BFD_RELOC_AARCH64_LDST8_LO12
,
4925 BFD_RELOC_AARCH64_LDST16_LO12
,
4926 BFD_RELOC_AARCH64_LDST32_LO12
,
4927 BFD_RELOC_AARCH64_LDST64_LO12
,
4928 BFD_RELOC_AARCH64_LDST128_LO12
4931 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4932 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4933 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4934 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4935 BFD_RELOC_AARCH64_NONE
4938 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4939 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4940 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4941 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4942 BFD_RELOC_AARCH64_NONE
4946 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4947 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4949 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4950 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4952 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4954 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4956 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4958 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4959 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4960 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4961 gas_assert (logsz
<= 3);
4963 gas_assert (logsz
<= 4);
4965 /* In reloc.c, these pseudo relocation types should be defined in similar
4966 order as above reloc_ldst_lo12 array. Because the array index calcuation
4967 below relies on this. */
4968 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4971 /* Check whether a register list REGINFO is valid. The registers must be
4972 numbered in increasing order (modulo 32), in increments of one or two.
4974 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4977 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4980 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4982 uint32_t i
, nb_regs
, prev_regno
, incr
;
4984 nb_regs
= 1 + (reginfo
& 0x3);
4986 prev_regno
= reginfo
& 0x1f;
4987 incr
= accept_alternate
? 2 : 1;
4989 for (i
= 1; i
< nb_regs
; ++i
)
4991 uint32_t curr_regno
;
4993 curr_regno
= reginfo
& 0x1f;
4994 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4996 prev_regno
= curr_regno
;
5002 /* Generic instruction operand parser. This does no encoding and no
5003 semantic validation; it merely squirrels values away in the inst
5004 structure. Returns TRUE or FALSE depending on whether the
5005 specified grammar matched. */
5008 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5011 char *backtrack_pos
= 0;
5012 const enum aarch64_opnd
*operands
= opcode
->operands
;
5015 skip_whitespace (str
);
5017 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5020 int isreg32
, isregzero
;
5021 int comma_skipped_p
= 0;
5022 aarch64_reg_type rtype
;
5023 struct neon_type_el vectype
;
5024 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5026 DEBUG_TRACE ("parse operand %d", i
);
5028 /* Assign the operand code. */
5029 info
->type
= operands
[i
];
5031 if (optional_operand_p (opcode
, i
))
5033 /* Remember where we are in case we need to backtrack. */
5034 gas_assert (!backtrack_pos
);
5035 backtrack_pos
= str
;
5038 /* Expect comma between operands; the backtrack mechanizm will take
5039 care of cases of omitted optional operand. */
5040 if (i
> 0 && ! skip_past_char (&str
, ','))
5042 set_syntax_error (_("comma expected between operands"));
5046 comma_skipped_p
= 1;
5048 switch (operands
[i
])
5050 case AARCH64_OPND_Rd
:
5051 case AARCH64_OPND_Rn
:
5052 case AARCH64_OPND_Rm
:
5053 case AARCH64_OPND_Rt
:
5054 case AARCH64_OPND_Rt2
:
5055 case AARCH64_OPND_Rs
:
5056 case AARCH64_OPND_Ra
:
5057 case AARCH64_OPND_Rt_SYS
:
5058 case AARCH64_OPND_PAIRREG
:
5059 po_int_reg_or_fail (1, 0);
5062 case AARCH64_OPND_Rd_SP
:
5063 case AARCH64_OPND_Rn_SP
:
5064 po_int_reg_or_fail (0, 1);
5067 case AARCH64_OPND_Rm_EXT
:
5068 case AARCH64_OPND_Rm_SFT
:
5069 po_misc_or_fail (parse_shifter_operand
5070 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5072 : SHIFTED_LOGIC_IMM
)));
5073 if (!info
->shifter
.operator_present
)
5075 /* Default to LSL if not present. Libopcodes prefers shifter
5076 kind to be explicit. */
5077 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5078 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5079 /* For Rm_EXT, libopcodes will carry out further check on whether
5080 or not stack pointer is used in the instruction (Recall that
5081 "the extend operator is not optional unless at least one of
5082 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5086 case AARCH64_OPND_Fd
:
5087 case AARCH64_OPND_Fn
:
5088 case AARCH64_OPND_Fm
:
5089 case AARCH64_OPND_Fa
:
5090 case AARCH64_OPND_Ft
:
5091 case AARCH64_OPND_Ft2
:
5092 case AARCH64_OPND_Sd
:
5093 case AARCH64_OPND_Sn
:
5094 case AARCH64_OPND_Sm
:
5095 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5096 if (val
== PARSE_FAIL
)
5098 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5101 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5103 info
->reg
.regno
= val
;
5104 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5107 case AARCH64_OPND_Vd
:
5108 case AARCH64_OPND_Vn
:
5109 case AARCH64_OPND_Vm
:
5110 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5111 if (val
== PARSE_FAIL
)
5113 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5116 if (vectype
.defined
& NTA_HASINDEX
)
5119 info
->reg
.regno
= val
;
5120 info
->qualifier
= vectype_to_qualifier (&vectype
);
5121 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5125 case AARCH64_OPND_VdD1
:
5126 case AARCH64_OPND_VnD1
:
5127 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5128 if (val
== PARSE_FAIL
)
5130 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5133 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5135 set_fatal_syntax_error
5136 (_("the top half of a 128-bit FP/SIMD register is expected"));
5139 info
->reg
.regno
= val
;
5140 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5141 here; it is correct for the purpose of encoding/decoding since
5142 only the register number is explicitly encoded in the related
5143 instructions, although this appears a bit hacky. */
5144 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5147 case AARCH64_OPND_Ed
:
5148 case AARCH64_OPND_En
:
5149 case AARCH64_OPND_Em
:
5150 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5151 if (val
== PARSE_FAIL
)
5153 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5156 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5159 info
->reglane
.regno
= val
;
5160 info
->reglane
.index
= vectype
.index
;
5161 info
->qualifier
= vectype_to_qualifier (&vectype
);
5162 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5166 case AARCH64_OPND_LVn
:
5167 case AARCH64_OPND_LVt
:
5168 case AARCH64_OPND_LVt_AL
:
5169 case AARCH64_OPND_LEt
:
5170 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5172 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5174 set_fatal_syntax_error (_("invalid register list"));
5177 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5178 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5179 if (operands
[i
] == AARCH64_OPND_LEt
)
5181 if (!(vectype
.defined
& NTA_HASINDEX
))
5183 info
->reglist
.has_index
= 1;
5184 info
->reglist
.index
= vectype
.index
;
5186 else if (!(vectype
.defined
& NTA_HASTYPE
))
5188 info
->qualifier
= vectype_to_qualifier (&vectype
);
5189 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5193 case AARCH64_OPND_Cn
:
5194 case AARCH64_OPND_Cm
:
5195 po_reg_or_fail (REG_TYPE_CN
);
5198 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5201 inst
.base
.operands
[i
].reg
.regno
= val
;
5204 case AARCH64_OPND_SHLL_IMM
:
5205 case AARCH64_OPND_IMM_VLSR
:
5206 po_imm_or_fail (1, 64);
5207 info
->imm
.value
= val
;
5210 case AARCH64_OPND_CCMP_IMM
:
5211 case AARCH64_OPND_FBITS
:
5212 case AARCH64_OPND_UIMM4
:
5213 case AARCH64_OPND_UIMM3_OP1
:
5214 case AARCH64_OPND_UIMM3_OP2
:
5215 case AARCH64_OPND_IMM_VLSL
:
5216 case AARCH64_OPND_IMM
:
5217 case AARCH64_OPND_WIDTH
:
5218 po_imm_nc_or_fail ();
5219 info
->imm
.value
= val
;
5222 case AARCH64_OPND_UIMM7
:
5223 po_imm_or_fail (0, 127);
5224 info
->imm
.value
= val
;
5227 case AARCH64_OPND_IDX
:
5228 case AARCH64_OPND_BIT_NUM
:
5229 case AARCH64_OPND_IMMR
:
5230 case AARCH64_OPND_IMMS
:
5231 po_imm_or_fail (0, 63);
5232 info
->imm
.value
= val
;
5235 case AARCH64_OPND_IMM0
:
5236 po_imm_nc_or_fail ();
5239 set_fatal_syntax_error (_("immediate zero expected"));
5242 info
->imm
.value
= 0;
5245 case AARCH64_OPND_FPIMM0
:
5248 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5249 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5250 it is probably not worth the effort to support it. */
5251 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5252 && !(res2
= parse_constant_immediate (&str
, &val
)))
5254 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5256 info
->imm
.value
= 0;
5257 info
->imm
.is_fp
= 1;
5260 set_fatal_syntax_error (_("immediate zero expected"));
5264 case AARCH64_OPND_IMM_MOV
:
5267 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5268 reg_name_p (str
, REG_TYPE_VN
))
5271 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5273 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5274 later. fix_mov_imm_insn will try to determine a machine
5275 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5276 message if the immediate cannot be moved by a single
5278 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5279 inst
.base
.operands
[i
].skip
= 1;
5283 case AARCH64_OPND_SIMD_IMM
:
5284 case AARCH64_OPND_SIMD_IMM_SFT
:
5285 if (! parse_big_immediate (&str
, &val
))
5287 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5289 /* need_libopcodes_p */ 1,
5292 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5293 shift, we don't check it here; we leave the checking to
5294 the libopcodes (operand_general_constraint_met_p). By
5295 doing this, we achieve better diagnostics. */
5296 if (skip_past_comma (&str
)
5297 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5299 if (!info
->shifter
.operator_present
5300 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5302 /* Default to LSL if not present. Libopcodes prefers shifter
5303 kind to be explicit. */
5304 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5305 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5309 case AARCH64_OPND_FPIMM
:
5310 case AARCH64_OPND_SIMD_FPIMM
:
5314 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5316 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5320 set_fatal_syntax_error (_("invalid floating-point constant"));
5323 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5324 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5328 case AARCH64_OPND_LIMM
:
5329 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5330 SHIFTED_LOGIC_IMM
));
5331 if (info
->shifter
.operator_present
)
5333 set_fatal_syntax_error
5334 (_("shift not allowed for bitmask immediate"));
5337 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5339 /* need_libopcodes_p */ 1,
5343 case AARCH64_OPND_AIMM
:
5344 if (opcode
->op
== OP_ADD
)
5345 /* ADD may have relocation types. */
5346 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5347 SHIFTED_ARITH_IMM
));
5349 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5350 SHIFTED_ARITH_IMM
));
5351 switch (inst
.reloc
.type
)
5353 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5354 info
->shifter
.amount
= 12;
5356 case BFD_RELOC_UNUSED
:
5357 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5358 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5359 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5360 inst
.reloc
.pc_rel
= 0;
5365 info
->imm
.value
= 0;
5366 if (!info
->shifter
.operator_present
)
5368 /* Default to LSL if not present. Libopcodes prefers shifter
5369 kind to be explicit. */
5370 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5371 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5375 case AARCH64_OPND_HALF
:
5377 /* #<imm16> or relocation. */
5378 int internal_fixup_p
;
5379 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5380 if (internal_fixup_p
)
5381 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5382 skip_whitespace (str
);
5383 if (skip_past_comma (&str
))
5385 /* {, LSL #<shift>} */
5386 if (! aarch64_gas_internal_fixup_p ())
5388 set_fatal_syntax_error (_("can't mix relocation modifier "
5389 "with explicit shift"));
5392 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5395 inst
.base
.operands
[i
].shifter
.amount
= 0;
5396 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5397 inst
.base
.operands
[i
].imm
.value
= 0;
5398 if (! process_movw_reloc_info ())
5403 case AARCH64_OPND_EXCEPTION
:
5404 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5405 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5407 /* need_libopcodes_p */ 0,
5411 case AARCH64_OPND_NZCV
:
5413 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5417 info
->imm
.value
= nzcv
->value
;
5420 po_imm_or_fail (0, 15);
5421 info
->imm
.value
= val
;
5425 case AARCH64_OPND_COND
:
5426 case AARCH64_OPND_COND1
:
5427 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5429 if (info
->cond
== NULL
)
5431 set_syntax_error (_("invalid condition"));
5434 else if (operands
[i
] == AARCH64_OPND_COND1
5435 && (info
->cond
->value
& 0xe) == 0xe)
5437 /* Not allow AL or NV. */
5438 set_default_error ();
5443 case AARCH64_OPND_ADDR_ADRP
:
5444 po_misc_or_fail (parse_adrp (&str
));
5445 /* Clear the value as operand needs to be relocated. */
5446 info
->imm
.value
= 0;
5449 case AARCH64_OPND_ADDR_PCREL14
:
5450 case AARCH64_OPND_ADDR_PCREL19
:
5451 case AARCH64_OPND_ADDR_PCREL21
:
5452 case AARCH64_OPND_ADDR_PCREL26
:
5453 po_misc_or_fail (parse_address_reloc (&str
, info
));
5454 if (!info
->addr
.pcrel
)
5456 set_syntax_error (_("invalid pc-relative address"));
5459 if (inst
.gen_lit_pool
5460 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5462 /* Only permit "=value" in the literal load instructions.
5463 The literal will be generated by programmer_friendly_fixup. */
5464 set_syntax_error (_("invalid use of \"=immediate\""));
5467 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5469 set_syntax_error (_("unrecognized relocation suffix"));
5472 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5474 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5475 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5479 info
->imm
.value
= 0;
5480 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5481 switch (opcode
->iclass
)
5485 /* e.g. CBZ or B.COND */
5486 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5487 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5491 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5492 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5496 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5498 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5499 : BFD_RELOC_AARCH64_JUMP26
;
5502 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5503 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5506 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5507 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5513 inst
.reloc
.pc_rel
= 1;
5517 case AARCH64_OPND_ADDR_SIMPLE
:
5518 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5519 /* [<Xn|SP>{, #<simm>}] */
5520 po_char_or_fail ('[');
5521 po_reg_or_fail (REG_TYPE_R64_SP
);
5522 /* Accept optional ", #0". */
5523 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5524 && skip_past_char (&str
, ','))
5526 skip_past_char (&str
, '#');
5527 if (! skip_past_char (&str
, '0'))
5529 set_fatal_syntax_error
5530 (_("the optional immediate offset can only be 0"));
5534 po_char_or_fail (']');
5535 info
->addr
.base_regno
= val
;
5538 case AARCH64_OPND_ADDR_REGOFF
:
5539 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5540 po_misc_or_fail (parse_address (&str
, info
, 0));
5541 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5542 || !info
->addr
.preind
|| info
->addr
.postind
5543 || info
->addr
.writeback
)
5545 set_syntax_error (_("invalid addressing mode"));
5548 if (!info
->shifter
.operator_present
)
5550 /* Default to LSL if not present. Libopcodes prefers shifter
5551 kind to be explicit. */
5552 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5553 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5555 /* Qualifier to be deduced by libopcodes. */
5558 case AARCH64_OPND_ADDR_SIMM7
:
5559 po_misc_or_fail (parse_address (&str
, info
, 0));
5560 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5561 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5563 set_syntax_error (_("invalid addressing mode"));
5566 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5568 /* need_libopcodes_p */ 1,
5572 case AARCH64_OPND_ADDR_SIMM9
:
5573 case AARCH64_OPND_ADDR_SIMM9_2
:
5574 po_misc_or_fail (parse_address_reloc (&str
, info
));
5575 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5576 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5577 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5578 && info
->addr
.writeback
))
5580 set_syntax_error (_("invalid addressing mode"));
5583 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5585 set_syntax_error (_("relocation not allowed"));
5588 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5590 /* need_libopcodes_p */ 1,
5594 case AARCH64_OPND_ADDR_UIMM12
:
5595 po_misc_or_fail (parse_address_reloc (&str
, info
));
5596 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5597 || !info
->addr
.preind
|| info
->addr
.writeback
)
5599 set_syntax_error (_("invalid addressing mode"));
5602 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5603 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5604 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5606 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5608 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5609 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5610 /* Leave qualifier to be determined by libopcodes. */
5613 case AARCH64_OPND_SIMD_ADDR_POST
:
5614 /* [<Xn|SP>], <Xm|#<amount>> */
5615 po_misc_or_fail (parse_address (&str
, info
, 1));
5616 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5618 set_syntax_error (_("invalid addressing mode"));
5621 if (!info
->addr
.offset
.is_reg
)
5623 if (inst
.reloc
.exp
.X_op
== O_constant
)
5624 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5627 set_fatal_syntax_error
5628 (_("writeback value should be an immediate constant"));
5635 case AARCH64_OPND_SYSREG
:
5636 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5639 set_syntax_error (_("unknown or missing system register name"));
5642 inst
.base
.operands
[i
].sysreg
= val
;
5645 case AARCH64_OPND_PSTATEFIELD
:
5646 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5649 set_syntax_error (_("unknown or missing PSTATE field name"));
5652 inst
.base
.operands
[i
].pstatefield
= val
;
5655 case AARCH64_OPND_SYSREG_IC
:
5656 inst
.base
.operands
[i
].sysins_op
=
5657 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5659 case AARCH64_OPND_SYSREG_DC
:
5660 inst
.base
.operands
[i
].sysins_op
=
5661 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5663 case AARCH64_OPND_SYSREG_AT
:
5664 inst
.base
.operands
[i
].sysins_op
=
5665 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5667 case AARCH64_OPND_SYSREG_TLBI
:
5668 inst
.base
.operands
[i
].sysins_op
=
5669 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5671 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5673 set_fatal_syntax_error ( _("unknown or missing operation name"));
5678 case AARCH64_OPND_BARRIER
:
5679 case AARCH64_OPND_BARRIER_ISB
:
5680 val
= parse_barrier (&str
);
5681 if (val
!= PARSE_FAIL
5682 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5684 /* ISB only accepts options name 'sy'. */
5686 (_("the specified option is not accepted in ISB"));
5687 /* Turn off backtrack as this optional operand is present. */
5691 /* This is an extension to accept a 0..15 immediate. */
5692 if (val
== PARSE_FAIL
)
5693 po_imm_or_fail (0, 15);
5694 info
->barrier
= aarch64_barrier_options
+ val
;
5697 case AARCH64_OPND_PRFOP
:
5698 val
= parse_pldop (&str
);
5699 /* This is an extension to accept a 0..31 immediate. */
5700 if (val
== PARSE_FAIL
)
5701 po_imm_or_fail (0, 31);
5702 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5705 case AARCH64_OPND_BARRIER_PSB
:
5706 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5707 if (val
== PARSE_FAIL
)
5712 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5715 /* If we get here, this operand was successfully parsed. */
5716 inst
.base
.operands
[i
].present
= 1;
5720 /* The parse routine should already have set the error, but in case
5721 not, set a default one here. */
5723 set_default_error ();
5725 if (! backtrack_pos
)
5726 goto parse_operands_return
;
5729 /* We reach here because this operand is marked as optional, and
5730 either no operand was supplied or the operand was supplied but it
5731 was syntactically incorrect. In the latter case we report an
5732 error. In the former case we perform a few more checks before
5733 dropping through to the code to insert the default operand. */
5735 char *tmp
= backtrack_pos
;
5736 char endchar
= END_OF_INSN
;
5738 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5740 skip_past_char (&tmp
, ',');
5742 if (*tmp
!= endchar
)
5743 /* The user has supplied an operand in the wrong format. */
5744 goto parse_operands_return
;
5746 /* Make sure there is not a comma before the optional operand.
5747 For example the fifth operand of 'sys' is optional:
5749 sys #0,c0,c0,#0, <--- wrong
5750 sys #0,c0,c0,#0 <--- correct. */
5751 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5753 set_fatal_syntax_error
5754 (_("unexpected comma before the omitted optional operand"));
5755 goto parse_operands_return
;
5759 /* Reaching here means we are dealing with an optional operand that is
5760 omitted from the assembly line. */
5761 gas_assert (optional_operand_p (opcode
, i
));
5763 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5765 /* Try again, skipping the optional operand at backtrack_pos. */
5766 str
= backtrack_pos
;
5769 /* Clear any error record after the omitted optional operand has been
5770 successfully handled. */
5774 /* Check if we have parsed all the operands. */
5775 if (*str
!= '\0' && ! error_p ())
5777 /* Set I to the index of the last present operand; this is
5778 for the purpose of diagnostics. */
5779 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5781 set_fatal_syntax_error
5782 (_("unexpected characters following instruction"));
5785 parse_operands_return
:
5789 DEBUG_TRACE ("parsing FAIL: %s - %s",
5790 operand_mismatch_kind_names
[get_error_kind ()],
5791 get_error_message ());
5792 /* Record the operand error properly; this is useful when there
5793 are multiple instruction templates for a mnemonic name, so that
5794 later on, we can select the error that most closely describes
5796 record_operand_error (opcode
, i
, get_error_kind (),
5797 get_error_message ());
5802 DEBUG_TRACE ("parsing SUCCESS");
5807 /* It does some fix-up to provide some programmer friendly feature while
5808 keeping the libopcodes happy, i.e. libopcodes only accepts
5809 the preferred architectural syntax.
5810 Return FALSE if there is any failure; otherwise return TRUE. */
5813 programmer_friendly_fixup (aarch64_instruction
*instr
)
5815 aarch64_inst
*base
= &instr
->base
;
5816 const aarch64_opcode
*opcode
= base
->opcode
;
5817 enum aarch64_op op
= opcode
->op
;
5818 aarch64_opnd_info
*operands
= base
->operands
;
5820 DEBUG_TRACE ("enter");
5822 switch (opcode
->iclass
)
5825 /* TBNZ Xn|Wn, #uimm6, label
5826 Test and Branch Not Zero: conditionally jumps to label if bit number
5827 uimm6 in register Xn is not zero. The bit number implies the width of
5828 the register, which may be written and should be disassembled as Wn if
5829 uimm is less than 32. */
5830 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5832 if (operands
[1].imm
.value
>= 32)
5834 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5838 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5842 /* LDR Wt, label | =value
5843 As a convenience assemblers will typically permit the notation
5844 "=value" in conjunction with the pc-relative literal load instructions
5845 to automatically place an immediate value or symbolic address in a
5846 nearby literal pool and generate a hidden label which references it.
5847 ISREG has been set to 0 in the case of =value. */
5848 if (instr
->gen_lit_pool
5849 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5851 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5852 if (op
== OP_LDRSW_LIT
)
5854 if (instr
->reloc
.exp
.X_op
!= O_constant
5855 && instr
->reloc
.exp
.X_op
!= O_big
5856 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5858 record_operand_error (opcode
, 1,
5859 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5860 _("constant expression expected"));
5863 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5865 record_operand_error (opcode
, 1,
5866 AARCH64_OPDE_OTHER_ERROR
,
5867 _("literal pool insertion failed"));
5875 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5876 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5877 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5878 A programmer-friendly assembler should accept a destination Xd in
5879 place of Wd, however that is not the preferred form for disassembly.
5881 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5882 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5883 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5884 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5889 /* In the 64-bit form, the final register operand is written as Wm
5890 for all but the (possibly omitted) UXTX/LSL and SXTX
5892 As a programmer-friendly assembler, we accept e.g.
5893 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5894 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5895 int idx
= aarch64_operand_index (opcode
->operands
,
5896 AARCH64_OPND_Rm_EXT
);
5897 gas_assert (idx
== 1 || idx
== 2);
5898 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5899 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5900 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5901 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5902 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5903 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5911 DEBUG_TRACE ("exit with SUCCESS");
5915 /* Check for loads and stores that will cause unpredictable behavior. */
5918 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5920 aarch64_inst
*base
= &instr
->base
;
5921 const aarch64_opcode
*opcode
= base
->opcode
;
5922 const aarch64_opnd_info
*opnds
= base
->operands
;
5923 switch (opcode
->iclass
)
5929 /* Loading/storing the base register is unpredictable if writeback. */
5930 if ((aarch64_get_operand_class (opnds
[0].type
)
5931 == AARCH64_OPND_CLASS_INT_REG
)
5932 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5933 && opnds
[1].addr
.base_regno
!= REG_SP
5934 && opnds
[1].addr
.writeback
)
5935 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5938 case ldstnapair_offs
:
5939 case ldstpair_indexed
:
5940 /* Loading/storing the base register is unpredictable if writeback. */
5941 if ((aarch64_get_operand_class (opnds
[0].type
)
5942 == AARCH64_OPND_CLASS_INT_REG
)
5943 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5944 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5945 && opnds
[2].addr
.base_regno
!= REG_SP
5946 && opnds
[2].addr
.writeback
)
5947 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5948 /* Load operations must load different registers. */
5949 if ((opcode
->opcode
& (1 << 22))
5950 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5951 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5958 /* A wrapper function to interface with libopcodes on encoding and
5959 record the error message if there is any.
5961 Return TRUE on success; otherwise return FALSE. */
5964 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5967 aarch64_operand_error error_info
;
5968 error_info
.kind
= AARCH64_OPDE_NIL
;
5969 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5973 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5974 record_operand_error_info (opcode
, &error_info
);
5979 #ifdef DEBUG_AARCH64
5981 dump_opcode_operands (const aarch64_opcode
*opcode
)
5984 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5986 aarch64_verbose ("\t\t opnd%d: %s", i
,
5987 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5988 ? aarch64_get_operand_name (opcode
->operands
[i
])
5989 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5993 #endif /* DEBUG_AARCH64 */
5995 /* This is the guts of the machine-dependent assembler. STR points to a
5996 machine dependent instruction. This function is supposed to emit
5997 the frags/bytes it assembles to. */
6000 md_assemble (char *str
)
6003 templates
*template;
6004 aarch64_opcode
*opcode
;
6005 aarch64_inst
*inst_base
;
6006 unsigned saved_cond
;
6008 /* Align the previous label if needed. */
6009 if (last_label_seen
!= NULL
)
6011 symbol_set_frag (last_label_seen
, frag_now
);
6012 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6013 S_SET_SEGMENT (last_label_seen
, now_seg
);
6016 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6018 DEBUG_TRACE ("\n\n");
6019 DEBUG_TRACE ("==============================");
6020 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6022 template = opcode_lookup (&p
);
6025 /* It wasn't an instruction, but it might be a register alias of
6026 the form alias .req reg directive. */
6027 if (!create_register_alias (str
, p
))
6028 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6033 skip_whitespace (p
);
6036 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6037 get_mnemonic_name (str
), str
);
6041 init_operand_error_report ();
6043 /* Sections are assumed to start aligned. In executable section, there is no
6044 MAP_DATA symbol pending. So we only align the address during
6045 MAP_DATA --> MAP_INSN transition.
6046 For other sections, this is not guaranteed. */
6047 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6048 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6049 frag_align_code (2, 0);
6051 saved_cond
= inst
.cond
;
6052 reset_aarch64_instruction (&inst
);
6053 inst
.cond
= saved_cond
;
6055 /* Iterate through all opcode entries with the same mnemonic name. */
6058 opcode
= template->opcode
;
6060 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6061 #ifdef DEBUG_AARCH64
6063 dump_opcode_operands (opcode
);
6064 #endif /* DEBUG_AARCH64 */
6066 mapping_state (MAP_INSN
);
6068 inst_base
= &inst
.base
;
6069 inst_base
->opcode
= opcode
;
6071 /* Truly conditionally executed instructions, e.g. b.cond. */
6072 if (opcode
->flags
& F_COND
)
6074 gas_assert (inst
.cond
!= COND_ALWAYS
);
6075 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6076 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6078 else if (inst
.cond
!= COND_ALWAYS
)
6080 /* It shouldn't arrive here, where the assembly looks like a
6081 conditional instruction but the found opcode is unconditional. */
6086 if (parse_operands (p
, opcode
)
6087 && programmer_friendly_fixup (&inst
)
6088 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6090 /* Check that this instruction is supported for this CPU. */
6091 if (!opcode
->avariant
6092 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
6094 as_bad (_("selected processor does not support `%s'"), str
);
6098 warn_unpredictable_ldst (&inst
, str
);
6100 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6101 || !inst
.reloc
.need_libopcodes_p
)
6105 /* If there is relocation generated for the instruction,
6106 store the instruction information for the future fix-up. */
6107 struct aarch64_inst
*copy
;
6108 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6109 if ((copy
= xmalloc (sizeof (struct aarch64_inst
))) == NULL
)
6111 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6117 template = template->next
;
6118 if (template != NULL
)
6120 reset_aarch64_instruction (&inst
);
6121 inst
.cond
= saved_cond
;
6124 while (template != NULL
);
6126 /* Issue the error messages if any. */
6127 output_operand_error_report (str
);
6130 /* Various frobbings of labels and their addresses. */
6133 aarch64_start_line_hook (void)
6135 last_label_seen
= NULL
;
6139 aarch64_frob_label (symbolS
* sym
)
6141 last_label_seen
= sym
;
6143 dwarf2_emit_label (sym
);
6147 aarch64_data_in_code (void)
6149 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6151 *input_line_pointer
= '/';
6152 input_line_pointer
+= 5;
6153 *input_line_pointer
= 0;
6161 aarch64_canonicalize_symbol_name (char *name
)
6165 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6166 *(name
+ len
- 5) = 0;
6171 /* Table of all register names defined by default. The user can
6172 define additional names with .req. Note that all register names
6173 should appear in both upper and lowercase variants. Some registers
6174 also have mixed-case names. */
6176 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6177 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6178 #define REGSET31(p,t) \
6179 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6180 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6181 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6182 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6183 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6184 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6185 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6186 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6187 #define REGSET(p,t) \
6188 REGSET31(p,t), REGNUM(p,31,t)
6190 /* These go into aarch64_reg_hsh hash-table. */
6191 static const reg_entry reg_names
[] = {
6192 /* Integer registers. */
6193 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6194 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6196 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6197 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6199 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6200 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6202 /* Coprocessor register numbers. */
6203 REGSET (c
, CN
), REGSET (C
, CN
),
6205 /* Floating-point single precision registers. */
6206 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6208 /* Floating-point double precision registers. */
6209 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6211 /* Floating-point half precision registers. */
6212 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6214 /* Floating-point byte precision registers. */
6215 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6217 /* Floating-point quad precision registers. */
6218 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6220 /* FP/SIMD registers. */
6221 REGSET (v
, VN
), REGSET (V
, VN
),
6236 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6237 static const asm_nzcv nzcv_names
[] = {
6238 {"nzcv", B (n
, z
, c
, v
)},
6239 {"nzcV", B (n
, z
, c
, V
)},
6240 {"nzCv", B (n
, z
, C
, v
)},
6241 {"nzCV", B (n
, z
, C
, V
)},
6242 {"nZcv", B (n
, Z
, c
, v
)},
6243 {"nZcV", B (n
, Z
, c
, V
)},
6244 {"nZCv", B (n
, Z
, C
, v
)},
6245 {"nZCV", B (n
, Z
, C
, V
)},
6246 {"Nzcv", B (N
, z
, c
, v
)},
6247 {"NzcV", B (N
, z
, c
, V
)},
6248 {"NzCv", B (N
, z
, C
, v
)},
6249 {"NzCV", B (N
, z
, C
, V
)},
6250 {"NZcv", B (N
, Z
, c
, v
)},
6251 {"NZcV", B (N
, Z
, c
, V
)},
6252 {"NZCv", B (N
, Z
, C
, v
)},
6253 {"NZCV", B (N
, Z
, C
, V
)}
6266 /* MD interface: bits in the object file. */
6268 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6269 for use in the a.out file, and stores them in the array pointed to by buf.
6270 This knows about the endian-ness of the target machine and does
6271 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6272 2 (short) and 4 (long) Floating numbers are put out as a series of
6273 LITTLENUMS (shorts, here at least). */
6276 md_number_to_chars (char *buf
, valueT val
, int n
)
6278 if (target_big_endian
)
6279 number_to_chars_bigendian (buf
, val
, n
);
6281 number_to_chars_littleendian (buf
, val
, n
);
6284 /* MD interface: Sections. */
6286 /* Estimate the size of a frag before relaxing. Assume everything fits in
6290 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6296 /* Round up a section size to the appropriate boundary. */
6299 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6304 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6305 of an rs_align_code fragment.
6307 Here we fill the frag with the appropriate info for padding the
6308 output stream. The resulting frag will consist of a fixed (fr_fix)
6309 and of a repeating (fr_var) part.
6311 The fixed content is always emitted before the repeating content and
6312 these two parts are used as follows in constructing the output:
6313 - the fixed part will be used to align to a valid instruction word
6314 boundary, in case that we start at a misaligned address; as no
6315 executable instruction can live at the misaligned location, we
6316 simply fill with zeros;
6317 - the variable part will be used to cover the remaining padding and
6318 we fill using the AArch64 NOP instruction.
6320 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6321 enough storage space for up to 3 bytes for padding the back to a valid
6322 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6325 aarch64_handle_align (fragS
* fragP
)
6327 /* NOP = d503201f */
6328 /* AArch64 instructions are always little-endian. */
6329 static char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6331 int bytes
, fix
, noop_size
;
6334 if (fragP
->fr_type
!= rs_align_code
)
6337 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6338 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6341 gas_assert (fragP
->tc_frag_data
.recorded
);
6344 noop_size
= sizeof (aarch64_noop
);
6346 fix
= bytes
& (noop_size
- 1);
6350 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6354 fragP
->fr_fix
+= fix
;
6358 memcpy (p
, aarch64_noop
, noop_size
);
6359 fragP
->fr_var
= noop_size
;
6362 /* Perform target specific initialisation of a frag.
6363 Note - despite the name this initialisation is not done when the frag
6364 is created, but only when its type is assigned. A frag can be created
6365 and used a long time before its type is set, so beware of assuming that
6366 this initialisationis performed first. */
6370 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6371 int max_chars ATTRIBUTE_UNUSED
)
6375 #else /* OBJ_ELF is defined. */
6377 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6379 /* Record a mapping symbol for alignment frags. We will delete this
6380 later if the alignment ends up empty. */
6381 if (!fragP
->tc_frag_data
.recorded
)
6382 fragP
->tc_frag_data
.recorded
= 1;
6384 switch (fragP
->fr_type
)
6389 mapping_state_2 (MAP_DATA
, max_chars
);
6392 mapping_state_2 (MAP_INSN
, max_chars
);
6399 /* Initialize the DWARF-2 unwind information for this procedure. */
6402 tc_aarch64_frame_initial_instructions (void)
6404 cfi_add_CFA_def_cfa (REG_SP
, 0);
6406 #endif /* OBJ_ELF */
6408 /* Convert REGNAME to a DWARF-2 register number. */
6411 tc_aarch64_regname_to_dw2regnum (char *regname
)
6413 const reg_entry
*reg
= parse_reg (®name
);
6419 case REG_TYPE_SP_32
:
6420 case REG_TYPE_SP_64
:
6430 return reg
->number
+ 64;
6438 /* Implement DWARF2_ADDR_SIZE. */
6441 aarch64_dwarf2_addr_size (void)
6443 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6447 return bfd_arch_bits_per_address (stdoutput
) / 8;
6450 /* MD interface: Symbol and relocation handling. */
6452 /* Return the address within the segment that a PC-relative fixup is
6453 relative to. For AArch64 PC-relative fixups applied to instructions
6454 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6457 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6459 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6461 /* If this is pc-relative and we are going to emit a relocation
6462 then we just want to put out any pipeline compensation that the linker
6463 will need. Otherwise we want to use the calculated base. */
6465 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6466 || aarch64_force_relocation (fixP
)))
6469 /* AArch64 should be consistent for all pc-relative relocations. */
6470 return base
+ AARCH64_PCREL_OFFSET
;
6473 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6474 Otherwise we have no need to default values of symbols. */
6477 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6480 if (name
[0] == '_' && name
[1] == 'G'
6481 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6485 if (symbol_find (name
))
6486 as_bad (_("GOT already in the symbol table"));
6488 GOT_symbol
= symbol_new (name
, undefined_section
,
6489 (valueT
) 0, &zero_address_frag
);
6499 /* Return non-zero if the indicated VALUE has overflowed the maximum
6500 range expressible by a unsigned number with the indicated number of
6504 unsigned_overflow (valueT value
, unsigned bits
)
6507 if (bits
>= sizeof (valueT
) * 8)
6509 lim
= (valueT
) 1 << bits
;
6510 return (value
>= lim
);
6514 /* Return non-zero if the indicated VALUE has overflowed the maximum
6515 range expressible by an signed number with the indicated number of
6519 signed_overflow (offsetT value
, unsigned bits
)
6522 if (bits
>= sizeof (offsetT
) * 8)
6524 lim
= (offsetT
) 1 << (bits
- 1);
6525 return (value
< -lim
|| value
>= lim
);
6528 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6529 unsigned immediate offset load/store instruction, try to encode it as
6530 an unscaled, 9-bit, signed immediate offset load/store instruction.
6531 Return TRUE if it is successful; otherwise return FALSE.
6533 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6534 in response to the standard LDR/STR mnemonics when the immediate offset is
6535 unambiguous, i.e. when it is negative or unaligned. */
6538 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6541 enum aarch64_op new_op
;
6542 const aarch64_opcode
*new_opcode
;
6544 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6546 switch (instr
->opcode
->op
)
6548 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6549 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6550 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6551 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6552 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6553 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6554 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6555 case OP_STR_POS
: new_op
= OP_STUR
; break;
6556 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6557 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6558 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6559 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6560 default: new_op
= OP_NIL
; break;
6563 if (new_op
== OP_NIL
)
6566 new_opcode
= aarch64_get_opcode (new_op
);
6567 gas_assert (new_opcode
!= NULL
);
6569 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6570 instr
->opcode
->op
, new_opcode
->op
);
6572 aarch64_replace_opcode (instr
, new_opcode
);
6574 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6575 qualifier matching may fail because the out-of-date qualifier will
6576 prevent the operand being updated with a new and correct qualifier. */
6577 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6578 AARCH64_OPND_ADDR_SIMM9
);
6579 gas_assert (idx
== 1);
6580 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6582 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6584 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6590 /* Called by fix_insn to fix a MOV immediate alias instruction.
6592 Operand for a generic move immediate instruction, which is an alias
6593 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6594 a 32-bit/64-bit immediate value into general register. An assembler error
6595 shall result if the immediate cannot be created by a single one of these
6596 instructions. If there is a choice, then to ensure reversability an
6597 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6600 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6602 const aarch64_opcode
*opcode
;
6604 /* Need to check if the destination is SP/ZR. The check has to be done
6605 before any aarch64_replace_opcode. */
6606 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6607 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6609 instr
->operands
[1].imm
.value
= value
;
6610 instr
->operands
[1].skip
= 0;
6614 /* Try the MOVZ alias. */
6615 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6616 aarch64_replace_opcode (instr
, opcode
);
6617 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6618 &instr
->value
, NULL
, NULL
))
6620 put_aarch64_insn (buf
, instr
->value
);
6623 /* Try the MOVK alias. */
6624 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6625 aarch64_replace_opcode (instr
, opcode
);
6626 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6627 &instr
->value
, NULL
, NULL
))
6629 put_aarch64_insn (buf
, instr
->value
);
6634 if (try_mov_bitmask_p
)
6636 /* Try the ORR alias. */
6637 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6638 aarch64_replace_opcode (instr
, opcode
);
6639 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6640 &instr
->value
, NULL
, NULL
))
6642 put_aarch64_insn (buf
, instr
->value
);
6647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6648 _("immediate cannot be moved by a single instruction"));
6651 /* An instruction operand which is immediate related may have symbol used
6652 in the assembly, e.g.
6655 .set u32, 0x00ffff00
6657 At the time when the assembly instruction is parsed, a referenced symbol,
6658 like 'u32' in the above example may not have been seen; a fixS is created
6659 in such a case and is handled here after symbols have been resolved.
6660 Instruction is fixed up with VALUE using the information in *FIXP plus
6661 extra information in FLAGS.
6663 This function is called by md_apply_fix to fix up instructions that need
6664 a fix-up described above but does not involve any linker-time relocation. */
6667 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6671 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6672 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6673 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6677 /* Now the instruction is about to be fixed-up, so the operand that
6678 was previously marked as 'ignored' needs to be unmarked in order
6679 to get the encoding done properly. */
6680 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6681 new_inst
->operands
[idx
].skip
= 0;
6684 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6688 case AARCH64_OPND_EXCEPTION
:
6689 if (unsigned_overflow (value
, 16))
6690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6691 _("immediate out of range"));
6692 insn
= get_aarch64_insn (buf
);
6693 insn
|= encode_svc_imm (value
);
6694 put_aarch64_insn (buf
, insn
);
6697 case AARCH64_OPND_AIMM
:
6698 /* ADD or SUB with immediate.
6699 NOTE this assumes we come here with a add/sub shifted reg encoding
6700 3 322|2222|2 2 2 21111 111111
6701 1 098|7654|3 2 1 09876 543210 98765 43210
6702 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6703 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6704 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6705 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6707 3 322|2222|2 2 221111111111
6708 1 098|7654|3 2 109876543210 98765 43210
6709 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6710 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6711 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6712 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6713 Fields sf Rn Rd are already set. */
6714 insn
= get_aarch64_insn (buf
);
6718 insn
= reencode_addsub_switch_add_sub (insn
);
6722 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6723 && unsigned_overflow (value
, 12))
6725 /* Try to shift the value by 12 to make it fit. */
6726 if (((value
>> 12) << 12) == value
6727 && ! unsigned_overflow (value
, 12 + 12))
6730 insn
|= encode_addsub_imm_shift_amount (1);
6734 if (unsigned_overflow (value
, 12))
6735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6736 _("immediate out of range"));
6738 insn
|= encode_addsub_imm (value
);
6740 put_aarch64_insn (buf
, insn
);
6743 case AARCH64_OPND_SIMD_IMM
:
6744 case AARCH64_OPND_SIMD_IMM_SFT
:
6745 case AARCH64_OPND_LIMM
:
6746 /* Bit mask immediate. */
6747 gas_assert (new_inst
!= NULL
);
6748 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6749 new_inst
->operands
[idx
].imm
.value
= value
;
6750 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6751 &new_inst
->value
, NULL
, NULL
))
6752 put_aarch64_insn (buf
, new_inst
->value
);
6754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6755 _("invalid immediate"));
6758 case AARCH64_OPND_HALF
:
6759 /* 16-bit unsigned immediate. */
6760 if (unsigned_overflow (value
, 16))
6761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6762 _("immediate out of range"));
6763 insn
= get_aarch64_insn (buf
);
6764 insn
|= encode_movw_imm (value
& 0xffff);
6765 put_aarch64_insn (buf
, insn
);
6768 case AARCH64_OPND_IMM_MOV
:
6769 /* Operand for a generic move immediate instruction, which is
6770 an alias instruction that generates a single MOVZ, MOVN or ORR
6771 instruction to loads a 32-bit/64-bit immediate value into general
6772 register. An assembler error shall result if the immediate cannot be
6773 created by a single one of these instructions. If there is a choice,
6774 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6775 and MOVZ or MOVN to ORR. */
6776 gas_assert (new_inst
!= NULL
);
6777 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6780 case AARCH64_OPND_ADDR_SIMM7
:
6781 case AARCH64_OPND_ADDR_SIMM9
:
6782 case AARCH64_OPND_ADDR_SIMM9_2
:
6783 case AARCH64_OPND_ADDR_UIMM12
:
6784 /* Immediate offset in an address. */
6785 insn
= get_aarch64_insn (buf
);
6787 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6788 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6789 || new_inst
->opcode
->operands
[2] == opnd
);
6791 /* Get the index of the address operand. */
6792 if (new_inst
->opcode
->operands
[1] == opnd
)
6793 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6796 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6799 /* Update the resolved offset value. */
6800 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6802 /* Encode/fix-up. */
6803 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6804 &new_inst
->value
, NULL
, NULL
))
6806 put_aarch64_insn (buf
, new_inst
->value
);
6809 else if (new_inst
->opcode
->iclass
== ldst_pos
6810 && try_to_encode_as_unscaled_ldst (new_inst
))
6812 put_aarch64_insn (buf
, new_inst
->value
);
6816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6817 _("immediate offset out of range"));
6822 as_fatal (_("unhandled operand code %d"), opnd
);
6826 /* Apply a fixup (fixP) to segment data, once it has been determined
6827 by our caller that we have all the info we need to fix it up.
6829 Parameter valP is the pointer to the value of the bits. */
6832 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6834 offsetT value
= *valP
;
6836 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6838 unsigned flags
= fixP
->fx_addnumber
;
6840 DEBUG_TRACE ("\n\n");
6841 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6842 DEBUG_TRACE ("Enter md_apply_fix");
6844 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6846 /* Note whether this will delete the relocation. */
6848 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6851 /* Process the relocations. */
6852 switch (fixP
->fx_r_type
)
6854 case BFD_RELOC_NONE
:
6855 /* This will need to go in the object file. */
6860 case BFD_RELOC_8_PCREL
:
6861 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6862 md_number_to_chars (buf
, value
, 1);
6866 case BFD_RELOC_16_PCREL
:
6867 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6868 md_number_to_chars (buf
, value
, 2);
6872 case BFD_RELOC_32_PCREL
:
6873 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6874 md_number_to_chars (buf
, value
, 4);
6878 case BFD_RELOC_64_PCREL
:
6879 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6880 md_number_to_chars (buf
, value
, 8);
6883 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6884 /* We claim that these fixups have been processed here, even if
6885 in fact we generate an error because we do not have a reloc
6886 for them, so tc_gen_reloc() will reject them. */
6888 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6891 _("undefined symbol %s used as an immediate value"),
6892 S_GET_NAME (fixP
->fx_addsy
));
6893 goto apply_fix_return
;
6895 fix_insn (fixP
, flags
, value
);
6898 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6899 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6903 _("pc-relative load offset not word aligned"));
6904 if (signed_overflow (value
, 21))
6905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6906 _("pc-relative load offset out of range"));
6907 insn
= get_aarch64_insn (buf
);
6908 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6909 put_aarch64_insn (buf
, insn
);
6913 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6914 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6916 if (signed_overflow (value
, 21))
6917 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6918 _("pc-relative address offset out of range"));
6919 insn
= get_aarch64_insn (buf
);
6920 insn
|= encode_adr_imm (value
);
6921 put_aarch64_insn (buf
, insn
);
6925 case BFD_RELOC_AARCH64_BRANCH19
:
6926 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6930 _("conditional branch target not word aligned"));
6931 if (signed_overflow (value
, 21))
6932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6933 _("conditional branch out of range"));
6934 insn
= get_aarch64_insn (buf
);
6935 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6936 put_aarch64_insn (buf
, insn
);
6940 case BFD_RELOC_AARCH64_TSTBR14
:
6941 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6945 _("conditional branch target not word aligned"));
6946 if (signed_overflow (value
, 16))
6947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6948 _("conditional branch out of range"));
6949 insn
= get_aarch64_insn (buf
);
6950 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6951 put_aarch64_insn (buf
, insn
);
6955 case BFD_RELOC_AARCH64_CALL26
:
6956 case BFD_RELOC_AARCH64_JUMP26
:
6957 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6961 _("branch target not word aligned"));
6962 if (signed_overflow (value
, 28))
6963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6964 _("branch out of range"));
6965 insn
= get_aarch64_insn (buf
);
6966 insn
|= encode_branch_ofs_26 (value
>> 2);
6967 put_aarch64_insn (buf
, insn
);
6971 case BFD_RELOC_AARCH64_MOVW_G0
:
6972 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6973 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6974 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6977 case BFD_RELOC_AARCH64_MOVW_G1
:
6978 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6979 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6980 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6983 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6985 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6986 /* Should always be exported to object file, see
6987 aarch64_force_relocation(). */
6988 gas_assert (!fixP
->fx_done
);
6989 gas_assert (seg
->use_rela_p
);
6991 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6993 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6994 /* Should always be exported to object file, see
6995 aarch64_force_relocation(). */
6996 gas_assert (!fixP
->fx_done
);
6997 gas_assert (seg
->use_rela_p
);
6999 case BFD_RELOC_AARCH64_MOVW_G2
:
7000 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7001 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7004 case BFD_RELOC_AARCH64_MOVW_G3
:
7007 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7009 insn
= get_aarch64_insn (buf
);
7013 /* REL signed addend must fit in 16 bits */
7014 if (signed_overflow (value
, 16))
7015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7016 _("offset out of range"));
7020 /* Check for overflow and scale. */
7021 switch (fixP
->fx_r_type
)
7023 case BFD_RELOC_AARCH64_MOVW_G0
:
7024 case BFD_RELOC_AARCH64_MOVW_G1
:
7025 case BFD_RELOC_AARCH64_MOVW_G2
:
7026 case BFD_RELOC_AARCH64_MOVW_G3
:
7027 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7028 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7029 if (unsigned_overflow (value
, scale
+ 16))
7030 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7031 _("unsigned value out of range"));
7033 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7034 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7035 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7036 /* NOTE: We can only come here with movz or movn. */
7037 if (signed_overflow (value
, scale
+ 16))
7038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7039 _("signed value out of range"));
7042 /* Force use of MOVN. */
7044 insn
= reencode_movzn_to_movn (insn
);
7048 /* Force use of MOVZ. */
7049 insn
= reencode_movzn_to_movz (insn
);
7053 /* Unchecked relocations. */
7059 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7060 insn
|= encode_movw_imm (value
& 0xffff);
7062 put_aarch64_insn (buf
, insn
);
7066 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7067 fixP
->fx_r_type
= (ilp32_p
7068 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7069 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7070 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7071 /* Should always be exported to object file, see
7072 aarch64_force_relocation(). */
7073 gas_assert (!fixP
->fx_done
);
7074 gas_assert (seg
->use_rela_p
);
7077 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7078 fixP
->fx_r_type
= (ilp32_p
7079 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7080 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7081 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7082 /* Should always be exported to object file, see
7083 aarch64_force_relocation(). */
7084 gas_assert (!fixP
->fx_done
);
7085 gas_assert (seg
->use_rela_p
);
7088 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7089 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7090 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7091 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7092 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7093 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7094 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7095 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7096 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7097 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7098 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7099 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7100 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7101 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7102 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7103 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7104 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7105 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7106 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7107 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7108 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7109 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7110 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7111 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7112 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7113 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7114 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7115 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7116 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7117 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7118 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7119 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7120 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7121 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7122 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7123 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7124 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7125 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7126 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7127 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7128 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7129 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7130 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7131 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7132 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7133 /* Should always be exported to object file, see
7134 aarch64_force_relocation(). */
7135 gas_assert (!fixP
->fx_done
);
7136 gas_assert (seg
->use_rela_p
);
7139 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7140 /* Should always be exported to object file, see
7141 aarch64_force_relocation(). */
7142 fixP
->fx_r_type
= (ilp32_p
7143 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7144 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7145 gas_assert (!fixP
->fx_done
);
7146 gas_assert (seg
->use_rela_p
);
7149 case BFD_RELOC_AARCH64_ADD_LO12
:
7150 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7151 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7152 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7153 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7154 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7155 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7156 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7157 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7158 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7159 case BFD_RELOC_AARCH64_LDST128_LO12
:
7160 case BFD_RELOC_AARCH64_LDST16_LO12
:
7161 case BFD_RELOC_AARCH64_LDST32_LO12
:
7162 case BFD_RELOC_AARCH64_LDST64_LO12
:
7163 case BFD_RELOC_AARCH64_LDST8_LO12
:
7164 /* Should always be exported to object file, see
7165 aarch64_force_relocation(). */
7166 gas_assert (!fixP
->fx_done
);
7167 gas_assert (seg
->use_rela_p
);
7170 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7171 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7172 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7175 case BFD_RELOC_UNUSED
:
7176 /* An error will already have been reported. */
7180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7181 _("unexpected %s fixup"),
7182 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7187 /* Free the allocated the struct aarch64_inst.
7188 N.B. currently there are very limited number of fix-up types actually use
7189 this field, so the impact on the performance should be minimal . */
7190 if (fixP
->tc_fix_data
.inst
!= NULL
)
7191 free (fixP
->tc_fix_data
.inst
);
7196 /* Translate internal representation of relocation info to BFD target
7200 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7203 bfd_reloc_code_real_type code
;
7205 reloc
= xmalloc (sizeof (arelent
));
7207 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
7208 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7209 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7213 if (section
->use_rela_p
)
7214 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7216 fixp
->fx_offset
= reloc
->address
;
7218 reloc
->addend
= fixp
->fx_offset
;
7220 code
= fixp
->fx_r_type
;
7225 code
= BFD_RELOC_16_PCREL
;
7230 code
= BFD_RELOC_32_PCREL
;
7235 code
= BFD_RELOC_64_PCREL
;
7242 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7243 if (reloc
->howto
== NULL
)
7245 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7247 ("cannot represent %s relocation in this object file format"),
7248 bfd_get_reloc_code_name (code
));
7255 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7258 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7260 bfd_reloc_code_real_type type
;
7264 FIXME: @@ Should look at CPU word size. */
7271 type
= BFD_RELOC_16
;
7274 type
= BFD_RELOC_32
;
7277 type
= BFD_RELOC_64
;
7280 as_bad (_("cannot do %u-byte relocation"), size
);
7281 type
= BFD_RELOC_UNUSED
;
7285 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7289 aarch64_force_relocation (struct fix
*fixp
)
7291 switch (fixp
->fx_r_type
)
7293 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7294 /* Perform these "immediate" internal relocations
7295 even if the symbol is extern or weak. */
7298 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7299 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7300 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7301 /* Pseudo relocs that need to be fixed up according to
7305 case BFD_RELOC_AARCH64_ADD_LO12
:
7306 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7307 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7308 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7309 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7310 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7311 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7312 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7313 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7314 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7315 case BFD_RELOC_AARCH64_LDST128_LO12
:
7316 case BFD_RELOC_AARCH64_LDST16_LO12
:
7317 case BFD_RELOC_AARCH64_LDST32_LO12
:
7318 case BFD_RELOC_AARCH64_LDST64_LO12
:
7319 case BFD_RELOC_AARCH64_LDST8_LO12
:
7320 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7321 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7322 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7323 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7324 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7325 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7326 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7327 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7328 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7329 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7330 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7331 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7332 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7333 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7334 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7335 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7336 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7337 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7338 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7339 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7340 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7341 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7342 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7343 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7344 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7345 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7346 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7347 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7348 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7349 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7350 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7351 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7352 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7353 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7354 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7355 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7356 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7357 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7358 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7359 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7360 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7361 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7362 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7363 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7364 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7365 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7366 /* Always leave these relocations for the linker. */
7373 return generic_force_reloc (fixp
);
7379 elf64_aarch64_target_format (void)
7381 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7383 /* FIXME: What to do for ilp32_p ? */
7384 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7386 if (target_big_endian
)
7387 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7389 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7393 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7395 elf_frob_symbol (symp
, puntp
);
7399 /* MD interface: Finalization. */
7401 /* A good place to do this, although this was probably not intended
7402 for this kind of use. We need to dump the literal pool before
7403 references are made to a null symbol pointer. */
7406 aarch64_cleanup (void)
7410 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7412 /* Put it at the end of the relevant section. */
7413 subseg_set (pool
->section
, pool
->sub_section
);
7419 /* Remove any excess mapping symbols generated for alignment frags in
7420 SEC. We may have created a mapping symbol before a zero byte
7421 alignment; remove it if there's a mapping symbol after the
7424 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7425 void *dummy ATTRIBUTE_UNUSED
)
7427 segment_info_type
*seginfo
= seg_info (sec
);
7430 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7433 for (fragp
= seginfo
->frchainP
->frch_root
;
7434 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7436 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7437 fragS
*next
= fragp
->fr_next
;
7439 /* Variable-sized frags have been converted to fixed size by
7440 this point. But if this was variable-sized to start with,
7441 there will be a fixed-size frag after it. So don't handle
7443 if (sym
== NULL
|| next
== NULL
)
7446 if (S_GET_VALUE (sym
) < next
->fr_address
)
7447 /* Not at the end of this frag. */
7449 know (S_GET_VALUE (sym
) == next
->fr_address
);
7453 if (next
->tc_frag_data
.first_map
!= NULL
)
7455 /* Next frag starts with a mapping symbol. Discard this
7457 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7461 if (next
->fr_next
== NULL
)
7463 /* This mapping symbol is at the end of the section. Discard
7465 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7466 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7470 /* As long as we have empty frags without any mapping symbols,
7472 /* If the next frag is non-empty and does not start with a
7473 mapping symbol, then this mapping symbol is required. */
7474 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7477 next
= next
->fr_next
;
7479 while (next
!= NULL
);
7484 /* Adjust the symbol table. */
7487 aarch64_adjust_symtab (void)
7490 /* Remove any overlapping mapping symbols generated by alignment frags. */
7491 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7492 /* Now do generic ELF adjustments. */
7493 elf_adjust_symtab ();
7498 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7500 const char *hash_err
;
7502 hash_err
= hash_insert (table
, key
, value
);
7504 printf ("Internal Error: Can't hash %s\n", key
);
7508 fill_instruction_hash_table (void)
7510 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7512 while (opcode
->name
!= NULL
)
7514 templates
*templ
, *new_templ
;
7515 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7517 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7518 new_templ
->opcode
= opcode
;
7519 new_templ
->next
= NULL
;
7522 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7525 new_templ
->next
= templ
->next
;
7526 templ
->next
= new_templ
;
7533 convert_to_upper (char *dst
, const char *src
, size_t num
)
7536 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7537 *dst
= TOUPPER (*src
);
7541 /* Assume STR point to a lower-case string, allocate, convert and return
7542 the corresponding upper-case string. */
7543 static inline const char*
7544 get_upper_str (const char *str
)
7547 size_t len
= strlen (str
);
7548 if ((ret
= xmalloc (len
+ 1)) == NULL
)
7550 convert_to_upper (ret
, str
, len
);
7554 /* MD interface: Initialization. */
7562 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7563 || (aarch64_cond_hsh
= hash_new ()) == NULL
7564 || (aarch64_shift_hsh
= hash_new ()) == NULL
7565 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7566 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7567 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7568 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7569 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7570 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7571 || (aarch64_reg_hsh
= hash_new ()) == NULL
7572 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7573 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7574 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7575 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7576 as_fatal (_("virtual memory exhausted"));
7578 fill_instruction_hash_table ();
7580 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7581 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7582 (void *) (aarch64_sys_regs
+ i
));
7584 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7585 checked_hash_insert (aarch64_pstatefield_hsh
,
7586 aarch64_pstatefields
[i
].name
,
7587 (void *) (aarch64_pstatefields
+ i
));
7589 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7590 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7591 aarch64_sys_regs_ic
[i
].name
,
7592 (void *) (aarch64_sys_regs_ic
+ i
));
7594 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7595 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7596 aarch64_sys_regs_dc
[i
].name
,
7597 (void *) (aarch64_sys_regs_dc
+ i
));
7599 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7600 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7601 aarch64_sys_regs_at
[i
].name
,
7602 (void *) (aarch64_sys_regs_at
+ i
));
7604 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7605 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7606 aarch64_sys_regs_tlbi
[i
].name
,
7607 (void *) (aarch64_sys_regs_tlbi
+ i
));
7609 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7610 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7611 (void *) (reg_names
+ i
));
7613 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7614 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7615 (void *) (nzcv_names
+ i
));
7617 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7619 const char *name
= aarch64_operand_modifiers
[i
].name
;
7620 checked_hash_insert (aarch64_shift_hsh
, name
,
7621 (void *) (aarch64_operand_modifiers
+ i
));
7622 /* Also hash the name in the upper case. */
7623 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7624 (void *) (aarch64_operand_modifiers
+ i
));
7627 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7630 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7631 the same condition code. */
7632 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7634 const char *name
= aarch64_conds
[i
].names
[j
];
7637 checked_hash_insert (aarch64_cond_hsh
, name
,
7638 (void *) (aarch64_conds
+ i
));
7639 /* Also hash the name in the upper case. */
7640 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7641 (void *) (aarch64_conds
+ i
));
7645 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7647 const char *name
= aarch64_barrier_options
[i
].name
;
7648 /* Skip xx00 - the unallocated values of option. */
7651 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7652 (void *) (aarch64_barrier_options
+ i
));
7653 /* Also hash the name in the upper case. */
7654 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7655 (void *) (aarch64_barrier_options
+ i
));
7658 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7660 const char* name
= aarch64_prfops
[i
].name
;
7661 /* Skip the unallocated hint encodings. */
7664 checked_hash_insert (aarch64_pldop_hsh
, name
,
7665 (void *) (aarch64_prfops
+ i
));
7666 /* Also hash the name in the upper case. */
7667 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7668 (void *) (aarch64_prfops
+ i
));
7671 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7673 const char* name
= aarch64_hint_options
[i
].name
;
7675 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7676 (void *) (aarch64_hint_options
+ i
));
7677 /* Also hash the name in the upper case. */
7678 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7679 (void *) (aarch64_hint_options
+ i
));
7682 /* Set the cpu variant based on the command-line options. */
7684 mcpu_cpu_opt
= march_cpu_opt
;
7687 mcpu_cpu_opt
= &cpu_default
;
7689 cpu_variant
= *mcpu_cpu_opt
;
7691 /* Record the CPU type. */
7692 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7694 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7697 /* Command line processing. */
7699 const char *md_shortopts
= "m:";
7701 #ifdef AARCH64_BI_ENDIAN
7702 #define OPTION_EB (OPTION_MD_BASE + 0)
7703 #define OPTION_EL (OPTION_MD_BASE + 1)
7705 #if TARGET_BYTES_BIG_ENDIAN
7706 #define OPTION_EB (OPTION_MD_BASE + 0)
7708 #define OPTION_EL (OPTION_MD_BASE + 1)
7712 struct option md_longopts
[] = {
7714 {"EB", no_argument
, NULL
, OPTION_EB
},
7717 {"EL", no_argument
, NULL
, OPTION_EL
},
7719 {NULL
, no_argument
, NULL
, 0}
7722 size_t md_longopts_size
= sizeof (md_longopts
);
7724 struct aarch64_option_table
7726 char *option
; /* Option name to match. */
7727 char *help
; /* Help information. */
7728 int *var
; /* Variable to change. */
7729 int value
; /* What to change it to. */
7730 char *deprecated
; /* If non-null, print this message. */
7733 static struct aarch64_option_table aarch64_opts
[] = {
7734 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7735 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7737 #ifdef DEBUG_AARCH64
7738 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7739 #endif /* DEBUG_AARCH64 */
7740 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7742 {"mno-verbose-error", N_("do not output verbose error messages"),
7743 &verbose_error_p
, 0, NULL
},
7744 {NULL
, NULL
, NULL
, 0, NULL
}
7747 struct aarch64_cpu_option_table
7750 const aarch64_feature_set value
;
7751 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7753 const char *canonical_name
;
7756 /* This list should, at a minimum, contain all the cpu names
7757 recognized by GCC. */
7758 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7759 {"all", AARCH64_ANY
, NULL
},
7760 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7761 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7762 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7763 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7764 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7765 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7766 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7767 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7768 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7769 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7770 "Samsung Exynos M1"},
7771 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7772 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7773 "Qualcomm QDF24XX"},
7774 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7775 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7777 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7778 in earlier releases and is superseded by 'xgene1' in all
7780 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7781 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7782 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7783 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7784 {"generic", AARCH64_ARCH_V8
, NULL
},
7786 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7789 struct aarch64_arch_option_table
7792 const aarch64_feature_set value
;
7795 /* This list should, at a minimum, contain all the architecture names
7796 recognized by GCC. */
7797 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7798 {"all", AARCH64_ANY
},
7799 {"armv8-a", AARCH64_ARCH_V8
},
7800 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7801 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7802 {NULL
, AARCH64_ARCH_NONE
}
7805 /* ISA extensions. */
7806 struct aarch64_option_cpu_value_table
7809 const aarch64_feature_set value
;
7812 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7813 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7814 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7815 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7816 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7817 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7818 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7819 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7820 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7821 | AARCH64_FEATURE_RDMA
, 0)},
7822 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7823 | AARCH64_FEATURE_FP
, 0)},
7824 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0)},
7825 {NULL
, AARCH64_ARCH_NONE
}
7828 struct aarch64_long_option_table
7830 char *option
; /* Substring to match. */
7831 char *help
; /* Help information. */
7832 int (*func
) (char *subopt
); /* Function to decode sub-option. */
7833 char *deprecated
; /* If non-null, print this message. */
7837 aarch64_parse_features (char *str
, const aarch64_feature_set
**opt_p
,
7838 bfd_boolean ext_only
)
7840 /* We insist on extensions being added before being removed. We achieve
7841 this by using the ADDING_VALUE variable to indicate whether we are
7842 adding an extension (1) or removing it (0) and only allowing it to
7843 change in the order -1 -> 1 -> 0. */
7844 int adding_value
= -1;
7845 aarch64_feature_set
*ext_set
= xmalloc (sizeof (aarch64_feature_set
));
7847 /* Copy the feature set, so that we can modify it. */
7851 while (str
!= NULL
&& *str
!= 0)
7853 const struct aarch64_option_cpu_value_table
*opt
;
7861 as_bad (_("invalid architectural extension"));
7865 ext
= strchr (++str
, '+');
7871 optlen
= strlen (str
);
7873 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7875 if (adding_value
!= 0)
7880 else if (optlen
> 0)
7882 if (adding_value
== -1)
7884 else if (adding_value
!= 1)
7886 as_bad (_("must specify extensions to add before specifying "
7887 "those to remove"));
7894 as_bad (_("missing architectural extension"));
7898 gas_assert (adding_value
!= -1);
7900 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7901 if (strncmp (opt
->name
, str
, optlen
) == 0)
7903 /* Add or remove the extension. */
7905 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7907 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7911 if (opt
->name
== NULL
)
7913 as_bad (_("unknown architectural extension `%s'"), str
);
7924 aarch64_parse_cpu (char *str
)
7926 const struct aarch64_cpu_option_table
*opt
;
7927 char *ext
= strchr (str
, '+');
7933 optlen
= strlen (str
);
7937 as_bad (_("missing cpu name `%s'"), str
);
7941 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7942 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7944 mcpu_cpu_opt
= &opt
->value
;
7946 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7951 as_bad (_("unknown cpu `%s'"), str
);
7956 aarch64_parse_arch (char *str
)
7958 const struct aarch64_arch_option_table
*opt
;
7959 char *ext
= strchr (str
, '+');
7965 optlen
= strlen (str
);
7969 as_bad (_("missing architecture name `%s'"), str
);
7973 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7974 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7976 march_cpu_opt
= &opt
->value
;
7978 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7983 as_bad (_("unknown architecture `%s'\n"), str
);
7988 struct aarch64_option_abi_value_table
7991 enum aarch64_abi_type value
;
7994 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7995 {"ilp32", AARCH64_ABI_ILP32
},
7996 {"lp64", AARCH64_ABI_LP64
},
8001 aarch64_parse_abi (char *str
)
8003 const struct aarch64_option_abi_value_table
*opt
;
8004 size_t optlen
= strlen (str
);
8008 as_bad (_("missing abi name `%s'"), str
);
8012 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
8013 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8015 aarch64_abi
= opt
->value
;
8019 as_bad (_("unknown abi `%s'\n"), str
);
8023 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8025 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8026 aarch64_parse_abi
, NULL
},
8027 #endif /* OBJ_ELF */
8028 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8029 aarch64_parse_cpu
, NULL
},
8030 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8031 aarch64_parse_arch
, NULL
},
8032 {NULL
, NULL
, 0, NULL
}
8036 md_parse_option (int c
, char *arg
)
8038 struct aarch64_option_table
*opt
;
8039 struct aarch64_long_option_table
*lopt
;
8045 target_big_endian
= 1;
8051 target_big_endian
= 0;
8056 /* Listing option. Just ignore these, we don't support additional
8061 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8063 if (c
== opt
->option
[0]
8064 && ((arg
== NULL
&& opt
->option
[1] == 0)
8065 || streq (arg
, opt
->option
+ 1)))
8067 /* If the option is deprecated, tell the user. */
8068 if (opt
->deprecated
!= NULL
)
8069 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8070 arg
? arg
: "", _(opt
->deprecated
));
8072 if (opt
->var
!= NULL
)
8073 *opt
->var
= opt
->value
;
8079 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8081 /* These options are expected to have an argument. */
8082 if (c
== lopt
->option
[0]
8084 && strncmp (arg
, lopt
->option
+ 1,
8085 strlen (lopt
->option
+ 1)) == 0)
8087 /* If the option is deprecated, tell the user. */
8088 if (lopt
->deprecated
!= NULL
)
8089 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8090 _(lopt
->deprecated
));
8092 /* Call the sup-option parser. */
8093 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8104 md_show_usage (FILE * fp
)
8106 struct aarch64_option_table
*opt
;
8107 struct aarch64_long_option_table
*lopt
;
8109 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8111 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8112 if (opt
->help
!= NULL
)
8113 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8115 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8116 if (lopt
->help
!= NULL
)
8117 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8121 -EB assemble code for a big-endian cpu\n"));
8126 -EL assemble code for a little-endian cpu\n"));
8130 /* Parse a .cpu directive. */
8133 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8135 const struct aarch64_cpu_option_table
*opt
;
8141 name
= input_line_pointer
;
8142 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8143 input_line_pointer
++;
8144 saved_char
= *input_line_pointer
;
8145 *input_line_pointer
= 0;
8147 ext
= strchr (name
, '+');
8150 optlen
= ext
- name
;
8152 optlen
= strlen (name
);
8154 /* Skip the first "all" entry. */
8155 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8156 if (strlen (opt
->name
) == optlen
8157 && strncmp (name
, opt
->name
, optlen
) == 0)
8159 mcpu_cpu_opt
= &opt
->value
;
8161 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8164 cpu_variant
= *mcpu_cpu_opt
;
8166 *input_line_pointer
= saved_char
;
8167 demand_empty_rest_of_line ();
8170 as_bad (_("unknown cpu `%s'"), name
);
8171 *input_line_pointer
= saved_char
;
8172 ignore_rest_of_line ();
8176 /* Parse a .arch directive. */
8179 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8181 const struct aarch64_arch_option_table
*opt
;
8187 name
= input_line_pointer
;
8188 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8189 input_line_pointer
++;
8190 saved_char
= *input_line_pointer
;
8191 *input_line_pointer
= 0;
8193 ext
= strchr (name
, '+');
8196 optlen
= ext
- name
;
8198 optlen
= strlen (name
);
8200 /* Skip the first "all" entry. */
8201 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8202 if (strlen (opt
->name
) == optlen
8203 && strncmp (name
, opt
->name
, optlen
) == 0)
8205 mcpu_cpu_opt
= &opt
->value
;
8207 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8210 cpu_variant
= *mcpu_cpu_opt
;
8212 *input_line_pointer
= saved_char
;
8213 demand_empty_rest_of_line ();
8217 as_bad (_("unknown architecture `%s'\n"), name
);
8218 *input_line_pointer
= saved_char
;
8219 ignore_rest_of_line ();
8222 /* Parse a .arch_extension directive. */
8225 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8228 char *ext
= input_line_pointer
;;
8230 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8231 input_line_pointer
++;
8232 saved_char
= *input_line_pointer
;
8233 *input_line_pointer
= 0;
8235 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8238 cpu_variant
= *mcpu_cpu_opt
;
8240 *input_line_pointer
= saved_char
;
8241 demand_empty_rest_of_line ();
8244 /* Copy symbol information. */
8247 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8249 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);