1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
59 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
60 static symbolS
*GOT_symbol
;
62 /* Which ABI to use. */
69 /* AArch64 ABI for the output file. */
70 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_LP64
;
72 /* When non-zero, program to a 32-bit model, in which the C data types
73 int, long and all pointer types are 32-bit objects (ILP32); or to a
74 64-bit model, in which the C int type is 32-bits but the C long type
75 and all pointer types are 64-bit objects (LP64). */
76 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
89 /* Bits for DEFINED field in neon_type_el. */
91 #define NTA_HASINDEX 2
95 enum neon_el_type type
;
96 unsigned char defined
;
101 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
105 bfd_reloc_code_real_type type
;
108 enum aarch64_opnd opnd
;
110 unsigned need_libopcodes_p
: 1;
113 struct aarch64_instruction
115 /* libopcodes structure for instruction intermediate representation. */
117 /* Record assembly errors found during the parsing. */
120 enum aarch64_operand_error_kind kind
;
123 /* The condition that appears in the assembly line. */
125 /* Relocation information (including the GAS internal fixup). */
127 /* Need to generate an immediate in the literal pool. */
128 unsigned gen_lit_pool
: 1;
131 typedef struct aarch64_instruction aarch64_instruction
;
133 static aarch64_instruction inst
;
135 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
136 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
138 /* Diagnostics inline function utilites.
140 These are lightweight utlities which should only be called by parse_operands
141 and other parsers. GAS processes each assembly line by parsing it against
142 instruction template(s), in the case of multiple templates (for the same
143 mnemonic name), those templates are tried one by one until one succeeds or
144 all fail. An assembly line may fail a few templates before being
145 successfully parsed; an error saved here in most cases is not a user error
146 but an error indicating the current template is not the right template.
147 Therefore it is very important that errors can be saved at a low cost during
148 the parsing; we don't want to slow down the whole parsing by recording
149 non-user errors in detail.
151 Remember that the objective is to help GAS pick up the most approapriate
152 error message in the case of multiple templates, e.g. FMOV which has 8
158 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
159 inst
.parsing_error
.error
= NULL
;
162 static inline bfd_boolean
165 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
168 static inline const char *
169 get_error_message (void)
171 return inst
.parsing_error
.error
;
174 static inline enum aarch64_operand_error_kind
175 get_error_kind (void)
177 return inst
.parsing_error
.kind
;
181 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
183 inst
.parsing_error
.kind
= kind
;
184 inst
.parsing_error
.error
= error
;
188 set_recoverable_error (const char *error
)
190 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
193 /* Use the DESC field of the corresponding aarch64_operand entry to compose
194 the error message. */
196 set_default_error (void)
198 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
202 set_syntax_error (const char *error
)
204 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
208 set_first_syntax_error (const char *error
)
211 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
215 set_fatal_syntax_error (const char *error
)
217 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
220 /* Number of littlenums required to hold an extended precision number. */
221 #define MAX_LITTLENUMS 6
223 /* Return value for certain parsers when the parsing fails; those parsers
224 return the information of the parsed result, e.g. register number, on
226 #define PARSE_FAIL -1
228 /* This is an invalid condition code that means no conditional field is
230 #define COND_ALWAYS 0x10
234 const char *template;
240 const char *template;
247 bfd_reloc_code_real_type reloc
;
250 /* Structure for a hash table entry for a register. */
254 unsigned char number
;
256 unsigned char builtin
;
259 /* Macros to define the register types and masks for the purpose
262 #undef AARCH64_REG_TYPES
263 #define AARCH64_REG_TYPES \
264 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
265 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
266 BASIC_REG_TYPE(SP_32) /* wsp */ \
267 BASIC_REG_TYPE(SP_64) /* sp */ \
268 BASIC_REG_TYPE(Z_32) /* wzr */ \
269 BASIC_REG_TYPE(Z_64) /* xzr */ \
270 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
271 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
272 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
273 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
274 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
275 BASIC_REG_TYPE(CN) /* c[0-7] */ \
276 BASIC_REG_TYPE(VN) /* v[0-31] */ \
277 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
278 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
279 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
280 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
281 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
282 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
283 /* Typecheck: any [BHSDQ]P FP. */ \
284 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
285 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
286 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
287 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
288 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
289 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
290 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
291 /* Any integer register; used for error messages only. */ \
292 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
293 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
294 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
295 /* Pseudo type to mark the end of the enumerator sequence. */ \
298 #undef BASIC_REG_TYPE
299 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
300 #undef MULTI_REG_TYPE
301 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
303 /* Register type enumerators. */
306 /* A list of REG_TYPE_*. */
310 #undef BASIC_REG_TYPE
311 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
313 #define REG_TYPE(T) (1 << REG_TYPE_##T)
314 #undef MULTI_REG_TYPE
315 #define MULTI_REG_TYPE(T,V) V,
317 /* Values indexed by aarch64_reg_type to assist the type checking. */
318 static const unsigned reg_type_masks
[] =
323 #undef BASIC_REG_TYPE
325 #undef MULTI_REG_TYPE
326 #undef AARCH64_REG_TYPES
328 /* Diagnostics used when we don't get a register of the expected type.
329 Note: this has to synchronized with aarch64_reg_type definitions
332 get_reg_expected_msg (aarch64_reg_type reg_type
)
339 msg
= N_("integer 32-bit register expected");
342 msg
= N_("integer 64-bit register expected");
345 msg
= N_("integer register expected");
347 case REG_TYPE_R_Z_SP
:
348 msg
= N_("integer, zero or SP register expected");
351 msg
= N_("8-bit SIMD scalar register expected");
354 msg
= N_("16-bit SIMD scalar or floating-point half precision "
355 "register expected");
358 msg
= N_("32-bit SIMD scalar or floating-point single precision "
359 "register expected");
362 msg
= N_("64-bit SIMD scalar or floating-point double precision "
363 "register expected");
366 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
367 "register expected");
370 msg
= N_("C0 - C15 expected");
372 case REG_TYPE_R_Z_BHSDQ_V
:
373 msg
= N_("register expected");
375 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
376 msg
= N_("SIMD scalar or floating-point register expected");
378 case REG_TYPE_VN
: /* any V reg */
379 msg
= N_("vector register expected");
382 as_fatal (_("invalid register type %d"), reg_type
);
387 /* Some well known registers that we refer to directly elsewhere. */
390 /* Instructions take 4 bytes in the object file. */
393 /* Define some common error messages. */
394 #define BAD_SP _("SP not allowed here")
396 static struct hash_control
*aarch64_ops_hsh
;
397 static struct hash_control
*aarch64_cond_hsh
;
398 static struct hash_control
*aarch64_shift_hsh
;
399 static struct hash_control
*aarch64_sys_regs_hsh
;
400 static struct hash_control
*aarch64_pstatefield_hsh
;
401 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
402 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
403 static struct hash_control
*aarch64_sys_regs_at_hsh
;
404 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
405 static struct hash_control
*aarch64_reg_hsh
;
406 static struct hash_control
*aarch64_barrier_opt_hsh
;
407 static struct hash_control
*aarch64_nzcv_hsh
;
408 static struct hash_control
*aarch64_pldop_hsh
;
409 static struct hash_control
*aarch64_hint_opt_hsh
;
411 /* Stuff needed to resolve the label ambiguity
420 static symbolS
*last_label_seen
;
422 /* Literal pool structure. Held on a per-section
423 and per-sub-section basis. */
425 #define MAX_LITERAL_POOL_SIZE 1024
426 typedef struct literal_expression
429 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
430 LITTLENUM_TYPE
* bignum
;
431 } literal_expression
;
433 typedef struct literal_pool
435 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
436 unsigned int next_free_entry
;
442 struct literal_pool
*next
;
445 /* Pointer to a linked list of literal pools. */
446 static literal_pool
*list_of_pools
= NULL
;
450 /* This array holds the chars that always start a comment. If the
451 pre-processor is disabled, these aren't very useful. */
452 const char comment_chars
[] = "";
454 /* This array holds the chars that only start a comment at the beginning of
455 a line. If the line seems to have the form '# 123 filename'
456 .line and .file directives will appear in the pre-processed output. */
457 /* Note that input_file.c hand checks for '#' at the beginning of the
458 first line of the input file. This is because the compiler outputs
459 #NO_APP at the beginning of its output. */
460 /* Also note that comments like this one will always work. */
461 const char line_comment_chars
[] = "#";
463 const char line_separator_chars
[] = ";";
465 /* Chars that can be used to separate mant
466 from exp in floating point numbers. */
467 const char EXP_CHARS
[] = "eE";
469 /* Chars that mean this number is a floating point constant. */
473 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
475 /* Prefix character that indicates the start of an immediate value. */
476 #define is_immediate_prefix(C) ((C) == '#')
478 /* Separator character handling. */
480 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
482 static inline bfd_boolean
483 skip_past_char (char **str
, char c
)
494 #define skip_past_comma(str) skip_past_char (str, ',')
496 /* Arithmetic expressions (possibly involving symbols). */
498 static bfd_boolean in_my_get_expression_p
= FALSE
;
500 /* Third argument to my_get_expression. */
501 #define GE_NO_PREFIX 0
502 #define GE_OPT_PREFIX 1
504 /* Return TRUE if the string pointed by *STR is successfully parsed
505 as an valid expression; *EP will be filled with the information of
506 such an expression. Otherwise return FALSE. */
509 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
514 int prefix_present_p
= 0;
521 if (is_immediate_prefix (**str
))
524 prefix_present_p
= 1;
531 memset (ep
, 0, sizeof (expressionS
));
533 save_in
= input_line_pointer
;
534 input_line_pointer
= *str
;
535 in_my_get_expression_p
= TRUE
;
536 seg
= expression (ep
);
537 in_my_get_expression_p
= FALSE
;
539 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
541 /* We found a bad expression in md_operand(). */
542 *str
= input_line_pointer
;
543 input_line_pointer
= save_in
;
544 if (prefix_present_p
&& ! error_p ())
545 set_fatal_syntax_error (_("bad expression"));
547 set_first_syntax_error (_("bad expression"));
552 if (seg
!= absolute_section
553 && seg
!= text_section
554 && seg
!= data_section
555 && seg
!= bss_section
&& seg
!= undefined_section
)
557 set_syntax_error (_("bad segment"));
558 *str
= input_line_pointer
;
559 input_line_pointer
= save_in
;
566 *str
= input_line_pointer
;
567 input_line_pointer
= save_in
;
571 /* Turn a string in input_line_pointer into a floating point constant
572 of type TYPE, and store the appropriate bytes in *LITP. The number
573 of LITTLENUMS emitted is stored in *SIZEP. An error message is
574 returned, or NULL on OK. */
577 md_atof (int type
, char *litP
, int *sizeP
)
579 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
582 /* We handle all bad expressions here, so that we can report the faulty
583 instruction in the error message. */
585 md_operand (expressionS
* exp
)
587 if (in_my_get_expression_p
)
588 exp
->X_op
= O_illegal
;
591 /* Immediate values. */
593 /* Errors may be set multiple times during parsing or bit encoding
594 (particularly in the Neon bits), but usually the earliest error which is set
595 will be the most meaningful. Avoid overwriting it with later (cascading)
596 errors by calling this function. */
599 first_error (const char *error
)
602 set_syntax_error (error
);
605 /* Similiar to first_error, but this function accepts formatted error
608 first_error_fmt (const char *format
, ...)
613 /* N.B. this single buffer will not cause error messages for different
614 instructions to pollute each other; this is because at the end of
615 processing of each assembly line, error message if any will be
616 collected by as_bad. */
617 static char buffer
[size
];
621 int ret ATTRIBUTE_UNUSED
;
622 va_start (args
, format
);
623 ret
= vsnprintf (buffer
, size
, format
, args
);
624 know (ret
<= size
- 1 && ret
>= 0);
626 set_syntax_error (buffer
);
630 /* Register parsing. */
632 /* Generic register parser which is called by other specialized
634 CCP points to what should be the beginning of a register name.
635 If it is indeed a valid register name, advance CCP over it and
636 return the reg_entry structure; otherwise return NULL.
637 It does not issue diagnostics. */
640 parse_reg (char **ccp
)
646 #ifdef REGISTER_PREFIX
647 if (*start
!= REGISTER_PREFIX
)
653 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
658 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
660 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
669 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
672 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
674 if (reg
->type
== type
)
679 case REG_TYPE_R64_SP
: /* 64-bit integer reg (inc SP exc XZR). */
680 case REG_TYPE_R_Z_SP
: /* Integer reg (inc {X}SP inc [WX]ZR). */
681 case REG_TYPE_R_Z_BHSDQ_V
: /* Any register apart from Cn. */
682 case REG_TYPE_BHSDQ
: /* Any [BHSDQ]P FP or SIMD scalar register. */
683 case REG_TYPE_VN
: /* Vector register. */
684 gas_assert (reg
->type
< REG_TYPE_MAX
&& type
< REG_TYPE_MAX
);
685 return ((reg_type_masks
[reg
->type
] & reg_type_masks
[type
])
686 == reg_type_masks
[reg
->type
]);
688 as_fatal ("unhandled type %d", type
);
693 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
694 Return the register number otherwise. *ISREG32 is set to one if the
695 register is 32-bit wide; *ISREGZERO is set to one if the register is
696 of type Z_32 or Z_64.
697 Note that this function does not issue any diagnostics. */
700 aarch64_reg_parse_32_64 (char **ccp
, int reject_sp
, int reject_rz
,
701 int *isreg32
, int *isregzero
)
704 const reg_entry
*reg
= parse_reg (&str
);
709 if (! aarch64_check_reg_type (reg
, REG_TYPE_R_Z_SP
))
718 *isreg32
= reg
->type
== REG_TYPE_SP_32
;
723 *isreg32
= reg
->type
== REG_TYPE_R_32
;
730 *isreg32
= reg
->type
== REG_TYPE_Z_32
;
742 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
743 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
744 otherwise return FALSE.
746 Accept only one occurrence of:
747 8b 16b 2h 4h 8h 2s 4s 1d 2d
750 parse_neon_type_for_operand (struct neon_type_el
*parsed_type
, char **str
)
754 unsigned element_size
;
755 enum neon_el_type type
;
765 width
= strtoul (ptr
, &ptr
, 10);
766 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
768 first_error_fmt (_("bad size %d in vector width specifier"), width
);
773 switch (TOLOWER (*ptr
))
801 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
803 first_error (_("missing element size"));
806 if (width
!= 0 && width
* element_size
!= 64 && width
* element_size
!= 128
807 && !(width
== 2 && element_size
== 16))
810 ("invalid element size %d and vector size combination %c"),
816 parsed_type
->type
= type
;
817 parsed_type
->width
= width
;
824 /* Parse a single type, e.g. ".8b", leading period included.
825 Only applicable to Vn registers.
827 Return TRUE on success; otherwise return FALSE. */
829 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
835 if (! parse_neon_type_for_operand (vectype
, &str
))
837 first_error (_("vector type expected"));
849 /* Parse a register of the type TYPE.
851 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
852 name or the parsed register is not of TYPE.
854 Otherwise return the register number, and optionally fill in the actual
855 type of the register in *RTYPE when multiple alternatives were given, and
856 return the register shape and element index information in *TYPEINFO.
858 IN_REG_LIST should be set with TRUE if the caller is parsing a register
862 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
863 struct neon_type_el
*typeinfo
, bfd_boolean in_reg_list
)
866 const reg_entry
*reg
= parse_reg (&str
);
867 struct neon_type_el atype
;
868 struct neon_type_el parsetype
;
869 bfd_boolean is_typed_vecreg
= FALSE
;
872 atype
.type
= NT_invtype
;
880 set_default_error ();
884 if (! aarch64_check_reg_type (reg
, type
))
886 DEBUG_TRACE ("reg type check failed");
887 set_default_error ();
892 if (type
== REG_TYPE_VN
893 && parse_neon_operand_type (&parsetype
, &str
))
895 /* Register if of the form Vn.[bhsdq]. */
896 is_typed_vecreg
= TRUE
;
898 if (parsetype
.width
== 0)
899 /* Expect index. In the new scheme we cannot have
900 Vn.[bhsdq] represent a scalar. Therefore any
901 Vn.[bhsdq] should have an index following it.
902 Except in reglists ofcourse. */
903 atype
.defined
|= NTA_HASINDEX
;
905 atype
.defined
|= NTA_HASTYPE
;
907 atype
.type
= parsetype
.type
;
908 atype
.width
= parsetype
.width
;
911 if (skip_past_char (&str
, '['))
915 /* Reject Sn[index] syntax. */
916 if (!is_typed_vecreg
)
918 first_error (_("this type of register can't be indexed"));
922 if (in_reg_list
== TRUE
)
924 first_error (_("index not allowed inside register list"));
928 atype
.defined
|= NTA_HASINDEX
;
930 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
932 if (exp
.X_op
!= O_constant
)
934 first_error (_("constant expression required"));
938 if (! skip_past_char (&str
, ']'))
941 atype
.index
= exp
.X_add_number
;
943 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
945 /* Indexed vector register expected. */
946 first_error (_("indexed vector register expected"));
950 /* A vector reg Vn should be typed or indexed. */
951 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
953 first_error (_("invalid use of vector register"));
969 Return the register number on success; return PARSE_FAIL otherwise.
971 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
972 the register (e.g. NEON double or quad reg when either has been requested).
974 If this is a NEON vector register with additional type information, fill
975 in the struct pointed to by VECTYPE (if non-NULL).
977 This parser does not handle register list. */
980 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
981 aarch64_reg_type
*rtype
, struct neon_type_el
*vectype
)
983 struct neon_type_el atype
;
985 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
986 /*in_reg_list= */ FALSE
);
988 if (reg
== PARSE_FAIL
)
999 static inline bfd_boolean
1000 eq_neon_type_el (struct neon_type_el e1
, struct neon_type_el e2
)
1004 && e1
.defined
== e2
.defined
1005 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1008 /* This function parses the NEON register list. On success, it returns
1009 the parsed register list information in the following encoded format:
1011 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1012 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1014 The information of the register shape and/or index is returned in
1017 It returns PARSE_FAIL if the register list is invalid.
1019 The list contains one to four registers.
1020 Each register can be one of:
1023 All <T> should be identical.
1024 All <index> should be identical.
1025 There are restrictions on <Vt> numbers which are checked later
1026 (by reg_list_valid_p). */
1029 parse_neon_reg_list (char **ccp
, struct neon_type_el
*vectype
)
1033 struct neon_type_el typeinfo
, typeinfo_first
;
1038 bfd_boolean error
= FALSE
;
1039 bfd_boolean expect_index
= FALSE
;
1043 set_syntax_error (_("expecting {"));
1049 typeinfo_first
.defined
= 0;
1050 typeinfo_first
.type
= NT_invtype
;
1051 typeinfo_first
.width
= -1;
1052 typeinfo_first
.index
= 0;
1061 str
++; /* skip over '-' */
1064 val
= parse_typed_reg (&str
, REG_TYPE_VN
, NULL
, &typeinfo
,
1065 /*in_reg_list= */ TRUE
);
1066 if (val
== PARSE_FAIL
)
1068 set_first_syntax_error (_("invalid vector register in list"));
1072 /* reject [bhsd]n */
1073 if (typeinfo
.defined
== 0)
1075 set_first_syntax_error (_("invalid scalar register in list"));
1080 if (typeinfo
.defined
& NTA_HASINDEX
)
1081 expect_index
= TRUE
;
1085 if (val
< val_range
)
1087 set_first_syntax_error
1088 (_("invalid range in vector register list"));
1097 typeinfo_first
= typeinfo
;
1098 else if (! eq_neon_type_el (typeinfo_first
, typeinfo
))
1100 set_first_syntax_error
1101 (_("type mismatch in vector register list"));
1106 for (i
= val_range
; i
<= val
; i
++)
1108 ret_val
|= i
<< (5 * nb_regs
);
1113 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1115 skip_whitespace (str
);
1118 set_first_syntax_error (_("end of vector register list not found"));
1123 skip_whitespace (str
);
1127 if (skip_past_char (&str
, '['))
1131 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1132 if (exp
.X_op
!= O_constant
)
1134 set_first_syntax_error (_("constant expression required."));
1137 if (! skip_past_char (&str
, ']'))
1140 typeinfo_first
.index
= exp
.X_add_number
;
1144 set_first_syntax_error (_("expected index"));
1151 set_first_syntax_error (_("too many registers in vector register list"));
1154 else if (nb_regs
== 0)
1156 set_first_syntax_error (_("empty vector register list"));
1162 *vectype
= typeinfo_first
;
1164 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1167 /* Directives: register aliases. */
1170 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1175 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1178 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1181 /* Only warn about a redefinition if it's not defined as the
1183 else if (new->number
!= number
|| new->type
!= type
)
1184 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1189 name
= xstrdup (str
);
1190 new = xmalloc (sizeof (reg_entry
));
1193 new->number
= number
;
1195 new->builtin
= FALSE
;
1197 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1203 /* Look for the .req directive. This is of the form:
1205 new_register_name .req existing_register_name
1207 If we find one, or if it looks sufficiently like one that we want to
1208 handle any error here, return TRUE. Otherwise return FALSE. */
1211 create_register_alias (char *newname
, char *p
)
1213 const reg_entry
*old
;
1214 char *oldname
, *nbuf
;
1217 /* The input scrubber ensures that whitespace after the mnemonic is
1218 collapsed to single spaces. */
1220 if (strncmp (oldname
, " .req ", 6) != 0)
1224 if (*oldname
== '\0')
1227 old
= hash_find (aarch64_reg_hsh
, oldname
);
1230 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1234 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1235 the desired alias name, and p points to its end. If not, then
1236 the desired alias name is in the global original_case_string. */
1237 #ifdef TC_CASE_SENSITIVE
1240 newname
= original_case_string
;
1241 nlen
= strlen (newname
);
1244 nbuf
= xmalloc (nlen
+ 1);
1245 memcpy (nbuf
, newname
, nlen
);
1248 /* Create aliases under the new name as stated; an all-lowercase
1249 version of the new name; and an all-uppercase version of the new
1251 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1253 for (p
= nbuf
; *p
; p
++)
1256 if (strncmp (nbuf
, newname
, nlen
))
1258 /* If this attempt to create an additional alias fails, do not bother
1259 trying to create the all-lower case alias. We will fail and issue
1260 a second, duplicate error message. This situation arises when the
1261 programmer does something like:
1264 The second .req creates the "Foo" alias but then fails to create
1265 the artificial FOO alias because it has already been created by the
1267 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1274 for (p
= nbuf
; *p
; p
++)
1277 if (strncmp (nbuf
, newname
, nlen
))
1278 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1285 /* Should never be called, as .req goes between the alias and the
1286 register name, not at the beginning of the line. */
1288 s_req (int a ATTRIBUTE_UNUSED
)
1290 as_bad (_("invalid syntax for .req directive"));
1293 /* The .unreq directive deletes an alias which was previously defined
1294 by .req. For example:
1300 s_unreq (int a ATTRIBUTE_UNUSED
)
1305 name
= input_line_pointer
;
1307 while (*input_line_pointer
!= 0
1308 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1309 ++input_line_pointer
;
1311 saved_char
= *input_line_pointer
;
1312 *input_line_pointer
= 0;
1315 as_bad (_("invalid syntax for .unreq directive"));
1318 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1321 as_bad (_("unknown register alias '%s'"), name
);
1322 else if (reg
->builtin
)
1323 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1330 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1331 free ((char *) reg
->name
);
1334 /* Also locate the all upper case and all lower case versions.
1335 Do not complain if we cannot find one or the other as it
1336 was probably deleted above. */
1338 nbuf
= strdup (name
);
1339 for (p
= nbuf
; *p
; p
++)
1341 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1344 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1345 free ((char *) reg
->name
);
1349 for (p
= nbuf
; *p
; p
++)
1351 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1354 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1355 free ((char *) reg
->name
);
1363 *input_line_pointer
= saved_char
;
1364 demand_empty_rest_of_line ();
1367 /* Directives: Instruction set selection. */
1370 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1371 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1372 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1373 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1375 /* Create a new mapping symbol for the transition to STATE. */
1378 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1381 const char *symname
;
1388 type
= BSF_NO_FLAGS
;
1392 type
= BSF_NO_FLAGS
;
1398 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1399 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1401 /* Save the mapping symbols for future reference. Also check that
1402 we do not place two mapping symbols at the same offset within a
1403 frag. We'll handle overlap between frags in
1404 check_mapping_symbols.
1406 If .fill or other data filling directive generates zero sized data,
1407 the mapping symbol for the following code will have the same value
1408 as the one generated for the data filling directive. In this case,
1409 we replace the old symbol with the new one at the same address. */
1412 if (frag
->tc_frag_data
.first_map
!= NULL
)
1414 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1415 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1418 frag
->tc_frag_data
.first_map
= symbolP
;
1420 if (frag
->tc_frag_data
.last_map
!= NULL
)
1422 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1423 S_GET_VALUE (symbolP
));
1424 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1425 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1428 frag
->tc_frag_data
.last_map
= symbolP
;
1431 /* We must sometimes convert a region marked as code to data during
1432 code alignment, if an odd number of bytes have to be padded. The
1433 code mapping symbol is pushed to an aligned address. */
1436 insert_data_mapping_symbol (enum mstate state
,
1437 valueT value
, fragS
* frag
, offsetT bytes
)
1439 /* If there was already a mapping symbol, remove it. */
1440 if (frag
->tc_frag_data
.last_map
!= NULL
1441 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1442 frag
->fr_address
+ value
)
1444 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1448 know (frag
->tc_frag_data
.first_map
== symp
);
1449 frag
->tc_frag_data
.first_map
= NULL
;
1451 frag
->tc_frag_data
.last_map
= NULL
;
1452 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1455 make_mapping_symbol (MAP_DATA
, value
, frag
);
1456 make_mapping_symbol (state
, value
+ bytes
, frag
);
1459 static void mapping_state_2 (enum mstate state
, int max_chars
);
1461 /* Set the mapping state to STATE. Only call this when about to
1462 emit some STATE bytes to the file. */
1465 mapping_state (enum mstate state
)
1467 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1469 if (state
== MAP_INSN
)
1470 /* AArch64 instructions require 4-byte alignment. When emitting
1471 instructions into any section, record the appropriate section
1473 record_alignment (now_seg
, 2);
1475 if (mapstate
== state
)
1476 /* The mapping symbol has already been emitted.
1477 There is nothing else to do. */
1480 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1481 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1482 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1483 evaluated later in the next else. */
1485 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1487 /* Only add the symbol if the offset is > 0:
1488 if we're at the first frag, check it's size > 0;
1489 if we're not at the first frag, then for sure
1490 the offset is > 0. */
1491 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1492 const int add_symbol
= (frag_now
!= frag_first
)
1493 || (frag_now_fix () > 0);
1496 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1500 mapping_state_2 (state
, 0);
1503 /* Same as mapping_state, but MAX_CHARS bytes have already been
1504 allocated. Put the mapping symbol that far back. */
1507 mapping_state_2 (enum mstate state
, int max_chars
)
1509 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1511 if (!SEG_NORMAL (now_seg
))
1514 if (mapstate
== state
)
1515 /* The mapping symbol has already been emitted.
1516 There is nothing else to do. */
1519 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1520 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1523 #define mapping_state(x) /* nothing */
1524 #define mapping_state_2(x, y) /* nothing */
1527 /* Directives: sectioning and alignment. */
1530 s_bss (int ignore ATTRIBUTE_UNUSED
)
1532 /* We don't support putting frags in the BSS segment, we fake it by
1533 marking in_bss, then looking at s_skip for clues. */
1534 subseg_set (bss_section
, 0);
1535 demand_empty_rest_of_line ();
1536 mapping_state (MAP_DATA
);
1540 s_even (int ignore ATTRIBUTE_UNUSED
)
1542 /* Never make frag if expect extra pass. */
1544 frag_align (1, 0, 0);
1546 record_alignment (now_seg
, 1);
1548 demand_empty_rest_of_line ();
1551 /* Directives: Literal pools. */
1553 static literal_pool
*
1554 find_literal_pool (int size
)
1558 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1560 if (pool
->section
== now_seg
1561 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1568 static literal_pool
*
1569 find_or_make_literal_pool (int size
)
1571 /* Next literal pool ID number. */
1572 static unsigned int latest_pool_num
= 1;
1575 pool
= find_literal_pool (size
);
1579 /* Create a new pool. */
1580 pool
= xmalloc (sizeof (*pool
));
1584 /* Currently we always put the literal pool in the current text
1585 section. If we were generating "small" model code where we
1586 knew that all code and initialised data was within 1MB then
1587 we could output literals to mergeable, read-only data
1590 pool
->next_free_entry
= 0;
1591 pool
->section
= now_seg
;
1592 pool
->sub_section
= now_subseg
;
1594 pool
->next
= list_of_pools
;
1595 pool
->symbol
= NULL
;
1597 /* Add it to the list. */
1598 list_of_pools
= pool
;
1601 /* New pools, and emptied pools, will have a NULL symbol. */
1602 if (pool
->symbol
== NULL
)
1604 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1605 (valueT
) 0, &zero_address_frag
);
1606 pool
->id
= latest_pool_num
++;
1613 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1614 Return TRUE on success, otherwise return FALSE. */
1616 add_to_lit_pool (expressionS
*exp
, int size
)
1621 pool
= find_or_make_literal_pool (size
);
1623 /* Check if this literal value is already in the pool. */
1624 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1626 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1628 if ((litexp
->X_op
== exp
->X_op
)
1629 && (exp
->X_op
== O_constant
)
1630 && (litexp
->X_add_number
== exp
->X_add_number
)
1631 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1634 if ((litexp
->X_op
== exp
->X_op
)
1635 && (exp
->X_op
== O_symbol
)
1636 && (litexp
->X_add_number
== exp
->X_add_number
)
1637 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1638 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1642 /* Do we need to create a new entry? */
1643 if (entry
== pool
->next_free_entry
)
1645 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1647 set_syntax_error (_("literal pool overflow"));
1651 pool
->literals
[entry
].exp
= *exp
;
1652 pool
->next_free_entry
+= 1;
1653 if (exp
->X_op
== O_big
)
1655 /* PR 16688: Bignums are held in a single global array. We must
1656 copy and preserve that value now, before it is overwritten. */
1657 pool
->literals
[entry
].bignum
= xmalloc (CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1658 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1659 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1662 pool
->literals
[entry
].bignum
= NULL
;
1665 exp
->X_op
= O_symbol
;
1666 exp
->X_add_number
= ((int) entry
) * size
;
1667 exp
->X_add_symbol
= pool
->symbol
;
1672 /* Can't use symbol_new here, so have to create a symbol and then at
1673 a later date assign it a value. Thats what these functions do. */
1676 symbol_locate (symbolS
* symbolP
,
1677 const char *name
,/* It is copied, the caller can modify. */
1678 segT segment
, /* Segment identifier (SEG_<something>). */
1679 valueT valu
, /* Symbol value. */
1680 fragS
* frag
) /* Associated fragment. */
1683 char *preserved_copy_of_name
;
1685 name_length
= strlen (name
) + 1; /* +1 for \0. */
1686 obstack_grow (¬es
, name
, name_length
);
1687 preserved_copy_of_name
= obstack_finish (¬es
);
1689 #ifdef tc_canonicalize_symbol_name
1690 preserved_copy_of_name
=
1691 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1694 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1696 S_SET_SEGMENT (symbolP
, segment
);
1697 S_SET_VALUE (symbolP
, valu
);
1698 symbol_clear_list_pointers (symbolP
);
1700 symbol_set_frag (symbolP
, frag
);
1702 /* Link to end of symbol chain. */
1704 extern int symbol_table_frozen
;
1706 if (symbol_table_frozen
)
1710 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1712 obj_symbol_new_hook (symbolP
);
1714 #ifdef tc_symbol_new_hook
1715 tc_symbol_new_hook (symbolP
);
1719 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1720 #endif /* DEBUG_SYMS */
1725 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1732 for (align
= 2; align
<= 4; align
++)
1734 int size
= 1 << align
;
1736 pool
= find_literal_pool (size
);
1737 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1740 mapping_state (MAP_DATA
);
1742 /* Align pool as you have word accesses.
1743 Only make a frag if we have to. */
1745 frag_align (align
, 0, 0);
1747 record_alignment (now_seg
, align
);
1749 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1751 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1752 (valueT
) frag_now_fix (), frag_now
);
1753 symbol_table_insert (pool
->symbol
);
1755 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1757 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1759 if (exp
->X_op
== O_big
)
1761 /* PR 16688: Restore the global bignum value. */
1762 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1763 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1764 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1767 /* First output the expression in the instruction to the pool. */
1768 emit_expr (exp
, size
); /* .word|.xword */
1770 if (exp
->X_op
== O_big
)
1772 free (pool
->literals
[entry
].bignum
);
1773 pool
->literals
[entry
].bignum
= NULL
;
1777 /* Mark the pool as empty. */
1778 pool
->next_free_entry
= 0;
1779 pool
->symbol
= NULL
;
1784 /* Forward declarations for functions below, in the MD interface
1786 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1787 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1789 /* Directives: Data. */
1790 /* N.B. the support for relocation suffix in this directive needs to be
1791 implemented properly. */
1794 s_aarch64_elf_cons (int nbytes
)
1798 #ifdef md_flush_pending_output
1799 md_flush_pending_output ();
1802 if (is_it_end_of_statement ())
1804 demand_empty_rest_of_line ();
1808 #ifdef md_cons_align
1809 md_cons_align (nbytes
);
1812 mapping_state (MAP_DATA
);
1815 struct reloc_table_entry
*reloc
;
1819 if (exp
.X_op
!= O_symbol
)
1820 emit_expr (&exp
, (unsigned int) nbytes
);
1823 skip_past_char (&input_line_pointer
, '#');
1824 if (skip_past_char (&input_line_pointer
, ':'))
1826 reloc
= find_reloc_table_entry (&input_line_pointer
);
1828 as_bad (_("unrecognized relocation suffix"));
1830 as_bad (_("unimplemented relocation suffix"));
1831 ignore_rest_of_line ();
1835 emit_expr (&exp
, (unsigned int) nbytes
);
1838 while (*input_line_pointer
++ == ',');
1840 /* Put terminator back into stream. */
1841 input_line_pointer
--;
1842 demand_empty_rest_of_line ();
1845 #endif /* OBJ_ELF */
1847 /* Output a 32-bit word, but mark as an instruction. */
1850 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1854 #ifdef md_flush_pending_output
1855 md_flush_pending_output ();
1858 if (is_it_end_of_statement ())
1860 demand_empty_rest_of_line ();
1864 /* Sections are assumed to start aligned. In executable section, there is no
1865 MAP_DATA symbol pending. So we only align the address during
1866 MAP_DATA --> MAP_INSN transition.
1867 For other sections, this is not guaranteed. */
1868 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1869 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1870 frag_align_code (2, 0);
1873 mapping_state (MAP_INSN
);
1879 if (exp
.X_op
!= O_constant
)
1881 as_bad (_("constant expression required"));
1882 ignore_rest_of_line ();
1886 if (target_big_endian
)
1888 unsigned int val
= exp
.X_add_number
;
1889 exp
.X_add_number
= SWAP_32 (val
);
1891 emit_expr (&exp
, 4);
1893 while (*input_line_pointer
++ == ',');
1895 /* Put terminator back into stream. */
1896 input_line_pointer
--;
1897 demand_empty_rest_of_line ();
1901 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
1904 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
1910 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1911 BFD_RELOC_AARCH64_TLSDESC_ADD
);
1913 demand_empty_rest_of_line ();
1916 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1919 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
1923 /* Since we're just labelling the code, there's no need to define a
1926 /* Make sure there is enough room in this frag for the following
1927 blr. This trick only works if the blr follows immediately after
1928 the .tlsdesc directive. */
1930 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1931 BFD_RELOC_AARCH64_TLSDESC_CALL
);
1933 demand_empty_rest_of_line ();
1936 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
1939 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
1945 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
1946 BFD_RELOC_AARCH64_TLSDESC_LDR
);
1948 demand_empty_rest_of_line ();
1950 #endif /* OBJ_ELF */
1952 static void s_aarch64_arch (int);
1953 static void s_aarch64_cpu (int);
1954 static void s_aarch64_arch_extension (int);
1956 /* This table describes all the machine specific pseudo-ops the assembler
1957 has to support. The fields are:
1958 pseudo-op name without dot
1959 function to call to execute this pseudo-op
1960 Integer arg to pass to the function. */
1962 const pseudo_typeS md_pseudo_table
[] = {
1963 /* Never called because '.req' does not start a line. */
1965 {"unreq", s_unreq
, 0},
1967 {"even", s_even
, 0},
1968 {"ltorg", s_ltorg
, 0},
1969 {"pool", s_ltorg
, 0},
1970 {"cpu", s_aarch64_cpu
, 0},
1971 {"arch", s_aarch64_arch
, 0},
1972 {"arch_extension", s_aarch64_arch_extension
, 0},
1973 {"inst", s_aarch64_inst
, 0},
1975 {"tlsdescadd", s_tlsdescadd
, 0},
1976 {"tlsdesccall", s_tlsdesccall
, 0},
1977 {"tlsdescldr", s_tlsdescldr
, 0},
1978 {"word", s_aarch64_elf_cons
, 4},
1979 {"long", s_aarch64_elf_cons
, 4},
1980 {"xword", s_aarch64_elf_cons
, 8},
1981 {"dword", s_aarch64_elf_cons
, 8},
1987 /* Check whether STR points to a register name followed by a comma or the
1988 end of line; REG_TYPE indicates which register types are checked
1989 against. Return TRUE if STR is such a register name; otherwise return
1990 FALSE. The function does not intend to produce any diagnostics, but since
1991 the register parser aarch64_reg_parse, which is called by this function,
1992 does produce diagnostics, we call clear_error to clear any diagnostics
1993 that may be generated by aarch64_reg_parse.
1994 Also, the function returns FALSE directly if there is any user error
1995 present at the function entry. This prevents the existing diagnostics
1996 state from being spoiled.
1997 The function currently serves parse_constant_immediate and
1998 parse_big_immediate only. */
2000 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2004 /* Prevent the diagnostics state from being spoiled. */
2008 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2010 /* Clear the parsing error that may be set by the reg parser. */
2013 if (reg
== PARSE_FAIL
)
2016 skip_whitespace (str
);
2017 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2023 /* Parser functions used exclusively in instruction operands. */
2025 /* Parse an immediate expression which may not be constant.
2027 To prevent the expression parser from pushing a register name
2028 into the symbol table as an undefined symbol, firstly a check is
2029 done to find out whether STR is a valid register name followed
2030 by a comma or the end of line. Return FALSE if STR is such a
2034 parse_immediate_expression (char **str
, expressionS
*exp
)
2036 if (reg_name_p (*str
, REG_TYPE_R_Z_BHSDQ_V
))
2038 set_recoverable_error (_("immediate operand required"));
2042 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2044 if (exp
->X_op
== O_absent
)
2046 set_fatal_syntax_error (_("missing immediate expression"));
2053 /* Constant immediate-value read function for use in insn parsing.
2054 STR points to the beginning of the immediate (with the optional
2055 leading #); *VAL receives the value.
2057 Return TRUE on success; otherwise return FALSE. */
2060 parse_constant_immediate (char **str
, int64_t * val
)
2064 if (! parse_immediate_expression (str
, &exp
))
2067 if (exp
.X_op
!= O_constant
)
2069 set_syntax_error (_("constant expression required"));
2073 *val
= exp
.X_add_number
;
2078 encode_imm_float_bits (uint32_t imm
)
2080 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2081 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2084 /* Return TRUE if the single-precision floating-point value encoded in IMM
2085 can be expressed in the AArch64 8-bit signed floating-point format with
2086 3-bit exponent and normalized 4 bits of precision; in other words, the
2087 floating-point value must be expressable as
2088 (+/-) n / 16 * power (2, r)
2089 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2092 aarch64_imm_float_p (uint32_t imm
)
2094 /* If a single-precision floating-point value has the following bit
2095 pattern, it can be expressed in the AArch64 8-bit floating-point
2098 3 32222222 2221111111111
2099 1 09876543 21098765432109876543210
2100 n Eeeeeexx xxxx0000000000000000000
2102 where n, e and each x are either 0 or 1 independently, with
2107 /* Prepare the pattern for 'Eeeeee'. */
2108 if (((imm
>> 30) & 0x1) == 0)
2109 pattern
= 0x3e000000;
2111 pattern
= 0x40000000;
2113 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2114 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2117 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2119 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2120 8-bit signed floating-point format with 3-bit exponent and normalized 4
2121 bits of precision (i.e. can be used in an FMOV instruction); return the
2122 equivalent single-precision encoding in *FPWORD.
2124 Otherwise return FALSE. */
2127 aarch64_double_precision_fmovable (uint64_t imm
, uint32_t *fpword
)
2129 /* If a double-precision floating-point value has the following bit
2130 pattern, it can be expressed in the AArch64 8-bit floating-point
2133 6 66655555555 554444444...21111111111
2134 3 21098765432 109876543...098765432109876543210
2135 n Eeeeeeeeexx xxxx00000...000000000000000000000
2137 where n, e and each x are either 0 or 1 independently, with
2141 uint32_t high32
= imm
>> 32;
2143 /* Lower 32 bits need to be 0s. */
2144 if ((imm
& 0xffffffff) != 0)
2147 /* Prepare the pattern for 'Eeeeeeeee'. */
2148 if (((high32
>> 30) & 0x1) == 0)
2149 pattern
= 0x3fc00000;
2151 pattern
= 0x40000000;
2153 if ((high32
& 0xffff) == 0 /* bits 32 - 47 are 0. */
2154 && (high32
& 0x7fc00000) == pattern
) /* bits 54 - 61 == ~ bit 62. */
2156 /* Convert to the single-precision encoding.
2158 n Eeeeeeeeexx xxxx00000...000000000000000000000
2160 n Eeeeeexx xxxx0000000000000000000. */
2161 *fpword
= ((high32
& 0xfe000000) /* nEeeeee. */
2162 | (((high32
>> 16) & 0x3f) << 19)); /* xxxxxx. */
2169 /* Parse a floating-point immediate. Return TRUE on success and return the
2170 value in *IMMED in the format of IEEE754 single-precision encoding.
2171 *CCP points to the start of the string; DP_P is TRUE when the immediate
2172 is expected to be in double-precision (N.B. this only matters when
2173 hexadecimal representation is involved).
2175 N.B. 0.0 is accepted by this function. */
2178 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
)
2182 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2183 int found_fpchar
= 0;
2185 unsigned fpword
= 0;
2186 bfd_boolean hex_p
= FALSE
;
2188 skip_past_char (&str
, '#');
2191 skip_whitespace (fpnum
);
2193 if (strncmp (fpnum
, "0x", 2) == 0)
2195 /* Support the hexadecimal representation of the IEEE754 encoding.
2196 Double-precision is expected when DP_P is TRUE, otherwise the
2197 representation should be in single-precision. */
2198 if (! parse_constant_immediate (&str
, &val
))
2203 if (! aarch64_double_precision_fmovable (val
, &fpword
))
2206 else if ((uint64_t) val
> 0xffffffff)
2215 /* We must not accidentally parse an integer as a floating-point number.
2216 Make sure that the value we parse is not an integer by checking for
2217 special characters '.' or 'e'. */
2218 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
2219 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
2233 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2236 /* Our FP word must be 32 bits (single-precision FP). */
2237 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2239 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2244 if (aarch64_imm_float_p (fpword
) || (fpword
& 0x7fffffff) == 0)
2252 set_fatal_syntax_error (_("invalid floating-point constant"));
2256 /* Less-generic immediate-value read function with the possibility of loading
2257 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2260 To prevent the expression parser from pushing a register name into the
2261 symbol table as an undefined symbol, a check is firstly done to find
2262 out whether STR is a valid register name followed by a comma or the end
2263 of line. Return FALSE if STR is such a register. */
2266 parse_big_immediate (char **str
, int64_t *imm
)
2270 if (reg_name_p (ptr
, REG_TYPE_R_Z_BHSDQ_V
))
2272 set_syntax_error (_("immediate operand required"));
2276 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2278 if (inst
.reloc
.exp
.X_op
== O_constant
)
2279 *imm
= inst
.reloc
.exp
.X_add_number
;
2286 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2287 if NEED_LIBOPCODES is non-zero, the fixup will need
2288 assistance from the libopcodes. */
2291 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2292 const aarch64_opnd_info
*operand
,
2293 int need_libopcodes_p
)
2295 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2296 reloc
->opnd
= operand
->type
;
2297 if (need_libopcodes_p
)
2298 reloc
->need_libopcodes_p
= 1;
2301 /* Return TRUE if the instruction needs to be fixed up later internally by
2302 the GAS; otherwise return FALSE. */
2304 static inline bfd_boolean
2305 aarch64_gas_internal_fixup_p (void)
2307 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2310 /* Assign the immediate value to the relavant field in *OPERAND if
2311 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2312 needs an internal fixup in a later stage.
2313 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2314 IMM.VALUE that may get assigned with the constant. */
2316 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2317 aarch64_opnd_info
*operand
,
2319 int need_libopcodes_p
,
2322 if (reloc
->exp
.X_op
== O_constant
)
2325 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2327 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2328 reloc
->type
= BFD_RELOC_UNUSED
;
2332 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2333 /* Tell libopcodes to ignore this operand or not. This is helpful
2334 when one of the operands needs to be fixed up later but we need
2335 libopcodes to check the other operands. */
2336 operand
->skip
= skip_p
;
2340 /* Relocation modifiers. Each entry in the table contains the textual
2341 name for the relocation which may be placed before a symbol used as
2342 a load/store offset, or add immediate. It must be surrounded by a
2343 leading and trailing colon, for example:
2345 ldr x0, [x1, #:rello:varsym]
2346 add x0, x1, #:rello:varsym */
2348 struct reloc_table_entry
2352 bfd_reloc_code_real_type adr_type
;
2353 bfd_reloc_code_real_type adrp_type
;
2354 bfd_reloc_code_real_type movw_type
;
2355 bfd_reloc_code_real_type add_type
;
2356 bfd_reloc_code_real_type ldst_type
;
2357 bfd_reloc_code_real_type ld_literal_type
;
2360 static struct reloc_table_entry reloc_table
[] = {
2361 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2366 BFD_RELOC_AARCH64_ADD_LO12
,
2367 BFD_RELOC_AARCH64_LDST_LO12
,
2370 /* Higher 21 bits of pc-relative page offset: ADRP */
2373 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2379 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2382 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2388 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2392 BFD_RELOC_AARCH64_MOVW_G0
,
2397 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2401 BFD_RELOC_AARCH64_MOVW_G0_S
,
2406 /* Less significant bits 0-15 of address/value: MOVK, no check */
2410 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2415 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2419 BFD_RELOC_AARCH64_MOVW_G1
,
2424 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2428 BFD_RELOC_AARCH64_MOVW_G1_S
,
2433 /* Less significant bits 16-31 of address/value: MOVK, no check */
2437 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2442 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2446 BFD_RELOC_AARCH64_MOVW_G2
,
2451 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2455 BFD_RELOC_AARCH64_MOVW_G2_S
,
2460 /* Less significant bits 32-47 of address/value: MOVK, no check */
2464 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2469 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2473 BFD_RELOC_AARCH64_MOVW_G3
,
2478 /* Get to the page containing GOT entry for a symbol. */
2481 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2485 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2487 /* 12 bit offset into the page containing GOT entry for that symbol. */
2493 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2496 /* 0-15 bits of address/value: MOVk, no check. */
2500 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2505 /* Most significant bits 16-31 of address/value: MOVZ. */
2509 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2514 /* 15 bit offset into the page containing GOT entry for that symbol. */
2520 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2523 /* Get to the page containing GOT TLS entry for a symbol */
2524 {"gottprel_g0_nc", 0,
2527 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2532 /* Get to the page containing GOT TLS entry for a symbol */
2536 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2541 /* Get to the page containing GOT TLS entry for a symbol */
2543 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2544 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2550 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2555 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2559 /* Lower 16 bits address/value: MOVk. */
2563 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2568 /* Most significant bits 16-31 of address/value: MOVZ. */
2572 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2577 /* Get to the page containing GOT TLS entry for a symbol */
2579 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2580 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2584 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2586 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2591 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
,
2592 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2595 /* Get to the page containing GOT TLS entry for a symbol.
2596 The same as GD, we allocate two consecutive GOT slots
2597 for module index and module offset, the only difference
2598 with GD is the module offset should be intialized to
2599 zero without any outstanding runtime relocation. */
2601 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2602 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2608 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2609 {"tlsldm_lo12_nc", 0,
2613 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2617 /* 12 bit offset into the module TLS base address. */
2622 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2623 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2626 /* Same as dtprel_lo12, no overflow check. */
2627 {"dtprel_lo12_nc", 0,
2631 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2632 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2635 /* bits[23:12] of offset to the module TLS base address. */
2640 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2644 /* bits[15:0] of offset to the module TLS base address. */
2648 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2653 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2657 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2662 /* bits[31:16] of offset to the module TLS base address. */
2666 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2671 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2675 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2680 /* bits[47:32] of offset to the module TLS base address. */
2684 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2689 /* Lower 16 bit offset into GOT entry for a symbol */
2690 {"tlsdesc_off_g0_nc", 0,
2693 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2698 /* Higher 16 bit offset into GOT entry for a symbol */
2699 {"tlsdesc_off_g1", 0,
2702 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2707 /* Get to the page containing GOT TLS entry for a symbol */
2710 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2714 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2716 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2717 {"gottprel_lo12", 0,
2722 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2725 /* Get tp offset for a symbol. */
2730 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2734 /* Get tp offset for a symbol. */
2739 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2743 /* Get tp offset for a symbol. */
2748 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2752 /* Get tp offset for a symbol. */
2753 {"tprel_lo12_nc", 0,
2757 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2761 /* Most significant bits 32-47 of address/value: MOVZ. */
2765 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2770 /* Most significant bits 16-31 of address/value: MOVZ. */
2774 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2779 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2783 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2788 /* Most significant bits 0-15 of address/value: MOVZ. */
2792 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2797 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2801 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2806 /* 15bit offset from got entry to base address of GOT table. */
2812 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2815 /* 14bit offset from got entry to base address of GOT table. */
2821 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2825 /* Given the address of a pointer pointing to the textual name of a
2826 relocation as may appear in assembler source, attempt to find its
2827 details in reloc_table. The pointer will be updated to the character
2828 after the trailing colon. On failure, NULL will be returned;
2829 otherwise return the reloc_table_entry. */
2831 static struct reloc_table_entry
*
2832 find_reloc_table_entry (char **str
)
2835 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
2837 int length
= strlen (reloc_table
[i
].name
);
2839 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
2840 && (*str
)[length
] == ':')
2842 *str
+= (length
+ 1);
2843 return &reloc_table
[i
];
2850 /* Mode argument to parse_shift and parser_shifter_operand. */
2851 enum parse_shift_mode
2853 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2855 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2857 SHIFTED_LSL
, /* bare "lsl #n" */
2858 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
2859 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
2862 /* Parse a <shift> operator on an AArch64 data processing instruction.
2863 Return TRUE on success; otherwise return FALSE. */
2865 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
2867 const struct aarch64_name_value_pair
*shift_op
;
2868 enum aarch64_modifier_kind kind
;
2874 for (p
= *str
; ISALPHA (*p
); p
++)
2879 set_syntax_error (_("shift expression expected"));
2883 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
2885 if (shift_op
== NULL
)
2887 set_syntax_error (_("shift operator expected"));
2891 kind
= aarch64_get_operand_modifier (shift_op
);
2893 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
2895 set_syntax_error (_("invalid use of 'MSL'"));
2901 case SHIFTED_LOGIC_IMM
:
2902 if (aarch64_extend_operator_p (kind
) == TRUE
)
2904 set_syntax_error (_("extending shift is not permitted"));
2909 case SHIFTED_ARITH_IMM
:
2910 if (kind
== AARCH64_MOD_ROR
)
2912 set_syntax_error (_("'ROR' shift is not permitted"));
2918 if (kind
!= AARCH64_MOD_LSL
)
2920 set_syntax_error (_("only 'LSL' shift is permitted"));
2925 case SHIFTED_REG_OFFSET
:
2926 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
2927 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
2929 set_fatal_syntax_error
2930 (_("invalid shift for the register offset addressing mode"));
2935 case SHIFTED_LSL_MSL
:
2936 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
2938 set_syntax_error (_("invalid shift operator"));
2947 /* Whitespace can appear here if the next thing is a bare digit. */
2948 skip_whitespace (p
);
2950 /* Parse shift amount. */
2952 if (mode
== SHIFTED_REG_OFFSET
&& *p
== ']')
2953 exp
.X_op
= O_absent
;
2956 if (is_immediate_prefix (*p
))
2961 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
2963 if (exp
.X_op
== O_absent
)
2965 if (aarch64_extend_operator_p (kind
) == FALSE
|| exp_has_prefix
)
2967 set_syntax_error (_("missing shift amount"));
2970 operand
->shifter
.amount
= 0;
2972 else if (exp
.X_op
!= O_constant
)
2974 set_syntax_error (_("constant shift amount required"));
2977 else if (exp
.X_add_number
< 0 || exp
.X_add_number
> 63)
2979 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2984 operand
->shifter
.amount
= exp
.X_add_number
;
2985 operand
->shifter
.amount_present
= 1;
2988 operand
->shifter
.operator_present
= 1;
2989 operand
->shifter
.kind
= kind
;
2995 /* Parse a <shifter_operand> for a data processing instruction:
2998 #<immediate>, LSL #imm
3000 Validation of immediate operands is deferred to md_apply_fix.
3002 Return TRUE on success; otherwise return FALSE. */
3005 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3006 enum parse_shift_mode mode
)
3010 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3015 /* Accept an immediate expression. */
3016 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3019 /* Accept optional LSL for arithmetic immediate values. */
3020 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3021 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3024 /* Not accept any shifter for logical immediate values. */
3025 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3026 && parse_shift (&p
, operand
, mode
))
3028 set_syntax_error (_("unexpected shift operator"));
3036 /* Parse a <shifter_operand> for a data processing instruction:
3041 #<immediate>, LSL #imm
3043 where <shift> is handled by parse_shift above, and the last two
3044 cases are handled by the function above.
3046 Validation of immediate operands is deferred to md_apply_fix.
3048 Return TRUE on success; otherwise return FALSE. */
3051 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3052 enum parse_shift_mode mode
)
3055 int isreg32
, isregzero
;
3056 enum aarch64_operand_class opd_class
3057 = aarch64_get_operand_class (operand
->type
);
3060 aarch64_reg_parse_32_64 (str
, 0, 0, &isreg32
, &isregzero
)) != PARSE_FAIL
)
3062 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3064 set_syntax_error (_("unexpected register in the immediate operand"));
3068 if (!isregzero
&& reg
== REG_SP
)
3070 set_syntax_error (BAD_SP
);
3074 operand
->reg
.regno
= reg
;
3075 operand
->qualifier
= isreg32
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
3077 /* Accept optional shift operation on register. */
3078 if (! skip_past_comma (str
))
3081 if (! parse_shift (str
, operand
, mode
))
3086 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3089 (_("integer register expected in the extended/shifted operand "
3094 /* We have a shifted immediate variable. */
3095 return parse_shifter_operand_imm (str
, operand
, mode
);
3098 /* Return TRUE on success; return FALSE otherwise. */
3101 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3102 enum parse_shift_mode mode
)
3106 /* Determine if we have the sequence of characters #: or just :
3107 coming next. If we do, then we check for a :rello: relocation
3108 modifier. If we don't, punt the whole lot to
3109 parse_shifter_operand. */
3111 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3113 struct reloc_table_entry
*entry
;
3121 /* Try to parse a relocation. Anything else is an error. */
3122 if (!(entry
= find_reloc_table_entry (str
)))
3124 set_syntax_error (_("unknown relocation modifier"));
3128 if (entry
->add_type
== 0)
3131 (_("this relocation modifier is not allowed on this instruction"));
3135 /* Save str before we decompose it. */
3138 /* Next, we parse the expression. */
3139 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3142 /* Record the relocation type (use the ADD variant here). */
3143 inst
.reloc
.type
= entry
->add_type
;
3144 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3146 /* If str is empty, we've reached the end, stop here. */
3150 /* Otherwise, we have a shifted reloc modifier, so rewind to
3151 recover the variable name and continue parsing for the shifter. */
3153 return parse_shifter_operand_imm (str
, operand
, mode
);
3156 return parse_shifter_operand (str
, operand
, mode
);
3159 /* Parse all forms of an address expression. Information is written
3160 to *OPERAND and/or inst.reloc.
3162 The A64 instruction set has the following addressing modes:
3165 [base] // in SIMD ld/st structure
3166 [base{,#0}] // in ld/st exclusive
3168 [base,Xm{,LSL #imm}]
3169 [base,Xm,SXTX {#imm}]
3170 [base,Wm,(S|U)XTW {#imm}]
3175 [base],Xm // in SIMD ld/st structure
3176 PC-relative (literal)
3180 (As a convenience, the notation "=immediate" is permitted in conjunction
3181 with the pc-relative literal load instructions to automatically place an
3182 immediate value or symbolic address in a nearby literal pool and generate
3183 a hidden label which references it.)
3185 Upon a successful parsing, the address structure in *OPERAND will be
3186 filled in the following way:
3188 .base_regno = <base>
3189 .offset.is_reg // 1 if the offset is a register
3191 .offset.regno = <Rm>
3193 For different addressing modes defined in the A64 ISA:
3196 .pcrel=0; .preind=1; .postind=0; .writeback=0
3198 .pcrel=0; .preind=1; .postind=0; .writeback=1
3200 .pcrel=0; .preind=0; .postind=1; .writeback=1
3201 PC-relative (literal)
3202 .pcrel=1; .preind=1; .postind=0; .writeback=0
3204 The shift/extension information, if any, will be stored in .shifter.
3206 It is the caller's responsibility to check for addressing modes not
3207 supported by the instruction, and to set inst.reloc.type. */
3210 parse_address_main (char **str
, aarch64_opnd_info
*operand
, int reloc
,
3211 int accept_reg_post_index
)
3215 int isreg32
, isregzero
;
3216 expressionS
*exp
= &inst
.reloc
.exp
;
3218 if (! skip_past_char (&p
, '['))
3220 /* =immediate or label. */
3221 operand
->addr
.pcrel
= 1;
3222 operand
->addr
.preind
= 1;
3224 /* #:<reloc_op>:<symbol> */
3225 skip_past_char (&p
, '#');
3226 if (reloc
&& skip_past_char (&p
, ':'))
3228 bfd_reloc_code_real_type ty
;
3229 struct reloc_table_entry
*entry
;
3231 /* Try to parse a relocation modifier. Anything else is
3233 entry
= find_reloc_table_entry (&p
);
3236 set_syntax_error (_("unknown relocation modifier"));
3240 switch (operand
->type
)
3242 case AARCH64_OPND_ADDR_PCREL21
:
3244 ty
= entry
->adr_type
;
3248 ty
= entry
->ld_literal_type
;
3255 (_("this relocation modifier is not allowed on this "
3261 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3263 set_syntax_error (_("invalid relocation expression"));
3267 /* #:<reloc_op>:<expr> */
3268 /* Record the relocation type. */
3269 inst
.reloc
.type
= ty
;
3270 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3275 if (skip_past_char (&p
, '='))
3276 /* =immediate; need to generate the literal in the literal pool. */
3277 inst
.gen_lit_pool
= 1;
3279 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3281 set_syntax_error (_("invalid address"));
3292 /* Accept SP and reject ZR */
3293 reg
= aarch64_reg_parse_32_64 (&p
, 0, 1, &isreg32
, &isregzero
);
3294 if (reg
== PARSE_FAIL
|| isreg32
)
3296 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3299 operand
->addr
.base_regno
= reg
;
3302 if (skip_past_comma (&p
))
3305 operand
->addr
.preind
= 1;
3307 /* Reject SP and accept ZR */
3308 reg
= aarch64_reg_parse_32_64 (&p
, 1, 0, &isreg32
, &isregzero
);
3309 if (reg
!= PARSE_FAIL
)
3312 operand
->addr
.offset
.regno
= reg
;
3313 operand
->addr
.offset
.is_reg
= 1;
3314 /* Shifted index. */
3315 if (skip_past_comma (&p
))
3318 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3319 /* Use the diagnostics set in parse_shift, so not set new
3320 error message here. */
3324 [base,Xm{,LSL #imm}]
3325 [base,Xm,SXTX {#imm}]
3326 [base,Wm,(S|U)XTW {#imm}] */
3327 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3328 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3329 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3333 set_syntax_error (_("invalid use of 32-bit register offset"));
3339 set_syntax_error (_("invalid use of 64-bit register offset"));
3345 /* [Xn,#:<reloc_op>:<symbol> */
3346 skip_past_char (&p
, '#');
3347 if (reloc
&& skip_past_char (&p
, ':'))
3349 struct reloc_table_entry
*entry
;
3351 /* Try to parse a relocation modifier. Anything else is
3353 if (!(entry
= find_reloc_table_entry (&p
)))
3355 set_syntax_error (_("unknown relocation modifier"));
3359 if (entry
->ldst_type
== 0)
3362 (_("this relocation modifier is not allowed on this "
3367 /* [Xn,#:<reloc_op>: */
3368 /* We now have the group relocation table entry corresponding to
3369 the name in the assembler source. Next, we parse the
3371 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3373 set_syntax_error (_("invalid relocation expression"));
3377 /* [Xn,#:<reloc_op>:<expr> */
3378 /* Record the load/store relocation type. */
3379 inst
.reloc
.type
= entry
->ldst_type
;
3380 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3382 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3384 set_syntax_error (_("invalid expression in the address"));
3391 if (! skip_past_char (&p
, ']'))
3393 set_syntax_error (_("']' expected"));
3397 if (skip_past_char (&p
, '!'))
3399 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3401 set_syntax_error (_("register offset not allowed in pre-indexed "
3402 "addressing mode"));
3406 operand
->addr
.writeback
= 1;
3408 else if (skip_past_comma (&p
))
3411 operand
->addr
.postind
= 1;
3412 operand
->addr
.writeback
= 1;
3414 if (operand
->addr
.preind
)
3416 set_syntax_error (_("cannot combine pre- and post-indexing"));
3420 if (accept_reg_post_index
3421 && (reg
= aarch64_reg_parse_32_64 (&p
, 1, 1, &isreg32
,
3422 &isregzero
)) != PARSE_FAIL
)
3427 set_syntax_error (_("invalid 32-bit register offset"));
3430 operand
->addr
.offset
.regno
= reg
;
3431 operand
->addr
.offset
.is_reg
= 1;
3433 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3436 set_syntax_error (_("invalid expression in the address"));
3441 /* If at this point neither .preind nor .postind is set, we have a
3442 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3443 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3445 if (operand
->addr
.writeback
)
3448 set_syntax_error (_("missing offset in the pre-indexed address"));
3451 operand
->addr
.preind
= 1;
3452 inst
.reloc
.exp
.X_op
= O_constant
;
3453 inst
.reloc
.exp
.X_add_number
= 0;
3460 /* Return TRUE on success; otherwise return FALSE. */
3462 parse_address (char **str
, aarch64_opnd_info
*operand
,
3463 int accept_reg_post_index
)
3465 return parse_address_main (str
, operand
, 0, accept_reg_post_index
);
3468 /* Return TRUE on success; otherwise return FALSE. */
3470 parse_address_reloc (char **str
, aarch64_opnd_info
*operand
)
3472 return parse_address_main (str
, operand
, 1, 0);
3475 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3476 Return TRUE on success; otherwise return FALSE. */
3478 parse_half (char **str
, int *internal_fixup_p
)
3482 skip_past_char (&p
, '#');
3484 gas_assert (internal_fixup_p
);
3485 *internal_fixup_p
= 0;
3489 struct reloc_table_entry
*entry
;
3491 /* Try to parse a relocation. Anything else is an error. */
3493 if (!(entry
= find_reloc_table_entry (&p
)))
3495 set_syntax_error (_("unknown relocation modifier"));
3499 if (entry
->movw_type
== 0)
3502 (_("this relocation modifier is not allowed on this instruction"));
3506 inst
.reloc
.type
= entry
->movw_type
;
3509 *internal_fixup_p
= 1;
3511 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3518 /* Parse an operand for an ADRP instruction:
3520 Return TRUE on success; otherwise return FALSE. */
3523 parse_adrp (char **str
)
3530 struct reloc_table_entry
*entry
;
3532 /* Try to parse a relocation. Anything else is an error. */
3534 if (!(entry
= find_reloc_table_entry (&p
)))
3536 set_syntax_error (_("unknown relocation modifier"));
3540 if (entry
->adrp_type
== 0)
3543 (_("this relocation modifier is not allowed on this instruction"));
3547 inst
.reloc
.type
= entry
->adrp_type
;
3550 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3552 inst
.reloc
.pc_rel
= 1;
3554 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3561 /* Miscellaneous. */
3563 /* Parse an option for a preload instruction. Returns the encoding for the
3564 option, or PARSE_FAIL. */
3567 parse_pldop (char **str
)
3570 const struct aarch64_name_value_pair
*o
;
3573 while (ISALNUM (*q
))
3576 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3584 /* Parse an option for a barrier instruction. Returns the encoding for the
3585 option, or PARSE_FAIL. */
3588 parse_barrier (char **str
)
3591 const asm_barrier_opt
*o
;
3594 while (ISALPHA (*q
))
3597 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3605 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3606 return 0 if successful. Otherwise return PARSE_FAIL. */
3609 parse_barrier_psb (char **str
,
3610 const struct aarch64_name_value_pair
** hint_opt
)
3613 const struct aarch64_name_value_pair
*o
;
3616 while (ISALPHA (*q
))
3619 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3622 set_fatal_syntax_error
3623 ( _("unknown or missing option to PSB"));
3627 if (o
->value
!= 0x11)
3629 /* PSB only accepts option name 'CSYNC'. */
3631 (_("the specified option is not accepted for PSB"));
3640 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3641 Returns the encoding for the option, or PARSE_FAIL.
3643 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3644 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3646 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3647 field, otherwise as a system register.
3651 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3652 int imple_defined_p
, int pstatefield_p
)
3656 const aarch64_sys_reg
*o
;
3660 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3662 *p
++ = TOLOWER (*q
);
3664 /* Assert that BUF be large enough. */
3665 gas_assert (p
- buf
== q
- *str
);
3667 o
= hash_find (sys_regs
, buf
);
3670 if (!imple_defined_p
)
3674 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
3675 unsigned int op0
, op1
, cn
, cm
, op2
;
3677 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
3680 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
3682 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
3687 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
3688 as_bad (_("selected processor does not support PSTATE field "
3690 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
3691 as_bad (_("selected processor does not support system register "
3693 if (aarch64_sys_reg_deprecated_p (o
))
3694 as_warn (_("system register name '%s' is deprecated and may be "
3695 "removed in a future release"), buf
);
3703 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3704 for the option, or NULL. */
3706 static const aarch64_sys_ins_reg
*
3707 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
3711 const aarch64_sys_ins_reg
*o
;
3714 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
3716 *p
++ = TOLOWER (*q
);
3719 o
= hash_find (sys_ins_regs
, buf
);
3723 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
3724 as_bad (_("selected processor does not support system register "
3731 #define po_char_or_fail(chr) do { \
3732 if (! skip_past_char (&str, chr)) \
3736 #define po_reg_or_fail(regtype) do { \
3737 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3738 if (val == PARSE_FAIL) \
3740 set_default_error (); \
3745 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3746 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3747 &isreg32, &isregzero); \
3748 if (val == PARSE_FAIL) \
3750 set_default_error (); \
3753 info->reg.regno = val; \
3755 info->qualifier = AARCH64_OPND_QLF_W; \
3757 info->qualifier = AARCH64_OPND_QLF_X; \
3760 #define po_imm_nc_or_fail() do { \
3761 if (! parse_constant_immediate (&str, &val)) \
3765 #define po_imm_or_fail(min, max) do { \
3766 if (! parse_constant_immediate (&str, &val)) \
3768 if (val < min || val > max) \
3770 set_fatal_syntax_error (_("immediate value out of range "\
3771 #min " to "#max)); \
3776 #define po_misc_or_fail(expr) do { \
3781 /* encode the 12-bit imm field of Add/sub immediate */
3782 static inline uint32_t
3783 encode_addsub_imm (uint32_t imm
)
3788 /* encode the shift amount field of Add/sub immediate */
3789 static inline uint32_t
3790 encode_addsub_imm_shift_amount (uint32_t cnt
)
3796 /* encode the imm field of Adr instruction */
3797 static inline uint32_t
3798 encode_adr_imm (uint32_t imm
)
3800 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
3801 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3804 /* encode the immediate field of Move wide immediate */
3805 static inline uint32_t
3806 encode_movw_imm (uint32_t imm
)
3811 /* encode the 26-bit offset of unconditional branch */
3812 static inline uint32_t
3813 encode_branch_ofs_26 (uint32_t ofs
)
3815 return ofs
& ((1 << 26) - 1);
3818 /* encode the 19-bit offset of conditional branch and compare & branch */
3819 static inline uint32_t
3820 encode_cond_branch_ofs_19 (uint32_t ofs
)
3822 return (ofs
& ((1 << 19) - 1)) << 5;
3825 /* encode the 19-bit offset of ld literal */
3826 static inline uint32_t
3827 encode_ld_lit_ofs_19 (uint32_t ofs
)
3829 return (ofs
& ((1 << 19) - 1)) << 5;
3832 /* Encode the 14-bit offset of test & branch. */
3833 static inline uint32_t
3834 encode_tst_branch_ofs_14 (uint32_t ofs
)
3836 return (ofs
& ((1 << 14) - 1)) << 5;
3839 /* Encode the 16-bit imm field of svc/hvc/smc. */
3840 static inline uint32_t
3841 encode_svc_imm (uint32_t imm
)
3846 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3847 static inline uint32_t
3848 reencode_addsub_switch_add_sub (uint32_t opcode
)
3850 return opcode
^ (1 << 30);
3853 static inline uint32_t
3854 reencode_movzn_to_movz (uint32_t opcode
)
3856 return opcode
| (1 << 30);
3859 static inline uint32_t
3860 reencode_movzn_to_movn (uint32_t opcode
)
3862 return opcode
& ~(1 << 30);
3865 /* Overall per-instruction processing. */
3867 /* We need to be able to fix up arbitrary expressions in some statements.
3868 This is so that we can handle symbols that are an arbitrary distance from
3869 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3870 which returns part of an address in a form which will be valid for
3871 a data instruction. We do this by pushing the expression into a symbol
3872 in the expr_section, and creating a fix for that. */
3875 fix_new_aarch64 (fragS
* frag
,
3877 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
3887 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
3891 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
3898 /* Diagnostics on operands errors. */
3900 /* By default, output verbose error message.
3901 Disable the verbose error message by -mno-verbose-error. */
3902 static int verbose_error_p
= 1;
3904 #ifdef DEBUG_AARCH64
3905 /* N.B. this is only for the purpose of debugging. */
3906 const char* operand_mismatch_kind_names
[] =
3909 "AARCH64_OPDE_RECOVERABLE",
3910 "AARCH64_OPDE_SYNTAX_ERROR",
3911 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3912 "AARCH64_OPDE_INVALID_VARIANT",
3913 "AARCH64_OPDE_OUT_OF_RANGE",
3914 "AARCH64_OPDE_UNALIGNED",
3915 "AARCH64_OPDE_REG_LIST",
3916 "AARCH64_OPDE_OTHER_ERROR",
3918 #endif /* DEBUG_AARCH64 */
3920 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3922 When multiple errors of different kinds are found in the same assembly
3923 line, only the error of the highest severity will be picked up for
3924 issuing the diagnostics. */
3926 static inline bfd_boolean
3927 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
3928 enum aarch64_operand_error_kind rhs
)
3930 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
3931 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
3932 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
3933 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
3934 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
3935 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
3936 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
3937 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
3941 /* Helper routine to get the mnemonic name from the assembly instruction
3942 line; should only be called for the diagnosis purpose, as there is
3943 string copy operation involved, which may affect the runtime
3944 performance if used in elsewhere. */
3947 get_mnemonic_name (const char *str
)
3949 static char mnemonic
[32];
3952 /* Get the first 15 bytes and assume that the full name is included. */
3953 strncpy (mnemonic
, str
, 31);
3954 mnemonic
[31] = '\0';
3956 /* Scan up to the end of the mnemonic, which must end in white space,
3957 '.', or end of string. */
3958 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
3963 /* Append '...' to the truncated long name. */
3964 if (ptr
- mnemonic
== 31)
3965 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
3971 reset_aarch64_instruction (aarch64_instruction
*instruction
)
3973 memset (instruction
, '\0', sizeof (aarch64_instruction
));
3974 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
3977 /* Data strutures storing one user error in the assembly code related to
3980 struct operand_error_record
3982 const aarch64_opcode
*opcode
;
3983 aarch64_operand_error detail
;
3984 struct operand_error_record
*next
;
3987 typedef struct operand_error_record operand_error_record
;
3989 struct operand_errors
3991 operand_error_record
*head
;
3992 operand_error_record
*tail
;
3995 typedef struct operand_errors operand_errors
;
3997 /* Top-level data structure reporting user errors for the current line of
3999 The way md_assemble works is that all opcodes sharing the same mnemonic
4000 name are iterated to find a match to the assembly line. In this data
4001 structure, each of the such opcodes will have one operand_error_record
4002 allocated and inserted. In other words, excessive errors related with
4003 a single opcode are disregarded. */
4004 operand_errors operand_error_report
;
4006 /* Free record nodes. */
4007 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4009 /* Initialize the data structure that stores the operand mismatch
4010 information on assembling one line of the assembly code. */
4012 init_operand_error_report (void)
4014 if (operand_error_report
.head
!= NULL
)
4016 gas_assert (operand_error_report
.tail
!= NULL
);
4017 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4018 free_opnd_error_record_nodes
= operand_error_report
.head
;
4019 operand_error_report
.head
= NULL
;
4020 operand_error_report
.tail
= NULL
;
4023 gas_assert (operand_error_report
.tail
== NULL
);
4026 /* Return TRUE if some operand error has been recorded during the
4027 parsing of the current assembly line using the opcode *OPCODE;
4028 otherwise return FALSE. */
4029 static inline bfd_boolean
4030 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4032 operand_error_record
*record
= operand_error_report
.head
;
4033 return record
&& record
->opcode
== opcode
;
4036 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4037 OPCODE field is initialized with OPCODE.
4038 N.B. only one record for each opcode, i.e. the maximum of one error is
4039 recorded for each instruction template. */
4042 add_operand_error_record (const operand_error_record
* new_record
)
4044 const aarch64_opcode
*opcode
= new_record
->opcode
;
4045 operand_error_record
* record
= operand_error_report
.head
;
4047 /* The record may have been created for this opcode. If not, we need
4049 if (! opcode_has_operand_error_p (opcode
))
4051 /* Get one empty record. */
4052 if (free_opnd_error_record_nodes
== NULL
)
4054 record
= XNEW (operand_error_record
);
4058 record
= free_opnd_error_record_nodes
;
4059 free_opnd_error_record_nodes
= record
->next
;
4061 record
->opcode
= opcode
;
4062 /* Insert at the head. */
4063 record
->next
= operand_error_report
.head
;
4064 operand_error_report
.head
= record
;
4065 if (operand_error_report
.tail
== NULL
)
4066 operand_error_report
.tail
= record
;
4068 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4069 && record
->detail
.index
<= new_record
->detail
.index
4070 && operand_error_higher_severity_p (record
->detail
.kind
,
4071 new_record
->detail
.kind
))
4073 /* In the case of multiple errors found on operands related with a
4074 single opcode, only record the error of the leftmost operand and
4075 only if the error is of higher severity. */
4076 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4077 " the existing error %s on operand %d",
4078 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4079 new_record
->detail
.index
,
4080 operand_mismatch_kind_names
[record
->detail
.kind
],
4081 record
->detail
.index
);
4085 record
->detail
= new_record
->detail
;
4089 record_operand_error_info (const aarch64_opcode
*opcode
,
4090 aarch64_operand_error
*error_info
)
4092 operand_error_record record
;
4093 record
.opcode
= opcode
;
4094 record
.detail
= *error_info
;
4095 add_operand_error_record (&record
);
4098 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4099 error message *ERROR, for operand IDX (count from 0). */
4102 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4103 enum aarch64_operand_error_kind kind
,
4106 aarch64_operand_error info
;
4107 memset(&info
, 0, sizeof (info
));
4111 record_operand_error_info (opcode
, &info
);
4115 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4116 enum aarch64_operand_error_kind kind
,
4117 const char* error
, const int *extra_data
)
4119 aarch64_operand_error info
;
4123 info
.data
[0] = extra_data
[0];
4124 info
.data
[1] = extra_data
[1];
4125 info
.data
[2] = extra_data
[2];
4126 record_operand_error_info (opcode
, &info
);
4130 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4131 const char* error
, int lower_bound
,
4134 int data
[3] = {lower_bound
, upper_bound
, 0};
4135 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4139 /* Remove the operand error record for *OPCODE. */
4140 static void ATTRIBUTE_UNUSED
4141 remove_operand_error_record (const aarch64_opcode
*opcode
)
4143 if (opcode_has_operand_error_p (opcode
))
4145 operand_error_record
* record
= operand_error_report
.head
;
4146 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4147 operand_error_report
.head
= record
->next
;
4148 record
->next
= free_opnd_error_record_nodes
;
4149 free_opnd_error_record_nodes
= record
;
4150 if (operand_error_report
.head
== NULL
)
4152 gas_assert (operand_error_report
.tail
== record
);
4153 operand_error_report
.tail
= NULL
;
4158 /* Given the instruction in *INSTR, return the index of the best matched
4159 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4161 Return -1 if there is no qualifier sequence; return the first match
4162 if there is multiple matches found. */
4165 find_best_match (const aarch64_inst
*instr
,
4166 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4168 int i
, num_opnds
, max_num_matched
, idx
;
4170 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4173 DEBUG_TRACE ("no operand");
4177 max_num_matched
= 0;
4180 /* For each pattern. */
4181 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4184 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4186 /* Most opcodes has much fewer patterns in the list. */
4187 if (empty_qualifier_sequence_p (qualifiers
) == TRUE
)
4189 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4190 if (i
!= 0 && idx
== -1)
4191 /* If nothing has been matched, return the 1st sequence. */
4196 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4197 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4200 if (num_matched
> max_num_matched
)
4202 max_num_matched
= num_matched
;
4207 DEBUG_TRACE ("return with %d", idx
);
4211 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
4212 corresponding operands in *INSTR. */
4215 assign_qualifier_sequence (aarch64_inst
*instr
,
4216 const aarch64_opnd_qualifier_t
*qualifiers
)
4219 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4220 gas_assert (num_opnds
);
4221 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4222 instr
->operands
[i
].qualifier
= *qualifiers
;
4225 /* Print operands for the diagnosis purpose. */
4228 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4229 const aarch64_opnd_info
*opnds
)
4233 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4235 const size_t size
= 128;
4238 /* We regard the opcode operand info more, however we also look into
4239 the inst->operands to support the disassembling of the optional
4241 The two operand code should be the same in all cases, apart from
4242 when the operand can be optional. */
4243 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4244 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4247 /* Generate the operand string in STR. */
4248 aarch64_print_operand (str
, size
, 0, opcode
, opnds
, i
, NULL
, NULL
);
4252 strcat (buf
, i
== 0 ? " " : ",");
4254 /* Append the operand string. */
4259 /* Send to stderr a string as information. */
4262 output_info (const char *format
, ...)
4268 file
= as_where (&line
);
4272 fprintf (stderr
, "%s:%u: ", file
, line
);
4274 fprintf (stderr
, "%s: ", file
);
4276 fprintf (stderr
, _("Info: "));
4277 va_start (args
, format
);
4278 vfprintf (stderr
, format
, args
);
4280 (void) putc ('\n', stderr
);
4283 /* Output one operand error record. */
4286 output_operand_error_record (const operand_error_record
*record
, char *str
)
4288 const aarch64_operand_error
*detail
= &record
->detail
;
4289 int idx
= detail
->index
;
4290 const aarch64_opcode
*opcode
= record
->opcode
;
4291 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4292 : AARCH64_OPND_NIL
);
4294 switch (detail
->kind
)
4296 case AARCH64_OPDE_NIL
:
4300 case AARCH64_OPDE_SYNTAX_ERROR
:
4301 case AARCH64_OPDE_RECOVERABLE
:
4302 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4303 case AARCH64_OPDE_OTHER_ERROR
:
4304 /* Use the prepared error message if there is, otherwise use the
4305 operand description string to describe the error. */
4306 if (detail
->error
!= NULL
)
4309 as_bad (_("%s -- `%s'"), detail
->error
, str
);
4311 as_bad (_("%s at operand %d -- `%s'"),
4312 detail
->error
, idx
+ 1, str
);
4316 gas_assert (idx
>= 0);
4317 as_bad (_("operand %d should be %s -- `%s'"), idx
+ 1,
4318 aarch64_get_operand_desc (opd_code
), str
);
4322 case AARCH64_OPDE_INVALID_VARIANT
:
4323 as_bad (_("operand mismatch -- `%s'"), str
);
4324 if (verbose_error_p
)
4326 /* We will try to correct the erroneous instruction and also provide
4327 more information e.g. all other valid variants.
4329 The string representation of the corrected instruction and other
4330 valid variants are generated by
4332 1) obtaining the intermediate representation of the erroneous
4334 2) manipulating the IR, e.g. replacing the operand qualifier;
4335 3) printing out the instruction by calling the printer functions
4336 shared with the disassembler.
4338 The limitation of this method is that the exact input assembly
4339 line cannot be accurately reproduced in some cases, for example an
4340 optional operand present in the actual assembly line will be
4341 omitted in the output; likewise for the optional syntax rules,
4342 e.g. the # before the immediate. Another limitation is that the
4343 assembly symbols and relocation operations in the assembly line
4344 currently cannot be printed out in the error report. Last but not
4345 least, when there is other error(s) co-exist with this error, the
4346 'corrected' instruction may be still incorrect, e.g. given
4347 'ldnp h0,h1,[x0,#6]!'
4348 this diagnosis will provide the version:
4349 'ldnp s0,s1,[x0,#6]!'
4350 which is still not right. */
4351 size_t len
= strlen (get_mnemonic_name (str
));
4354 const size_t size
= 2048;
4356 aarch64_inst
*inst_base
= &inst
.base
;
4357 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4360 reset_aarch64_instruction (&inst
);
4361 inst_base
->opcode
= opcode
;
4363 /* Reset the error report so that there is no side effect on the
4364 following operand parsing. */
4365 init_operand_error_report ();
4368 result
= parse_operands (str
+ len
, opcode
)
4369 && programmer_friendly_fixup (&inst
);
4370 gas_assert (result
);
4371 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4373 gas_assert (!result
);
4375 /* Find the most matched qualifier sequence. */
4376 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4377 gas_assert (qlf_idx
> -1);
4379 /* Assign the qualifiers. */
4380 assign_qualifier_sequence (inst_base
,
4381 opcode
->qualifiers_list
[qlf_idx
]);
4383 /* Print the hint. */
4384 output_info (_(" did you mean this?"));
4385 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4386 print_operands (buf
, opcode
, inst_base
->operands
);
4387 output_info (_(" %s"), buf
);
4389 /* Print out other variant(s) if there is any. */
4391 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4392 output_info (_(" other valid variant(s):"));
4394 /* For each pattern. */
4395 qualifiers_list
= opcode
->qualifiers_list
;
4396 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4398 /* Most opcodes has much fewer patterns in the list.
4399 First NIL qualifier indicates the end in the list. */
4400 if (empty_qualifier_sequence_p (*qualifiers_list
) == TRUE
)
4405 /* Mnemonics name. */
4406 snprintf (buf
, size
, "\t%s", get_mnemonic_name (str
));
4408 /* Assign the qualifiers. */
4409 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4411 /* Print instruction. */
4412 print_operands (buf
, opcode
, inst_base
->operands
);
4414 output_info (_(" %s"), buf
);
4420 case AARCH64_OPDE_OUT_OF_RANGE
:
4421 if (detail
->data
[0] != detail
->data
[1])
4422 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
4423 detail
->error
? detail
->error
: _("immediate value"),
4424 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4426 as_bad (_("%s expected to be %d at operand %d -- `%s'"),
4427 detail
->error
? detail
->error
: _("immediate value"),
4428 detail
->data
[0], idx
+ 1, str
);
4431 case AARCH64_OPDE_REG_LIST
:
4432 if (detail
->data
[0] == 1)
4433 as_bad (_("invalid number of registers in the list; "
4434 "only 1 register is expected at operand %d -- `%s'"),
4437 as_bad (_("invalid number of registers in the list; "
4438 "%d registers are expected at operand %d -- `%s'"),
4439 detail
->data
[0], idx
+ 1, str
);
4442 case AARCH64_OPDE_UNALIGNED
:
4443 as_bad (_("immediate value should be a multiple of "
4444 "%d at operand %d -- `%s'"),
4445 detail
->data
[0], idx
+ 1, str
);
4454 /* Process and output the error message about the operand mismatching.
4456 When this function is called, the operand error information had
4457 been collected for an assembly line and there will be multiple
4458 errors in the case of mulitple instruction templates; output the
4459 error message that most closely describes the problem. */
4462 output_operand_error_report (char *str
)
4464 int largest_error_pos
;
4465 const char *msg
= NULL
;
4466 enum aarch64_operand_error_kind kind
;
4467 operand_error_record
*curr
;
4468 operand_error_record
*head
= operand_error_report
.head
;
4469 operand_error_record
*record
= NULL
;
4471 /* No error to report. */
4475 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4477 /* Only one error. */
4478 if (head
== operand_error_report
.tail
)
4480 DEBUG_TRACE ("single opcode entry with error kind: %s",
4481 operand_mismatch_kind_names
[head
->detail
.kind
]);
4482 output_operand_error_record (head
, str
);
4486 /* Find the error kind of the highest severity. */
4487 DEBUG_TRACE ("multiple opcode entres with error kind");
4488 kind
= AARCH64_OPDE_NIL
;
4489 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4491 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4492 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4493 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
))
4494 kind
= curr
->detail
.kind
;
4496 gas_assert (kind
!= AARCH64_OPDE_NIL
);
4498 /* Pick up one of errors of KIND to report. */
4499 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4500 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4502 if (curr
->detail
.kind
!= kind
)
4504 /* If there are multiple errors, pick up the one with the highest
4505 mismatching operand index. In the case of multiple errors with
4506 the equally highest operand index, pick up the first one or the
4507 first one with non-NULL error message. */
4508 if (curr
->detail
.index
> largest_error_pos
4509 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4510 && curr
->detail
.error
!= NULL
))
4512 largest_error_pos
= curr
->detail
.index
;
4514 msg
= record
->detail
.error
;
4518 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4519 DEBUG_TRACE ("Pick up error kind %s to report",
4520 operand_mismatch_kind_names
[record
->detail
.kind
]);
4523 output_operand_error_record (record
, str
);
4526 /* Write an AARCH64 instruction to buf - always little-endian. */
4528 put_aarch64_insn (char *buf
, uint32_t insn
)
4530 unsigned char *where
= (unsigned char *) buf
;
4532 where
[1] = insn
>> 8;
4533 where
[2] = insn
>> 16;
4534 where
[3] = insn
>> 24;
4538 get_aarch64_insn (char *buf
)
4540 unsigned char *where
= (unsigned char *) buf
;
4542 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4547 output_inst (struct aarch64_inst
*new_inst
)
4551 to
= frag_more (INSN_SIZE
);
4553 frag_now
->tc_frag_data
.recorded
= 1;
4555 put_aarch64_insn (to
, inst
.base
.value
);
4557 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4559 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4560 INSN_SIZE
, &inst
.reloc
.exp
,
4563 DEBUG_TRACE ("Prepared relocation fix up");
4564 /* Don't check the addend value against the instruction size,
4565 that's the job of our code in md_apply_fix(). */
4566 fixp
->fx_no_overflow
= 1;
4567 if (new_inst
!= NULL
)
4568 fixp
->tc_fix_data
.inst
= new_inst
;
4569 if (aarch64_gas_internal_fixup_p ())
4571 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4572 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4573 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4577 dwarf2_emit_insn (INSN_SIZE
);
4580 /* Link together opcodes of the same name. */
4584 aarch64_opcode
*opcode
;
4585 struct templates
*next
;
4588 typedef struct templates templates
;
4591 lookup_mnemonic (const char *start
, int len
)
4593 templates
*templ
= NULL
;
4595 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4599 /* Subroutine of md_assemble, responsible for looking up the primary
4600 opcode from the mnemonic the user wrote. STR points to the
4601 beginning of the mnemonic. */
4604 opcode_lookup (char **str
)
4607 const aarch64_cond
*cond
;
4611 /* Scan up to the end of the mnemonic, which must end in white space,
4612 '.', or end of string. */
4613 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4620 inst
.cond
= COND_ALWAYS
;
4622 /* Handle a possible condition. */
4625 cond
= hash_find_n (aarch64_cond_hsh
, end
+ 1, 2);
4628 inst
.cond
= cond
->value
;
4642 if (inst
.cond
== COND_ALWAYS
)
4644 /* Look for unaffixed mnemonic. */
4645 return lookup_mnemonic (base
, len
);
4649 /* append ".c" to mnemonic if conditional */
4650 memcpy (condname
, base
, len
);
4651 memcpy (condname
+ len
, ".c", 2);
4654 return lookup_mnemonic (base
, len
);
4660 /* Internal helper routine converting a vector neon_type_el structure
4661 *VECTYPE to a corresponding operand qualifier. */
4663 static inline aarch64_opnd_qualifier_t
4664 vectype_to_qualifier (const struct neon_type_el
*vectype
)
4666 /* Element size in bytes indexed by neon_el_type. */
4667 const unsigned char ele_size
[5]
4669 const unsigned int ele_base
[5] =
4671 AARCH64_OPND_QLF_V_8B
,
4672 AARCH64_OPND_QLF_V_2H
,
4673 AARCH64_OPND_QLF_V_2S
,
4674 AARCH64_OPND_QLF_V_1D
,
4675 AARCH64_OPND_QLF_V_1Q
4678 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
4679 goto vectype_conversion_fail
;
4681 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
4683 if (vectype
->defined
& NTA_HASINDEX
)
4684 /* Vector element register. */
4685 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
4688 /* Vector register. */
4689 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
4692 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
4693 goto vectype_conversion_fail
;
4695 /* The conversion is by calculating the offset from the base operand
4696 qualifier for the vector type. The operand qualifiers are regular
4697 enough that the offset can established by shifting the vector width by
4698 a vector-type dependent amount. */
4700 if (vectype
->type
== NT_b
)
4702 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
4704 else if (vectype
->type
>= NT_d
)
4709 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
4710 gas_assert (AARCH64_OPND_QLF_V_8B
<= offset
4711 && offset
<= AARCH64_OPND_QLF_V_1Q
);
4715 vectype_conversion_fail
:
4716 first_error (_("bad vector arrangement type"));
4717 return AARCH64_OPND_QLF_NIL
;
4720 /* Process an optional operand that is found omitted from the assembly line.
4721 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4722 instruction's opcode entry while IDX is the index of this omitted operand.
4726 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
4727 int idx
, aarch64_opnd_info
*operand
)
4729 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
4730 gas_assert (optional_operand_p (opcode
, idx
));
4731 gas_assert (!operand
->present
);
4735 case AARCH64_OPND_Rd
:
4736 case AARCH64_OPND_Rn
:
4737 case AARCH64_OPND_Rm
:
4738 case AARCH64_OPND_Rt
:
4739 case AARCH64_OPND_Rt2
:
4740 case AARCH64_OPND_Rs
:
4741 case AARCH64_OPND_Ra
:
4742 case AARCH64_OPND_Rt_SYS
:
4743 case AARCH64_OPND_Rd_SP
:
4744 case AARCH64_OPND_Rn_SP
:
4745 case AARCH64_OPND_Fd
:
4746 case AARCH64_OPND_Fn
:
4747 case AARCH64_OPND_Fm
:
4748 case AARCH64_OPND_Fa
:
4749 case AARCH64_OPND_Ft
:
4750 case AARCH64_OPND_Ft2
:
4751 case AARCH64_OPND_Sd
:
4752 case AARCH64_OPND_Sn
:
4753 case AARCH64_OPND_Sm
:
4754 case AARCH64_OPND_Vd
:
4755 case AARCH64_OPND_Vn
:
4756 case AARCH64_OPND_Vm
:
4757 case AARCH64_OPND_VdD1
:
4758 case AARCH64_OPND_VnD1
:
4759 operand
->reg
.regno
= default_value
;
4762 case AARCH64_OPND_Ed
:
4763 case AARCH64_OPND_En
:
4764 case AARCH64_OPND_Em
:
4765 operand
->reglane
.regno
= default_value
;
4768 case AARCH64_OPND_IDX
:
4769 case AARCH64_OPND_BIT_NUM
:
4770 case AARCH64_OPND_IMMR
:
4771 case AARCH64_OPND_IMMS
:
4772 case AARCH64_OPND_SHLL_IMM
:
4773 case AARCH64_OPND_IMM_VLSL
:
4774 case AARCH64_OPND_IMM_VLSR
:
4775 case AARCH64_OPND_CCMP_IMM
:
4776 case AARCH64_OPND_FBITS
:
4777 case AARCH64_OPND_UIMM4
:
4778 case AARCH64_OPND_UIMM3_OP1
:
4779 case AARCH64_OPND_UIMM3_OP2
:
4780 case AARCH64_OPND_IMM
:
4781 case AARCH64_OPND_WIDTH
:
4782 case AARCH64_OPND_UIMM7
:
4783 case AARCH64_OPND_NZCV
:
4784 operand
->imm
.value
= default_value
;
4787 case AARCH64_OPND_EXCEPTION
:
4788 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
4791 case AARCH64_OPND_BARRIER_ISB
:
4792 operand
->barrier
= aarch64_barrier_options
+ default_value
;
4799 /* Process the relocation type for move wide instructions.
4800 Return TRUE on success; otherwise return FALSE. */
4803 process_movw_reloc_info (void)
4808 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
4810 if (inst
.base
.opcode
->op
== OP_MOVK
)
4811 switch (inst
.reloc
.type
)
4813 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4814 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4815 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4816 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4817 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4818 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4819 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4821 (_("the specified relocation type is not allowed for MOVK"));
4827 switch (inst
.reloc
.type
)
4829 case BFD_RELOC_AARCH64_MOVW_G0
:
4830 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
4831 case BFD_RELOC_AARCH64_MOVW_G0_S
:
4832 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
4833 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
4834 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
4835 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
4836 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
4837 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
4838 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
4839 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
4842 case BFD_RELOC_AARCH64_MOVW_G1
:
4843 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
4844 case BFD_RELOC_AARCH64_MOVW_G1_S
:
4845 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
4846 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
4847 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
4848 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
4849 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
4850 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
4851 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
4852 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
4855 case BFD_RELOC_AARCH64_MOVW_G2
:
4856 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
4857 case BFD_RELOC_AARCH64_MOVW_G2_S
:
4858 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
4859 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
4862 set_fatal_syntax_error
4863 (_("the specified relocation type is not allowed for 32-bit "
4869 case BFD_RELOC_AARCH64_MOVW_G3
:
4872 set_fatal_syntax_error
4873 (_("the specified relocation type is not allowed for 32-bit "
4880 /* More cases should be added when more MOVW-related relocation types
4881 are supported in GAS. */
4882 gas_assert (aarch64_gas_internal_fixup_p ());
4883 /* The shift amount should have already been set by the parser. */
4886 inst
.base
.operands
[1].shifter
.amount
= shift
;
4890 /* A primitive log caculator. */
4892 static inline unsigned int
4893 get_logsz (unsigned int size
)
4895 const unsigned char ls
[16] =
4896 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4902 gas_assert (ls
[size
- 1] != (unsigned char)-1);
4903 return ls
[size
- 1];
4906 /* Determine and return the real reloc type code for an instruction
4907 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4909 static inline bfd_reloc_code_real_type
4910 ldst_lo12_determine_real_reloc_type (void)
4913 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
4914 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
4916 const bfd_reloc_code_real_type reloc_ldst_lo12
[3][5] = {
4918 BFD_RELOC_AARCH64_LDST8_LO12
,
4919 BFD_RELOC_AARCH64_LDST16_LO12
,
4920 BFD_RELOC_AARCH64_LDST32_LO12
,
4921 BFD_RELOC_AARCH64_LDST64_LO12
,
4922 BFD_RELOC_AARCH64_LDST128_LO12
4925 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
4926 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
4927 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
4928 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
4929 BFD_RELOC_AARCH64_NONE
4932 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
4933 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
4934 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
4935 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
4936 BFD_RELOC_AARCH64_NONE
4940 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
4941 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4943 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
));
4944 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
4946 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
4948 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
4950 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
4952 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
4953 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
4954 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
4955 gas_assert (logsz
<= 3);
4957 gas_assert (logsz
<= 4);
4959 /* In reloc.c, these pseudo relocation types should be defined in similar
4960 order as above reloc_ldst_lo12 array. Because the array index calcuation
4961 below relies on this. */
4962 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
4965 /* Check whether a register list REGINFO is valid. The registers must be
4966 numbered in increasing order (modulo 32), in increments of one or two.
4968 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4971 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4974 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
4976 uint32_t i
, nb_regs
, prev_regno
, incr
;
4978 nb_regs
= 1 + (reginfo
& 0x3);
4980 prev_regno
= reginfo
& 0x1f;
4981 incr
= accept_alternate
? 2 : 1;
4983 for (i
= 1; i
< nb_regs
; ++i
)
4985 uint32_t curr_regno
;
4987 curr_regno
= reginfo
& 0x1f;
4988 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
4990 prev_regno
= curr_regno
;
4996 /* Generic instruction operand parser. This does no encoding and no
4997 semantic validation; it merely squirrels values away in the inst
4998 structure. Returns TRUE or FALSE depending on whether the
4999 specified grammar matched. */
5002 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5005 char *backtrack_pos
= 0;
5006 const enum aarch64_opnd
*operands
= opcode
->operands
;
5009 skip_whitespace (str
);
5011 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5014 int isreg32
, isregzero
;
5015 int comma_skipped_p
= 0;
5016 aarch64_reg_type rtype
;
5017 struct neon_type_el vectype
;
5018 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5020 DEBUG_TRACE ("parse operand %d", i
);
5022 /* Assign the operand code. */
5023 info
->type
= operands
[i
];
5025 if (optional_operand_p (opcode
, i
))
5027 /* Remember where we are in case we need to backtrack. */
5028 gas_assert (!backtrack_pos
);
5029 backtrack_pos
= str
;
5032 /* Expect comma between operands; the backtrack mechanizm will take
5033 care of cases of omitted optional operand. */
5034 if (i
> 0 && ! skip_past_char (&str
, ','))
5036 set_syntax_error (_("comma expected between operands"));
5040 comma_skipped_p
= 1;
5042 switch (operands
[i
])
5044 case AARCH64_OPND_Rd
:
5045 case AARCH64_OPND_Rn
:
5046 case AARCH64_OPND_Rm
:
5047 case AARCH64_OPND_Rt
:
5048 case AARCH64_OPND_Rt2
:
5049 case AARCH64_OPND_Rs
:
5050 case AARCH64_OPND_Ra
:
5051 case AARCH64_OPND_Rt_SYS
:
5052 case AARCH64_OPND_PAIRREG
:
5053 po_int_reg_or_fail (1, 0);
5056 case AARCH64_OPND_Rd_SP
:
5057 case AARCH64_OPND_Rn_SP
:
5058 po_int_reg_or_fail (0, 1);
5061 case AARCH64_OPND_Rm_EXT
:
5062 case AARCH64_OPND_Rm_SFT
:
5063 po_misc_or_fail (parse_shifter_operand
5064 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5066 : SHIFTED_LOGIC_IMM
)));
5067 if (!info
->shifter
.operator_present
)
5069 /* Default to LSL if not present. Libopcodes prefers shifter
5070 kind to be explicit. */
5071 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5072 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5073 /* For Rm_EXT, libopcodes will carry out further check on whether
5074 or not stack pointer is used in the instruction (Recall that
5075 "the extend operator is not optional unless at least one of
5076 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5080 case AARCH64_OPND_Fd
:
5081 case AARCH64_OPND_Fn
:
5082 case AARCH64_OPND_Fm
:
5083 case AARCH64_OPND_Fa
:
5084 case AARCH64_OPND_Ft
:
5085 case AARCH64_OPND_Ft2
:
5086 case AARCH64_OPND_Sd
:
5087 case AARCH64_OPND_Sn
:
5088 case AARCH64_OPND_Sm
:
5089 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5090 if (val
== PARSE_FAIL
)
5092 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5095 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5097 info
->reg
.regno
= val
;
5098 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5101 case AARCH64_OPND_Vd
:
5102 case AARCH64_OPND_Vn
:
5103 case AARCH64_OPND_Vm
:
5104 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5105 if (val
== PARSE_FAIL
)
5107 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5110 if (vectype
.defined
& NTA_HASINDEX
)
5113 info
->reg
.regno
= val
;
5114 info
->qualifier
= vectype_to_qualifier (&vectype
);
5115 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5119 case AARCH64_OPND_VdD1
:
5120 case AARCH64_OPND_VnD1
:
5121 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5122 if (val
== PARSE_FAIL
)
5124 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5127 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5129 set_fatal_syntax_error
5130 (_("the top half of a 128-bit FP/SIMD register is expected"));
5133 info
->reg
.regno
= val
;
5134 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5135 here; it is correct for the purpose of encoding/decoding since
5136 only the register number is explicitly encoded in the related
5137 instructions, although this appears a bit hacky. */
5138 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5141 case AARCH64_OPND_Ed
:
5142 case AARCH64_OPND_En
:
5143 case AARCH64_OPND_Em
:
5144 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5145 if (val
== PARSE_FAIL
)
5147 first_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5150 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5153 info
->reglane
.regno
= val
;
5154 info
->reglane
.index
= vectype
.index
;
5155 info
->qualifier
= vectype_to_qualifier (&vectype
);
5156 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5160 case AARCH64_OPND_LVn
:
5161 case AARCH64_OPND_LVt
:
5162 case AARCH64_OPND_LVt_AL
:
5163 case AARCH64_OPND_LEt
:
5164 if ((val
= parse_neon_reg_list (&str
, &vectype
)) == PARSE_FAIL
)
5166 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5168 set_fatal_syntax_error (_("invalid register list"));
5171 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5172 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5173 if (operands
[i
] == AARCH64_OPND_LEt
)
5175 if (!(vectype
.defined
& NTA_HASINDEX
))
5177 info
->reglist
.has_index
= 1;
5178 info
->reglist
.index
= vectype
.index
;
5180 else if (!(vectype
.defined
& NTA_HASTYPE
))
5182 info
->qualifier
= vectype_to_qualifier (&vectype
);
5183 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5187 case AARCH64_OPND_Cn
:
5188 case AARCH64_OPND_Cm
:
5189 po_reg_or_fail (REG_TYPE_CN
);
5192 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN
)));
5195 inst
.base
.operands
[i
].reg
.regno
= val
;
5198 case AARCH64_OPND_SHLL_IMM
:
5199 case AARCH64_OPND_IMM_VLSR
:
5200 po_imm_or_fail (1, 64);
5201 info
->imm
.value
= val
;
5204 case AARCH64_OPND_CCMP_IMM
:
5205 case AARCH64_OPND_FBITS
:
5206 case AARCH64_OPND_UIMM4
:
5207 case AARCH64_OPND_UIMM3_OP1
:
5208 case AARCH64_OPND_UIMM3_OP2
:
5209 case AARCH64_OPND_IMM_VLSL
:
5210 case AARCH64_OPND_IMM
:
5211 case AARCH64_OPND_WIDTH
:
5212 po_imm_nc_or_fail ();
5213 info
->imm
.value
= val
;
5216 case AARCH64_OPND_UIMM7
:
5217 po_imm_or_fail (0, 127);
5218 info
->imm
.value
= val
;
5221 case AARCH64_OPND_IDX
:
5222 case AARCH64_OPND_BIT_NUM
:
5223 case AARCH64_OPND_IMMR
:
5224 case AARCH64_OPND_IMMS
:
5225 po_imm_or_fail (0, 63);
5226 info
->imm
.value
= val
;
5229 case AARCH64_OPND_IMM0
:
5230 po_imm_nc_or_fail ();
5233 set_fatal_syntax_error (_("immediate zero expected"));
5236 info
->imm
.value
= 0;
5239 case AARCH64_OPND_FPIMM0
:
5242 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5243 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5244 it is probably not worth the effort to support it. */
5245 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
))
5246 && !(res2
= parse_constant_immediate (&str
, &val
)))
5248 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5250 info
->imm
.value
= 0;
5251 info
->imm
.is_fp
= 1;
5254 set_fatal_syntax_error (_("immediate zero expected"));
5258 case AARCH64_OPND_IMM_MOV
:
5261 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5262 reg_name_p (str
, REG_TYPE_VN
))
5265 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5267 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5268 later. fix_mov_imm_insn will try to determine a machine
5269 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5270 message if the immediate cannot be moved by a single
5272 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5273 inst
.base
.operands
[i
].skip
= 1;
5277 case AARCH64_OPND_SIMD_IMM
:
5278 case AARCH64_OPND_SIMD_IMM_SFT
:
5279 if (! parse_big_immediate (&str
, &val
))
5281 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5283 /* need_libopcodes_p */ 1,
5286 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5287 shift, we don't check it here; we leave the checking to
5288 the libopcodes (operand_general_constraint_met_p). By
5289 doing this, we achieve better diagnostics. */
5290 if (skip_past_comma (&str
)
5291 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5293 if (!info
->shifter
.operator_present
5294 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5296 /* Default to LSL if not present. Libopcodes prefers shifter
5297 kind to be explicit. */
5298 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5299 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5303 case AARCH64_OPND_FPIMM
:
5304 case AARCH64_OPND_SIMD_FPIMM
:
5308 = (aarch64_get_qualifier_esize (inst
.base
.operands
[0].qualifier
)
5310 if (! parse_aarch64_imm_float (&str
, &qfloat
, dp_p
))
5314 set_fatal_syntax_error (_("invalid floating-point constant"));
5317 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5318 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5322 case AARCH64_OPND_LIMM
:
5323 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5324 SHIFTED_LOGIC_IMM
));
5325 if (info
->shifter
.operator_present
)
5327 set_fatal_syntax_error
5328 (_("shift not allowed for bitmask immediate"));
5331 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5333 /* need_libopcodes_p */ 1,
5337 case AARCH64_OPND_AIMM
:
5338 if (opcode
->op
== OP_ADD
)
5339 /* ADD may have relocation types. */
5340 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5341 SHIFTED_ARITH_IMM
));
5343 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5344 SHIFTED_ARITH_IMM
));
5345 switch (inst
.reloc
.type
)
5347 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5348 info
->shifter
.amount
= 12;
5350 case BFD_RELOC_UNUSED
:
5351 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5352 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5353 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5354 inst
.reloc
.pc_rel
= 0;
5359 info
->imm
.value
= 0;
5360 if (!info
->shifter
.operator_present
)
5362 /* Default to LSL if not present. Libopcodes prefers shifter
5363 kind to be explicit. */
5364 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5365 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5369 case AARCH64_OPND_HALF
:
5371 /* #<imm16> or relocation. */
5372 int internal_fixup_p
;
5373 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
5374 if (internal_fixup_p
)
5375 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5376 skip_whitespace (str
);
5377 if (skip_past_comma (&str
))
5379 /* {, LSL #<shift>} */
5380 if (! aarch64_gas_internal_fixup_p ())
5382 set_fatal_syntax_error (_("can't mix relocation modifier "
5383 "with explicit shift"));
5386 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5389 inst
.base
.operands
[i
].shifter
.amount
= 0;
5390 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5391 inst
.base
.operands
[i
].imm
.value
= 0;
5392 if (! process_movw_reloc_info ())
5397 case AARCH64_OPND_EXCEPTION
:
5398 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
));
5399 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5401 /* need_libopcodes_p */ 0,
5405 case AARCH64_OPND_NZCV
:
5407 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
5411 info
->imm
.value
= nzcv
->value
;
5414 po_imm_or_fail (0, 15);
5415 info
->imm
.value
= val
;
5419 case AARCH64_OPND_COND
:
5420 case AARCH64_OPND_COND1
:
5421 info
->cond
= hash_find_n (aarch64_cond_hsh
, str
, 2);
5423 if (info
->cond
== NULL
)
5425 set_syntax_error (_("invalid condition"));
5428 else if (operands
[i
] == AARCH64_OPND_COND1
5429 && (info
->cond
->value
& 0xe) == 0xe)
5431 /* Not allow AL or NV. */
5432 set_default_error ();
5437 case AARCH64_OPND_ADDR_ADRP
:
5438 po_misc_or_fail (parse_adrp (&str
));
5439 /* Clear the value as operand needs to be relocated. */
5440 info
->imm
.value
= 0;
5443 case AARCH64_OPND_ADDR_PCREL14
:
5444 case AARCH64_OPND_ADDR_PCREL19
:
5445 case AARCH64_OPND_ADDR_PCREL21
:
5446 case AARCH64_OPND_ADDR_PCREL26
:
5447 po_misc_or_fail (parse_address_reloc (&str
, info
));
5448 if (!info
->addr
.pcrel
)
5450 set_syntax_error (_("invalid pc-relative address"));
5453 if (inst
.gen_lit_pool
5454 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
5456 /* Only permit "=value" in the literal load instructions.
5457 The literal will be generated by programmer_friendly_fixup. */
5458 set_syntax_error (_("invalid use of \"=immediate\""));
5461 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
5463 set_syntax_error (_("unrecognized relocation suffix"));
5466 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
5468 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
5469 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5473 info
->imm
.value
= 0;
5474 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5475 switch (opcode
->iclass
)
5479 /* e.g. CBZ or B.COND */
5480 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5481 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
5485 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
5486 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
5490 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
5492 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
5493 : BFD_RELOC_AARCH64_JUMP26
;
5496 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
5497 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
5500 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
5501 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
5507 inst
.reloc
.pc_rel
= 1;
5511 case AARCH64_OPND_ADDR_SIMPLE
:
5512 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
5513 /* [<Xn|SP>{, #<simm>}] */
5514 po_char_or_fail ('[');
5515 po_reg_or_fail (REG_TYPE_R64_SP
);
5516 /* Accept optional ", #0". */
5517 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
5518 && skip_past_char (&str
, ','))
5520 skip_past_char (&str
, '#');
5521 if (! skip_past_char (&str
, '0'))
5523 set_fatal_syntax_error
5524 (_("the optional immediate offset can only be 0"));
5528 po_char_or_fail (']');
5529 info
->addr
.base_regno
= val
;
5532 case AARCH64_OPND_ADDR_REGOFF
:
5533 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5534 po_misc_or_fail (parse_address (&str
, info
, 0));
5535 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
5536 || !info
->addr
.preind
|| info
->addr
.postind
5537 || info
->addr
.writeback
)
5539 set_syntax_error (_("invalid addressing mode"));
5542 if (!info
->shifter
.operator_present
)
5544 /* Default to LSL if not present. Libopcodes prefers shifter
5545 kind to be explicit. */
5546 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5547 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5549 /* Qualifier to be deduced by libopcodes. */
5552 case AARCH64_OPND_ADDR_SIMM7
:
5553 po_misc_or_fail (parse_address (&str
, info
, 0));
5554 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5555 || (!info
->addr
.preind
&& !info
->addr
.postind
))
5557 set_syntax_error (_("invalid addressing mode"));
5560 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5562 /* need_libopcodes_p */ 1,
5566 case AARCH64_OPND_ADDR_SIMM9
:
5567 case AARCH64_OPND_ADDR_SIMM9_2
:
5568 po_misc_or_fail (parse_address_reloc (&str
, info
));
5569 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5570 || (!info
->addr
.preind
&& !info
->addr
.postind
)
5571 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
5572 && info
->addr
.writeback
))
5574 set_syntax_error (_("invalid addressing mode"));
5577 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5579 set_syntax_error (_("relocation not allowed"));
5582 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5584 /* need_libopcodes_p */ 1,
5588 case AARCH64_OPND_ADDR_UIMM12
:
5589 po_misc_or_fail (parse_address_reloc (&str
, info
));
5590 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
5591 || !info
->addr
.preind
|| info
->addr
.writeback
)
5593 set_syntax_error (_("invalid addressing mode"));
5596 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5597 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5598 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5600 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
5602 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
))
5603 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
5604 /* Leave qualifier to be determined by libopcodes. */
5607 case AARCH64_OPND_SIMD_ADDR_POST
:
5608 /* [<Xn|SP>], <Xm|#<amount>> */
5609 po_misc_or_fail (parse_address (&str
, info
, 1));
5610 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
5612 set_syntax_error (_("invalid addressing mode"));
5615 if (!info
->addr
.offset
.is_reg
)
5617 if (inst
.reloc
.exp
.X_op
== O_constant
)
5618 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
5621 set_fatal_syntax_error
5622 (_("writeback value should be an immediate constant"));
5629 case AARCH64_OPND_SYSREG
:
5630 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0))
5633 set_syntax_error (_("unknown or missing system register name"));
5636 inst
.base
.operands
[i
].sysreg
= val
;
5639 case AARCH64_OPND_PSTATEFIELD
:
5640 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1))
5643 set_syntax_error (_("unknown or missing PSTATE field name"));
5646 inst
.base
.operands
[i
].pstatefield
= val
;
5649 case AARCH64_OPND_SYSREG_IC
:
5650 inst
.base
.operands
[i
].sysins_op
=
5651 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
5653 case AARCH64_OPND_SYSREG_DC
:
5654 inst
.base
.operands
[i
].sysins_op
=
5655 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
5657 case AARCH64_OPND_SYSREG_AT
:
5658 inst
.base
.operands
[i
].sysins_op
=
5659 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
5661 case AARCH64_OPND_SYSREG_TLBI
:
5662 inst
.base
.operands
[i
].sysins_op
=
5663 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
5665 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
5667 set_fatal_syntax_error ( _("unknown or missing operation name"));
5672 case AARCH64_OPND_BARRIER
:
5673 case AARCH64_OPND_BARRIER_ISB
:
5674 val
= parse_barrier (&str
);
5675 if (val
!= PARSE_FAIL
5676 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
5678 /* ISB only accepts options name 'sy'. */
5680 (_("the specified option is not accepted in ISB"));
5681 /* Turn off backtrack as this optional operand is present. */
5685 /* This is an extension to accept a 0..15 immediate. */
5686 if (val
== PARSE_FAIL
)
5687 po_imm_or_fail (0, 15);
5688 info
->barrier
= aarch64_barrier_options
+ val
;
5691 case AARCH64_OPND_PRFOP
:
5692 val
= parse_pldop (&str
);
5693 /* This is an extension to accept a 0..31 immediate. */
5694 if (val
== PARSE_FAIL
)
5695 po_imm_or_fail (0, 31);
5696 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
5699 case AARCH64_OPND_BARRIER_PSB
:
5700 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
5701 if (val
== PARSE_FAIL
)
5706 as_fatal (_("unhandled operand code %d"), operands
[i
]);
5709 /* If we get here, this operand was successfully parsed. */
5710 inst
.base
.operands
[i
].present
= 1;
5714 /* The parse routine should already have set the error, but in case
5715 not, set a default one here. */
5717 set_default_error ();
5719 if (! backtrack_pos
)
5720 goto parse_operands_return
;
5723 /* We reach here because this operand is marked as optional, and
5724 either no operand was supplied or the operand was supplied but it
5725 was syntactically incorrect. In the latter case we report an
5726 error. In the former case we perform a few more checks before
5727 dropping through to the code to insert the default operand. */
5729 char *tmp
= backtrack_pos
;
5730 char endchar
= END_OF_INSN
;
5732 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
5734 skip_past_char (&tmp
, ',');
5736 if (*tmp
!= endchar
)
5737 /* The user has supplied an operand in the wrong format. */
5738 goto parse_operands_return
;
5740 /* Make sure there is not a comma before the optional operand.
5741 For example the fifth operand of 'sys' is optional:
5743 sys #0,c0,c0,#0, <--- wrong
5744 sys #0,c0,c0,#0 <--- correct. */
5745 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
5747 set_fatal_syntax_error
5748 (_("unexpected comma before the omitted optional operand"));
5749 goto parse_operands_return
;
5753 /* Reaching here means we are dealing with an optional operand that is
5754 omitted from the assembly line. */
5755 gas_assert (optional_operand_p (opcode
, i
));
5757 process_omitted_operand (operands
[i
], opcode
, i
, info
);
5759 /* Try again, skipping the optional operand at backtrack_pos. */
5760 str
= backtrack_pos
;
5763 /* Clear any error record after the omitted optional operand has been
5764 successfully handled. */
5768 /* Check if we have parsed all the operands. */
5769 if (*str
!= '\0' && ! error_p ())
5771 /* Set I to the index of the last present operand; this is
5772 for the purpose of diagnostics. */
5773 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
5775 set_fatal_syntax_error
5776 (_("unexpected characters following instruction"));
5779 parse_operands_return
:
5783 DEBUG_TRACE ("parsing FAIL: %s - %s",
5784 operand_mismatch_kind_names
[get_error_kind ()],
5785 get_error_message ());
5786 /* Record the operand error properly; this is useful when there
5787 are multiple instruction templates for a mnemonic name, so that
5788 later on, we can select the error that most closely describes
5790 record_operand_error (opcode
, i
, get_error_kind (),
5791 get_error_message ());
5796 DEBUG_TRACE ("parsing SUCCESS");
5801 /* It does some fix-up to provide some programmer friendly feature while
5802 keeping the libopcodes happy, i.e. libopcodes only accepts
5803 the preferred architectural syntax.
5804 Return FALSE if there is any failure; otherwise return TRUE. */
5807 programmer_friendly_fixup (aarch64_instruction
*instr
)
5809 aarch64_inst
*base
= &instr
->base
;
5810 const aarch64_opcode
*opcode
= base
->opcode
;
5811 enum aarch64_op op
= opcode
->op
;
5812 aarch64_opnd_info
*operands
= base
->operands
;
5814 DEBUG_TRACE ("enter");
5816 switch (opcode
->iclass
)
5819 /* TBNZ Xn|Wn, #uimm6, label
5820 Test and Branch Not Zero: conditionally jumps to label if bit number
5821 uimm6 in register Xn is not zero. The bit number implies the width of
5822 the register, which may be written and should be disassembled as Wn if
5823 uimm is less than 32. */
5824 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
5826 if (operands
[1].imm
.value
>= 32)
5828 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
5832 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
5836 /* LDR Wt, label | =value
5837 As a convenience assemblers will typically permit the notation
5838 "=value" in conjunction with the pc-relative literal load instructions
5839 to automatically place an immediate value or symbolic address in a
5840 nearby literal pool and generate a hidden label which references it.
5841 ISREG has been set to 0 in the case of =value. */
5842 if (instr
->gen_lit_pool
5843 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
5845 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
5846 if (op
== OP_LDRSW_LIT
)
5848 if (instr
->reloc
.exp
.X_op
!= O_constant
5849 && instr
->reloc
.exp
.X_op
!= O_big
5850 && instr
->reloc
.exp
.X_op
!= O_symbol
)
5852 record_operand_error (opcode
, 1,
5853 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
5854 _("constant expression expected"));
5857 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
5859 record_operand_error (opcode
, 1,
5860 AARCH64_OPDE_OTHER_ERROR
,
5861 _("literal pool insertion failed"));
5869 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5870 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5871 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5872 A programmer-friendly assembler should accept a destination Xd in
5873 place of Wd, however that is not the preferred form for disassembly.
5875 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
5876 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
5877 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
5878 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
5883 /* In the 64-bit form, the final register operand is written as Wm
5884 for all but the (possibly omitted) UXTX/LSL and SXTX
5886 As a programmer-friendly assembler, we accept e.g.
5887 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5888 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5889 int idx
= aarch64_operand_index (opcode
->operands
,
5890 AARCH64_OPND_Rm_EXT
);
5891 gas_assert (idx
== 1 || idx
== 2);
5892 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
5893 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
5894 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
5895 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
5896 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
5897 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
5905 DEBUG_TRACE ("exit with SUCCESS");
5909 /* Check for loads and stores that will cause unpredictable behavior. */
5912 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
5914 aarch64_inst
*base
= &instr
->base
;
5915 const aarch64_opcode
*opcode
= base
->opcode
;
5916 const aarch64_opnd_info
*opnds
= base
->operands
;
5917 switch (opcode
->iclass
)
5923 /* Loading/storing the base register is unpredictable if writeback. */
5924 if ((aarch64_get_operand_class (opnds
[0].type
)
5925 == AARCH64_OPND_CLASS_INT_REG
)
5926 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
5927 && opnds
[1].addr
.base_regno
!= REG_SP
5928 && opnds
[1].addr
.writeback
)
5929 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5932 case ldstnapair_offs
:
5933 case ldstpair_indexed
:
5934 /* Loading/storing the base register is unpredictable if writeback. */
5935 if ((aarch64_get_operand_class (opnds
[0].type
)
5936 == AARCH64_OPND_CLASS_INT_REG
)
5937 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
5938 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
5939 && opnds
[2].addr
.base_regno
!= REG_SP
5940 && opnds
[2].addr
.writeback
)
5941 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
5942 /* Load operations must load different registers. */
5943 if ((opcode
->opcode
& (1 << 22))
5944 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
5945 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
5952 /* A wrapper function to interface with libopcodes on encoding and
5953 record the error message if there is any.
5955 Return TRUE on success; otherwise return FALSE. */
5958 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
5961 aarch64_operand_error error_info
;
5962 error_info
.kind
= AARCH64_OPDE_NIL
;
5963 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
))
5967 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
5968 record_operand_error_info (opcode
, &error_info
);
5973 #ifdef DEBUG_AARCH64
5975 dump_opcode_operands (const aarch64_opcode
*opcode
)
5978 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
5980 aarch64_verbose ("\t\t opnd%d: %s", i
,
5981 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
5982 ? aarch64_get_operand_name (opcode
->operands
[i
])
5983 : aarch64_get_operand_desc (opcode
->operands
[i
]));
5987 #endif /* DEBUG_AARCH64 */
5989 /* This is the guts of the machine-dependent assembler. STR points to a
5990 machine dependent instruction. This function is supposed to emit
5991 the frags/bytes it assembles to. */
5994 md_assemble (char *str
)
5997 templates
*template;
5998 aarch64_opcode
*opcode
;
5999 aarch64_inst
*inst_base
;
6000 unsigned saved_cond
;
6002 /* Align the previous label if needed. */
6003 if (last_label_seen
!= NULL
)
6005 symbol_set_frag (last_label_seen
, frag_now
);
6006 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6007 S_SET_SEGMENT (last_label_seen
, now_seg
);
6010 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6012 DEBUG_TRACE ("\n\n");
6013 DEBUG_TRACE ("==============================");
6014 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6016 template = opcode_lookup (&p
);
6019 /* It wasn't an instruction, but it might be a register alias of
6020 the form alias .req reg directive. */
6021 if (!create_register_alias (str
, p
))
6022 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6027 skip_whitespace (p
);
6030 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6031 get_mnemonic_name (str
), str
);
6035 init_operand_error_report ();
6037 /* Sections are assumed to start aligned. In executable section, there is no
6038 MAP_DATA symbol pending. So we only align the address during
6039 MAP_DATA --> MAP_INSN transition.
6040 For other sections, this is not guaranteed. */
6041 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6042 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6043 frag_align_code (2, 0);
6045 saved_cond
= inst
.cond
;
6046 reset_aarch64_instruction (&inst
);
6047 inst
.cond
= saved_cond
;
6049 /* Iterate through all opcode entries with the same mnemonic name. */
6052 opcode
= template->opcode
;
6054 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6055 #ifdef DEBUG_AARCH64
6057 dump_opcode_operands (opcode
);
6058 #endif /* DEBUG_AARCH64 */
6060 mapping_state (MAP_INSN
);
6062 inst_base
= &inst
.base
;
6063 inst_base
->opcode
= opcode
;
6065 /* Truly conditionally executed instructions, e.g. b.cond. */
6066 if (opcode
->flags
& F_COND
)
6068 gas_assert (inst
.cond
!= COND_ALWAYS
);
6069 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6070 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6072 else if (inst
.cond
!= COND_ALWAYS
)
6074 /* It shouldn't arrive here, where the assembly looks like a
6075 conditional instruction but the found opcode is unconditional. */
6080 if (parse_operands (p
, opcode
)
6081 && programmer_friendly_fixup (&inst
)
6082 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6084 /* Check that this instruction is supported for this CPU. */
6085 if (!opcode
->avariant
6086 || !AARCH64_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
6088 as_bad (_("selected processor does not support `%s'"), str
);
6092 warn_unpredictable_ldst (&inst
, str
);
6094 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6095 || !inst
.reloc
.need_libopcodes_p
)
6099 /* If there is relocation generated for the instruction,
6100 store the instruction information for the future fix-up. */
6101 struct aarch64_inst
*copy
;
6102 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6103 copy
= XNEW (struct aarch64_inst
);
6104 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6110 template = template->next
;
6111 if (template != NULL
)
6113 reset_aarch64_instruction (&inst
);
6114 inst
.cond
= saved_cond
;
6117 while (template != NULL
);
6119 /* Issue the error messages if any. */
6120 output_operand_error_report (str
);
6123 /* Various frobbings of labels and their addresses. */
6126 aarch64_start_line_hook (void)
6128 last_label_seen
= NULL
;
6132 aarch64_frob_label (symbolS
* sym
)
6134 last_label_seen
= sym
;
6136 dwarf2_emit_label (sym
);
6140 aarch64_data_in_code (void)
6142 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
6144 *input_line_pointer
= '/';
6145 input_line_pointer
+= 5;
6146 *input_line_pointer
= 0;
6154 aarch64_canonicalize_symbol_name (char *name
)
6158 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
6159 *(name
+ len
- 5) = 0;
6164 /* Table of all register names defined by default. The user can
6165 define additional names with .req. Note that all register names
6166 should appear in both upper and lowercase variants. Some registers
6167 also have mixed-case names. */
6169 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
6170 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
6171 #define REGSET31(p,t) \
6172 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
6173 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
6174 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
6175 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
6176 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
6177 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
6178 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
6179 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
6180 #define REGSET(p,t) \
6181 REGSET31(p,t), REGNUM(p,31,t)
6183 /* These go into aarch64_reg_hsh hash-table. */
6184 static const reg_entry reg_names
[] = {
6185 /* Integer registers. */
6186 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
6187 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
6189 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
6190 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
6192 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
6193 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
6195 /* Coprocessor register numbers. */
6196 REGSET (c
, CN
), REGSET (C
, CN
),
6198 /* Floating-point single precision registers. */
6199 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
6201 /* Floating-point double precision registers. */
6202 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
6204 /* Floating-point half precision registers. */
6205 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
6207 /* Floating-point byte precision registers. */
6208 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
6210 /* Floating-point quad precision registers. */
6211 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
6213 /* FP/SIMD registers. */
6214 REGSET (v
, VN
), REGSET (V
, VN
),
6229 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
6230 static const asm_nzcv nzcv_names
[] = {
6231 {"nzcv", B (n
, z
, c
, v
)},
6232 {"nzcV", B (n
, z
, c
, V
)},
6233 {"nzCv", B (n
, z
, C
, v
)},
6234 {"nzCV", B (n
, z
, C
, V
)},
6235 {"nZcv", B (n
, Z
, c
, v
)},
6236 {"nZcV", B (n
, Z
, c
, V
)},
6237 {"nZCv", B (n
, Z
, C
, v
)},
6238 {"nZCV", B (n
, Z
, C
, V
)},
6239 {"Nzcv", B (N
, z
, c
, v
)},
6240 {"NzcV", B (N
, z
, c
, V
)},
6241 {"NzCv", B (N
, z
, C
, v
)},
6242 {"NzCV", B (N
, z
, C
, V
)},
6243 {"NZcv", B (N
, Z
, c
, v
)},
6244 {"NZcV", B (N
, Z
, c
, V
)},
6245 {"NZCv", B (N
, Z
, C
, v
)},
6246 {"NZCV", B (N
, Z
, C
, V
)}
6259 /* MD interface: bits in the object file. */
6261 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
6262 for use in the a.out file, and stores them in the array pointed to by buf.
6263 This knows about the endian-ness of the target machine and does
6264 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
6265 2 (short) and 4 (long) Floating numbers are put out as a series of
6266 LITTLENUMS (shorts, here at least). */
6269 md_number_to_chars (char *buf
, valueT val
, int n
)
6271 if (target_big_endian
)
6272 number_to_chars_bigendian (buf
, val
, n
);
6274 number_to_chars_littleendian (buf
, val
, n
);
6277 /* MD interface: Sections. */
6279 /* Estimate the size of a frag before relaxing. Assume everything fits in
6283 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
6289 /* Round up a section size to the appropriate boundary. */
6292 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
6297 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
6298 of an rs_align_code fragment.
6300 Here we fill the frag with the appropriate info for padding the
6301 output stream. The resulting frag will consist of a fixed (fr_fix)
6302 and of a repeating (fr_var) part.
6304 The fixed content is always emitted before the repeating content and
6305 these two parts are used as follows in constructing the output:
6306 - the fixed part will be used to align to a valid instruction word
6307 boundary, in case that we start at a misaligned address; as no
6308 executable instruction can live at the misaligned location, we
6309 simply fill with zeros;
6310 - the variable part will be used to cover the remaining padding and
6311 we fill using the AArch64 NOP instruction.
6313 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
6314 enough storage space for up to 3 bytes for padding the back to a valid
6315 instruction alignment and exactly 4 bytes to store the NOP pattern. */
6318 aarch64_handle_align (fragS
* fragP
)
6320 /* NOP = d503201f */
6321 /* AArch64 instructions are always little-endian. */
6322 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
6324 int bytes
, fix
, noop_size
;
6327 if (fragP
->fr_type
!= rs_align_code
)
6330 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
6331 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
6334 gas_assert (fragP
->tc_frag_data
.recorded
);
6337 noop_size
= sizeof (aarch64_noop
);
6339 fix
= bytes
& (noop_size
- 1);
6343 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
6347 fragP
->fr_fix
+= fix
;
6351 memcpy (p
, aarch64_noop
, noop_size
);
6352 fragP
->fr_var
= noop_size
;
6355 /* Perform target specific initialisation of a frag.
6356 Note - despite the name this initialisation is not done when the frag
6357 is created, but only when its type is assigned. A frag can be created
6358 and used a long time before its type is set, so beware of assuming that
6359 this initialisationis performed first. */
6363 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
6364 int max_chars ATTRIBUTE_UNUSED
)
6368 #else /* OBJ_ELF is defined. */
6370 aarch64_init_frag (fragS
* fragP
, int max_chars
)
6372 /* Record a mapping symbol for alignment frags. We will delete this
6373 later if the alignment ends up empty. */
6374 if (!fragP
->tc_frag_data
.recorded
)
6375 fragP
->tc_frag_data
.recorded
= 1;
6377 switch (fragP
->fr_type
)
6382 mapping_state_2 (MAP_DATA
, max_chars
);
6385 mapping_state_2 (MAP_INSN
, max_chars
);
6392 /* Initialize the DWARF-2 unwind information for this procedure. */
6395 tc_aarch64_frame_initial_instructions (void)
6397 cfi_add_CFA_def_cfa (REG_SP
, 0);
6399 #endif /* OBJ_ELF */
6401 /* Convert REGNAME to a DWARF-2 register number. */
6404 tc_aarch64_regname_to_dw2regnum (char *regname
)
6406 const reg_entry
*reg
= parse_reg (®name
);
6412 case REG_TYPE_SP_32
:
6413 case REG_TYPE_SP_64
:
6423 return reg
->number
+ 64;
6431 /* Implement DWARF2_ADDR_SIZE. */
6434 aarch64_dwarf2_addr_size (void)
6436 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6440 return bfd_arch_bits_per_address (stdoutput
) / 8;
6443 /* MD interface: Symbol and relocation handling. */
6445 /* Return the address within the segment that a PC-relative fixup is
6446 relative to. For AArch64 PC-relative fixups applied to instructions
6447 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
6450 md_pcrel_from_section (fixS
* fixP
, segT seg
)
6452 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6454 /* If this is pc-relative and we are going to emit a relocation
6455 then we just want to put out any pipeline compensation that the linker
6456 will need. Otherwise we want to use the calculated base. */
6458 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
6459 || aarch64_force_relocation (fixP
)))
6462 /* AArch64 should be consistent for all pc-relative relocations. */
6463 return base
+ AARCH64_PCREL_OFFSET
;
6466 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
6467 Otherwise we have no need to default values of symbols. */
6470 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6473 if (name
[0] == '_' && name
[1] == 'G'
6474 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
6478 if (symbol_find (name
))
6479 as_bad (_("GOT already in the symbol table"));
6481 GOT_symbol
= symbol_new (name
, undefined_section
,
6482 (valueT
) 0, &zero_address_frag
);
6492 /* Return non-zero if the indicated VALUE has overflowed the maximum
6493 range expressible by a unsigned number with the indicated number of
6497 unsigned_overflow (valueT value
, unsigned bits
)
6500 if (bits
>= sizeof (valueT
) * 8)
6502 lim
= (valueT
) 1 << bits
;
6503 return (value
>= lim
);
6507 /* Return non-zero if the indicated VALUE has overflowed the maximum
6508 range expressible by an signed number with the indicated number of
6512 signed_overflow (offsetT value
, unsigned bits
)
6515 if (bits
>= sizeof (offsetT
) * 8)
6517 lim
= (offsetT
) 1 << (bits
- 1);
6518 return (value
< -lim
|| value
>= lim
);
6521 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
6522 unsigned immediate offset load/store instruction, try to encode it as
6523 an unscaled, 9-bit, signed immediate offset load/store instruction.
6524 Return TRUE if it is successful; otherwise return FALSE.
6526 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
6527 in response to the standard LDR/STR mnemonics when the immediate offset is
6528 unambiguous, i.e. when it is negative or unaligned. */
6531 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
6534 enum aarch64_op new_op
;
6535 const aarch64_opcode
*new_opcode
;
6537 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
6539 switch (instr
->opcode
->op
)
6541 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
6542 case OP_STRB_POS
: new_op
= OP_STURB
; break;
6543 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
6544 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
6545 case OP_STRH_POS
: new_op
= OP_STURH
; break;
6546 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
6547 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
6548 case OP_STR_POS
: new_op
= OP_STUR
; break;
6549 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
6550 case OP_STRF_POS
: new_op
= OP_STURV
; break;
6551 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
6552 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
6553 default: new_op
= OP_NIL
; break;
6556 if (new_op
== OP_NIL
)
6559 new_opcode
= aarch64_get_opcode (new_op
);
6560 gas_assert (new_opcode
!= NULL
);
6562 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
6563 instr
->opcode
->op
, new_opcode
->op
);
6565 aarch64_replace_opcode (instr
, new_opcode
);
6567 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
6568 qualifier matching may fail because the out-of-date qualifier will
6569 prevent the operand being updated with a new and correct qualifier. */
6570 idx
= aarch64_operand_index (instr
->opcode
->operands
,
6571 AARCH64_OPND_ADDR_SIMM9
);
6572 gas_assert (idx
== 1);
6573 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
6575 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
6577 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
))
6583 /* Called by fix_insn to fix a MOV immediate alias instruction.
6585 Operand for a generic move immediate instruction, which is an alias
6586 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6587 a 32-bit/64-bit immediate value into general register. An assembler error
6588 shall result if the immediate cannot be created by a single one of these
6589 instructions. If there is a choice, then to ensure reversability an
6590 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6593 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
6595 const aarch64_opcode
*opcode
;
6597 /* Need to check if the destination is SP/ZR. The check has to be done
6598 before any aarch64_replace_opcode. */
6599 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
6600 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
6602 instr
->operands
[1].imm
.value
= value
;
6603 instr
->operands
[1].skip
= 0;
6607 /* Try the MOVZ alias. */
6608 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
6609 aarch64_replace_opcode (instr
, opcode
);
6610 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6611 &instr
->value
, NULL
, NULL
))
6613 put_aarch64_insn (buf
, instr
->value
);
6616 /* Try the MOVK alias. */
6617 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
6618 aarch64_replace_opcode (instr
, opcode
);
6619 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6620 &instr
->value
, NULL
, NULL
))
6622 put_aarch64_insn (buf
, instr
->value
);
6627 if (try_mov_bitmask_p
)
6629 /* Try the ORR alias. */
6630 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
6631 aarch64_replace_opcode (instr
, opcode
);
6632 if (aarch64_opcode_encode (instr
->opcode
, instr
,
6633 &instr
->value
, NULL
, NULL
))
6635 put_aarch64_insn (buf
, instr
->value
);
6640 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6641 _("immediate cannot be moved by a single instruction"));
6644 /* An instruction operand which is immediate related may have symbol used
6645 in the assembly, e.g.
6648 .set u32, 0x00ffff00
6650 At the time when the assembly instruction is parsed, a referenced symbol,
6651 like 'u32' in the above example may not have been seen; a fixS is created
6652 in such a case and is handled here after symbols have been resolved.
6653 Instruction is fixed up with VALUE using the information in *FIXP plus
6654 extra information in FLAGS.
6656 This function is called by md_apply_fix to fix up instructions that need
6657 a fix-up described above but does not involve any linker-time relocation. */
6660 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
6664 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6665 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
6666 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
6670 /* Now the instruction is about to be fixed-up, so the operand that
6671 was previously marked as 'ignored' needs to be unmarked in order
6672 to get the encoding done properly. */
6673 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6674 new_inst
->operands
[idx
].skip
= 0;
6677 gas_assert (opnd
!= AARCH64_OPND_NIL
);
6681 case AARCH64_OPND_EXCEPTION
:
6682 if (unsigned_overflow (value
, 16))
6683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6684 _("immediate out of range"));
6685 insn
= get_aarch64_insn (buf
);
6686 insn
|= encode_svc_imm (value
);
6687 put_aarch64_insn (buf
, insn
);
6690 case AARCH64_OPND_AIMM
:
6691 /* ADD or SUB with immediate.
6692 NOTE this assumes we come here with a add/sub shifted reg encoding
6693 3 322|2222|2 2 2 21111 111111
6694 1 098|7654|3 2 1 09876 543210 98765 43210
6695 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6696 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6697 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6698 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6700 3 322|2222|2 2 221111111111
6701 1 098|7654|3 2 109876543210 98765 43210
6702 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6703 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6704 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6705 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6706 Fields sf Rn Rd are already set. */
6707 insn
= get_aarch64_insn (buf
);
6711 insn
= reencode_addsub_switch_add_sub (insn
);
6715 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
6716 && unsigned_overflow (value
, 12))
6718 /* Try to shift the value by 12 to make it fit. */
6719 if (((value
>> 12) << 12) == value
6720 && ! unsigned_overflow (value
, 12 + 12))
6723 insn
|= encode_addsub_imm_shift_amount (1);
6727 if (unsigned_overflow (value
, 12))
6728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6729 _("immediate out of range"));
6731 insn
|= encode_addsub_imm (value
);
6733 put_aarch64_insn (buf
, insn
);
6736 case AARCH64_OPND_SIMD_IMM
:
6737 case AARCH64_OPND_SIMD_IMM_SFT
:
6738 case AARCH64_OPND_LIMM
:
6739 /* Bit mask immediate. */
6740 gas_assert (new_inst
!= NULL
);
6741 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
6742 new_inst
->operands
[idx
].imm
.value
= value
;
6743 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6744 &new_inst
->value
, NULL
, NULL
))
6745 put_aarch64_insn (buf
, new_inst
->value
);
6747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6748 _("invalid immediate"));
6751 case AARCH64_OPND_HALF
:
6752 /* 16-bit unsigned immediate. */
6753 if (unsigned_overflow (value
, 16))
6754 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6755 _("immediate out of range"));
6756 insn
= get_aarch64_insn (buf
);
6757 insn
|= encode_movw_imm (value
& 0xffff);
6758 put_aarch64_insn (buf
, insn
);
6761 case AARCH64_OPND_IMM_MOV
:
6762 /* Operand for a generic move immediate instruction, which is
6763 an alias instruction that generates a single MOVZ, MOVN or ORR
6764 instruction to loads a 32-bit/64-bit immediate value into general
6765 register. An assembler error shall result if the immediate cannot be
6766 created by a single one of these instructions. If there is a choice,
6767 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6768 and MOVZ or MOVN to ORR. */
6769 gas_assert (new_inst
!= NULL
);
6770 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
6773 case AARCH64_OPND_ADDR_SIMM7
:
6774 case AARCH64_OPND_ADDR_SIMM9
:
6775 case AARCH64_OPND_ADDR_SIMM9_2
:
6776 case AARCH64_OPND_ADDR_UIMM12
:
6777 /* Immediate offset in an address. */
6778 insn
= get_aarch64_insn (buf
);
6780 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
6781 gas_assert (new_inst
->opcode
->operands
[1] == opnd
6782 || new_inst
->opcode
->operands
[2] == opnd
);
6784 /* Get the index of the address operand. */
6785 if (new_inst
->opcode
->operands
[1] == opnd
)
6786 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6789 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6792 /* Update the resolved offset value. */
6793 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
6795 /* Encode/fix-up. */
6796 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
6797 &new_inst
->value
, NULL
, NULL
))
6799 put_aarch64_insn (buf
, new_inst
->value
);
6802 else if (new_inst
->opcode
->iclass
== ldst_pos
6803 && try_to_encode_as_unscaled_ldst (new_inst
))
6805 put_aarch64_insn (buf
, new_inst
->value
);
6809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6810 _("immediate offset out of range"));
6815 as_fatal (_("unhandled operand code %d"), opnd
);
6819 /* Apply a fixup (fixP) to segment data, once it has been determined
6820 by our caller that we have all the info we need to fix it up.
6822 Parameter valP is the pointer to the value of the bits. */
6825 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
6827 offsetT value
= *valP
;
6829 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
6831 unsigned flags
= fixP
->fx_addnumber
;
6833 DEBUG_TRACE ("\n\n");
6834 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6835 DEBUG_TRACE ("Enter md_apply_fix");
6837 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
6839 /* Note whether this will delete the relocation. */
6841 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
6844 /* Process the relocations. */
6845 switch (fixP
->fx_r_type
)
6847 case BFD_RELOC_NONE
:
6848 /* This will need to go in the object file. */
6853 case BFD_RELOC_8_PCREL
:
6854 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6855 md_number_to_chars (buf
, value
, 1);
6859 case BFD_RELOC_16_PCREL
:
6860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6861 md_number_to_chars (buf
, value
, 2);
6865 case BFD_RELOC_32_PCREL
:
6866 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6867 md_number_to_chars (buf
, value
, 4);
6871 case BFD_RELOC_64_PCREL
:
6872 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6873 md_number_to_chars (buf
, value
, 8);
6876 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
6877 /* We claim that these fixups have been processed here, even if
6878 in fact we generate an error because we do not have a reloc
6879 for them, so tc_gen_reloc() will reject them. */
6881 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
6883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6884 _("undefined symbol %s used as an immediate value"),
6885 S_GET_NAME (fixP
->fx_addsy
));
6886 goto apply_fix_return
;
6888 fix_insn (fixP
, flags
, value
);
6891 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
6892 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6896 _("pc-relative load offset not word aligned"));
6897 if (signed_overflow (value
, 21))
6898 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6899 _("pc-relative load offset out of range"));
6900 insn
= get_aarch64_insn (buf
);
6901 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
6902 put_aarch64_insn (buf
, insn
);
6906 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
6907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6909 if (signed_overflow (value
, 21))
6910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6911 _("pc-relative address offset out of range"));
6912 insn
= get_aarch64_insn (buf
);
6913 insn
|= encode_adr_imm (value
);
6914 put_aarch64_insn (buf
, insn
);
6918 case BFD_RELOC_AARCH64_BRANCH19
:
6919 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6923 _("conditional branch target not word aligned"));
6924 if (signed_overflow (value
, 21))
6925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6926 _("conditional branch out of range"));
6927 insn
= get_aarch64_insn (buf
);
6928 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
6929 put_aarch64_insn (buf
, insn
);
6933 case BFD_RELOC_AARCH64_TSTBR14
:
6934 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6937 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6938 _("conditional branch target not word aligned"));
6939 if (signed_overflow (value
, 16))
6940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6941 _("conditional branch out of range"));
6942 insn
= get_aarch64_insn (buf
);
6943 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
6944 put_aarch64_insn (buf
, insn
);
6948 case BFD_RELOC_AARCH64_CALL26
:
6949 case BFD_RELOC_AARCH64_JUMP26
:
6950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
6953 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6954 _("branch target not word aligned"));
6955 if (signed_overflow (value
, 28))
6956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6957 _("branch out of range"));
6958 insn
= get_aarch64_insn (buf
);
6959 insn
|= encode_branch_ofs_26 (value
>> 2);
6960 put_aarch64_insn (buf
, insn
);
6964 case BFD_RELOC_AARCH64_MOVW_G0
:
6965 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
6966 case BFD_RELOC_AARCH64_MOVW_G0_S
:
6967 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
6970 case BFD_RELOC_AARCH64_MOVW_G1
:
6971 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
6972 case BFD_RELOC_AARCH64_MOVW_G1_S
:
6973 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
6976 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
6978 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6979 /* Should always be exported to object file, see
6980 aarch64_force_relocation(). */
6981 gas_assert (!fixP
->fx_done
);
6982 gas_assert (seg
->use_rela_p
);
6984 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
6986 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6987 /* Should always be exported to object file, see
6988 aarch64_force_relocation(). */
6989 gas_assert (!fixP
->fx_done
);
6990 gas_assert (seg
->use_rela_p
);
6992 case BFD_RELOC_AARCH64_MOVW_G2
:
6993 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
6994 case BFD_RELOC_AARCH64_MOVW_G2_S
:
6997 case BFD_RELOC_AARCH64_MOVW_G3
:
7000 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7002 insn
= get_aarch64_insn (buf
);
7006 /* REL signed addend must fit in 16 bits */
7007 if (signed_overflow (value
, 16))
7008 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7009 _("offset out of range"));
7013 /* Check for overflow and scale. */
7014 switch (fixP
->fx_r_type
)
7016 case BFD_RELOC_AARCH64_MOVW_G0
:
7017 case BFD_RELOC_AARCH64_MOVW_G1
:
7018 case BFD_RELOC_AARCH64_MOVW_G2
:
7019 case BFD_RELOC_AARCH64_MOVW_G3
:
7020 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7021 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7022 if (unsigned_overflow (value
, scale
+ 16))
7023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7024 _("unsigned value out of range"));
7026 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7027 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7028 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7029 /* NOTE: We can only come here with movz or movn. */
7030 if (signed_overflow (value
, scale
+ 16))
7031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7032 _("signed value out of range"));
7035 /* Force use of MOVN. */
7037 insn
= reencode_movzn_to_movn (insn
);
7041 /* Force use of MOVZ. */
7042 insn
= reencode_movzn_to_movz (insn
);
7046 /* Unchecked relocations. */
7052 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7053 insn
|= encode_movw_imm (value
& 0xffff);
7055 put_aarch64_insn (buf
, insn
);
7059 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7060 fixP
->fx_r_type
= (ilp32_p
7061 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7062 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7063 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7064 /* Should always be exported to object file, see
7065 aarch64_force_relocation(). */
7066 gas_assert (!fixP
->fx_done
);
7067 gas_assert (seg
->use_rela_p
);
7070 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7071 fixP
->fx_r_type
= (ilp32_p
7072 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7073 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
);
7074 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7075 /* Should always be exported to object file, see
7076 aarch64_force_relocation(). */
7077 gas_assert (!fixP
->fx_done
);
7078 gas_assert (seg
->use_rela_p
);
7081 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7082 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7083 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7084 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7085 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7086 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7087 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7088 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7089 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7090 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7091 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7092 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7093 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7094 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7095 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7096 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7097 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7098 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7099 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7100 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7101 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7102 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7103 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7104 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7105 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7106 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7107 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7108 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7109 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7110 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7111 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7112 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7113 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7114 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7115 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7116 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7117 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7118 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7119 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7120 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7121 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7122 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7123 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7124 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7125 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7126 /* Should always be exported to object file, see
7127 aarch64_force_relocation(). */
7128 gas_assert (!fixP
->fx_done
);
7129 gas_assert (seg
->use_rela_p
);
7132 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7133 /* Should always be exported to object file, see
7134 aarch64_force_relocation(). */
7135 fixP
->fx_r_type
= (ilp32_p
7136 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7137 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
7138 gas_assert (!fixP
->fx_done
);
7139 gas_assert (seg
->use_rela_p
);
7142 case BFD_RELOC_AARCH64_ADD_LO12
:
7143 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7144 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7145 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7146 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7147 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7148 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7149 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7150 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7151 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7152 case BFD_RELOC_AARCH64_LDST128_LO12
:
7153 case BFD_RELOC_AARCH64_LDST16_LO12
:
7154 case BFD_RELOC_AARCH64_LDST32_LO12
:
7155 case BFD_RELOC_AARCH64_LDST64_LO12
:
7156 case BFD_RELOC_AARCH64_LDST8_LO12
:
7157 /* Should always be exported to object file, see
7158 aarch64_force_relocation(). */
7159 gas_assert (!fixP
->fx_done
);
7160 gas_assert (seg
->use_rela_p
);
7163 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
7164 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
7165 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
7168 case BFD_RELOC_UNUSED
:
7169 /* An error will already have been reported. */
7173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7174 _("unexpected %s fixup"),
7175 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7180 /* Free the allocated the struct aarch64_inst.
7181 N.B. currently there are very limited number of fix-up types actually use
7182 this field, so the impact on the performance should be minimal . */
7183 if (fixP
->tc_fix_data
.inst
!= NULL
)
7184 free (fixP
->tc_fix_data
.inst
);
7189 /* Translate internal representation of relocation info to BFD target
7193 tc_gen_reloc (asection
* section
, fixS
* fixp
)
7196 bfd_reloc_code_real_type code
;
7198 reloc
= XNEW (arelent
);
7200 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7201 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7202 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7206 if (section
->use_rela_p
)
7207 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
7209 fixp
->fx_offset
= reloc
->address
;
7211 reloc
->addend
= fixp
->fx_offset
;
7213 code
= fixp
->fx_r_type
;
7218 code
= BFD_RELOC_16_PCREL
;
7223 code
= BFD_RELOC_32_PCREL
;
7228 code
= BFD_RELOC_64_PCREL
;
7235 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7236 if (reloc
->howto
== NULL
)
7238 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7240 ("cannot represent %s relocation in this object file format"),
7241 bfd_get_reloc_code_name (code
));
7248 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7251 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
7253 bfd_reloc_code_real_type type
;
7257 FIXME: @@ Should look at CPU word size. */
7264 type
= BFD_RELOC_16
;
7267 type
= BFD_RELOC_32
;
7270 type
= BFD_RELOC_64
;
7273 as_bad (_("cannot do %u-byte relocation"), size
);
7274 type
= BFD_RELOC_UNUSED
;
7278 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7282 aarch64_force_relocation (struct fix
*fixp
)
7284 switch (fixp
->fx_r_type
)
7286 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7287 /* Perform these "immediate" internal relocations
7288 even if the symbol is extern or weak. */
7291 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
7292 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7293 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7294 /* Pseudo relocs that need to be fixed up according to
7298 case BFD_RELOC_AARCH64_ADD_LO12
:
7299 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
7300 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
7301 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
7302 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
7303 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
7304 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
7305 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
7306 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
7307 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
7308 case BFD_RELOC_AARCH64_LDST128_LO12
:
7309 case BFD_RELOC_AARCH64_LDST16_LO12
:
7310 case BFD_RELOC_AARCH64_LDST32_LO12
:
7311 case BFD_RELOC_AARCH64_LDST64_LO12
:
7312 case BFD_RELOC_AARCH64_LDST8_LO12
:
7313 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
:
7314 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
7315 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
7316 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
7317 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
:
7318 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
7319 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7320 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7321 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
7322 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
7323 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
7324 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
7325 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
7326 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
7327 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
7328 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
7329 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
7330 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
7331 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
7332 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
7333 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
7334 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
7335 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
7336 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
7337 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
7338 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
7339 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
7340 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
7341 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
7342 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
7343 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
7344 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
7345 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
7346 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
7347 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
7348 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
7349 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
7350 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
7351 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
7352 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
7353 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
7354 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
7355 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
7356 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
7357 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
7358 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
7359 /* Always leave these relocations for the linker. */
7366 return generic_force_reloc (fixp
);
7372 elf64_aarch64_target_format (void)
7374 if (strcmp (TARGET_OS
, "cloudabi") == 0)
7376 /* FIXME: What to do for ilp32_p ? */
7377 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
7379 if (target_big_endian
)
7380 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
7382 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
7386 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
7388 elf_frob_symbol (symp
, puntp
);
7392 /* MD interface: Finalization. */
7394 /* A good place to do this, although this was probably not intended
7395 for this kind of use. We need to dump the literal pool before
7396 references are made to a null symbol pointer. */
7399 aarch64_cleanup (void)
7403 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
7405 /* Put it at the end of the relevant section. */
7406 subseg_set (pool
->section
, pool
->sub_section
);
7412 /* Remove any excess mapping symbols generated for alignment frags in
7413 SEC. We may have created a mapping symbol before a zero byte
7414 alignment; remove it if there's a mapping symbol after the
7417 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
7418 void *dummy ATTRIBUTE_UNUSED
)
7420 segment_info_type
*seginfo
= seg_info (sec
);
7423 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
7426 for (fragp
= seginfo
->frchainP
->frch_root
;
7427 fragp
!= NULL
; fragp
= fragp
->fr_next
)
7429 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
7430 fragS
*next
= fragp
->fr_next
;
7432 /* Variable-sized frags have been converted to fixed size by
7433 this point. But if this was variable-sized to start with,
7434 there will be a fixed-size frag after it. So don't handle
7436 if (sym
== NULL
|| next
== NULL
)
7439 if (S_GET_VALUE (sym
) < next
->fr_address
)
7440 /* Not at the end of this frag. */
7442 know (S_GET_VALUE (sym
) == next
->fr_address
);
7446 if (next
->tc_frag_data
.first_map
!= NULL
)
7448 /* Next frag starts with a mapping symbol. Discard this
7450 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7454 if (next
->fr_next
== NULL
)
7456 /* This mapping symbol is at the end of the section. Discard
7458 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
7459 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
7463 /* As long as we have empty frags without any mapping symbols,
7465 /* If the next frag is non-empty and does not start with a
7466 mapping symbol, then this mapping symbol is required. */
7467 if (next
->fr_address
!= next
->fr_next
->fr_address
)
7470 next
= next
->fr_next
;
7472 while (next
!= NULL
);
7477 /* Adjust the symbol table. */
7480 aarch64_adjust_symtab (void)
7483 /* Remove any overlapping mapping symbols generated by alignment frags. */
7484 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
7485 /* Now do generic ELF adjustments. */
7486 elf_adjust_symtab ();
7491 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
7493 const char *hash_err
;
7495 hash_err
= hash_insert (table
, key
, value
);
7497 printf ("Internal Error: Can't hash %s\n", key
);
7501 fill_instruction_hash_table (void)
7503 aarch64_opcode
*opcode
= aarch64_opcode_table
;
7505 while (opcode
->name
!= NULL
)
7507 templates
*templ
, *new_templ
;
7508 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
7510 new_templ
= (templates
*) xmalloc (sizeof (templates
));
7511 new_templ
->opcode
= opcode
;
7512 new_templ
->next
= NULL
;
7515 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
7518 new_templ
->next
= templ
->next
;
7519 templ
->next
= new_templ
;
7526 convert_to_upper (char *dst
, const char *src
, size_t num
)
7529 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
7530 *dst
= TOUPPER (*src
);
7534 /* Assume STR point to a lower-case string, allocate, convert and return
7535 the corresponding upper-case string. */
7536 static inline const char*
7537 get_upper_str (const char *str
)
7540 size_t len
= strlen (str
);
7541 ret
= XNEWVEC (char, len
+ 1);
7542 convert_to_upper (ret
, str
, len
);
7546 /* MD interface: Initialization. */
7554 if ((aarch64_ops_hsh
= hash_new ()) == NULL
7555 || (aarch64_cond_hsh
= hash_new ()) == NULL
7556 || (aarch64_shift_hsh
= hash_new ()) == NULL
7557 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
7558 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
7559 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
7560 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
7561 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
7562 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
7563 || (aarch64_reg_hsh
= hash_new ()) == NULL
7564 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
7565 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
7566 || (aarch64_pldop_hsh
= hash_new ()) == NULL
7567 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
7568 as_fatal (_("virtual memory exhausted"));
7570 fill_instruction_hash_table ();
7572 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
7573 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
7574 (void *) (aarch64_sys_regs
+ i
));
7576 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
7577 checked_hash_insert (aarch64_pstatefield_hsh
,
7578 aarch64_pstatefields
[i
].name
,
7579 (void *) (aarch64_pstatefields
+ i
));
7581 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
7582 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
7583 aarch64_sys_regs_ic
[i
].name
,
7584 (void *) (aarch64_sys_regs_ic
+ i
));
7586 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
7587 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
7588 aarch64_sys_regs_dc
[i
].name
,
7589 (void *) (aarch64_sys_regs_dc
+ i
));
7591 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
7592 checked_hash_insert (aarch64_sys_regs_at_hsh
,
7593 aarch64_sys_regs_at
[i
].name
,
7594 (void *) (aarch64_sys_regs_at
+ i
));
7596 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
7597 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
7598 aarch64_sys_regs_tlbi
[i
].name
,
7599 (void *) (aarch64_sys_regs_tlbi
+ i
));
7601 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
7602 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
7603 (void *) (reg_names
+ i
));
7605 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
7606 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
7607 (void *) (nzcv_names
+ i
));
7609 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
7611 const char *name
= aarch64_operand_modifiers
[i
].name
;
7612 checked_hash_insert (aarch64_shift_hsh
, name
,
7613 (void *) (aarch64_operand_modifiers
+ i
));
7614 /* Also hash the name in the upper case. */
7615 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
7616 (void *) (aarch64_operand_modifiers
+ i
));
7619 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
7622 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
7623 the same condition code. */
7624 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
7626 const char *name
= aarch64_conds
[i
].names
[j
];
7629 checked_hash_insert (aarch64_cond_hsh
, name
,
7630 (void *) (aarch64_conds
+ i
));
7631 /* Also hash the name in the upper case. */
7632 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
7633 (void *) (aarch64_conds
+ i
));
7637 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
7639 const char *name
= aarch64_barrier_options
[i
].name
;
7640 /* Skip xx00 - the unallocated values of option. */
7643 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
7644 (void *) (aarch64_barrier_options
+ i
));
7645 /* Also hash the name in the upper case. */
7646 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
7647 (void *) (aarch64_barrier_options
+ i
));
7650 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
7652 const char* name
= aarch64_prfops
[i
].name
;
7653 /* Skip the unallocated hint encodings. */
7656 checked_hash_insert (aarch64_pldop_hsh
, name
,
7657 (void *) (aarch64_prfops
+ i
));
7658 /* Also hash the name in the upper case. */
7659 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7660 (void *) (aarch64_prfops
+ i
));
7663 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
7665 const char* name
= aarch64_hint_options
[i
].name
;
7667 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
7668 (void *) (aarch64_hint_options
+ i
));
7669 /* Also hash the name in the upper case. */
7670 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
7671 (void *) (aarch64_hint_options
+ i
));
7674 /* Set the cpu variant based on the command-line options. */
7676 mcpu_cpu_opt
= march_cpu_opt
;
7679 mcpu_cpu_opt
= &cpu_default
;
7681 cpu_variant
= *mcpu_cpu_opt
;
7683 /* Record the CPU type. */
7684 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
7686 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
7689 /* Command line processing. */
7691 const char *md_shortopts
= "m:";
7693 #ifdef AARCH64_BI_ENDIAN
7694 #define OPTION_EB (OPTION_MD_BASE + 0)
7695 #define OPTION_EL (OPTION_MD_BASE + 1)
7697 #if TARGET_BYTES_BIG_ENDIAN
7698 #define OPTION_EB (OPTION_MD_BASE + 0)
7700 #define OPTION_EL (OPTION_MD_BASE + 1)
7704 struct option md_longopts
[] = {
7706 {"EB", no_argument
, NULL
, OPTION_EB
},
7709 {"EL", no_argument
, NULL
, OPTION_EL
},
7711 {NULL
, no_argument
, NULL
, 0}
7714 size_t md_longopts_size
= sizeof (md_longopts
);
7716 struct aarch64_option_table
7718 const char *option
; /* Option name to match. */
7719 const char *help
; /* Help information. */
7720 int *var
; /* Variable to change. */
7721 int value
; /* What to change it to. */
7722 char *deprecated
; /* If non-null, print this message. */
7725 static struct aarch64_option_table aarch64_opts
[] = {
7726 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
7727 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
7729 #ifdef DEBUG_AARCH64
7730 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
7731 #endif /* DEBUG_AARCH64 */
7732 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
7734 {"mno-verbose-error", N_("do not output verbose error messages"),
7735 &verbose_error_p
, 0, NULL
},
7736 {NULL
, NULL
, NULL
, 0, NULL
}
7739 struct aarch64_cpu_option_table
7742 const aarch64_feature_set value
;
7743 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7745 const char *canonical_name
;
7748 /* This list should, at a minimum, contain all the cpu names
7749 recognized by GCC. */
7750 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
7751 {"all", AARCH64_ANY
, NULL
},
7752 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7753 AARCH64_FEATURE_CRC
), "Cortex-A35"},
7754 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7755 AARCH64_FEATURE_CRC
), "Cortex-A53"},
7756 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7757 AARCH64_FEATURE_CRC
), "Cortex-A57"},
7758 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7759 AARCH64_FEATURE_CRC
), "Cortex-A72"},
7760 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7761 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7762 "Samsung Exynos M1"},
7763 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7764 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7765 "Qualcomm QDF24XX"},
7766 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7767 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
7769 /* The 'xgene-1' name is an older name for 'xgene1', which was used
7770 in earlier releases and is superseded by 'xgene1' in all
7772 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7773 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
7774 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
7775 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
7776 {"generic", AARCH64_ARCH_V8
, NULL
},
7778 {NULL
, AARCH64_ARCH_NONE
, NULL
}
7781 struct aarch64_arch_option_table
7784 const aarch64_feature_set value
;
7787 /* This list should, at a minimum, contain all the architecture names
7788 recognized by GCC. */
7789 static const struct aarch64_arch_option_table aarch64_archs
[] = {
7790 {"all", AARCH64_ANY
},
7791 {"armv8-a", AARCH64_ARCH_V8
},
7792 {"armv8.1-a", AARCH64_ARCH_V8_1
},
7793 {"armv8.2-a", AARCH64_ARCH_V8_2
},
7794 {NULL
, AARCH64_ARCH_NONE
}
7797 /* ISA extensions. */
7798 struct aarch64_option_cpu_value_table
7801 const aarch64_feature_set value
;
7804 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
7805 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0)},
7806 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0)},
7807 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
7808 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0)},
7809 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
7810 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0)},
7811 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0)},
7812 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0)},
7813 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
7814 | AARCH64_FEATURE_RDMA
, 0)},
7815 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
7816 | AARCH64_FEATURE_FP
, 0)},
7817 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0)},
7818 {NULL
, AARCH64_ARCH_NONE
}
7821 struct aarch64_long_option_table
7823 const char *option
; /* Substring to match. */
7824 const char *help
; /* Help information. */
7825 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
7826 char *deprecated
; /* If non-null, print this message. */
7830 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
7831 bfd_boolean ext_only
)
7833 /* We insist on extensions being added before being removed. We achieve
7834 this by using the ADDING_VALUE variable to indicate whether we are
7835 adding an extension (1) or removing it (0) and only allowing it to
7836 change in the order -1 -> 1 -> 0. */
7837 int adding_value
= -1;
7838 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
7840 /* Copy the feature set, so that we can modify it. */
7844 while (str
!= NULL
&& *str
!= 0)
7846 const struct aarch64_option_cpu_value_table
*opt
;
7847 const char *ext
= NULL
;
7854 as_bad (_("invalid architectural extension"));
7858 ext
= strchr (++str
, '+');
7864 optlen
= strlen (str
);
7866 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
7868 if (adding_value
!= 0)
7873 else if (optlen
> 0)
7875 if (adding_value
== -1)
7877 else if (adding_value
!= 1)
7879 as_bad (_("must specify extensions to add before specifying "
7880 "those to remove"));
7887 as_bad (_("missing architectural extension"));
7891 gas_assert (adding_value
!= -1);
7893 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
7894 if (strncmp (opt
->name
, str
, optlen
) == 0)
7896 /* Add or remove the extension. */
7898 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
7900 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
7904 if (opt
->name
== NULL
)
7906 as_bad (_("unknown architectural extension `%s'"), str
);
7917 aarch64_parse_cpu (const char *str
)
7919 const struct aarch64_cpu_option_table
*opt
;
7920 const char *ext
= strchr (str
, '+');
7926 optlen
= strlen (str
);
7930 as_bad (_("missing cpu name `%s'"), str
);
7934 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
7935 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7937 mcpu_cpu_opt
= &opt
->value
;
7939 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
7944 as_bad (_("unknown cpu `%s'"), str
);
7949 aarch64_parse_arch (const char *str
)
7951 const struct aarch64_arch_option_table
*opt
;
7952 const char *ext
= strchr (str
, '+');
7958 optlen
= strlen (str
);
7962 as_bad (_("missing architecture name `%s'"), str
);
7966 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
7967 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
7969 march_cpu_opt
= &opt
->value
;
7971 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
7976 as_bad (_("unknown architecture `%s'\n"), str
);
7981 struct aarch64_option_abi_value_table
7984 enum aarch64_abi_type value
;
7987 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
7988 {"ilp32", AARCH64_ABI_ILP32
},
7989 {"lp64", AARCH64_ABI_LP64
},
7994 aarch64_parse_abi (const char *str
)
7996 const struct aarch64_option_abi_value_table
*opt
;
7997 size_t optlen
= strlen (str
);
8001 as_bad (_("missing abi name `%s'"), str
);
8005 for (opt
= aarch64_abis
; opt
->name
!= NULL
; opt
++)
8006 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
8008 aarch64_abi
= opt
->value
;
8012 as_bad (_("unknown abi `%s'\n"), str
);
8016 static struct aarch64_long_option_table aarch64_long_opts
[] = {
8018 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
8019 aarch64_parse_abi
, NULL
},
8020 #endif /* OBJ_ELF */
8021 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
8022 aarch64_parse_cpu
, NULL
},
8023 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
8024 aarch64_parse_arch
, NULL
},
8025 {NULL
, NULL
, 0, NULL
}
8029 md_parse_option (int c
, const char *arg
)
8031 struct aarch64_option_table
*opt
;
8032 struct aarch64_long_option_table
*lopt
;
8038 target_big_endian
= 1;
8044 target_big_endian
= 0;
8049 /* Listing option. Just ignore these, we don't support additional
8054 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8056 if (c
== opt
->option
[0]
8057 && ((arg
== NULL
&& opt
->option
[1] == 0)
8058 || streq (arg
, opt
->option
+ 1)))
8060 /* If the option is deprecated, tell the user. */
8061 if (opt
->deprecated
!= NULL
)
8062 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
8063 arg
? arg
: "", _(opt
->deprecated
));
8065 if (opt
->var
!= NULL
)
8066 *opt
->var
= opt
->value
;
8072 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8074 /* These options are expected to have an argument. */
8075 if (c
== lopt
->option
[0]
8077 && strncmp (arg
, lopt
->option
+ 1,
8078 strlen (lopt
->option
+ 1)) == 0)
8080 /* If the option is deprecated, tell the user. */
8081 if (lopt
->deprecated
!= NULL
)
8082 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
8083 _(lopt
->deprecated
));
8085 /* Call the sup-option parser. */
8086 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
8097 md_show_usage (FILE * fp
)
8099 struct aarch64_option_table
*opt
;
8100 struct aarch64_long_option_table
*lopt
;
8102 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
8104 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
8105 if (opt
->help
!= NULL
)
8106 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
8108 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
8109 if (lopt
->help
!= NULL
)
8110 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
8114 -EB assemble code for a big-endian cpu\n"));
8119 -EL assemble code for a little-endian cpu\n"));
8123 /* Parse a .cpu directive. */
8126 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
8128 const struct aarch64_cpu_option_table
*opt
;
8134 name
= input_line_pointer
;
8135 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8136 input_line_pointer
++;
8137 saved_char
= *input_line_pointer
;
8138 *input_line_pointer
= 0;
8140 ext
= strchr (name
, '+');
8143 optlen
= ext
- name
;
8145 optlen
= strlen (name
);
8147 /* Skip the first "all" entry. */
8148 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
8149 if (strlen (opt
->name
) == optlen
8150 && strncmp (name
, opt
->name
, optlen
) == 0)
8152 mcpu_cpu_opt
= &opt
->value
;
8154 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8157 cpu_variant
= *mcpu_cpu_opt
;
8159 *input_line_pointer
= saved_char
;
8160 demand_empty_rest_of_line ();
8163 as_bad (_("unknown cpu `%s'"), name
);
8164 *input_line_pointer
= saved_char
;
8165 ignore_rest_of_line ();
8169 /* Parse a .arch directive. */
8172 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
8174 const struct aarch64_arch_option_table
*opt
;
8180 name
= input_line_pointer
;
8181 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8182 input_line_pointer
++;
8183 saved_char
= *input_line_pointer
;
8184 *input_line_pointer
= 0;
8186 ext
= strchr (name
, '+');
8189 optlen
= ext
- name
;
8191 optlen
= strlen (name
);
8193 /* Skip the first "all" entry. */
8194 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
8195 if (strlen (opt
->name
) == optlen
8196 && strncmp (name
, opt
->name
, optlen
) == 0)
8198 mcpu_cpu_opt
= &opt
->value
;
8200 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
8203 cpu_variant
= *mcpu_cpu_opt
;
8205 *input_line_pointer
= saved_char
;
8206 demand_empty_rest_of_line ();
8210 as_bad (_("unknown architecture `%s'\n"), name
);
8211 *input_line_pointer
= saved_char
;
8212 ignore_rest_of_line ();
8215 /* Parse a .arch_extension directive. */
8218 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
8221 char *ext
= input_line_pointer
;;
8223 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
8224 input_line_pointer
++;
8225 saved_char
= *input_line_pointer
;
8226 *input_line_pointer
= 0;
8228 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
8231 cpu_variant
= *mcpu_cpu_opt
;
8233 *input_line_pointer
= saved_char
;
8234 demand_empty_rest_of_line ();
8237 /* Copy symbol information. */
8240 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
8242 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);