1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GAS.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
25 #include "bfd_stdint.h"
27 #include "safe-ctype.h"
32 #include "elf/aarch64.h"
33 #include "dw2gencfi.h"
36 #include "dwarf2dbg.h"
38 /* Types of processor to assemble for. */
40 #define CPU_DEFAULT AARCH64_ARCH_V8
43 #define streq(a, b) (strcmp (a, b) == 0)
45 #define END_OF_INSN '\0'
47 static aarch64_feature_set cpu_variant
;
49 /* Variables that we set while parsing command-line options. Once all
50 options have been read we re-process these values to set the real
52 static const aarch64_feature_set
*mcpu_cpu_opt
= NULL
;
53 static const aarch64_feature_set
*march_cpu_opt
= NULL
;
55 /* Constants for known architecture features. */
56 static const aarch64_feature_set cpu_default
= CPU_DEFAULT
;
58 /* Currently active instruction sequence. */
59 static aarch64_instr_sequence
*insn_sequence
= NULL
;
62 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
63 static symbolS
*GOT_symbol
;
65 /* Which ABI to use. */
74 #define DEFAULT_ARCH "aarch64"
77 /* DEFAULT_ARCH is initialized in gas/configure.tgt. */
78 static const char *default_arch
= DEFAULT_ARCH
;
80 /* AArch64 ABI for the output file. */
81 static enum aarch64_abi_type aarch64_abi
= AARCH64_ABI_NONE
;
83 /* When non-zero, program to a 32-bit model, in which the C data types
84 int, long and all pointer types are 32-bit objects (ILP32); or to a
85 64-bit model, in which the C int type is 32-bits but the C long type
86 and all pointer types are 64-bit objects (LP64). */
87 #define ilp32_p (aarch64_abi == AARCH64_ABI_ILP32)
102 /* Bits for DEFINED field in vector_type_el. */
103 #define NTA_HASTYPE 1
104 #define NTA_HASINDEX 2
105 #define NTA_HASVARWIDTH 4
107 struct vector_type_el
109 enum vector_el_type type
;
110 unsigned char defined
;
115 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
119 bfd_reloc_code_real_type type
;
122 enum aarch64_opnd opnd
;
124 unsigned need_libopcodes_p
: 1;
127 struct aarch64_instruction
129 /* libopcodes structure for instruction intermediate representation. */
131 /* Record assembly errors found during the parsing. */
134 enum aarch64_operand_error_kind kind
;
137 /* The condition that appears in the assembly line. */
139 /* Relocation information (including the GAS internal fixup). */
141 /* Need to generate an immediate in the literal pool. */
142 unsigned gen_lit_pool
: 1;
145 typedef struct aarch64_instruction aarch64_instruction
;
147 static aarch64_instruction inst
;
149 static bfd_boolean
parse_operands (char *, const aarch64_opcode
*);
150 static bfd_boolean
programmer_friendly_fixup (aarch64_instruction
*);
153 # define now_instr_sequence seg_info \
154 (now_seg)->tc_segment_info_data.insn_sequence
156 static struct aarch64_instr_sequence now_instr_sequence
;
159 /* Diagnostics inline function utilities.
161 These are lightweight utilities which should only be called by parse_operands
162 and other parsers. GAS processes each assembly line by parsing it against
163 instruction template(s), in the case of multiple templates (for the same
164 mnemonic name), those templates are tried one by one until one succeeds or
165 all fail. An assembly line may fail a few templates before being
166 successfully parsed; an error saved here in most cases is not a user error
167 but an error indicating the current template is not the right template.
168 Therefore it is very important that errors can be saved at a low cost during
169 the parsing; we don't want to slow down the whole parsing by recording
170 non-user errors in detail.
172 Remember that the objective is to help GAS pick up the most appropriate
173 error message in the case of multiple templates, e.g. FMOV which has 8
179 inst
.parsing_error
.kind
= AARCH64_OPDE_NIL
;
180 inst
.parsing_error
.error
= NULL
;
183 static inline bfd_boolean
186 return inst
.parsing_error
.kind
!= AARCH64_OPDE_NIL
;
189 static inline const char *
190 get_error_message (void)
192 return inst
.parsing_error
.error
;
195 static inline enum aarch64_operand_error_kind
196 get_error_kind (void)
198 return inst
.parsing_error
.kind
;
202 set_error (enum aarch64_operand_error_kind kind
, const char *error
)
204 inst
.parsing_error
.kind
= kind
;
205 inst
.parsing_error
.error
= error
;
209 set_recoverable_error (const char *error
)
211 set_error (AARCH64_OPDE_RECOVERABLE
, error
);
214 /* Use the DESC field of the corresponding aarch64_operand entry to compose
215 the error message. */
217 set_default_error (void)
219 set_error (AARCH64_OPDE_SYNTAX_ERROR
, NULL
);
223 set_syntax_error (const char *error
)
225 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
229 set_first_syntax_error (const char *error
)
232 set_error (AARCH64_OPDE_SYNTAX_ERROR
, error
);
236 set_fatal_syntax_error (const char *error
)
238 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR
, error
);
241 /* Number of littlenums required to hold an extended precision number. */
242 #define MAX_LITTLENUMS 6
244 /* Return value for certain parsers when the parsing fails; those parsers
245 return the information of the parsed result, e.g. register number, on
247 #define PARSE_FAIL -1
249 /* This is an invalid condition code that means no conditional field is
251 #define COND_ALWAYS 0x10
255 const char *template;
261 const char *template;
268 bfd_reloc_code_real_type reloc
;
271 /* Macros to define the register types and masks for the purpose
274 #undef AARCH64_REG_TYPES
275 #define AARCH64_REG_TYPES \
276 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
277 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
278 BASIC_REG_TYPE(SP_32) /* wsp */ \
279 BASIC_REG_TYPE(SP_64) /* sp */ \
280 BASIC_REG_TYPE(Z_32) /* wzr */ \
281 BASIC_REG_TYPE(Z_64) /* xzr */ \
282 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
283 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
284 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
285 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
286 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
287 BASIC_REG_TYPE(VN) /* v[0-31] */ \
288 BASIC_REG_TYPE(ZN) /* z[0-31] */ \
289 BASIC_REG_TYPE(PN) /* p[0-15] */ \
290 /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
291 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
292 /* Typecheck: same, plus SVE registers. */ \
293 MULTI_REG_TYPE(SVE_BASE, REG_TYPE(R_64) | REG_TYPE(SP_64) \
295 /* Typecheck: x[0-30], w[0-30] or [xw]zr. */ \
296 MULTI_REG_TYPE(R_Z, REG_TYPE(R_32) | REG_TYPE(R_64) \
297 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
298 /* Typecheck: same, plus SVE registers. */ \
299 MULTI_REG_TYPE(SVE_OFFSET, REG_TYPE(R_32) | REG_TYPE(R_64) \
300 | REG_TYPE(Z_32) | REG_TYPE(Z_64) \
302 /* Typecheck: x[0-30], w[0-30] or {w}sp. */ \
303 MULTI_REG_TYPE(R_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
304 | REG_TYPE(SP_32) | REG_TYPE(SP_64)) \
305 /* Typecheck: any int (inc {W}SP inc [WX]ZR). */ \
306 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
307 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
308 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
309 /* Typecheck: any [BHSDQ]P FP. */ \
310 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
311 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
312 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR). */ \
313 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
314 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
315 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
316 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
317 /* Typecheck: as above, but also Zn, Pn, and {W}SP. This should only \
318 be used for SVE instructions, since Zn and Pn are valid symbols \
319 in other contexts. */ \
320 MULTI_REG_TYPE(R_Z_SP_BHSDQ_VZP, REG_TYPE(R_32) | REG_TYPE(R_64) \
321 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
322 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
323 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
324 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \
325 | REG_TYPE(ZN) | REG_TYPE(PN)) \
326 /* Any integer register; used for error messages only. */ \
327 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
328 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
329 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
330 /* Pseudo type to mark the end of the enumerator sequence. */ \
333 #undef BASIC_REG_TYPE
334 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
335 #undef MULTI_REG_TYPE
336 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
338 /* Register type enumerators. */
339 typedef enum aarch64_reg_type_
341 /* A list of REG_TYPE_*. */
345 #undef BASIC_REG_TYPE
346 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
348 #define REG_TYPE(T) (1 << REG_TYPE_##T)
349 #undef MULTI_REG_TYPE
350 #define MULTI_REG_TYPE(T,V) V,
352 /* Structure for a hash table entry for a register. */
356 unsigned char number
;
357 ENUM_BITFIELD (aarch64_reg_type_
) type
: 8;
358 unsigned char builtin
;
361 /* Values indexed by aarch64_reg_type to assist the type checking. */
362 static const unsigned reg_type_masks
[] =
367 #undef BASIC_REG_TYPE
369 #undef MULTI_REG_TYPE
370 #undef AARCH64_REG_TYPES
372 /* Diagnostics used when we don't get a register of the expected type.
373 Note: this has to synchronized with aarch64_reg_type definitions
376 get_reg_expected_msg (aarch64_reg_type reg_type
)
383 msg
= N_("integer 32-bit register expected");
386 msg
= N_("integer 64-bit register expected");
389 msg
= N_("integer register expected");
391 case REG_TYPE_R64_SP
:
392 msg
= N_("64-bit integer or SP register expected");
394 case REG_TYPE_SVE_BASE
:
395 msg
= N_("base register expected");
398 msg
= N_("integer or zero register expected");
400 case REG_TYPE_SVE_OFFSET
:
401 msg
= N_("offset register expected");
404 msg
= N_("integer or SP register expected");
406 case REG_TYPE_R_Z_SP
:
407 msg
= N_("integer, zero or SP register expected");
410 msg
= N_("8-bit SIMD scalar register expected");
413 msg
= N_("16-bit SIMD scalar or floating-point half precision "
414 "register expected");
417 msg
= N_("32-bit SIMD scalar or floating-point single precision "
418 "register expected");
421 msg
= N_("64-bit SIMD scalar or floating-point double precision "
422 "register expected");
425 msg
= N_("128-bit SIMD scalar or floating-point quad precision "
426 "register expected");
428 case REG_TYPE_R_Z_BHSDQ_V
:
429 case REG_TYPE_R_Z_SP_BHSDQ_VZP
:
430 msg
= N_("register expected");
432 case REG_TYPE_BHSDQ
: /* any [BHSDQ]P FP */
433 msg
= N_("SIMD scalar or floating-point register expected");
435 case REG_TYPE_VN
: /* any V reg */
436 msg
= N_("vector register expected");
439 msg
= N_("SVE vector register expected");
442 msg
= N_("SVE predicate register expected");
445 as_fatal (_("invalid register type %d"), reg_type
);
450 /* Some well known registers that we refer to directly elsewhere. */
453 /* Instructions take 4 bytes in the object file. */
456 static struct hash_control
*aarch64_ops_hsh
;
457 static struct hash_control
*aarch64_cond_hsh
;
458 static struct hash_control
*aarch64_shift_hsh
;
459 static struct hash_control
*aarch64_sys_regs_hsh
;
460 static struct hash_control
*aarch64_pstatefield_hsh
;
461 static struct hash_control
*aarch64_sys_regs_ic_hsh
;
462 static struct hash_control
*aarch64_sys_regs_dc_hsh
;
463 static struct hash_control
*aarch64_sys_regs_at_hsh
;
464 static struct hash_control
*aarch64_sys_regs_tlbi_hsh
;
465 static struct hash_control
*aarch64_sys_regs_sr_hsh
;
466 static struct hash_control
*aarch64_reg_hsh
;
467 static struct hash_control
*aarch64_barrier_opt_hsh
;
468 static struct hash_control
*aarch64_nzcv_hsh
;
469 static struct hash_control
*aarch64_pldop_hsh
;
470 static struct hash_control
*aarch64_hint_opt_hsh
;
472 /* Stuff needed to resolve the label ambiguity
481 static symbolS
*last_label_seen
;
483 /* Literal pool structure. Held on a per-section
484 and per-sub-section basis. */
486 #define MAX_LITERAL_POOL_SIZE 1024
487 typedef struct literal_expression
490 /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */
491 LITTLENUM_TYPE
* bignum
;
492 } literal_expression
;
494 typedef struct literal_pool
496 literal_expression literals
[MAX_LITERAL_POOL_SIZE
];
497 unsigned int next_free_entry
;
503 struct literal_pool
*next
;
506 /* Pointer to a linked list of literal pools. */
507 static literal_pool
*list_of_pools
= NULL
;
511 /* This array holds the chars that always start a comment. If the
512 pre-processor is disabled, these aren't very useful. */
513 const char comment_chars
[] = "";
515 /* This array holds the chars that only start a comment at the beginning of
516 a line. If the line seems to have the form '# 123 filename'
517 .line and .file directives will appear in the pre-processed output. */
518 /* Note that input_file.c hand checks for '#' at the beginning of the
519 first line of the input file. This is because the compiler outputs
520 #NO_APP at the beginning of its output. */
521 /* Also note that comments like this one will always work. */
522 const char line_comment_chars
[] = "#";
524 const char line_separator_chars
[] = ";";
526 /* Chars that can be used to separate mant
527 from exp in floating point numbers. */
528 const char EXP_CHARS
[] = "eE";
530 /* Chars that mean this number is a floating point constant. */
534 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
536 /* Prefix character that indicates the start of an immediate value. */
537 #define is_immediate_prefix(C) ((C) == '#')
539 /* Separator character handling. */
541 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
543 static inline bfd_boolean
544 skip_past_char (char **str
, char c
)
555 #define skip_past_comma(str) skip_past_char (str, ',')
557 /* Arithmetic expressions (possibly involving symbols). */
559 static bfd_boolean in_my_get_expression_p
= FALSE
;
561 /* Third argument to my_get_expression. */
562 #define GE_NO_PREFIX 0
563 #define GE_OPT_PREFIX 1
565 /* Return TRUE if the string pointed by *STR is successfully parsed
566 as an valid expression; *EP will be filled with the information of
567 such an expression. Otherwise return FALSE. */
570 my_get_expression (expressionS
* ep
, char **str
, int prefix_mode
,
575 int prefix_present_p
= 0;
582 if (is_immediate_prefix (**str
))
585 prefix_present_p
= 1;
592 memset (ep
, 0, sizeof (expressionS
));
594 save_in
= input_line_pointer
;
595 input_line_pointer
= *str
;
596 in_my_get_expression_p
= TRUE
;
597 seg
= expression (ep
);
598 in_my_get_expression_p
= FALSE
;
600 if (ep
->X_op
== O_illegal
|| (reject_absent
&& ep
->X_op
== O_absent
))
602 /* We found a bad expression in md_operand(). */
603 *str
= input_line_pointer
;
604 input_line_pointer
= save_in
;
605 if (prefix_present_p
&& ! error_p ())
606 set_fatal_syntax_error (_("bad expression"));
608 set_first_syntax_error (_("bad expression"));
613 if (seg
!= absolute_section
614 && seg
!= text_section
615 && seg
!= data_section
616 && seg
!= bss_section
&& seg
!= undefined_section
)
618 set_syntax_error (_("bad segment"));
619 *str
= input_line_pointer
;
620 input_line_pointer
= save_in
;
627 *str
= input_line_pointer
;
628 input_line_pointer
= save_in
;
632 /* Turn a string in input_line_pointer into a floating point constant
633 of type TYPE, and store the appropriate bytes in *LITP. The number
634 of LITTLENUMS emitted is stored in *SIZEP. An error message is
635 returned, or NULL on OK. */
638 md_atof (int type
, char *litP
, int *sizeP
)
640 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
643 /* We handle all bad expressions here, so that we can report the faulty
644 instruction in the error message. */
646 md_operand (expressionS
* exp
)
648 if (in_my_get_expression_p
)
649 exp
->X_op
= O_illegal
;
652 /* Immediate values. */
654 /* Errors may be set multiple times during parsing or bit encoding
655 (particularly in the Neon bits), but usually the earliest error which is set
656 will be the most meaningful. Avoid overwriting it with later (cascading)
657 errors by calling this function. */
660 first_error (const char *error
)
663 set_syntax_error (error
);
666 /* Similar to first_error, but this function accepts formatted error
669 first_error_fmt (const char *format
, ...)
674 /* N.B. this single buffer will not cause error messages for different
675 instructions to pollute each other; this is because at the end of
676 processing of each assembly line, error message if any will be
677 collected by as_bad. */
678 static char buffer
[size
];
682 int ret ATTRIBUTE_UNUSED
;
683 va_start (args
, format
);
684 ret
= vsnprintf (buffer
, size
, format
, args
);
685 know (ret
<= size
- 1 && ret
>= 0);
687 set_syntax_error (buffer
);
691 /* Register parsing. */
693 /* Generic register parser which is called by other specialized
695 CCP points to what should be the beginning of a register name.
696 If it is indeed a valid register name, advance CCP over it and
697 return the reg_entry structure; otherwise return NULL.
698 It does not issue diagnostics. */
701 parse_reg (char **ccp
)
707 #ifdef REGISTER_PREFIX
708 if (*start
!= REGISTER_PREFIX
)
714 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
719 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
721 reg
= (reg_entry
*) hash_find_n (aarch64_reg_hsh
, start
, p
- start
);
730 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
733 aarch64_check_reg_type (const reg_entry
*reg
, aarch64_reg_type type
)
735 return (reg_type_masks
[type
] & (1 << reg
->type
)) != 0;
738 /* Try to parse a base or offset register. Allow SVE base and offset
739 registers if REG_TYPE includes SVE registers. Return the register
740 entry on success, setting *QUALIFIER to the register qualifier.
741 Return null otherwise.
743 Note that this function does not issue any diagnostics. */
745 static const reg_entry
*
746 aarch64_addr_reg_parse (char **ccp
, aarch64_reg_type reg_type
,
747 aarch64_opnd_qualifier_t
*qualifier
)
750 const reg_entry
*reg
= parse_reg (&str
);
760 *qualifier
= AARCH64_OPND_QLF_W
;
766 *qualifier
= AARCH64_OPND_QLF_X
;
770 if ((reg_type_masks
[reg_type
] & (1 << REG_TYPE_ZN
)) == 0
773 switch (TOLOWER (str
[1]))
776 *qualifier
= AARCH64_OPND_QLF_S_S
;
779 *qualifier
= AARCH64_OPND_QLF_S_D
;
796 /* Try to parse a base or offset register. Return the register entry
797 on success, setting *QUALIFIER to the register qualifier. Return null
800 Note that this function does not issue any diagnostics. */
802 static const reg_entry
*
803 aarch64_reg_parse_32_64 (char **ccp
, aarch64_opnd_qualifier_t
*qualifier
)
805 return aarch64_addr_reg_parse (ccp
, REG_TYPE_R_Z_SP
, qualifier
);
808 /* Parse the qualifier of a vector register or vector element of type
809 REG_TYPE. Fill in *PARSED_TYPE and return TRUE if the parsing
810 succeeds; otherwise return FALSE.
812 Accept only one occurrence of:
813 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
816 parse_vector_type_for_operand (aarch64_reg_type reg_type
,
817 struct vector_type_el
*parsed_type
, char **str
)
821 unsigned element_size
;
822 enum vector_el_type type
;
825 gas_assert (*ptr
== '.');
828 if (reg_type
== REG_TYPE_ZN
|| reg_type
== REG_TYPE_PN
|| !ISDIGIT (*ptr
))
833 width
= strtoul (ptr
, &ptr
, 10);
834 if (width
!= 1 && width
!= 2 && width
!= 4 && width
!= 8 && width
!= 16)
836 first_error_fmt (_("bad size %d in vector width specifier"), width
);
841 switch (TOLOWER (*ptr
))
860 if (reg_type
== REG_TYPE_ZN
|| width
== 1)
869 first_error_fmt (_("unexpected character `%c' in element size"), *ptr
);
871 first_error (_("missing element size"));
874 if (width
!= 0 && width
* element_size
!= 64
875 && width
* element_size
!= 128
876 && !(width
== 2 && element_size
== 16)
877 && !(width
== 4 && element_size
== 8))
880 ("invalid element size %d and vector size combination %c"),
886 parsed_type
->type
= type
;
887 parsed_type
->width
= width
;
894 /* *STR contains an SVE zero/merge predication suffix. Parse it into
895 *PARSED_TYPE and point *STR at the end of the suffix. */
898 parse_predication_for_operand (struct vector_type_el
*parsed_type
, char **str
)
903 gas_assert (*ptr
== '/');
905 switch (TOLOWER (*ptr
))
908 parsed_type
->type
= NT_zero
;
911 parsed_type
->type
= NT_merge
;
914 if (*ptr
!= '\0' && *ptr
!= ',')
915 first_error_fmt (_("unexpected character `%c' in predication type"),
918 first_error (_("missing predication type"));
921 parsed_type
->width
= 0;
926 /* Parse a register of the type TYPE.
928 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
929 name or the parsed register is not of TYPE.
931 Otherwise return the register number, and optionally fill in the actual
932 type of the register in *RTYPE when multiple alternatives were given, and
933 return the register shape and element index information in *TYPEINFO.
935 IN_REG_LIST should be set with TRUE if the caller is parsing a register
939 parse_typed_reg (char **ccp
, aarch64_reg_type type
, aarch64_reg_type
*rtype
,
940 struct vector_type_el
*typeinfo
, bfd_boolean in_reg_list
)
943 const reg_entry
*reg
= parse_reg (&str
);
944 struct vector_type_el atype
;
945 struct vector_type_el parsetype
;
946 bfd_boolean is_typed_vecreg
= FALSE
;
949 atype
.type
= NT_invtype
;
957 set_default_error ();
961 if (! aarch64_check_reg_type (reg
, type
))
963 DEBUG_TRACE ("reg type check failed");
964 set_default_error ();
969 if ((type
== REG_TYPE_VN
|| type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
970 && (*str
== '.' || (type
== REG_TYPE_PN
&& *str
== '/')))
974 if (!parse_vector_type_for_operand (type
, &parsetype
, &str
))
979 if (!parse_predication_for_operand (&parsetype
, &str
))
983 /* Register if of the form Vn.[bhsdq]. */
984 is_typed_vecreg
= TRUE
;
986 if (type
== REG_TYPE_ZN
|| type
== REG_TYPE_PN
)
988 /* The width is always variable; we don't allow an integer width
990 gas_assert (parsetype
.width
== 0);
991 atype
.defined
|= NTA_HASVARWIDTH
| NTA_HASTYPE
;
993 else if (parsetype
.width
== 0)
994 /* Expect index. In the new scheme we cannot have
995 Vn.[bhsdq] represent a scalar. Therefore any
996 Vn.[bhsdq] should have an index following it.
997 Except in reglists of course. */
998 atype
.defined
|= NTA_HASINDEX
;
1000 atype
.defined
|= NTA_HASTYPE
;
1002 atype
.type
= parsetype
.type
;
1003 atype
.width
= parsetype
.width
;
1006 if (skip_past_char (&str
, '['))
1010 /* Reject Sn[index] syntax. */
1011 if (!is_typed_vecreg
)
1013 first_error (_("this type of register can't be indexed"));
1019 first_error (_("index not allowed inside register list"));
1023 atype
.defined
|= NTA_HASINDEX
;
1025 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1027 if (exp
.X_op
!= O_constant
)
1029 first_error (_("constant expression required"));
1033 if (! skip_past_char (&str
, ']'))
1036 atype
.index
= exp
.X_add_number
;
1038 else if (!in_reg_list
&& (atype
.defined
& NTA_HASINDEX
) != 0)
1040 /* Indexed vector register expected. */
1041 first_error (_("indexed vector register expected"));
1045 /* A vector reg Vn should be typed or indexed. */
1046 if (type
== REG_TYPE_VN
&& atype
.defined
== 0)
1048 first_error (_("invalid use of vector register"));
1064 Return the register number on success; return PARSE_FAIL otherwise.
1066 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
1067 the register (e.g. NEON double or quad reg when either has been requested).
1069 If this is a NEON vector register with additional type information, fill
1070 in the struct pointed to by VECTYPE (if non-NULL).
1072 This parser does not handle register list. */
1075 aarch64_reg_parse (char **ccp
, aarch64_reg_type type
,
1076 aarch64_reg_type
*rtype
, struct vector_type_el
*vectype
)
1078 struct vector_type_el atype
;
1080 int reg
= parse_typed_reg (&str
, type
, rtype
, &atype
,
1081 /*in_reg_list= */ FALSE
);
1083 if (reg
== PARSE_FAIL
)
1094 static inline bfd_boolean
1095 eq_vector_type_el (struct vector_type_el e1
, struct vector_type_el e2
)
1099 && e1
.defined
== e2
.defined
1100 && e1
.width
== e2
.width
&& e1
.index
== e2
.index
;
1103 /* This function parses a list of vector registers of type TYPE.
1104 On success, it returns the parsed register list information in the
1105 following encoded format:
1107 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1108 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1110 The information of the register shape and/or index is returned in
1113 It returns PARSE_FAIL if the register list is invalid.
1115 The list contains one to four registers.
1116 Each register can be one of:
1119 All <T> should be identical.
1120 All <index> should be identical.
1121 There are restrictions on <Vt> numbers which are checked later
1122 (by reg_list_valid_p). */
1125 parse_vector_reg_list (char **ccp
, aarch64_reg_type type
,
1126 struct vector_type_el
*vectype
)
1130 struct vector_type_el typeinfo
, typeinfo_first
;
1135 bfd_boolean error
= FALSE
;
1136 bfd_boolean expect_index
= FALSE
;
1140 set_syntax_error (_("expecting {"));
1146 typeinfo_first
.defined
= 0;
1147 typeinfo_first
.type
= NT_invtype
;
1148 typeinfo_first
.width
= -1;
1149 typeinfo_first
.index
= 0;
1158 str
++; /* skip over '-' */
1161 val
= parse_typed_reg (&str
, type
, NULL
, &typeinfo
,
1162 /*in_reg_list= */ TRUE
);
1163 if (val
== PARSE_FAIL
)
1165 set_first_syntax_error (_("invalid vector register in list"));
1169 /* reject [bhsd]n */
1170 if (type
== REG_TYPE_VN
&& typeinfo
.defined
== 0)
1172 set_first_syntax_error (_("invalid scalar register in list"));
1177 if (typeinfo
.defined
& NTA_HASINDEX
)
1178 expect_index
= TRUE
;
1182 if (val
< val_range
)
1184 set_first_syntax_error
1185 (_("invalid range in vector register list"));
1194 typeinfo_first
= typeinfo
;
1195 else if (! eq_vector_type_el (typeinfo_first
, typeinfo
))
1197 set_first_syntax_error
1198 (_("type mismatch in vector register list"));
1203 for (i
= val_range
; i
<= val
; i
++)
1205 ret_val
|= i
<< (5 * nb_regs
);
1210 while (skip_past_comma (&str
) || (in_range
= 1, *str
== '-'));
1212 skip_whitespace (str
);
1215 set_first_syntax_error (_("end of vector register list not found"));
1220 skip_whitespace (str
);
1224 if (skip_past_char (&str
, '['))
1228 my_get_expression (&exp
, &str
, GE_NO_PREFIX
, 1);
1229 if (exp
.X_op
!= O_constant
)
1231 set_first_syntax_error (_("constant expression required."));
1234 if (! skip_past_char (&str
, ']'))
1237 typeinfo_first
.index
= exp
.X_add_number
;
1241 set_first_syntax_error (_("expected index"));
1248 set_first_syntax_error (_("too many registers in vector register list"));
1251 else if (nb_regs
== 0)
1253 set_first_syntax_error (_("empty vector register list"));
1259 *vectype
= typeinfo_first
;
1261 return error
? PARSE_FAIL
: (ret_val
<< 2) | (nb_regs
- 1);
1264 /* Directives: register aliases. */
1267 insert_reg_alias (char *str
, int number
, aarch64_reg_type type
)
1272 if ((new = hash_find (aarch64_reg_hsh
, str
)) != 0)
1275 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1278 /* Only warn about a redefinition if it's not defined as the
1280 else if (new->number
!= number
|| new->type
!= type
)
1281 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1286 name
= xstrdup (str
);
1287 new = XNEW (reg_entry
);
1290 new->number
= number
;
1292 new->builtin
= FALSE
;
1294 if (hash_insert (aarch64_reg_hsh
, name
, (void *) new))
1300 /* Look for the .req directive. This is of the form:
1302 new_register_name .req existing_register_name
1304 If we find one, or if it looks sufficiently like one that we want to
1305 handle any error here, return TRUE. Otherwise return FALSE. */
1308 create_register_alias (char *newname
, char *p
)
1310 const reg_entry
*old
;
1311 char *oldname
, *nbuf
;
1314 /* The input scrubber ensures that whitespace after the mnemonic is
1315 collapsed to single spaces. */
1317 if (strncmp (oldname
, " .req ", 6) != 0)
1321 if (*oldname
== '\0')
1324 old
= hash_find (aarch64_reg_hsh
, oldname
);
1327 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
1331 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1332 the desired alias name, and p points to its end. If not, then
1333 the desired alias name is in the global original_case_string. */
1334 #ifdef TC_CASE_SENSITIVE
1337 newname
= original_case_string
;
1338 nlen
= strlen (newname
);
1341 nbuf
= xmemdup0 (newname
, nlen
);
1343 /* Create aliases under the new name as stated; an all-lowercase
1344 version of the new name; and an all-uppercase version of the new
1346 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
1348 for (p
= nbuf
; *p
; p
++)
1351 if (strncmp (nbuf
, newname
, nlen
))
1353 /* If this attempt to create an additional alias fails, do not bother
1354 trying to create the all-lower case alias. We will fail and issue
1355 a second, duplicate error message. This situation arises when the
1356 programmer does something like:
1359 The second .req creates the "Foo" alias but then fails to create
1360 the artificial FOO alias because it has already been created by the
1362 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
1369 for (p
= nbuf
; *p
; p
++)
1372 if (strncmp (nbuf
, newname
, nlen
))
1373 insert_reg_alias (nbuf
, old
->number
, old
->type
);
1380 /* Should never be called, as .req goes between the alias and the
1381 register name, not at the beginning of the line. */
1383 s_req (int a ATTRIBUTE_UNUSED
)
1385 as_bad (_("invalid syntax for .req directive"));
1388 /* The .unreq directive deletes an alias which was previously defined
1389 by .req. For example:
1395 s_unreq (int a ATTRIBUTE_UNUSED
)
1400 name
= input_line_pointer
;
1402 while (*input_line_pointer
!= 0
1403 && *input_line_pointer
!= ' ' && *input_line_pointer
!= '\n')
1404 ++input_line_pointer
;
1406 saved_char
= *input_line_pointer
;
1407 *input_line_pointer
= 0;
1410 as_bad (_("invalid syntax for .unreq directive"));
1413 reg_entry
*reg
= hash_find (aarch64_reg_hsh
, name
);
1416 as_bad (_("unknown register alias '%s'"), name
);
1417 else if (reg
->builtin
)
1418 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1425 hash_delete (aarch64_reg_hsh
, name
, FALSE
);
1426 free ((char *) reg
->name
);
1429 /* Also locate the all upper case and all lower case versions.
1430 Do not complain if we cannot find one or the other as it
1431 was probably deleted above. */
1433 nbuf
= strdup (name
);
1434 for (p
= nbuf
; *p
; p
++)
1436 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1439 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1440 free ((char *) reg
->name
);
1444 for (p
= nbuf
; *p
; p
++)
1446 reg
= hash_find (aarch64_reg_hsh
, nbuf
);
1449 hash_delete (aarch64_reg_hsh
, nbuf
, FALSE
);
1450 free ((char *) reg
->name
);
1458 *input_line_pointer
= saved_char
;
1459 demand_empty_rest_of_line ();
1462 /* Directives: Instruction set selection. */
1465 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1466 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1467 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1468 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1470 /* Create a new mapping symbol for the transition to STATE. */
1473 make_mapping_symbol (enum mstate state
, valueT value
, fragS
* frag
)
1476 const char *symname
;
1483 type
= BSF_NO_FLAGS
;
1487 type
= BSF_NO_FLAGS
;
1493 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
1494 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
1496 /* Save the mapping symbols for future reference. Also check that
1497 we do not place two mapping symbols at the same offset within a
1498 frag. We'll handle overlap between frags in
1499 check_mapping_symbols.
1501 If .fill or other data filling directive generates zero sized data,
1502 the mapping symbol for the following code will have the same value
1503 as the one generated for the data filling directive. In this case,
1504 we replace the old symbol with the new one at the same address. */
1507 if (frag
->tc_frag_data
.first_map
!= NULL
)
1509 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
1510 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
,
1513 frag
->tc_frag_data
.first_map
= symbolP
;
1515 if (frag
->tc_frag_data
.last_map
!= NULL
)
1517 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <=
1518 S_GET_VALUE (symbolP
));
1519 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
1520 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
,
1523 frag
->tc_frag_data
.last_map
= symbolP
;
1526 /* We must sometimes convert a region marked as code to data during
1527 code alignment, if an odd number of bytes have to be padded. The
1528 code mapping symbol is pushed to an aligned address. */
1531 insert_data_mapping_symbol (enum mstate state
,
1532 valueT value
, fragS
* frag
, offsetT bytes
)
1534 /* If there was already a mapping symbol, remove it. */
1535 if (frag
->tc_frag_data
.last_map
!= NULL
1536 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) ==
1537 frag
->fr_address
+ value
)
1539 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
1543 know (frag
->tc_frag_data
.first_map
== symp
);
1544 frag
->tc_frag_data
.first_map
= NULL
;
1546 frag
->tc_frag_data
.last_map
= NULL
;
1547 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
1550 make_mapping_symbol (MAP_DATA
, value
, frag
);
1551 make_mapping_symbol (state
, value
+ bytes
, frag
);
1554 static void mapping_state_2 (enum mstate state
, int max_chars
);
1556 /* Set the mapping state to STATE. Only call this when about to
1557 emit some STATE bytes to the file. */
1560 mapping_state (enum mstate state
)
1562 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1564 if (state
== MAP_INSN
)
1565 /* AArch64 instructions require 4-byte alignment. When emitting
1566 instructions into any section, record the appropriate section
1568 record_alignment (now_seg
, 2);
1570 if (mapstate
== state
)
1571 /* The mapping symbol has already been emitted.
1572 There is nothing else to do. */
1575 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1576 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
) && !subseg_text_p (now_seg
))
1577 /* Emit MAP_DATA within executable section in order. Otherwise, it will be
1578 evaluated later in the next else. */
1580 else if (TRANSITION (MAP_UNDEFINED
, MAP_INSN
))
1582 /* Only add the symbol if the offset is > 0:
1583 if we're at the first frag, check it's size > 0;
1584 if we're not at the first frag, then for sure
1585 the offset is > 0. */
1586 struct frag
*const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
1587 const int add_symbol
= (frag_now
!= frag_first
)
1588 || (frag_now_fix () > 0);
1591 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
1595 mapping_state_2 (state
, 0);
1598 /* Same as mapping_state, but MAX_CHARS bytes have already been
1599 allocated. Put the mapping symbol that far back. */
1602 mapping_state_2 (enum mstate state
, int max_chars
)
1604 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1606 if (!SEG_NORMAL (now_seg
))
1609 if (mapstate
== state
)
1610 /* The mapping symbol has already been emitted.
1611 There is nothing else to do. */
1614 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
1615 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
1618 #define mapping_state(x) /* nothing */
1619 #define mapping_state_2(x, y) /* nothing */
1622 /* Directives: sectioning and alignment. */
1625 s_bss (int ignore ATTRIBUTE_UNUSED
)
1627 /* We don't support putting frags in the BSS segment, we fake it by
1628 marking in_bss, then looking at s_skip for clues. */
1629 subseg_set (bss_section
, 0);
1630 demand_empty_rest_of_line ();
1631 mapping_state (MAP_DATA
);
1635 s_even (int ignore ATTRIBUTE_UNUSED
)
1637 /* Never make frag if expect extra pass. */
1639 frag_align (1, 0, 0);
1641 record_alignment (now_seg
, 1);
1643 demand_empty_rest_of_line ();
1646 /* Directives: Literal pools. */
1648 static literal_pool
*
1649 find_literal_pool (int size
)
1653 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
1655 if (pool
->section
== now_seg
1656 && pool
->sub_section
== now_subseg
&& pool
->size
== size
)
1663 static literal_pool
*
1664 find_or_make_literal_pool (int size
)
1666 /* Next literal pool ID number. */
1667 static unsigned int latest_pool_num
= 1;
1670 pool
= find_literal_pool (size
);
1674 /* Create a new pool. */
1675 pool
= XNEW (literal_pool
);
1679 /* Currently we always put the literal pool in the current text
1680 section. If we were generating "small" model code where we
1681 knew that all code and initialised data was within 1MB then
1682 we could output literals to mergeable, read-only data
1685 pool
->next_free_entry
= 0;
1686 pool
->section
= now_seg
;
1687 pool
->sub_section
= now_subseg
;
1689 pool
->next
= list_of_pools
;
1690 pool
->symbol
= NULL
;
1692 /* Add it to the list. */
1693 list_of_pools
= pool
;
1696 /* New pools, and emptied pools, will have a NULL symbol. */
1697 if (pool
->symbol
== NULL
)
1699 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1700 (valueT
) 0, &zero_address_frag
);
1701 pool
->id
= latest_pool_num
++;
1708 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1709 Return TRUE on success, otherwise return FALSE. */
1711 add_to_lit_pool (expressionS
*exp
, int size
)
1716 pool
= find_or_make_literal_pool (size
);
1718 /* Check if this literal value is already in the pool. */
1719 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1721 expressionS
* litexp
= & pool
->literals
[entry
].exp
;
1723 if ((litexp
->X_op
== exp
->X_op
)
1724 && (exp
->X_op
== O_constant
)
1725 && (litexp
->X_add_number
== exp
->X_add_number
)
1726 && (litexp
->X_unsigned
== exp
->X_unsigned
))
1729 if ((litexp
->X_op
== exp
->X_op
)
1730 && (exp
->X_op
== O_symbol
)
1731 && (litexp
->X_add_number
== exp
->X_add_number
)
1732 && (litexp
->X_add_symbol
== exp
->X_add_symbol
)
1733 && (litexp
->X_op_symbol
== exp
->X_op_symbol
))
1737 /* Do we need to create a new entry? */
1738 if (entry
== pool
->next_free_entry
)
1740 if (entry
>= MAX_LITERAL_POOL_SIZE
)
1742 set_syntax_error (_("literal pool overflow"));
1746 pool
->literals
[entry
].exp
= *exp
;
1747 pool
->next_free_entry
+= 1;
1748 if (exp
->X_op
== O_big
)
1750 /* PR 16688: Bignums are held in a single global array. We must
1751 copy and preserve that value now, before it is overwritten. */
1752 pool
->literals
[entry
].bignum
= XNEWVEC (LITTLENUM_TYPE
,
1754 memcpy (pool
->literals
[entry
].bignum
, generic_bignum
,
1755 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1758 pool
->literals
[entry
].bignum
= NULL
;
1761 exp
->X_op
= O_symbol
;
1762 exp
->X_add_number
= ((int) entry
) * size
;
1763 exp
->X_add_symbol
= pool
->symbol
;
1768 /* Can't use symbol_new here, so have to create a symbol and then at
1769 a later date assign it a value. That's what these functions do. */
1772 symbol_locate (symbolS
* symbolP
,
1773 const char *name
,/* It is copied, the caller can modify. */
1774 segT segment
, /* Segment identifier (SEG_<something>). */
1775 valueT valu
, /* Symbol value. */
1776 fragS
* frag
) /* Associated fragment. */
1779 char *preserved_copy_of_name
;
1781 name_length
= strlen (name
) + 1; /* +1 for \0. */
1782 obstack_grow (¬es
, name
, name_length
);
1783 preserved_copy_of_name
= obstack_finish (¬es
);
1785 #ifdef tc_canonicalize_symbol_name
1786 preserved_copy_of_name
=
1787 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1790 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1792 S_SET_SEGMENT (symbolP
, segment
);
1793 S_SET_VALUE (symbolP
, valu
);
1794 symbol_clear_list_pointers (symbolP
);
1796 symbol_set_frag (symbolP
, frag
);
1798 /* Link to end of symbol chain. */
1800 extern int symbol_table_frozen
;
1802 if (symbol_table_frozen
)
1806 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1808 obj_symbol_new_hook (symbolP
);
1810 #ifdef tc_symbol_new_hook
1811 tc_symbol_new_hook (symbolP
);
1815 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1816 #endif /* DEBUG_SYMS */
1821 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
1828 for (align
= 2; align
<= 4; align
++)
1830 int size
= 1 << align
;
1832 pool
= find_literal_pool (size
);
1833 if (pool
== NULL
|| pool
->symbol
== NULL
|| pool
->next_free_entry
== 0)
1836 /* Align pool as you have word accesses.
1837 Only make a frag if we have to. */
1839 frag_align (align
, 0, 0);
1841 mapping_state (MAP_DATA
);
1843 record_alignment (now_seg
, align
);
1845 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
1847 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
1848 (valueT
) frag_now_fix (), frag_now
);
1849 symbol_table_insert (pool
->symbol
);
1851 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
1853 expressionS
* exp
= & pool
->literals
[entry
].exp
;
1855 if (exp
->X_op
== O_big
)
1857 /* PR 16688: Restore the global bignum value. */
1858 gas_assert (pool
->literals
[entry
].bignum
!= NULL
);
1859 memcpy (generic_bignum
, pool
->literals
[entry
].bignum
,
1860 CHARS_PER_LITTLENUM
* exp
->X_add_number
);
1863 /* First output the expression in the instruction to the pool. */
1864 emit_expr (exp
, size
); /* .word|.xword */
1866 if (exp
->X_op
== O_big
)
1868 free (pool
->literals
[entry
].bignum
);
1869 pool
->literals
[entry
].bignum
= NULL
;
1873 /* Mark the pool as empty. */
1874 pool
->next_free_entry
= 0;
1875 pool
->symbol
= NULL
;
1880 /* Forward declarations for functions below, in the MD interface
1882 static fixS
*fix_new_aarch64 (fragS
*, int, short, expressionS
*, int, int);
1883 static struct reloc_table_entry
* find_reloc_table_entry (char **);
1885 /* Directives: Data. */
1886 /* N.B. the support for relocation suffix in this directive needs to be
1887 implemented properly. */
1890 s_aarch64_elf_cons (int nbytes
)
1894 #ifdef md_flush_pending_output
1895 md_flush_pending_output ();
1898 if (is_it_end_of_statement ())
1900 demand_empty_rest_of_line ();
1904 #ifdef md_cons_align
1905 md_cons_align (nbytes
);
1908 mapping_state (MAP_DATA
);
1911 struct reloc_table_entry
*reloc
;
1915 if (exp
.X_op
!= O_symbol
)
1916 emit_expr (&exp
, (unsigned int) nbytes
);
1919 skip_past_char (&input_line_pointer
, '#');
1920 if (skip_past_char (&input_line_pointer
, ':'))
1922 reloc
= find_reloc_table_entry (&input_line_pointer
);
1924 as_bad (_("unrecognized relocation suffix"));
1926 as_bad (_("unimplemented relocation suffix"));
1927 ignore_rest_of_line ();
1931 emit_expr (&exp
, (unsigned int) nbytes
);
1934 while (*input_line_pointer
++ == ',');
1936 /* Put terminator back into stream. */
1937 input_line_pointer
--;
1938 demand_empty_rest_of_line ();
1941 #endif /* OBJ_ELF */
1943 /* Output a 32-bit word, but mark as an instruction. */
1946 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED
)
1950 #ifdef md_flush_pending_output
1951 md_flush_pending_output ();
1954 if (is_it_end_of_statement ())
1956 demand_empty_rest_of_line ();
1960 /* Sections are assumed to start aligned. In executable section, there is no
1961 MAP_DATA symbol pending. So we only align the address during
1962 MAP_DATA --> MAP_INSN transition.
1963 For other sections, this is not guaranteed. */
1964 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
1965 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
1966 frag_align_code (2, 0);
1969 mapping_state (MAP_INSN
);
1975 if (exp
.X_op
!= O_constant
)
1977 as_bad (_("constant expression required"));
1978 ignore_rest_of_line ();
1982 if (target_big_endian
)
1984 unsigned int val
= exp
.X_add_number
;
1985 exp
.X_add_number
= SWAP_32 (val
);
1987 emit_expr (&exp
, 4);
1989 while (*input_line_pointer
++ == ',');
1991 /* Put terminator back into stream. */
1992 input_line_pointer
--;
1993 demand_empty_rest_of_line ();
1997 s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED
)
1999 demand_empty_rest_of_line ();
2000 struct fde_entry
*fde
= frchain_now
->frch_cfi_data
->cur_fde_data
;
2001 fde
->pauth_key
= AARCH64_PAUTH_KEY_B
;
2005 /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */
2008 s_tlsdescadd (int ignored ATTRIBUTE_UNUSED
)
2014 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2015 BFD_RELOC_AARCH64_TLSDESC_ADD
);
2017 demand_empty_rest_of_line ();
2020 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
2023 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED
)
2027 /* Since we're just labelling the code, there's no need to define a
2030 /* Make sure there is enough room in this frag for the following
2031 blr. This trick only works if the blr follows immediately after
2032 the .tlsdesc directive. */
2034 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2035 BFD_RELOC_AARCH64_TLSDESC_CALL
);
2037 demand_empty_rest_of_line ();
2040 /* Emit BFD_RELOC_AARCH64_TLSDESC_LDR on the next LDR instruction. */
2043 s_tlsdescldr (int ignored ATTRIBUTE_UNUSED
)
2049 fix_new_aarch64 (frag_now
, frag_more (0) - frag_now
->fr_literal
, 4, &exp
, 0,
2050 BFD_RELOC_AARCH64_TLSDESC_LDR
);
2052 demand_empty_rest_of_line ();
2054 #endif /* OBJ_ELF */
2056 static void s_aarch64_arch (int);
2057 static void s_aarch64_cpu (int);
2058 static void s_aarch64_arch_extension (int);
2060 /* This table describes all the machine specific pseudo-ops the assembler
2061 has to support. The fields are:
2062 pseudo-op name without dot
2063 function to call to execute this pseudo-op
2064 Integer arg to pass to the function. */
2066 const pseudo_typeS md_pseudo_table
[] = {
2067 /* Never called because '.req' does not start a line. */
2069 {"unreq", s_unreq
, 0},
2071 {"even", s_even
, 0},
2072 {"ltorg", s_ltorg
, 0},
2073 {"pool", s_ltorg
, 0},
2074 {"cpu", s_aarch64_cpu
, 0},
2075 {"arch", s_aarch64_arch
, 0},
2076 {"arch_extension", s_aarch64_arch_extension
, 0},
2077 {"inst", s_aarch64_inst
, 0},
2078 {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame
, 0},
2080 {"tlsdescadd", s_tlsdescadd
, 0},
2081 {"tlsdesccall", s_tlsdesccall
, 0},
2082 {"tlsdescldr", s_tlsdescldr
, 0},
2083 {"word", s_aarch64_elf_cons
, 4},
2084 {"long", s_aarch64_elf_cons
, 4},
2085 {"xword", s_aarch64_elf_cons
, 8},
2086 {"dword", s_aarch64_elf_cons
, 8},
2092 /* Check whether STR points to a register name followed by a comma or the
2093 end of line; REG_TYPE indicates which register types are checked
2094 against. Return TRUE if STR is such a register name; otherwise return
2095 FALSE. The function does not intend to produce any diagnostics, but since
2096 the register parser aarch64_reg_parse, which is called by this function,
2097 does produce diagnostics, we call clear_error to clear any diagnostics
2098 that may be generated by aarch64_reg_parse.
2099 Also, the function returns FALSE directly if there is any user error
2100 present at the function entry. This prevents the existing diagnostics
2101 state from being spoiled.
2102 The function currently serves parse_constant_immediate and
2103 parse_big_immediate only. */
2105 reg_name_p (char *str
, aarch64_reg_type reg_type
)
2109 /* Prevent the diagnostics state from being spoiled. */
2113 reg
= aarch64_reg_parse (&str
, reg_type
, NULL
, NULL
);
2115 /* Clear the parsing error that may be set by the reg parser. */
2118 if (reg
== PARSE_FAIL
)
2121 skip_whitespace (str
);
2122 if (*str
== ',' || is_end_of_line
[(unsigned int) *str
])
2128 /* Parser functions used exclusively in instruction operands. */
2130 /* Parse an immediate expression which may not be constant.
2132 To prevent the expression parser from pushing a register name
2133 into the symbol table as an undefined symbol, firstly a check is
2134 done to find out whether STR is a register of type REG_TYPE followed
2135 by a comma or the end of line. Return FALSE if STR is such a string. */
2138 parse_immediate_expression (char **str
, expressionS
*exp
,
2139 aarch64_reg_type reg_type
)
2141 if (reg_name_p (*str
, reg_type
))
2143 set_recoverable_error (_("immediate operand required"));
2147 my_get_expression (exp
, str
, GE_OPT_PREFIX
, 1);
2149 if (exp
->X_op
== O_absent
)
2151 set_fatal_syntax_error (_("missing immediate expression"));
2158 /* Constant immediate-value read function for use in insn parsing.
2159 STR points to the beginning of the immediate (with the optional
2160 leading #); *VAL receives the value. REG_TYPE says which register
2161 names should be treated as registers rather than as symbolic immediates.
2163 Return TRUE on success; otherwise return FALSE. */
2166 parse_constant_immediate (char **str
, int64_t *val
, aarch64_reg_type reg_type
)
2170 if (! parse_immediate_expression (str
, &exp
, reg_type
))
2173 if (exp
.X_op
!= O_constant
)
2175 set_syntax_error (_("constant expression required"));
2179 *val
= exp
.X_add_number
;
2184 encode_imm_float_bits (uint32_t imm
)
2186 return ((imm
>> 19) & 0x7f) /* b[25:19] -> b[6:0] */
2187 | ((imm
>> (31 - 7)) & 0x80); /* b[31] -> b[7] */
2190 /* Return TRUE if the single-precision floating-point value encoded in IMM
2191 can be expressed in the AArch64 8-bit signed floating-point format with
2192 3-bit exponent and normalized 4 bits of precision; in other words, the
2193 floating-point value must be expressable as
2194 (+/-) n / 16 * power (2, r)
2195 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2198 aarch64_imm_float_p (uint32_t imm
)
2200 /* If a single-precision floating-point value has the following bit
2201 pattern, it can be expressed in the AArch64 8-bit floating-point
2204 3 32222222 2221111111111
2205 1 09876543 21098765432109876543210
2206 n Eeeeeexx xxxx0000000000000000000
2208 where n, e and each x are either 0 or 1 independently, with
2213 /* Prepare the pattern for 'Eeeeee'. */
2214 if (((imm
>> 30) & 0x1) == 0)
2215 pattern
= 0x3e000000;
2217 pattern
= 0x40000000;
2219 return (imm
& 0x7ffff) == 0 /* lower 19 bits are 0. */
2220 && ((imm
& 0x7e000000) == pattern
); /* bits 25 - 29 == ~ bit 30. */
2223 /* Return TRUE if the IEEE double value encoded in IMM can be expressed
2224 as an IEEE float without any loss of precision. Store the value in
2228 can_convert_double_to_float (uint64_t imm
, uint32_t *fpword
)
2230 /* If a double-precision floating-point value has the following bit
2231 pattern, it can be expressed in a float:
2233 6 66655555555 5544 44444444 33333333 33222222 22221111 111111
2234 3 21098765432 1098 76543210 98765432 10987654 32109876 54321098 76543210
2235 n E~~~eeeeeee ssss ssssssss ssssssss SSS00000 00000000 00000000 00000000
2237 -----------------------------> nEeeeeee esssssss ssssssss sssssSSS
2238 if Eeee_eeee != 1111_1111
2240 where n, e, s and S are either 0 or 1 independently and where ~ is the
2244 uint32_t high32
= imm
>> 32;
2245 uint32_t low32
= imm
;
2247 /* Lower 29 bits need to be 0s. */
2248 if ((imm
& 0x1fffffff) != 0)
2251 /* Prepare the pattern for 'Eeeeeeeee'. */
2252 if (((high32
>> 30) & 0x1) == 0)
2253 pattern
= 0x38000000;
2255 pattern
= 0x40000000;
2258 if ((high32
& 0x78000000) != pattern
)
2261 /* Check Eeee_eeee != 1111_1111. */
2262 if ((high32
& 0x7ff00000) == 0x47f00000)
2265 *fpword
= ((high32
& 0xc0000000) /* 1 n bit and 1 E bit. */
2266 | ((high32
<< 3) & 0x3ffffff8) /* 7 e and 20 s bits. */
2267 | (low32
>> 29)); /* 3 S bits. */
2271 /* Return true if we should treat OPERAND as a double-precision
2272 floating-point operand rather than a single-precision one. */
2274 double_precision_operand_p (const aarch64_opnd_info
*operand
)
2276 /* Check for unsuffixed SVE registers, which are allowed
2277 for LDR and STR but not in instructions that require an
2278 immediate. We get better error messages if we arbitrarily
2279 pick one size, parse the immediate normally, and then
2280 report the match failure in the normal way. */
2281 return (operand
->qualifier
== AARCH64_OPND_QLF_NIL
2282 || aarch64_get_qualifier_esize (operand
->qualifier
) == 8);
2285 /* Parse a floating-point immediate. Return TRUE on success and return the
2286 value in *IMMED in the format of IEEE754 single-precision encoding.
2287 *CCP points to the start of the string; DP_P is TRUE when the immediate
2288 is expected to be in double-precision (N.B. this only matters when
2289 hexadecimal representation is involved). REG_TYPE says which register
2290 names should be treated as registers rather than as symbolic immediates.
2292 This routine accepts any IEEE float; it is up to the callers to reject
2296 parse_aarch64_imm_float (char **ccp
, int *immed
, bfd_boolean dp_p
,
2297 aarch64_reg_type reg_type
)
2301 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2303 unsigned fpword
= 0;
2304 bfd_boolean hex_p
= FALSE
;
2306 skip_past_char (&str
, '#');
2309 skip_whitespace (fpnum
);
2311 if (strncmp (fpnum
, "0x", 2) == 0)
2313 /* Support the hexadecimal representation of the IEEE754 encoding.
2314 Double-precision is expected when DP_P is TRUE, otherwise the
2315 representation should be in single-precision. */
2316 if (! parse_constant_immediate (&str
, &val
, reg_type
))
2321 if (!can_convert_double_to_float (val
, &fpword
))
2324 else if ((uint64_t) val
> 0xffffffff)
2331 else if (reg_name_p (str
, reg_type
))
2333 set_recoverable_error (_("immediate operand required"));
2341 if ((str
= atof_ieee (str
, 's', words
)) == NULL
)
2344 /* Our FP word must be 32 bits (single-precision FP). */
2345 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
2347 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
2357 set_fatal_syntax_error (_("invalid floating-point constant"));
2361 /* Less-generic immediate-value read function with the possibility of loading
2362 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2365 To prevent the expression parser from pushing a register name into the
2366 symbol table as an undefined symbol, a check is firstly done to find
2367 out whether STR is a register of type REG_TYPE followed by a comma or
2368 the end of line. Return FALSE if STR is such a register. */
2371 parse_big_immediate (char **str
, int64_t *imm
, aarch64_reg_type reg_type
)
2375 if (reg_name_p (ptr
, reg_type
))
2377 set_syntax_error (_("immediate operand required"));
2381 my_get_expression (&inst
.reloc
.exp
, &ptr
, GE_OPT_PREFIX
, 1);
2383 if (inst
.reloc
.exp
.X_op
== O_constant
)
2384 *imm
= inst
.reloc
.exp
.X_add_number
;
2391 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2392 if NEED_LIBOPCODES is non-zero, the fixup will need
2393 assistance from the libopcodes. */
2396 aarch64_set_gas_internal_fixup (struct reloc
*reloc
,
2397 const aarch64_opnd_info
*operand
,
2398 int need_libopcodes_p
)
2400 reloc
->type
= BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2401 reloc
->opnd
= operand
->type
;
2402 if (need_libopcodes_p
)
2403 reloc
->need_libopcodes_p
= 1;
2406 /* Return TRUE if the instruction needs to be fixed up later internally by
2407 the GAS; otherwise return FALSE. */
2409 static inline bfd_boolean
2410 aarch64_gas_internal_fixup_p (void)
2412 return inst
.reloc
.type
== BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
;
2415 /* Assign the immediate value to the relevant field in *OPERAND if
2416 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2417 needs an internal fixup in a later stage.
2418 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2419 IMM.VALUE that may get assigned with the constant. */
2421 assign_imm_if_const_or_fixup_later (struct reloc
*reloc
,
2422 aarch64_opnd_info
*operand
,
2424 int need_libopcodes_p
,
2427 if (reloc
->exp
.X_op
== O_constant
)
2430 operand
->addr
.offset
.imm
= reloc
->exp
.X_add_number
;
2432 operand
->imm
.value
= reloc
->exp
.X_add_number
;
2433 reloc
->type
= BFD_RELOC_UNUSED
;
2437 aarch64_set_gas_internal_fixup (reloc
, operand
, need_libopcodes_p
);
2438 /* Tell libopcodes to ignore this operand or not. This is helpful
2439 when one of the operands needs to be fixed up later but we need
2440 libopcodes to check the other operands. */
2441 operand
->skip
= skip_p
;
2445 /* Relocation modifiers. Each entry in the table contains the textual
2446 name for the relocation which may be placed before a symbol used as
2447 a load/store offset, or add immediate. It must be surrounded by a
2448 leading and trailing colon, for example:
2450 ldr x0, [x1, #:rello:varsym]
2451 add x0, x1, #:rello:varsym */
2453 struct reloc_table_entry
2457 bfd_reloc_code_real_type adr_type
;
2458 bfd_reloc_code_real_type adrp_type
;
2459 bfd_reloc_code_real_type movw_type
;
2460 bfd_reloc_code_real_type add_type
;
2461 bfd_reloc_code_real_type ldst_type
;
2462 bfd_reloc_code_real_type ld_literal_type
;
2465 static struct reloc_table_entry reloc_table
[] = {
2466 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2471 BFD_RELOC_AARCH64_ADD_LO12
,
2472 BFD_RELOC_AARCH64_LDST_LO12
,
2475 /* Higher 21 bits of pc-relative page offset: ADRP */
2478 BFD_RELOC_AARCH64_ADR_HI21_PCREL
,
2484 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2487 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
,
2493 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2497 BFD_RELOC_AARCH64_MOVW_G0
,
2502 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2506 BFD_RELOC_AARCH64_MOVW_G0_S
,
2511 /* Less significant bits 0-15 of address/value: MOVK, no check */
2515 BFD_RELOC_AARCH64_MOVW_G0_NC
,
2520 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2524 BFD_RELOC_AARCH64_MOVW_G1
,
2529 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2533 BFD_RELOC_AARCH64_MOVW_G1_S
,
2538 /* Less significant bits 16-31 of address/value: MOVK, no check */
2542 BFD_RELOC_AARCH64_MOVW_G1_NC
,
2547 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2551 BFD_RELOC_AARCH64_MOVW_G2
,
2556 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2560 BFD_RELOC_AARCH64_MOVW_G2_S
,
2565 /* Less significant bits 32-47 of address/value: MOVK, no check */
2569 BFD_RELOC_AARCH64_MOVW_G2_NC
,
2574 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2578 BFD_RELOC_AARCH64_MOVW_G3
,
2583 /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
2587 BFD_RELOC_AARCH64_MOVW_PREL_G0
,
2592 /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
2596 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
,
2601 /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
2605 BFD_RELOC_AARCH64_MOVW_PREL_G1
,
2610 /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
2614 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
,
2619 /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
2623 BFD_RELOC_AARCH64_MOVW_PREL_G2
,
2628 /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
2632 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
,
2637 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2641 BFD_RELOC_AARCH64_MOVW_PREL_G3
,
2646 /* Get to the page containing GOT entry for a symbol. */
2649 BFD_RELOC_AARCH64_ADR_GOT_PAGE
,
2653 BFD_RELOC_AARCH64_GOT_LD_PREL19
},
2655 /* 12 bit offset into the page containing GOT entry for that symbol. */
2661 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
,
2664 /* 0-15 bits of address/value: MOVk, no check. */
2668 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
,
2673 /* Most significant bits 16-31 of address/value: MOVZ. */
2677 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
,
2682 /* 15 bit offset into the page containing GOT entry for that symbol. */
2688 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
,
2691 /* Get to the page containing GOT TLS entry for a symbol */
2692 {"gottprel_g0_nc", 0,
2695 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
,
2700 /* Get to the page containing GOT TLS entry for a symbol */
2704 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
,
2709 /* Get to the page containing GOT TLS entry for a symbol */
2711 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
, /* adr_type */
2712 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
,
2718 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2723 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
,
2727 /* Lower 16 bits address/value: MOVk. */
2731 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
,
2736 /* Most significant bits 16-31 of address/value: MOVZ. */
2740 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
,
2745 /* Get to the page containing GOT TLS entry for a symbol */
2747 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
, /* adr_type */
2748 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
,
2752 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
},
2754 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2759 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
,
2760 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
,
2763 /* Get to the page containing GOT TLS entry for a symbol.
2764 The same as GD, we allocate two consecutive GOT slots
2765 for module index and module offset, the only difference
2766 with GD is the module offset should be initialized to
2767 zero without any outstanding runtime relocation. */
2769 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
, /* adr_type */
2770 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
,
2776 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2777 {"tlsldm_lo12_nc", 0,
2781 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
,
2785 /* 12 bit offset into the module TLS base address. */
2790 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
,
2791 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
,
2794 /* Same as dtprel_lo12, no overflow check. */
2795 {"dtprel_lo12_nc", 0,
2799 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
,
2800 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
,
2803 /* bits[23:12] of offset to the module TLS base address. */
2808 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
,
2812 /* bits[15:0] of offset to the module TLS base address. */
2816 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
,
2821 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. */
2825 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
,
2830 /* bits[31:16] of offset to the module TLS base address. */
2834 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
,
2839 /* No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. */
2843 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
,
2848 /* bits[47:32] of offset to the module TLS base address. */
2852 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
,
2857 /* Lower 16 bit offset into GOT entry for a symbol */
2858 {"tlsdesc_off_g0_nc", 0,
2861 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
,
2866 /* Higher 16 bit offset into GOT entry for a symbol */
2867 {"tlsdesc_off_g1", 0,
2870 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
,
2875 /* Get to the page containing GOT TLS entry for a symbol */
2878 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
,
2882 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
},
2884 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2885 {"gottprel_lo12", 0,
2890 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
,
2893 /* Get tp offset for a symbol. */
2898 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2902 /* Get tp offset for a symbol. */
2907 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
,
2908 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
,
2911 /* Get tp offset for a symbol. */
2916 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
,
2920 /* Get tp offset for a symbol. */
2921 {"tprel_lo12_nc", 0,
2925 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
,
2926 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
,
2929 /* Most significant bits 32-47 of address/value: MOVZ. */
2933 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
,
2938 /* Most significant bits 16-31 of address/value: MOVZ. */
2942 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
,
2947 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2951 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
,
2956 /* Most significant bits 0-15 of address/value: MOVZ. */
2960 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
,
2965 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2969 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
,
2974 /* 15bit offset from got entry to base address of GOT table. */
2980 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
,
2983 /* 14bit offset from got entry to base address of GOT table. */
2989 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
,
2993 /* Given the address of a pointer pointing to the textual name of a
2994 relocation as may appear in assembler source, attempt to find its
2995 details in reloc_table. The pointer will be updated to the character
2996 after the trailing colon. On failure, NULL will be returned;
2997 otherwise return the reloc_table_entry. */
2999 static struct reloc_table_entry
*
3000 find_reloc_table_entry (char **str
)
3003 for (i
= 0; i
< ARRAY_SIZE (reloc_table
); i
++)
3005 int length
= strlen (reloc_table
[i
].name
);
3007 if (strncasecmp (reloc_table
[i
].name
, *str
, length
) == 0
3008 && (*str
)[length
] == ':')
3010 *str
+= (length
+ 1);
3011 return &reloc_table
[i
];
3018 /* Mode argument to parse_shift and parser_shifter_operand. */
3019 enum parse_shift_mode
3021 SHIFTED_NONE
, /* no shifter allowed */
3022 SHIFTED_ARITH_IMM
, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
3024 SHIFTED_LOGIC_IMM
, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
3026 SHIFTED_LSL
, /* bare "lsl #n" */
3027 SHIFTED_MUL
, /* bare "mul #n" */
3028 SHIFTED_LSL_MSL
, /* "lsl|msl #n" */
3029 SHIFTED_MUL_VL
, /* "mul vl" */
3030 SHIFTED_REG_OFFSET
/* [su]xtw|sxtx {#n} or lsl #n */
3033 /* Parse a <shift> operator on an AArch64 data processing instruction.
3034 Return TRUE on success; otherwise return FALSE. */
3036 parse_shift (char **str
, aarch64_opnd_info
*operand
, enum parse_shift_mode mode
)
3038 const struct aarch64_name_value_pair
*shift_op
;
3039 enum aarch64_modifier_kind kind
;
3045 for (p
= *str
; ISALPHA (*p
); p
++)
3050 set_syntax_error (_("shift expression expected"));
3054 shift_op
= hash_find_n (aarch64_shift_hsh
, *str
, p
- *str
);
3056 if (shift_op
== NULL
)
3058 set_syntax_error (_("shift operator expected"));
3062 kind
= aarch64_get_operand_modifier (shift_op
);
3064 if (kind
== AARCH64_MOD_MSL
&& mode
!= SHIFTED_LSL_MSL
)
3066 set_syntax_error (_("invalid use of 'MSL'"));
3070 if (kind
== AARCH64_MOD_MUL
3071 && mode
!= SHIFTED_MUL
3072 && mode
!= SHIFTED_MUL_VL
)
3074 set_syntax_error (_("invalid use of 'MUL'"));
3080 case SHIFTED_LOGIC_IMM
:
3081 if (aarch64_extend_operator_p (kind
))
3083 set_syntax_error (_("extending shift is not permitted"));
3088 case SHIFTED_ARITH_IMM
:
3089 if (kind
== AARCH64_MOD_ROR
)
3091 set_syntax_error (_("'ROR' shift is not permitted"));
3097 if (kind
!= AARCH64_MOD_LSL
)
3099 set_syntax_error (_("only 'LSL' shift is permitted"));
3105 if (kind
!= AARCH64_MOD_MUL
)
3107 set_syntax_error (_("only 'MUL' is permitted"));
3112 case SHIFTED_MUL_VL
:
3113 /* "MUL VL" consists of two separate tokens. Require the first
3114 token to be "MUL" and look for a following "VL". */
3115 if (kind
== AARCH64_MOD_MUL
)
3117 skip_whitespace (p
);
3118 if (strncasecmp (p
, "vl", 2) == 0 && !ISALPHA (p
[2]))
3121 kind
= AARCH64_MOD_MUL_VL
;
3125 set_syntax_error (_("only 'MUL VL' is permitted"));
3128 case SHIFTED_REG_OFFSET
:
3129 if (kind
!= AARCH64_MOD_UXTW
&& kind
!= AARCH64_MOD_LSL
3130 && kind
!= AARCH64_MOD_SXTW
&& kind
!= AARCH64_MOD_SXTX
)
3132 set_fatal_syntax_error
3133 (_("invalid shift for the register offset addressing mode"));
3138 case SHIFTED_LSL_MSL
:
3139 if (kind
!= AARCH64_MOD_LSL
&& kind
!= AARCH64_MOD_MSL
)
3141 set_syntax_error (_("invalid shift operator"));
3150 /* Whitespace can appear here if the next thing is a bare digit. */
3151 skip_whitespace (p
);
3153 /* Parse shift amount. */
3155 if ((mode
== SHIFTED_REG_OFFSET
&& *p
== ']') || kind
== AARCH64_MOD_MUL_VL
)
3156 exp
.X_op
= O_absent
;
3159 if (is_immediate_prefix (*p
))
3164 my_get_expression (&exp
, &p
, GE_NO_PREFIX
, 0);
3166 if (kind
== AARCH64_MOD_MUL_VL
)
3167 /* For consistency, give MUL VL the same shift amount as an implicit
3169 operand
->shifter
.amount
= 1;
3170 else if (exp
.X_op
== O_absent
)
3172 if (!aarch64_extend_operator_p (kind
) || exp_has_prefix
)
3174 set_syntax_error (_("missing shift amount"));
3177 operand
->shifter
.amount
= 0;
3179 else if (exp
.X_op
!= O_constant
)
3181 set_syntax_error (_("constant shift amount required"));
3184 /* For parsing purposes, MUL #n has no inherent range. The range
3185 depends on the operand and will be checked by operand-specific
3187 else if (kind
!= AARCH64_MOD_MUL
3188 && (exp
.X_add_number
< 0 || exp
.X_add_number
> 63))
3190 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
3195 operand
->shifter
.amount
= exp
.X_add_number
;
3196 operand
->shifter
.amount_present
= 1;
3199 operand
->shifter
.operator_present
= 1;
3200 operand
->shifter
.kind
= kind
;
3206 /* Parse a <shifter_operand> for a data processing instruction:
3209 #<immediate>, LSL #imm
3211 Validation of immediate operands is deferred to md_apply_fix.
3213 Return TRUE on success; otherwise return FALSE. */
3216 parse_shifter_operand_imm (char **str
, aarch64_opnd_info
*operand
,
3217 enum parse_shift_mode mode
)
3221 if (mode
!= SHIFTED_ARITH_IMM
&& mode
!= SHIFTED_LOGIC_IMM
)
3226 /* Accept an immediate expression. */
3227 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX
, 1))
3230 /* Accept optional LSL for arithmetic immediate values. */
3231 if (mode
== SHIFTED_ARITH_IMM
&& skip_past_comma (&p
))
3232 if (! parse_shift (&p
, operand
, SHIFTED_LSL
))
3235 /* Not accept any shifter for logical immediate values. */
3236 if (mode
== SHIFTED_LOGIC_IMM
&& skip_past_comma (&p
)
3237 && parse_shift (&p
, operand
, mode
))
3239 set_syntax_error (_("unexpected shift operator"));
3247 /* Parse a <shifter_operand> for a data processing instruction:
3252 #<immediate>, LSL #imm
3254 where <shift> is handled by parse_shift above, and the last two
3255 cases are handled by the function above.
3257 Validation of immediate operands is deferred to md_apply_fix.
3259 Return TRUE on success; otherwise return FALSE. */
3262 parse_shifter_operand (char **str
, aarch64_opnd_info
*operand
,
3263 enum parse_shift_mode mode
)
3265 const reg_entry
*reg
;
3266 aarch64_opnd_qualifier_t qualifier
;
3267 enum aarch64_operand_class opd_class
3268 = aarch64_get_operand_class (operand
->type
);
3270 reg
= aarch64_reg_parse_32_64 (str
, &qualifier
);
3273 if (opd_class
== AARCH64_OPND_CLASS_IMMEDIATE
)
3275 set_syntax_error (_("unexpected register in the immediate operand"));
3279 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_Z
))
3281 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z
)));
3285 operand
->reg
.regno
= reg
->number
;
3286 operand
->qualifier
= qualifier
;
3288 /* Accept optional shift operation on register. */
3289 if (! skip_past_comma (str
))
3292 if (! parse_shift (str
, operand
, mode
))
3297 else if (opd_class
== AARCH64_OPND_CLASS_MODIFIED_REG
)
3300 (_("integer register expected in the extended/shifted operand "
3305 /* We have a shifted immediate variable. */
3306 return parse_shifter_operand_imm (str
, operand
, mode
);
3309 /* Return TRUE on success; return FALSE otherwise. */
3312 parse_shifter_operand_reloc (char **str
, aarch64_opnd_info
*operand
,
3313 enum parse_shift_mode mode
)
3317 /* Determine if we have the sequence of characters #: or just :
3318 coming next. If we do, then we check for a :rello: relocation
3319 modifier. If we don't, punt the whole lot to
3320 parse_shifter_operand. */
3322 if ((p
[0] == '#' && p
[1] == ':') || p
[0] == ':')
3324 struct reloc_table_entry
*entry
;
3332 /* Try to parse a relocation. Anything else is an error. */
3333 if (!(entry
= find_reloc_table_entry (str
)))
3335 set_syntax_error (_("unknown relocation modifier"));
3339 if (entry
->add_type
== 0)
3342 (_("this relocation modifier is not allowed on this instruction"));
3346 /* Save str before we decompose it. */
3349 /* Next, we parse the expression. */
3350 if (! my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
, 1))
3353 /* Record the relocation type (use the ADD variant here). */
3354 inst
.reloc
.type
= entry
->add_type
;
3355 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3357 /* If str is empty, we've reached the end, stop here. */
3361 /* Otherwise, we have a shifted reloc modifier, so rewind to
3362 recover the variable name and continue parsing for the shifter. */
3364 return parse_shifter_operand_imm (str
, operand
, mode
);
3367 return parse_shifter_operand (str
, operand
, mode
);
3370 /* Parse all forms of an address expression. Information is written
3371 to *OPERAND and/or inst.reloc.
3373 The A64 instruction set has the following addressing modes:
3376 [base] // in SIMD ld/st structure
3377 [base{,#0}] // in ld/st exclusive
3379 [base,Xm{,LSL #imm}]
3380 [base,Xm,SXTX {#imm}]
3381 [base,Wm,(S|U)XTW {#imm}]
3386 [base],Xm // in SIMD ld/st structure
3387 PC-relative (literal)
3391 [base,Zm.D{,LSL #imm}]
3392 [base,Zm.S,(S|U)XTW {#imm}]
3393 [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
3396 [Zn.S,Zm.S{,LSL #imm}] // in ADR
3397 [Zn.D,Zm.D{,LSL #imm}] // in ADR
3398 [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
3400 (As a convenience, the notation "=immediate" is permitted in conjunction
3401 with the pc-relative literal load instructions to automatically place an
3402 immediate value or symbolic address in a nearby literal pool and generate
3403 a hidden label which references it.)
3405 Upon a successful parsing, the address structure in *OPERAND will be
3406 filled in the following way:
3408 .base_regno = <base>
3409 .offset.is_reg // 1 if the offset is a register
3411 .offset.regno = <Rm>
3413 For different addressing modes defined in the A64 ISA:
3416 .pcrel=0; .preind=1; .postind=0; .writeback=0
3418 .pcrel=0; .preind=1; .postind=0; .writeback=1
3420 .pcrel=0; .preind=0; .postind=1; .writeback=1
3421 PC-relative (literal)
3422 .pcrel=1; .preind=1; .postind=0; .writeback=0
3424 The shift/extension information, if any, will be stored in .shifter.
3425 The base and offset qualifiers will be stored in *BASE_QUALIFIER and
3426 *OFFSET_QUALIFIER respectively, with NIL being used if there's no
3427 corresponding register.
3429 BASE_TYPE says which types of base register should be accepted and
3430 OFFSET_TYPE says the same for offset registers. IMM_SHIFT_MODE
3431 is the type of shifter that is allowed for immediate offsets,
3432 or SHIFTED_NONE if none.
3434 In all other respects, it is the caller's responsibility to check
3435 for addressing modes not supported by the instruction, and to set
3439 parse_address_main (char **str
, aarch64_opnd_info
*operand
,
3440 aarch64_opnd_qualifier_t
*base_qualifier
,
3441 aarch64_opnd_qualifier_t
*offset_qualifier
,
3442 aarch64_reg_type base_type
, aarch64_reg_type offset_type
,
3443 enum parse_shift_mode imm_shift_mode
)
3446 const reg_entry
*reg
;
3447 expressionS
*exp
= &inst
.reloc
.exp
;
3449 *base_qualifier
= AARCH64_OPND_QLF_NIL
;
3450 *offset_qualifier
= AARCH64_OPND_QLF_NIL
;
3451 if (! skip_past_char (&p
, '['))
3453 /* =immediate or label. */
3454 operand
->addr
.pcrel
= 1;
3455 operand
->addr
.preind
= 1;
3457 /* #:<reloc_op>:<symbol> */
3458 skip_past_char (&p
, '#');
3459 if (skip_past_char (&p
, ':'))
3461 bfd_reloc_code_real_type ty
;
3462 struct reloc_table_entry
*entry
;
3464 /* Try to parse a relocation modifier. Anything else is
3466 entry
= find_reloc_table_entry (&p
);
3469 set_syntax_error (_("unknown relocation modifier"));
3473 switch (operand
->type
)
3475 case AARCH64_OPND_ADDR_PCREL21
:
3477 ty
= entry
->adr_type
;
3481 ty
= entry
->ld_literal_type
;
3488 (_("this relocation modifier is not allowed on this "
3494 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3496 set_syntax_error (_("invalid relocation expression"));
3500 /* #:<reloc_op>:<expr> */
3501 /* Record the relocation type. */
3502 inst
.reloc
.type
= ty
;
3503 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3508 if (skip_past_char (&p
, '='))
3509 /* =immediate; need to generate the literal in the literal pool. */
3510 inst
.gen_lit_pool
= 1;
3512 if (!my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3514 set_syntax_error (_("invalid address"));
3525 reg
= aarch64_addr_reg_parse (&p
, base_type
, base_qualifier
);
3526 if (!reg
|| !aarch64_check_reg_type (reg
, base_type
))
3528 set_syntax_error (_(get_reg_expected_msg (base_type
)));
3531 operand
->addr
.base_regno
= reg
->number
;
3534 if (skip_past_comma (&p
))
3537 operand
->addr
.preind
= 1;
3539 reg
= aarch64_addr_reg_parse (&p
, offset_type
, offset_qualifier
);
3542 if (!aarch64_check_reg_type (reg
, offset_type
))
3544 set_syntax_error (_(get_reg_expected_msg (offset_type
)));
3549 operand
->addr
.offset
.regno
= reg
->number
;
3550 operand
->addr
.offset
.is_reg
= 1;
3551 /* Shifted index. */
3552 if (skip_past_comma (&p
))
3555 if (! parse_shift (&p
, operand
, SHIFTED_REG_OFFSET
))
3556 /* Use the diagnostics set in parse_shift, so not set new
3557 error message here. */
3561 [base,Xm{,LSL #imm}]
3562 [base,Xm,SXTX {#imm}]
3563 [base,Wm,(S|U)XTW {#imm}] */
3564 if (operand
->shifter
.kind
== AARCH64_MOD_NONE
3565 || operand
->shifter
.kind
== AARCH64_MOD_LSL
3566 || operand
->shifter
.kind
== AARCH64_MOD_SXTX
)
3568 if (*offset_qualifier
== AARCH64_OPND_QLF_W
)
3570 set_syntax_error (_("invalid use of 32-bit register offset"));
3573 if (aarch64_get_qualifier_esize (*base_qualifier
)
3574 != aarch64_get_qualifier_esize (*offset_qualifier
))
3576 set_syntax_error (_("offset has different size from base"));
3580 else if (*offset_qualifier
== AARCH64_OPND_QLF_X
)
3582 set_syntax_error (_("invalid use of 64-bit register offset"));
3588 /* [Xn,#:<reloc_op>:<symbol> */
3589 skip_past_char (&p
, '#');
3590 if (skip_past_char (&p
, ':'))
3592 struct reloc_table_entry
*entry
;
3594 /* Try to parse a relocation modifier. Anything else is
3596 if (!(entry
= find_reloc_table_entry (&p
)))
3598 set_syntax_error (_("unknown relocation modifier"));
3602 if (entry
->ldst_type
== 0)
3605 (_("this relocation modifier is not allowed on this "
3610 /* [Xn,#:<reloc_op>: */
3611 /* We now have the group relocation table entry corresponding to
3612 the name in the assembler source. Next, we parse the
3614 if (! my_get_expression (exp
, &p
, GE_NO_PREFIX
, 1))
3616 set_syntax_error (_("invalid relocation expression"));
3620 /* [Xn,#:<reloc_op>:<expr> */
3621 /* Record the load/store relocation type. */
3622 inst
.reloc
.type
= entry
->ldst_type
;
3623 inst
.reloc
.pc_rel
= entry
->pc_rel
;
3627 if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3629 set_syntax_error (_("invalid expression in the address"));
3633 if (imm_shift_mode
!= SHIFTED_NONE
&& skip_past_comma (&p
))
3634 /* [Xn,<expr>,<shifter> */
3635 if (! parse_shift (&p
, operand
, imm_shift_mode
))
3641 if (! skip_past_char (&p
, ']'))
3643 set_syntax_error (_("']' expected"));
3647 if (skip_past_char (&p
, '!'))
3649 if (operand
->addr
.preind
&& operand
->addr
.offset
.is_reg
)
3651 set_syntax_error (_("register offset not allowed in pre-indexed "
3652 "addressing mode"));
3656 operand
->addr
.writeback
= 1;
3658 else if (skip_past_comma (&p
))
3661 operand
->addr
.postind
= 1;
3662 operand
->addr
.writeback
= 1;
3664 if (operand
->addr
.preind
)
3666 set_syntax_error (_("cannot combine pre- and post-indexing"));
3670 reg
= aarch64_reg_parse_32_64 (&p
, offset_qualifier
);
3674 if (!aarch64_check_reg_type (reg
, REG_TYPE_R_64
))
3676 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64
)));
3680 operand
->addr
.offset
.regno
= reg
->number
;
3681 operand
->addr
.offset
.is_reg
= 1;
3683 else if (! my_get_expression (exp
, &p
, GE_OPT_PREFIX
, 1))
3686 set_syntax_error (_("invalid expression in the address"));
3691 /* If at this point neither .preind nor .postind is set, we have a
3692 bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */
3693 if (operand
->addr
.preind
== 0 && operand
->addr
.postind
== 0)
3695 if (operand
->addr
.writeback
)
3698 set_syntax_error (_("missing offset in the pre-indexed address"));
3702 operand
->addr
.preind
= 1;
3703 inst
.reloc
.exp
.X_op
= O_constant
;
3704 inst
.reloc
.exp
.X_add_number
= 0;
3711 /* Parse a base AArch64 address (as opposed to an SVE one). Return TRUE
3714 parse_address (char **str
, aarch64_opnd_info
*operand
)
3716 aarch64_opnd_qualifier_t base_qualifier
, offset_qualifier
;
3717 return parse_address_main (str
, operand
, &base_qualifier
, &offset_qualifier
,
3718 REG_TYPE_R64_SP
, REG_TYPE_R_Z
, SHIFTED_NONE
);
3721 /* Parse an address in which SVE vector registers and MUL VL are allowed.
3722 The arguments have the same meaning as for parse_address_main.
3723 Return TRUE on success. */
3725 parse_sve_address (char **str
, aarch64_opnd_info
*operand
,
3726 aarch64_opnd_qualifier_t
*base_qualifier
,
3727 aarch64_opnd_qualifier_t
*offset_qualifier
)
3729 return parse_address_main (str
, operand
, base_qualifier
, offset_qualifier
,
3730 REG_TYPE_SVE_BASE
, REG_TYPE_SVE_OFFSET
,
3734 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3735 Return TRUE on success; otherwise return FALSE. */
3737 parse_half (char **str
, int *internal_fixup_p
)
3741 skip_past_char (&p
, '#');
3743 gas_assert (internal_fixup_p
);
3744 *internal_fixup_p
= 0;
3748 struct reloc_table_entry
*entry
;
3750 /* Try to parse a relocation. Anything else is an error. */
3752 if (!(entry
= find_reloc_table_entry (&p
)))
3754 set_syntax_error (_("unknown relocation modifier"));
3758 if (entry
->movw_type
== 0)
3761 (_("this relocation modifier is not allowed on this instruction"));
3765 inst
.reloc
.type
= entry
->movw_type
;
3768 *internal_fixup_p
= 1;
3770 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3777 /* Parse an operand for an ADRP instruction:
3779 Return TRUE on success; otherwise return FALSE. */
3782 parse_adrp (char **str
)
3789 struct reloc_table_entry
*entry
;
3791 /* Try to parse a relocation. Anything else is an error. */
3793 if (!(entry
= find_reloc_table_entry (&p
)))
3795 set_syntax_error (_("unknown relocation modifier"));
3799 if (entry
->adrp_type
== 0)
3802 (_("this relocation modifier is not allowed on this instruction"));
3806 inst
.reloc
.type
= entry
->adrp_type
;
3809 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_HI21_PCREL
;
3811 inst
.reloc
.pc_rel
= 1;
3813 if (! my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
, 1))
3820 /* Miscellaneous. */
3822 /* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
3823 of SIZE tokens in which index I gives the token for field value I,
3824 or is null if field value I is invalid. REG_TYPE says which register
3825 names should be treated as registers rather than as symbolic immediates.
3827 Return true on success, moving *STR past the operand and storing the
3828 field value in *VAL. */
3831 parse_enum_string (char **str
, int64_t *val
, const char *const *array
,
3832 size_t size
, aarch64_reg_type reg_type
)
3838 /* Match C-like tokens. */
3840 while (ISALNUM (*q
))
3843 for (i
= 0; i
< size
; ++i
)
3845 && strncasecmp (array
[i
], p
, q
- p
) == 0
3846 && array
[i
][q
- p
] == 0)
3853 if (!parse_immediate_expression (&p
, &exp
, reg_type
))
3856 if (exp
.X_op
== O_constant
3857 && (uint64_t) exp
.X_add_number
< size
)
3859 *val
= exp
.X_add_number
;
3864 /* Use the default error for this operand. */
3868 /* Parse an option for a preload instruction. Returns the encoding for the
3869 option, or PARSE_FAIL. */
3872 parse_pldop (char **str
)
3875 const struct aarch64_name_value_pair
*o
;
3878 while (ISALNUM (*q
))
3881 o
= hash_find_n (aarch64_pldop_hsh
, p
, q
- p
);
3889 /* Parse an option for a barrier instruction. Returns the encoding for the
3890 option, or PARSE_FAIL. */
3893 parse_barrier (char **str
)
3896 const asm_barrier_opt
*o
;
3899 while (ISALPHA (*q
))
3902 o
= hash_find_n (aarch64_barrier_opt_hsh
, p
, q
- p
);
3910 /* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
3911 return 0 if successful. Otherwise return PARSE_FAIL. */
3914 parse_barrier_psb (char **str
,
3915 const struct aarch64_name_value_pair
** hint_opt
)
3918 const struct aarch64_name_value_pair
*o
;
3921 while (ISALPHA (*q
))
3924 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3927 set_fatal_syntax_error
3928 ( _("unknown or missing option to PSB"));
3932 if (o
->value
!= 0x11)
3934 /* PSB only accepts option name 'CSYNC'. */
3936 (_("the specified option is not accepted for PSB"));
3945 /* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
3946 return 0 if successful. Otherwise return PARSE_FAIL. */
3949 parse_bti_operand (char **str
,
3950 const struct aarch64_name_value_pair
** hint_opt
)
3953 const struct aarch64_name_value_pair
*o
;
3956 while (ISALPHA (*q
))
3959 o
= hash_find_n (aarch64_hint_opt_hsh
, p
, q
- p
);
3962 set_fatal_syntax_error
3963 ( _("unknown option to BTI"));
3969 /* Valid BTI operands. */
3977 (_("unknown option to BTI"));
3986 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3987 Returns the encoding for the option, or PARSE_FAIL.
3989 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3990 implementation defined system register name S<op0>_<op1>_<Cn>_<Cm>_<op2>.
3992 If PSTATEFIELD_P is non-zero, the function will parse the name as a PSTATE
3993 field, otherwise as a system register.
3997 parse_sys_reg (char **str
, struct hash_control
*sys_regs
,
3998 int imple_defined_p
, int pstatefield_p
,
4003 const aarch64_sys_reg
*o
;
4007 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4009 *p
++ = TOLOWER (*q
);
4011 /* Assert that BUF be large enough. */
4012 gas_assert (p
- buf
== q
- *str
);
4014 o
= hash_find (sys_regs
, buf
);
4017 if (!imple_defined_p
)
4021 /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
4022 unsigned int op0
, op1
, cn
, cm
, op2
;
4024 if (sscanf (buf
, "s%u_%u_c%u_c%u_%u", &op0
, &op1
, &cn
, &cm
, &op2
)
4027 if (op0
> 3 || op1
> 7 || cn
> 15 || cm
> 15 || op2
> 7)
4029 value
= (op0
<< 14) | (op1
<< 11) | (cn
<< 7) | (cm
<< 3) | op2
;
4036 if (pstatefield_p
&& !aarch64_pstatefield_supported_p (cpu_variant
, o
))
4037 as_bad (_("selected processor does not support PSTATE field "
4039 if (!pstatefield_p
&& !aarch64_sys_reg_supported_p (cpu_variant
, o
))
4040 as_bad (_("selected processor does not support system register "
4042 if (aarch64_sys_reg_deprecated_p (o
))
4043 as_warn (_("system register name '%s' is deprecated and may be "
4044 "removed in a future release"), buf
);
4054 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
4055 for the option, or NULL. */
4057 static const aarch64_sys_ins_reg
*
4058 parse_sys_ins_reg (char **str
, struct hash_control
*sys_ins_regs
)
4062 const aarch64_sys_ins_reg
*o
;
4065 for (q
= *str
; ISALNUM (*q
) || *q
== '_'; q
++)
4067 *p
++ = TOLOWER (*q
);
4070 o
= hash_find (sys_ins_regs
, buf
);
4074 if (!aarch64_sys_ins_reg_supported_p (cpu_variant
, o
))
4075 as_bad (_("selected processor does not support system register "
4082 #define po_char_or_fail(chr) do { \
4083 if (! skip_past_char (&str, chr)) \
4087 #define po_reg_or_fail(regtype) do { \
4088 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
4089 if (val == PARSE_FAIL) \
4091 set_default_error (); \
4096 #define po_int_reg_or_fail(reg_type) do { \
4097 reg = aarch64_reg_parse_32_64 (&str, &qualifier); \
4098 if (!reg || !aarch64_check_reg_type (reg, reg_type)) \
4100 set_default_error (); \
4103 info->reg.regno = reg->number; \
4104 info->qualifier = qualifier; \
4107 #define po_imm_nc_or_fail() do { \
4108 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4112 #define po_imm_or_fail(min, max) do { \
4113 if (! parse_constant_immediate (&str, &val, imm_reg_type)) \
4115 if (val < min || val > max) \
4117 set_fatal_syntax_error (_("immediate value out of range "\
4118 #min " to "#max)); \
4123 #define po_enum_or_fail(array) do { \
4124 if (!parse_enum_string (&str, &val, array, \
4125 ARRAY_SIZE (array), imm_reg_type)) \
4129 #define po_misc_or_fail(expr) do { \
4134 /* encode the 12-bit imm field of Add/sub immediate */
4135 static inline uint32_t
4136 encode_addsub_imm (uint32_t imm
)
4141 /* encode the shift amount field of Add/sub immediate */
4142 static inline uint32_t
4143 encode_addsub_imm_shift_amount (uint32_t cnt
)
4149 /* encode the imm field of Adr instruction */
4150 static inline uint32_t
4151 encode_adr_imm (uint32_t imm
)
4153 return (((imm
& 0x3) << 29) /* [1:0] -> [30:29] */
4154 | ((imm
& (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
4157 /* encode the immediate field of Move wide immediate */
4158 static inline uint32_t
4159 encode_movw_imm (uint32_t imm
)
4164 /* encode the 26-bit offset of unconditional branch */
4165 static inline uint32_t
4166 encode_branch_ofs_26 (uint32_t ofs
)
4168 return ofs
& ((1 << 26) - 1);
4171 /* encode the 19-bit offset of conditional branch and compare & branch */
4172 static inline uint32_t
4173 encode_cond_branch_ofs_19 (uint32_t ofs
)
4175 return (ofs
& ((1 << 19) - 1)) << 5;
4178 /* encode the 19-bit offset of ld literal */
4179 static inline uint32_t
4180 encode_ld_lit_ofs_19 (uint32_t ofs
)
4182 return (ofs
& ((1 << 19) - 1)) << 5;
4185 /* Encode the 14-bit offset of test & branch. */
4186 static inline uint32_t
4187 encode_tst_branch_ofs_14 (uint32_t ofs
)
4189 return (ofs
& ((1 << 14) - 1)) << 5;
4192 /* Encode the 16-bit imm field of svc/hvc/smc. */
4193 static inline uint32_t
4194 encode_svc_imm (uint32_t imm
)
4199 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
4200 static inline uint32_t
4201 reencode_addsub_switch_add_sub (uint32_t opcode
)
4203 return opcode
^ (1 << 30);
4206 static inline uint32_t
4207 reencode_movzn_to_movz (uint32_t opcode
)
4209 return opcode
| (1 << 30);
4212 static inline uint32_t
4213 reencode_movzn_to_movn (uint32_t opcode
)
4215 return opcode
& ~(1 << 30);
4218 /* Overall per-instruction processing. */
4220 /* We need to be able to fix up arbitrary expressions in some statements.
4221 This is so that we can handle symbols that are an arbitrary distance from
4222 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
4223 which returns part of an address in a form which will be valid for
4224 a data instruction. We do this by pushing the expression into a symbol
4225 in the expr_section, and creating a fix for that. */
4228 fix_new_aarch64 (fragS
* frag
,
4230 short int size
, expressionS
* exp
, int pc_rel
, int reloc
)
4240 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
4244 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
4251 /* Diagnostics on operands errors. */
4253 /* By default, output verbose error message.
4254 Disable the verbose error message by -mno-verbose-error. */
4255 static int verbose_error_p
= 1;
4257 #ifdef DEBUG_AARCH64
4258 /* N.B. this is only for the purpose of debugging. */
4259 const char* operand_mismatch_kind_names
[] =
4262 "AARCH64_OPDE_RECOVERABLE",
4263 "AARCH64_OPDE_SYNTAX_ERROR",
4264 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
4265 "AARCH64_OPDE_INVALID_VARIANT",
4266 "AARCH64_OPDE_OUT_OF_RANGE",
4267 "AARCH64_OPDE_UNALIGNED",
4268 "AARCH64_OPDE_REG_LIST",
4269 "AARCH64_OPDE_OTHER_ERROR",
4271 #endif /* DEBUG_AARCH64 */
4273 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
4275 When multiple errors of different kinds are found in the same assembly
4276 line, only the error of the highest severity will be picked up for
4277 issuing the diagnostics. */
4279 static inline bfd_boolean
4280 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs
,
4281 enum aarch64_operand_error_kind rhs
)
4283 gas_assert (AARCH64_OPDE_RECOVERABLE
> AARCH64_OPDE_NIL
);
4284 gas_assert (AARCH64_OPDE_SYNTAX_ERROR
> AARCH64_OPDE_RECOVERABLE
);
4285 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR
> AARCH64_OPDE_SYNTAX_ERROR
);
4286 gas_assert (AARCH64_OPDE_INVALID_VARIANT
> AARCH64_OPDE_FATAL_SYNTAX_ERROR
);
4287 gas_assert (AARCH64_OPDE_OUT_OF_RANGE
> AARCH64_OPDE_INVALID_VARIANT
);
4288 gas_assert (AARCH64_OPDE_UNALIGNED
> AARCH64_OPDE_OUT_OF_RANGE
);
4289 gas_assert (AARCH64_OPDE_REG_LIST
> AARCH64_OPDE_UNALIGNED
);
4290 gas_assert (AARCH64_OPDE_OTHER_ERROR
> AARCH64_OPDE_REG_LIST
);
4294 /* Helper routine to get the mnemonic name from the assembly instruction
4295 line; should only be called for the diagnosis purpose, as there is
4296 string copy operation involved, which may affect the runtime
4297 performance if used in elsewhere. */
4300 get_mnemonic_name (const char *str
)
4302 static char mnemonic
[32];
4305 /* Get the first 15 bytes and assume that the full name is included. */
4306 strncpy (mnemonic
, str
, 31);
4307 mnemonic
[31] = '\0';
4309 /* Scan up to the end of the mnemonic, which must end in white space,
4310 '.', or end of string. */
4311 for (ptr
= mnemonic
; is_part_of_name(*ptr
); ++ptr
)
4316 /* Append '...' to the truncated long name. */
4317 if (ptr
- mnemonic
== 31)
4318 mnemonic
[28] = mnemonic
[29] = mnemonic
[30] = '.';
4324 reset_aarch64_instruction (aarch64_instruction
*instruction
)
4326 memset (instruction
, '\0', sizeof (aarch64_instruction
));
4327 instruction
->reloc
.type
= BFD_RELOC_UNUSED
;
4330 /* Data structures storing one user error in the assembly code related to
4333 struct operand_error_record
4335 const aarch64_opcode
*opcode
;
4336 aarch64_operand_error detail
;
4337 struct operand_error_record
*next
;
4340 typedef struct operand_error_record operand_error_record
;
4342 struct operand_errors
4344 operand_error_record
*head
;
4345 operand_error_record
*tail
;
4348 typedef struct operand_errors operand_errors
;
4350 /* Top-level data structure reporting user errors for the current line of
4352 The way md_assemble works is that all opcodes sharing the same mnemonic
4353 name are iterated to find a match to the assembly line. In this data
4354 structure, each of the such opcodes will have one operand_error_record
4355 allocated and inserted. In other words, excessive errors related with
4356 a single opcode are disregarded. */
4357 operand_errors operand_error_report
;
4359 /* Free record nodes. */
4360 static operand_error_record
*free_opnd_error_record_nodes
= NULL
;
4362 /* Initialize the data structure that stores the operand mismatch
4363 information on assembling one line of the assembly code. */
4365 init_operand_error_report (void)
4367 if (operand_error_report
.head
!= NULL
)
4369 gas_assert (operand_error_report
.tail
!= NULL
);
4370 operand_error_report
.tail
->next
= free_opnd_error_record_nodes
;
4371 free_opnd_error_record_nodes
= operand_error_report
.head
;
4372 operand_error_report
.head
= NULL
;
4373 operand_error_report
.tail
= NULL
;
4376 gas_assert (operand_error_report
.tail
== NULL
);
4379 /* Return TRUE if some operand error has been recorded during the
4380 parsing of the current assembly line using the opcode *OPCODE;
4381 otherwise return FALSE. */
4382 static inline bfd_boolean
4383 opcode_has_operand_error_p (const aarch64_opcode
*opcode
)
4385 operand_error_record
*record
= operand_error_report
.head
;
4386 return record
&& record
->opcode
== opcode
;
4389 /* Add the error record *NEW_RECORD to operand_error_report. The record's
4390 OPCODE field is initialized with OPCODE.
4391 N.B. only one record for each opcode, i.e. the maximum of one error is
4392 recorded for each instruction template. */
4395 add_operand_error_record (const operand_error_record
* new_record
)
4397 const aarch64_opcode
*opcode
= new_record
->opcode
;
4398 operand_error_record
* record
= operand_error_report
.head
;
4400 /* The record may have been created for this opcode. If not, we need
4402 if (! opcode_has_operand_error_p (opcode
))
4404 /* Get one empty record. */
4405 if (free_opnd_error_record_nodes
== NULL
)
4407 record
= XNEW (operand_error_record
);
4411 record
= free_opnd_error_record_nodes
;
4412 free_opnd_error_record_nodes
= record
->next
;
4414 record
->opcode
= opcode
;
4415 /* Insert at the head. */
4416 record
->next
= operand_error_report
.head
;
4417 operand_error_report
.head
= record
;
4418 if (operand_error_report
.tail
== NULL
)
4419 operand_error_report
.tail
= record
;
4421 else if (record
->detail
.kind
!= AARCH64_OPDE_NIL
4422 && record
->detail
.index
<= new_record
->detail
.index
4423 && operand_error_higher_severity_p (record
->detail
.kind
,
4424 new_record
->detail
.kind
))
4426 /* In the case of multiple errors found on operands related with a
4427 single opcode, only record the error of the leftmost operand and
4428 only if the error is of higher severity. */
4429 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
4430 " the existing error %s on operand %d",
4431 operand_mismatch_kind_names
[new_record
->detail
.kind
],
4432 new_record
->detail
.index
,
4433 operand_mismatch_kind_names
[record
->detail
.kind
],
4434 record
->detail
.index
);
4438 record
->detail
= new_record
->detail
;
4442 record_operand_error_info (const aarch64_opcode
*opcode
,
4443 aarch64_operand_error
*error_info
)
4445 operand_error_record record
;
4446 record
.opcode
= opcode
;
4447 record
.detail
= *error_info
;
4448 add_operand_error_record (&record
);
4451 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
4452 error message *ERROR, for operand IDX (count from 0). */
4455 record_operand_error (const aarch64_opcode
*opcode
, int idx
,
4456 enum aarch64_operand_error_kind kind
,
4459 aarch64_operand_error info
;
4460 memset(&info
, 0, sizeof (info
));
4464 info
.non_fatal
= FALSE
;
4465 record_operand_error_info (opcode
, &info
);
4469 record_operand_error_with_data (const aarch64_opcode
*opcode
, int idx
,
4470 enum aarch64_operand_error_kind kind
,
4471 const char* error
, const int *extra_data
)
4473 aarch64_operand_error info
;
4477 info
.data
[0] = extra_data
[0];
4478 info
.data
[1] = extra_data
[1];
4479 info
.data
[2] = extra_data
[2];
4480 info
.non_fatal
= FALSE
;
4481 record_operand_error_info (opcode
, &info
);
4485 record_operand_out_of_range_error (const aarch64_opcode
*opcode
, int idx
,
4486 const char* error
, int lower_bound
,
4489 int data
[3] = {lower_bound
, upper_bound
, 0};
4490 record_operand_error_with_data (opcode
, idx
, AARCH64_OPDE_OUT_OF_RANGE
,
4494 /* Remove the operand error record for *OPCODE. */
4495 static void ATTRIBUTE_UNUSED
4496 remove_operand_error_record (const aarch64_opcode
*opcode
)
4498 if (opcode_has_operand_error_p (opcode
))
4500 operand_error_record
* record
= operand_error_report
.head
;
4501 gas_assert (record
!= NULL
&& operand_error_report
.tail
!= NULL
);
4502 operand_error_report
.head
= record
->next
;
4503 record
->next
= free_opnd_error_record_nodes
;
4504 free_opnd_error_record_nodes
= record
;
4505 if (operand_error_report
.head
== NULL
)
4507 gas_assert (operand_error_report
.tail
== record
);
4508 operand_error_report
.tail
= NULL
;
4513 /* Given the instruction in *INSTR, return the index of the best matched
4514 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
4516 Return -1 if there is no qualifier sequence; return the first match
4517 if there is multiple matches found. */
4520 find_best_match (const aarch64_inst
*instr
,
4521 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
)
4523 int i
, num_opnds
, max_num_matched
, idx
;
4525 num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4528 DEBUG_TRACE ("no operand");
4532 max_num_matched
= 0;
4535 /* For each pattern. */
4536 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4539 const aarch64_opnd_qualifier_t
*qualifiers
= *qualifiers_list
;
4541 /* Most opcodes has much fewer patterns in the list. */
4542 if (empty_qualifier_sequence_p (qualifiers
))
4544 DEBUG_TRACE_IF (i
== 0, "empty list of qualifier sequence");
4548 for (j
= 0, num_matched
= 0; j
< num_opnds
; ++j
, ++qualifiers
)
4549 if (*qualifiers
== instr
->operands
[j
].qualifier
)
4552 if (num_matched
> max_num_matched
)
4554 max_num_matched
= num_matched
;
4559 DEBUG_TRACE ("return with %d", idx
);
4563 /* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
4564 corresponding operands in *INSTR. */
4567 assign_qualifier_sequence (aarch64_inst
*instr
,
4568 const aarch64_opnd_qualifier_t
*qualifiers
)
4571 int num_opnds
= aarch64_num_of_operands (instr
->opcode
);
4572 gas_assert (num_opnds
);
4573 for (i
= 0; i
< num_opnds
; ++i
, ++qualifiers
)
4574 instr
->operands
[i
].qualifier
= *qualifiers
;
4577 /* Print operands for the diagnosis purpose. */
4580 print_operands (char *buf
, const aarch64_opcode
*opcode
,
4581 const aarch64_opnd_info
*opnds
)
4585 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
4589 /* We regard the opcode operand info more, however we also look into
4590 the inst->operands to support the disassembling of the optional
4592 The two operand code should be the same in all cases, apart from
4593 when the operand can be optional. */
4594 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
4595 || opnds
[i
].type
== AARCH64_OPND_NIL
)
4598 /* Generate the operand string in STR. */
4599 aarch64_print_operand (str
, sizeof (str
), 0, opcode
, opnds
, i
, NULL
, NULL
,
4604 strcat (buf
, i
== 0 ? " " : ", ");
4606 /* Append the operand string. */
4611 /* Send to stderr a string as information. */
4614 output_info (const char *format
, ...)
4620 file
= as_where (&line
);
4624 fprintf (stderr
, "%s:%u: ", file
, line
);
4626 fprintf (stderr
, "%s: ", file
);
4628 fprintf (stderr
, _("Info: "));
4629 va_start (args
, format
);
4630 vfprintf (stderr
, format
, args
);
4632 (void) putc ('\n', stderr
);
4635 /* Output one operand error record. */
4638 output_operand_error_record (const operand_error_record
*record
, char *str
)
4640 const aarch64_operand_error
*detail
= &record
->detail
;
4641 int idx
= detail
->index
;
4642 const aarch64_opcode
*opcode
= record
->opcode
;
4643 enum aarch64_opnd opd_code
= (idx
>= 0 ? opcode
->operands
[idx
]
4644 : AARCH64_OPND_NIL
);
4646 typedef void (*handler_t
)(const char *format
, ...);
4647 handler_t handler
= detail
->non_fatal
? as_warn
: as_bad
;
4649 switch (detail
->kind
)
4651 case AARCH64_OPDE_NIL
:
4654 case AARCH64_OPDE_SYNTAX_ERROR
:
4655 case AARCH64_OPDE_RECOVERABLE
:
4656 case AARCH64_OPDE_FATAL_SYNTAX_ERROR
:
4657 case AARCH64_OPDE_OTHER_ERROR
:
4658 /* Use the prepared error message if there is, otherwise use the
4659 operand description string to describe the error. */
4660 if (detail
->error
!= NULL
)
4663 handler (_("%s -- `%s'"), detail
->error
, str
);
4665 handler (_("%s at operand %d -- `%s'"),
4666 detail
->error
, idx
+ 1, str
);
4670 gas_assert (idx
>= 0);
4671 handler (_("operand %d must be %s -- `%s'"), idx
+ 1,
4672 aarch64_get_operand_desc (opd_code
), str
);
4676 case AARCH64_OPDE_INVALID_VARIANT
:
4677 handler (_("operand mismatch -- `%s'"), str
);
4678 if (verbose_error_p
)
4680 /* We will try to correct the erroneous instruction and also provide
4681 more information e.g. all other valid variants.
4683 The string representation of the corrected instruction and other
4684 valid variants are generated by
4686 1) obtaining the intermediate representation of the erroneous
4688 2) manipulating the IR, e.g. replacing the operand qualifier;
4689 3) printing out the instruction by calling the printer functions
4690 shared with the disassembler.
4692 The limitation of this method is that the exact input assembly
4693 line cannot be accurately reproduced in some cases, for example an
4694 optional operand present in the actual assembly line will be
4695 omitted in the output; likewise for the optional syntax rules,
4696 e.g. the # before the immediate. Another limitation is that the
4697 assembly symbols and relocation operations in the assembly line
4698 currently cannot be printed out in the error report. Last but not
4699 least, when there is other error(s) co-exist with this error, the
4700 'corrected' instruction may be still incorrect, e.g. given
4701 'ldnp h0,h1,[x0,#6]!'
4702 this diagnosis will provide the version:
4703 'ldnp s0,s1,[x0,#6]!'
4704 which is still not right. */
4705 size_t len
= strlen (get_mnemonic_name (str
));
4709 aarch64_inst
*inst_base
= &inst
.base
;
4710 const aarch64_opnd_qualifier_seq_t
*qualifiers_list
;
4713 reset_aarch64_instruction (&inst
);
4714 inst_base
->opcode
= opcode
;
4716 /* Reset the error report so that there is no side effect on the
4717 following operand parsing. */
4718 init_operand_error_report ();
4721 result
= parse_operands (str
+ len
, opcode
)
4722 && programmer_friendly_fixup (&inst
);
4723 gas_assert (result
);
4724 result
= aarch64_opcode_encode (opcode
, inst_base
, &inst_base
->value
,
4725 NULL
, NULL
, insn_sequence
);
4726 gas_assert (!result
);
4728 /* Find the most matched qualifier sequence. */
4729 qlf_idx
= find_best_match (inst_base
, opcode
->qualifiers_list
);
4730 gas_assert (qlf_idx
> -1);
4732 /* Assign the qualifiers. */
4733 assign_qualifier_sequence (inst_base
,
4734 opcode
->qualifiers_list
[qlf_idx
]);
4736 /* Print the hint. */
4737 output_info (_(" did you mean this?"));
4738 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4739 print_operands (buf
, opcode
, inst_base
->operands
);
4740 output_info (_(" %s"), buf
);
4742 /* Print out other variant(s) if there is any. */
4744 !empty_qualifier_sequence_p (opcode
->qualifiers_list
[1]))
4745 output_info (_(" other valid variant(s):"));
4747 /* For each pattern. */
4748 qualifiers_list
= opcode
->qualifiers_list
;
4749 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
, ++qualifiers_list
)
4751 /* Most opcodes has much fewer patterns in the list.
4752 First NIL qualifier indicates the end in the list. */
4753 if (empty_qualifier_sequence_p (*qualifiers_list
))
4758 /* Mnemonics name. */
4759 snprintf (buf
, sizeof (buf
), "\t%s", get_mnemonic_name (str
));
4761 /* Assign the qualifiers. */
4762 assign_qualifier_sequence (inst_base
, *qualifiers_list
);
4764 /* Print instruction. */
4765 print_operands (buf
, opcode
, inst_base
->operands
);
4767 output_info (_(" %s"), buf
);
4773 case AARCH64_OPDE_UNTIED_OPERAND
:
4774 handler (_("operand %d must be the same register as operand 1 -- `%s'"),
4775 detail
->index
+ 1, str
);
4778 case AARCH64_OPDE_OUT_OF_RANGE
:
4779 if (detail
->data
[0] != detail
->data
[1])
4780 handler (_("%s out of range %d to %d at operand %d -- `%s'"),
4781 detail
->error
? detail
->error
: _("immediate value"),
4782 detail
->data
[0], detail
->data
[1], idx
+ 1, str
);
4784 handler (_("%s must be %d at operand %d -- `%s'"),
4785 detail
->error
? detail
->error
: _("immediate value"),
4786 detail
->data
[0], idx
+ 1, str
);
4789 case AARCH64_OPDE_REG_LIST
:
4790 if (detail
->data
[0] == 1)
4791 handler (_("invalid number of registers in the list; "
4792 "only 1 register is expected at operand %d -- `%s'"),
4795 handler (_("invalid number of registers in the list; "
4796 "%d registers are expected at operand %d -- `%s'"),
4797 detail
->data
[0], idx
+ 1, str
);
4800 case AARCH64_OPDE_UNALIGNED
:
4801 handler (_("immediate value must be a multiple of "
4802 "%d at operand %d -- `%s'"),
4803 detail
->data
[0], idx
+ 1, str
);
4812 /* Process and output the error message about the operand mismatching.
4814 When this function is called, the operand error information had
4815 been collected for an assembly line and there will be multiple
4816 errors in the case of multiple instruction templates; output the
4817 error message that most closely describes the problem.
4819 The errors to be printed can be filtered on printing all errors
4820 or only non-fatal errors. This distinction has to be made because
4821 the error buffer may already be filled with fatal errors we don't want to
4822 print due to the different instruction templates. */
4825 output_operand_error_report (char *str
, bfd_boolean non_fatal_only
)
4827 int largest_error_pos
;
4828 const char *msg
= NULL
;
4829 enum aarch64_operand_error_kind kind
;
4830 operand_error_record
*curr
;
4831 operand_error_record
*head
= operand_error_report
.head
;
4832 operand_error_record
*record
= NULL
;
4834 /* No error to report. */
4838 gas_assert (head
!= NULL
&& operand_error_report
.tail
!= NULL
);
4840 /* Only one error. */
4841 if (head
== operand_error_report
.tail
)
4843 /* If the only error is a non-fatal one and we don't want to print it,
4845 if (!non_fatal_only
|| head
->detail
.non_fatal
)
4847 DEBUG_TRACE ("single opcode entry with error kind: %s",
4848 operand_mismatch_kind_names
[head
->detail
.kind
]);
4849 output_operand_error_record (head
, str
);
4854 /* Find the error kind of the highest severity. */
4855 DEBUG_TRACE ("multiple opcode entries with error kind");
4856 kind
= AARCH64_OPDE_NIL
;
4857 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4859 gas_assert (curr
->detail
.kind
!= AARCH64_OPDE_NIL
);
4860 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names
[curr
->detail
.kind
]);
4861 if (operand_error_higher_severity_p (curr
->detail
.kind
, kind
)
4862 && (!non_fatal_only
|| (non_fatal_only
&& curr
->detail
.non_fatal
)))
4863 kind
= curr
->detail
.kind
;
4866 gas_assert (kind
!= AARCH64_OPDE_NIL
|| non_fatal_only
);
4868 /* Pick up one of errors of KIND to report. */
4869 largest_error_pos
= -2; /* Index can be -1 which means unknown index. */
4870 for (curr
= head
; curr
!= NULL
; curr
= curr
->next
)
4872 /* If we don't want to print non-fatal errors then don't consider them
4874 if (curr
->detail
.kind
!= kind
4875 || (non_fatal_only
&& !curr
->detail
.non_fatal
))
4877 /* If there are multiple errors, pick up the one with the highest
4878 mismatching operand index. In the case of multiple errors with
4879 the equally highest operand index, pick up the first one or the
4880 first one with non-NULL error message. */
4881 if (curr
->detail
.index
> largest_error_pos
4882 || (curr
->detail
.index
== largest_error_pos
&& msg
== NULL
4883 && curr
->detail
.error
!= NULL
))
4885 largest_error_pos
= curr
->detail
.index
;
4887 msg
= record
->detail
.error
;
4891 /* The way errors are collected in the back-end is a bit non-intuitive. But
4892 essentially, because each operand template is tried recursively you may
4893 always have errors collected from the previous tried OPND. These are
4894 usually skipped if there is one successful match. However now with the
4895 non-fatal errors we have to ignore those previously collected hard errors
4896 when we're only interested in printing the non-fatal ones. This condition
4897 prevents us from printing errors that are not appropriate, since we did
4898 match a condition, but it also has warnings that it wants to print. */
4899 if (non_fatal_only
&& !record
)
4902 gas_assert (largest_error_pos
!= -2 && record
!= NULL
);
4903 DEBUG_TRACE ("Pick up error kind %s to report",
4904 operand_mismatch_kind_names
[record
->detail
.kind
]);
4907 output_operand_error_record (record
, str
);
4910 /* Write an AARCH64 instruction to buf - always little-endian. */
4912 put_aarch64_insn (char *buf
, uint32_t insn
)
4914 unsigned char *where
= (unsigned char *) buf
;
4916 where
[1] = insn
>> 8;
4917 where
[2] = insn
>> 16;
4918 where
[3] = insn
>> 24;
4922 get_aarch64_insn (char *buf
)
4924 unsigned char *where
= (unsigned char *) buf
;
4926 result
= (where
[0] | (where
[1] << 8) | (where
[2] << 16) | (where
[3] << 24));
4931 output_inst (struct aarch64_inst
*new_inst
)
4935 to
= frag_more (INSN_SIZE
);
4937 frag_now
->tc_frag_data
.recorded
= 1;
4939 put_aarch64_insn (to
, inst
.base
.value
);
4941 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4943 fixS
*fixp
= fix_new_aarch64 (frag_now
, to
- frag_now
->fr_literal
,
4944 INSN_SIZE
, &inst
.reloc
.exp
,
4947 DEBUG_TRACE ("Prepared relocation fix up");
4948 /* Don't check the addend value against the instruction size,
4949 that's the job of our code in md_apply_fix(). */
4950 fixp
->fx_no_overflow
= 1;
4951 if (new_inst
!= NULL
)
4952 fixp
->tc_fix_data
.inst
= new_inst
;
4953 if (aarch64_gas_internal_fixup_p ())
4955 gas_assert (inst
.reloc
.opnd
!= AARCH64_OPND_NIL
);
4956 fixp
->tc_fix_data
.opnd
= inst
.reloc
.opnd
;
4957 fixp
->fx_addnumber
= inst
.reloc
.flags
;
4961 dwarf2_emit_insn (INSN_SIZE
);
4964 /* Link together opcodes of the same name. */
4968 aarch64_opcode
*opcode
;
4969 struct templates
*next
;
4972 typedef struct templates templates
;
4975 lookup_mnemonic (const char *start
, int len
)
4977 templates
*templ
= NULL
;
4979 templ
= hash_find_n (aarch64_ops_hsh
, start
, len
);
4983 /* Subroutine of md_assemble, responsible for looking up the primary
4984 opcode from the mnemonic the user wrote. STR points to the
4985 beginning of the mnemonic. */
4988 opcode_lookup (char **str
)
4990 char *end
, *base
, *dot
;
4991 const aarch64_cond
*cond
;
4995 /* Scan up to the end of the mnemonic, which must end in white space,
4996 '.', or end of string. */
4998 for (base
= end
= *str
; is_part_of_name(*end
); end
++)
4999 if (*end
== '.' && !dot
)
5002 if (end
== base
|| dot
== base
)
5005 inst
.cond
= COND_ALWAYS
;
5007 /* Handle a possible condition. */
5010 cond
= hash_find_n (aarch64_cond_hsh
, dot
+ 1, end
- dot
- 1);
5013 inst
.cond
= cond
->value
;
5029 if (inst
.cond
== COND_ALWAYS
)
5031 /* Look for unaffixed mnemonic. */
5032 return lookup_mnemonic (base
, len
);
5036 /* append ".c" to mnemonic if conditional */
5037 memcpy (condname
, base
, len
);
5038 memcpy (condname
+ len
, ".c", 2);
5041 return lookup_mnemonic (base
, len
);
5047 /* Internal helper routine converting a vector_type_el structure *VECTYPE
5048 to a corresponding operand qualifier. */
5050 static inline aarch64_opnd_qualifier_t
5051 vectype_to_qualifier (const struct vector_type_el
*vectype
)
5053 /* Element size in bytes indexed by vector_el_type. */
5054 const unsigned char ele_size
[5]
5056 const unsigned int ele_base
[5] =
5058 AARCH64_OPND_QLF_V_4B
,
5059 AARCH64_OPND_QLF_V_2H
,
5060 AARCH64_OPND_QLF_V_2S
,
5061 AARCH64_OPND_QLF_V_1D
,
5062 AARCH64_OPND_QLF_V_1Q
5065 if (!vectype
->defined
|| vectype
->type
== NT_invtype
)
5066 goto vectype_conversion_fail
;
5068 if (vectype
->type
== NT_zero
)
5069 return AARCH64_OPND_QLF_P_Z
;
5070 if (vectype
->type
== NT_merge
)
5071 return AARCH64_OPND_QLF_P_M
;
5073 gas_assert (vectype
->type
>= NT_b
&& vectype
->type
<= NT_q
);
5075 if (vectype
->defined
& (NTA_HASINDEX
| NTA_HASVARWIDTH
))
5077 /* Special case S_4B. */
5078 if (vectype
->type
== NT_b
&& vectype
->width
== 4)
5079 return AARCH64_OPND_QLF_S_4B
;
5081 /* Vector element register. */
5082 return AARCH64_OPND_QLF_S_B
+ vectype
->type
;
5086 /* Vector register. */
5087 int reg_size
= ele_size
[vectype
->type
] * vectype
->width
;
5090 if (reg_size
!= 16 && reg_size
!= 8 && reg_size
!= 4)
5091 goto vectype_conversion_fail
;
5093 /* The conversion is by calculating the offset from the base operand
5094 qualifier for the vector type. The operand qualifiers are regular
5095 enough that the offset can established by shifting the vector width by
5096 a vector-type dependent amount. */
5098 if (vectype
->type
== NT_b
)
5100 else if (vectype
->type
== NT_h
|| vectype
->type
== NT_s
)
5102 else if (vectype
->type
>= NT_d
)
5107 offset
= ele_base
[vectype
->type
] + (vectype
->width
>> shift
);
5108 gas_assert (AARCH64_OPND_QLF_V_4B
<= offset
5109 && offset
<= AARCH64_OPND_QLF_V_1Q
);
5113 vectype_conversion_fail
:
5114 first_error (_("bad vector arrangement type"));
5115 return AARCH64_OPND_QLF_NIL
;
5118 /* Process an optional operand that is found omitted from the assembly line.
5119 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
5120 instruction's opcode entry while IDX is the index of this omitted operand.
5124 process_omitted_operand (enum aarch64_opnd type
, const aarch64_opcode
*opcode
,
5125 int idx
, aarch64_opnd_info
*operand
)
5127 aarch64_insn default_value
= get_optional_operand_default_value (opcode
);
5128 gas_assert (optional_operand_p (opcode
, idx
));
5129 gas_assert (!operand
->present
);
5133 case AARCH64_OPND_Rd
:
5134 case AARCH64_OPND_Rn
:
5135 case AARCH64_OPND_Rm
:
5136 case AARCH64_OPND_Rt
:
5137 case AARCH64_OPND_Rt2
:
5138 case AARCH64_OPND_Rs
:
5139 case AARCH64_OPND_Ra
:
5140 case AARCH64_OPND_Rt_SYS
:
5141 case AARCH64_OPND_Rd_SP
:
5142 case AARCH64_OPND_Rn_SP
:
5143 case AARCH64_OPND_Rm_SP
:
5144 case AARCH64_OPND_Fd
:
5145 case AARCH64_OPND_Fn
:
5146 case AARCH64_OPND_Fm
:
5147 case AARCH64_OPND_Fa
:
5148 case AARCH64_OPND_Ft
:
5149 case AARCH64_OPND_Ft2
:
5150 case AARCH64_OPND_Sd
:
5151 case AARCH64_OPND_Sn
:
5152 case AARCH64_OPND_Sm
:
5153 case AARCH64_OPND_Va
:
5154 case AARCH64_OPND_Vd
:
5155 case AARCH64_OPND_Vn
:
5156 case AARCH64_OPND_Vm
:
5157 case AARCH64_OPND_VdD1
:
5158 case AARCH64_OPND_VnD1
:
5159 operand
->reg
.regno
= default_value
;
5162 case AARCH64_OPND_Ed
:
5163 case AARCH64_OPND_En
:
5164 case AARCH64_OPND_Em
:
5165 case AARCH64_OPND_Em16
:
5166 case AARCH64_OPND_SM3_IMM2
:
5167 operand
->reglane
.regno
= default_value
;
5170 case AARCH64_OPND_IDX
:
5171 case AARCH64_OPND_BIT_NUM
:
5172 case AARCH64_OPND_IMMR
:
5173 case AARCH64_OPND_IMMS
:
5174 case AARCH64_OPND_SHLL_IMM
:
5175 case AARCH64_OPND_IMM_VLSL
:
5176 case AARCH64_OPND_IMM_VLSR
:
5177 case AARCH64_OPND_CCMP_IMM
:
5178 case AARCH64_OPND_FBITS
:
5179 case AARCH64_OPND_UIMM4
:
5180 case AARCH64_OPND_UIMM3_OP1
:
5181 case AARCH64_OPND_UIMM3_OP2
:
5182 case AARCH64_OPND_IMM
:
5183 case AARCH64_OPND_IMM_2
:
5184 case AARCH64_OPND_WIDTH
:
5185 case AARCH64_OPND_UIMM7
:
5186 case AARCH64_OPND_NZCV
:
5187 case AARCH64_OPND_SVE_PATTERN
:
5188 case AARCH64_OPND_SVE_PRFOP
:
5189 operand
->imm
.value
= default_value
;
5192 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5193 operand
->imm
.value
= default_value
;
5194 operand
->shifter
.kind
= AARCH64_MOD_MUL
;
5195 operand
->shifter
.amount
= 1;
5198 case AARCH64_OPND_EXCEPTION
:
5199 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
5202 case AARCH64_OPND_BARRIER_ISB
:
5203 operand
->barrier
= aarch64_barrier_options
+ default_value
;
5206 case AARCH64_OPND_BTI_TARGET
:
5207 operand
->hint_option
= aarch64_hint_options
+ default_value
;
5215 /* Process the relocation type for move wide instructions.
5216 Return TRUE on success; otherwise return FALSE. */
5219 process_movw_reloc_info (void)
5224 is32
= inst
.base
.operands
[0].qualifier
== AARCH64_OPND_QLF_W
? 1 : 0;
5226 if (inst
.base
.opcode
->op
== OP_MOVK
)
5227 switch (inst
.reloc
.type
)
5229 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5230 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5231 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5232 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5233 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5234 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5235 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5236 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5237 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5238 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5239 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5241 (_("the specified relocation type is not allowed for MOVK"));
5247 switch (inst
.reloc
.type
)
5249 case BFD_RELOC_AARCH64_MOVW_G0
:
5250 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
5251 case BFD_RELOC_AARCH64_MOVW_G0_S
:
5252 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
5253 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
5254 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
5255 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
5256 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
5257 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
5258 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
5259 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
5260 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
5261 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
5264 case BFD_RELOC_AARCH64_MOVW_G1
:
5265 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
5266 case BFD_RELOC_AARCH64_MOVW_G1_S
:
5267 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
5268 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
5269 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
5270 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
5271 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
5272 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
5273 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
5274 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
5275 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
5276 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
5279 case BFD_RELOC_AARCH64_MOVW_G2
:
5280 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
5281 case BFD_RELOC_AARCH64_MOVW_G2_S
:
5282 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
5283 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
5284 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
5285 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
5288 set_fatal_syntax_error
5289 (_("the specified relocation type is not allowed for 32-bit "
5295 case BFD_RELOC_AARCH64_MOVW_G3
:
5296 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
5299 set_fatal_syntax_error
5300 (_("the specified relocation type is not allowed for 32-bit "
5307 /* More cases should be added when more MOVW-related relocation types
5308 are supported in GAS. */
5309 gas_assert (aarch64_gas_internal_fixup_p ());
5310 /* The shift amount should have already been set by the parser. */
5313 inst
.base
.operands
[1].shifter
.amount
= shift
;
5317 /* A primitive log calculator. */
5319 static inline unsigned int
5320 get_logsz (unsigned int size
)
5322 const unsigned char ls
[16] =
5323 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
5329 gas_assert (ls
[size
- 1] != (unsigned char)-1);
5330 return ls
[size
- 1];
5333 /* Determine and return the real reloc type code for an instruction
5334 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
5336 static inline bfd_reloc_code_real_type
5337 ldst_lo12_determine_real_reloc_type (void)
5340 enum aarch64_opnd_qualifier opd0_qlf
= inst
.base
.operands
[0].qualifier
;
5341 enum aarch64_opnd_qualifier opd1_qlf
= inst
.base
.operands
[1].qualifier
;
5343 const bfd_reloc_code_real_type reloc_ldst_lo12
[5][5] = {
5345 BFD_RELOC_AARCH64_LDST8_LO12
,
5346 BFD_RELOC_AARCH64_LDST16_LO12
,
5347 BFD_RELOC_AARCH64_LDST32_LO12
,
5348 BFD_RELOC_AARCH64_LDST64_LO12
,
5349 BFD_RELOC_AARCH64_LDST128_LO12
5352 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
,
5353 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
,
5354 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
,
5355 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
,
5356 BFD_RELOC_AARCH64_NONE
5359 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
,
5360 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
,
5361 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
,
5362 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
,
5363 BFD_RELOC_AARCH64_NONE
5366 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
,
5367 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
,
5368 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
,
5369 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
,
5370 BFD_RELOC_AARCH64_NONE
5373 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
,
5374 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
,
5375 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
,
5376 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
,
5377 BFD_RELOC_AARCH64_NONE
5381 gas_assert (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
5382 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5384 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
5386 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
5388 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
));
5389 gas_assert (inst
.base
.opcode
->operands
[1] == AARCH64_OPND_ADDR_UIMM12
);
5391 if (opd1_qlf
== AARCH64_OPND_QLF_NIL
)
5393 aarch64_get_expected_qualifier (inst
.base
.opcode
->qualifiers_list
,
5395 gas_assert (opd1_qlf
!= AARCH64_OPND_QLF_NIL
);
5397 logsz
= get_logsz (aarch64_get_qualifier_esize (opd1_qlf
));
5398 if (inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
5399 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
5400 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
5401 || inst
.reloc
.type
== BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
)
5402 gas_assert (logsz
<= 3);
5404 gas_assert (logsz
<= 4);
5406 /* In reloc.c, these pseudo relocation types should be defined in similar
5407 order as above reloc_ldst_lo12 array. Because the array index calculation
5408 below relies on this. */
5409 return reloc_ldst_lo12
[inst
.reloc
.type
- BFD_RELOC_AARCH64_LDST_LO12
][logsz
];
5412 /* Check whether a register list REGINFO is valid. The registers must be
5413 numbered in increasing order (modulo 32), in increments of one or two.
5415 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
5418 Return FALSE if such a register list is invalid, otherwise return TRUE. */
5421 reg_list_valid_p (uint32_t reginfo
, int accept_alternate
)
5423 uint32_t i
, nb_regs
, prev_regno
, incr
;
5425 nb_regs
= 1 + (reginfo
& 0x3);
5427 prev_regno
= reginfo
& 0x1f;
5428 incr
= accept_alternate
? 2 : 1;
5430 for (i
= 1; i
< nb_regs
; ++i
)
5432 uint32_t curr_regno
;
5434 curr_regno
= reginfo
& 0x1f;
5435 if (curr_regno
!= ((prev_regno
+ incr
) & 0x1f))
5437 prev_regno
= curr_regno
;
5443 /* Generic instruction operand parser. This does no encoding and no
5444 semantic validation; it merely squirrels values away in the inst
5445 structure. Returns TRUE or FALSE depending on whether the
5446 specified grammar matched. */
5449 parse_operands (char *str
, const aarch64_opcode
*opcode
)
5452 char *backtrack_pos
= 0;
5453 const enum aarch64_opnd
*operands
= opcode
->operands
;
5454 aarch64_reg_type imm_reg_type
;
5457 skip_whitespace (str
);
5459 if (AARCH64_CPU_HAS_FEATURE (AARCH64_FEATURE_SVE
, *opcode
->avariant
))
5460 imm_reg_type
= REG_TYPE_R_Z_SP_BHSDQ_VZP
;
5462 imm_reg_type
= REG_TYPE_R_Z_BHSDQ_V
;
5464 for (i
= 0; operands
[i
] != AARCH64_OPND_NIL
; i
++)
5467 const reg_entry
*reg
;
5468 int comma_skipped_p
= 0;
5469 aarch64_reg_type rtype
;
5470 struct vector_type_el vectype
;
5471 aarch64_opnd_qualifier_t qualifier
, base_qualifier
, offset_qualifier
;
5472 aarch64_opnd_info
*info
= &inst
.base
.operands
[i
];
5473 aarch64_reg_type reg_type
;
5475 DEBUG_TRACE ("parse operand %d", i
);
5477 /* Assign the operand code. */
5478 info
->type
= operands
[i
];
5480 if (optional_operand_p (opcode
, i
))
5482 /* Remember where we are in case we need to backtrack. */
5483 gas_assert (!backtrack_pos
);
5484 backtrack_pos
= str
;
5487 /* Expect comma between operands; the backtrack mechanism will take
5488 care of cases of omitted optional operand. */
5489 if (i
> 0 && ! skip_past_char (&str
, ','))
5491 set_syntax_error (_("comma expected between operands"));
5495 comma_skipped_p
= 1;
5497 switch (operands
[i
])
5499 case AARCH64_OPND_Rd
:
5500 case AARCH64_OPND_Rn
:
5501 case AARCH64_OPND_Rm
:
5502 case AARCH64_OPND_Rt
:
5503 case AARCH64_OPND_Rt2
:
5504 case AARCH64_OPND_Rs
:
5505 case AARCH64_OPND_Ra
:
5506 case AARCH64_OPND_Rt_SYS
:
5507 case AARCH64_OPND_PAIRREG
:
5508 case AARCH64_OPND_SVE_Rm
:
5509 po_int_reg_or_fail (REG_TYPE_R_Z
);
5512 case AARCH64_OPND_Rd_SP
:
5513 case AARCH64_OPND_Rn_SP
:
5514 case AARCH64_OPND_SVE_Rn_SP
:
5515 case AARCH64_OPND_Rm_SP
:
5516 po_int_reg_or_fail (REG_TYPE_R_SP
);
5519 case AARCH64_OPND_Rm_EXT
:
5520 case AARCH64_OPND_Rm_SFT
:
5521 po_misc_or_fail (parse_shifter_operand
5522 (&str
, info
, (operands
[i
] == AARCH64_OPND_Rm_EXT
5524 : SHIFTED_LOGIC_IMM
)));
5525 if (!info
->shifter
.operator_present
)
5527 /* Default to LSL if not present. Libopcodes prefers shifter
5528 kind to be explicit. */
5529 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5530 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5531 /* For Rm_EXT, libopcodes will carry out further check on whether
5532 or not stack pointer is used in the instruction (Recall that
5533 "the extend operator is not optional unless at least one of
5534 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
5538 case AARCH64_OPND_Fd
:
5539 case AARCH64_OPND_Fn
:
5540 case AARCH64_OPND_Fm
:
5541 case AARCH64_OPND_Fa
:
5542 case AARCH64_OPND_Ft
:
5543 case AARCH64_OPND_Ft2
:
5544 case AARCH64_OPND_Sd
:
5545 case AARCH64_OPND_Sn
:
5546 case AARCH64_OPND_Sm
:
5547 case AARCH64_OPND_SVE_VZn
:
5548 case AARCH64_OPND_SVE_Vd
:
5549 case AARCH64_OPND_SVE_Vm
:
5550 case AARCH64_OPND_SVE_Vn
:
5551 val
= aarch64_reg_parse (&str
, REG_TYPE_BHSDQ
, &rtype
, NULL
);
5552 if (val
== PARSE_FAIL
)
5554 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ
)));
5557 gas_assert (rtype
>= REG_TYPE_FP_B
&& rtype
<= REG_TYPE_FP_Q
);
5559 info
->reg
.regno
= val
;
5560 info
->qualifier
= AARCH64_OPND_QLF_S_B
+ (rtype
- REG_TYPE_FP_B
);
5563 case AARCH64_OPND_SVE_Pd
:
5564 case AARCH64_OPND_SVE_Pg3
:
5565 case AARCH64_OPND_SVE_Pg4_5
:
5566 case AARCH64_OPND_SVE_Pg4_10
:
5567 case AARCH64_OPND_SVE_Pg4_16
:
5568 case AARCH64_OPND_SVE_Pm
:
5569 case AARCH64_OPND_SVE_Pn
:
5570 case AARCH64_OPND_SVE_Pt
:
5571 reg_type
= REG_TYPE_PN
;
5574 case AARCH64_OPND_SVE_Za_5
:
5575 case AARCH64_OPND_SVE_Za_16
:
5576 case AARCH64_OPND_SVE_Zd
:
5577 case AARCH64_OPND_SVE_Zm_5
:
5578 case AARCH64_OPND_SVE_Zm_16
:
5579 case AARCH64_OPND_SVE_Zn
:
5580 case AARCH64_OPND_SVE_Zt
:
5581 reg_type
= REG_TYPE_ZN
;
5584 case AARCH64_OPND_Va
:
5585 case AARCH64_OPND_Vd
:
5586 case AARCH64_OPND_Vn
:
5587 case AARCH64_OPND_Vm
:
5588 reg_type
= REG_TYPE_VN
;
5590 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5591 if (val
== PARSE_FAIL
)
5593 first_error (_(get_reg_expected_msg (reg_type
)));
5596 if (vectype
.defined
& NTA_HASINDEX
)
5599 info
->reg
.regno
= val
;
5600 if ((reg_type
== REG_TYPE_PN
|| reg_type
== REG_TYPE_ZN
)
5601 && vectype
.type
== NT_invtype
)
5602 /* Unqualified Pn and Zn registers are allowed in certain
5603 contexts. Rely on F_STRICT qualifier checking to catch
5605 info
->qualifier
= AARCH64_OPND_QLF_NIL
;
5608 info
->qualifier
= vectype_to_qualifier (&vectype
);
5609 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5614 case AARCH64_OPND_VdD1
:
5615 case AARCH64_OPND_VnD1
:
5616 val
= aarch64_reg_parse (&str
, REG_TYPE_VN
, NULL
, &vectype
);
5617 if (val
== PARSE_FAIL
)
5619 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN
)));
5622 if (vectype
.type
!= NT_d
|| vectype
.index
!= 1)
5624 set_fatal_syntax_error
5625 (_("the top half of a 128-bit FP/SIMD register is expected"));
5628 info
->reg
.regno
= val
;
5629 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
5630 here; it is correct for the purpose of encoding/decoding since
5631 only the register number is explicitly encoded in the related
5632 instructions, although this appears a bit hacky. */
5633 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
5636 case AARCH64_OPND_SVE_Zm3_INDEX
:
5637 case AARCH64_OPND_SVE_Zm3_22_INDEX
:
5638 case AARCH64_OPND_SVE_Zm4_INDEX
:
5639 case AARCH64_OPND_SVE_Zn_INDEX
:
5640 reg_type
= REG_TYPE_ZN
;
5641 goto vector_reg_index
;
5643 case AARCH64_OPND_Ed
:
5644 case AARCH64_OPND_En
:
5645 case AARCH64_OPND_Em
:
5646 case AARCH64_OPND_Em16
:
5647 case AARCH64_OPND_SM3_IMM2
:
5648 reg_type
= REG_TYPE_VN
;
5650 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5651 if (val
== PARSE_FAIL
)
5653 first_error (_(get_reg_expected_msg (reg_type
)));
5656 if (vectype
.type
== NT_invtype
|| !(vectype
.defined
& NTA_HASINDEX
))
5659 info
->reglane
.regno
= val
;
5660 info
->reglane
.index
= vectype
.index
;
5661 info
->qualifier
= vectype_to_qualifier (&vectype
);
5662 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5666 case AARCH64_OPND_SVE_ZnxN
:
5667 case AARCH64_OPND_SVE_ZtxN
:
5668 reg_type
= REG_TYPE_ZN
;
5669 goto vector_reg_list
;
5671 case AARCH64_OPND_LVn
:
5672 case AARCH64_OPND_LVt
:
5673 case AARCH64_OPND_LVt_AL
:
5674 case AARCH64_OPND_LEt
:
5675 reg_type
= REG_TYPE_VN
;
5677 if (reg_type
== REG_TYPE_ZN
5678 && get_opcode_dependent_value (opcode
) == 1
5681 val
= aarch64_reg_parse (&str
, reg_type
, NULL
, &vectype
);
5682 if (val
== PARSE_FAIL
)
5684 first_error (_(get_reg_expected_msg (reg_type
)));
5687 info
->reglist
.first_regno
= val
;
5688 info
->reglist
.num_regs
= 1;
5692 val
= parse_vector_reg_list (&str
, reg_type
, &vectype
);
5693 if (val
== PARSE_FAIL
)
5695 if (! reg_list_valid_p (val
, /* accept_alternate */ 0))
5697 set_fatal_syntax_error (_("invalid register list"));
5700 info
->reglist
.first_regno
= (val
>> 2) & 0x1f;
5701 info
->reglist
.num_regs
= (val
& 0x3) + 1;
5703 if (operands
[i
] == AARCH64_OPND_LEt
)
5705 if (!(vectype
.defined
& NTA_HASINDEX
))
5707 info
->reglist
.has_index
= 1;
5708 info
->reglist
.index
= vectype
.index
;
5712 if (vectype
.defined
& NTA_HASINDEX
)
5714 if (!(vectype
.defined
& NTA_HASTYPE
))
5716 if (reg_type
== REG_TYPE_ZN
)
5717 set_fatal_syntax_error (_("missing type suffix"));
5721 info
->qualifier
= vectype_to_qualifier (&vectype
);
5722 if (info
->qualifier
== AARCH64_OPND_QLF_NIL
)
5726 case AARCH64_OPND_CRn
:
5727 case AARCH64_OPND_CRm
:
5729 char prefix
= *(str
++);
5730 if (prefix
!= 'c' && prefix
!= 'C')
5733 po_imm_nc_or_fail ();
5736 set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
5739 info
->qualifier
= AARCH64_OPND_QLF_CR
;
5740 info
->imm
.value
= val
;
5744 case AARCH64_OPND_SHLL_IMM
:
5745 case AARCH64_OPND_IMM_VLSR
:
5746 po_imm_or_fail (1, 64);
5747 info
->imm
.value
= val
;
5750 case AARCH64_OPND_CCMP_IMM
:
5751 case AARCH64_OPND_SIMM5
:
5752 case AARCH64_OPND_FBITS
:
5753 case AARCH64_OPND_UIMM4
:
5754 case AARCH64_OPND_UIMM4_ADDG
:
5755 case AARCH64_OPND_UIMM10
:
5756 case AARCH64_OPND_UIMM3_OP1
:
5757 case AARCH64_OPND_UIMM3_OP2
:
5758 case AARCH64_OPND_IMM_VLSL
:
5759 case AARCH64_OPND_IMM
:
5760 case AARCH64_OPND_IMM_2
:
5761 case AARCH64_OPND_WIDTH
:
5762 case AARCH64_OPND_SVE_INV_LIMM
:
5763 case AARCH64_OPND_SVE_LIMM
:
5764 case AARCH64_OPND_SVE_LIMM_MOV
:
5765 case AARCH64_OPND_SVE_SHLIMM_PRED
:
5766 case AARCH64_OPND_SVE_SHLIMM_UNPRED
:
5767 case AARCH64_OPND_SVE_SHRIMM_PRED
:
5768 case AARCH64_OPND_SVE_SHRIMM_UNPRED
:
5769 case AARCH64_OPND_SVE_SIMM5
:
5770 case AARCH64_OPND_SVE_SIMM5B
:
5771 case AARCH64_OPND_SVE_SIMM6
:
5772 case AARCH64_OPND_SVE_SIMM8
:
5773 case AARCH64_OPND_SVE_UIMM3
:
5774 case AARCH64_OPND_SVE_UIMM7
:
5775 case AARCH64_OPND_SVE_UIMM8
:
5776 case AARCH64_OPND_SVE_UIMM8_53
:
5777 case AARCH64_OPND_IMM_ROT1
:
5778 case AARCH64_OPND_IMM_ROT2
:
5779 case AARCH64_OPND_IMM_ROT3
:
5780 case AARCH64_OPND_SVE_IMM_ROT1
:
5781 case AARCH64_OPND_SVE_IMM_ROT2
:
5782 po_imm_nc_or_fail ();
5783 info
->imm
.value
= val
;
5786 case AARCH64_OPND_SVE_AIMM
:
5787 case AARCH64_OPND_SVE_ASIMM
:
5788 po_imm_nc_or_fail ();
5789 info
->imm
.value
= val
;
5790 skip_whitespace (str
);
5791 if (skip_past_comma (&str
))
5792 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
5794 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
5797 case AARCH64_OPND_SVE_PATTERN
:
5798 po_enum_or_fail (aarch64_sve_pattern_array
);
5799 info
->imm
.value
= val
;
5802 case AARCH64_OPND_SVE_PATTERN_SCALED
:
5803 po_enum_or_fail (aarch64_sve_pattern_array
);
5804 info
->imm
.value
= val
;
5805 if (skip_past_comma (&str
)
5806 && !parse_shift (&str
, info
, SHIFTED_MUL
))
5808 if (!info
->shifter
.operator_present
)
5810 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5811 info
->shifter
.kind
= AARCH64_MOD_MUL
;
5812 info
->shifter
.amount
= 1;
5816 case AARCH64_OPND_SVE_PRFOP
:
5817 po_enum_or_fail (aarch64_sve_prfop_array
);
5818 info
->imm
.value
= val
;
5821 case AARCH64_OPND_UIMM7
:
5822 po_imm_or_fail (0, 127);
5823 info
->imm
.value
= val
;
5826 case AARCH64_OPND_IDX
:
5827 case AARCH64_OPND_MASK
:
5828 case AARCH64_OPND_BIT_NUM
:
5829 case AARCH64_OPND_IMMR
:
5830 case AARCH64_OPND_IMMS
:
5831 po_imm_or_fail (0, 63);
5832 info
->imm
.value
= val
;
5835 case AARCH64_OPND_IMM0
:
5836 po_imm_nc_or_fail ();
5839 set_fatal_syntax_error (_("immediate zero expected"));
5842 info
->imm
.value
= 0;
5845 case AARCH64_OPND_FPIMM0
:
5848 bfd_boolean res1
= FALSE
, res2
= FALSE
;
5849 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
5850 it is probably not worth the effort to support it. */
5851 if (!(res1
= parse_aarch64_imm_float (&str
, &qfloat
, FALSE
,
5854 || !(res2
= parse_constant_immediate (&str
, &val
,
5857 if ((res1
&& qfloat
== 0) || (res2
&& val
== 0))
5859 info
->imm
.value
= 0;
5860 info
->imm
.is_fp
= 1;
5863 set_fatal_syntax_error (_("immediate zero expected"));
5867 case AARCH64_OPND_IMM_MOV
:
5870 if (reg_name_p (str
, REG_TYPE_R_Z_SP
) ||
5871 reg_name_p (str
, REG_TYPE_VN
))
5874 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5876 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
5877 later. fix_mov_imm_insn will try to determine a machine
5878 instruction (MOVZ, MOVN or ORR) for it and will issue an error
5879 message if the immediate cannot be moved by a single
5881 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
5882 inst
.base
.operands
[i
].skip
= 1;
5886 case AARCH64_OPND_SIMD_IMM
:
5887 case AARCH64_OPND_SIMD_IMM_SFT
:
5888 if (! parse_big_immediate (&str
, &val
, imm_reg_type
))
5890 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5892 /* need_libopcodes_p */ 1,
5895 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
5896 shift, we don't check it here; we leave the checking to
5897 the libopcodes (operand_general_constraint_met_p). By
5898 doing this, we achieve better diagnostics. */
5899 if (skip_past_comma (&str
)
5900 && ! parse_shift (&str
, info
, SHIFTED_LSL_MSL
))
5902 if (!info
->shifter
.operator_present
5903 && info
->type
== AARCH64_OPND_SIMD_IMM_SFT
)
5905 /* Default to LSL if not present. Libopcodes prefers shifter
5906 kind to be explicit. */
5907 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5908 info
->shifter
.kind
= AARCH64_MOD_LSL
;
5912 case AARCH64_OPND_FPIMM
:
5913 case AARCH64_OPND_SIMD_FPIMM
:
5914 case AARCH64_OPND_SVE_FPIMM8
:
5919 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5920 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
)
5921 || !aarch64_imm_float_p (qfloat
))
5924 set_fatal_syntax_error (_("invalid floating-point"
5928 inst
.base
.operands
[i
].imm
.value
= encode_imm_float_bits (qfloat
);
5929 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5933 case AARCH64_OPND_SVE_I1_HALF_ONE
:
5934 case AARCH64_OPND_SVE_I1_HALF_TWO
:
5935 case AARCH64_OPND_SVE_I1_ZERO_ONE
:
5940 dp_p
= double_precision_operand_p (&inst
.base
.operands
[0]);
5941 if (!parse_aarch64_imm_float (&str
, &qfloat
, dp_p
, imm_reg_type
))
5944 set_fatal_syntax_error (_("invalid floating-point"
5948 inst
.base
.operands
[i
].imm
.value
= qfloat
;
5949 inst
.base
.operands
[i
].imm
.is_fp
= 1;
5953 case AARCH64_OPND_LIMM
:
5954 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5955 SHIFTED_LOGIC_IMM
));
5956 if (info
->shifter
.operator_present
)
5958 set_fatal_syntax_error
5959 (_("shift not allowed for bitmask immediate"));
5962 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
5964 /* need_libopcodes_p */ 1,
5968 case AARCH64_OPND_AIMM
:
5969 if (opcode
->op
== OP_ADD
)
5970 /* ADD may have relocation types. */
5971 po_misc_or_fail (parse_shifter_operand_reloc (&str
, info
,
5972 SHIFTED_ARITH_IMM
));
5974 po_misc_or_fail (parse_shifter_operand (&str
, info
,
5975 SHIFTED_ARITH_IMM
));
5976 switch (inst
.reloc
.type
)
5978 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
5979 info
->shifter
.amount
= 12;
5981 case BFD_RELOC_UNUSED
:
5982 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
5983 if (info
->shifter
.kind
!= AARCH64_MOD_NONE
)
5984 inst
.reloc
.flags
= FIXUP_F_HAS_EXPLICIT_SHIFT
;
5985 inst
.reloc
.pc_rel
= 0;
5990 info
->imm
.value
= 0;
5991 if (!info
->shifter
.operator_present
)
5993 /* Default to LSL if not present. Libopcodes prefers shifter
5994 kind to be explicit. */
5995 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
5996 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6000 case AARCH64_OPND_HALF
:
6002 /* #<imm16> or relocation. */
6003 int internal_fixup_p
;
6004 po_misc_or_fail (parse_half (&str
, &internal_fixup_p
));
6005 if (internal_fixup_p
)
6006 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 0);
6007 skip_whitespace (str
);
6008 if (skip_past_comma (&str
))
6010 /* {, LSL #<shift>} */
6011 if (! aarch64_gas_internal_fixup_p ())
6013 set_fatal_syntax_error (_("can't mix relocation modifier "
6014 "with explicit shift"));
6017 po_misc_or_fail (parse_shift (&str
, info
, SHIFTED_LSL
));
6020 inst
.base
.operands
[i
].shifter
.amount
= 0;
6021 inst
.base
.operands
[i
].shifter
.kind
= AARCH64_MOD_LSL
;
6022 inst
.base
.operands
[i
].imm
.value
= 0;
6023 if (! process_movw_reloc_info ())
6028 case AARCH64_OPND_EXCEPTION
:
6029 po_misc_or_fail (parse_immediate_expression (&str
, &inst
.reloc
.exp
,
6031 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6033 /* need_libopcodes_p */ 0,
6037 case AARCH64_OPND_NZCV
:
6039 const asm_nzcv
*nzcv
= hash_find_n (aarch64_nzcv_hsh
, str
, 4);
6043 info
->imm
.value
= nzcv
->value
;
6046 po_imm_or_fail (0, 15);
6047 info
->imm
.value
= val
;
6051 case AARCH64_OPND_COND
:
6052 case AARCH64_OPND_COND1
:
6057 while (ISALPHA (*str
));
6058 info
->cond
= hash_find_n (aarch64_cond_hsh
, start
, str
- start
);
6059 if (info
->cond
== NULL
)
6061 set_syntax_error (_("invalid condition"));
6064 else if (operands
[i
] == AARCH64_OPND_COND1
6065 && (info
->cond
->value
& 0xe) == 0xe)
6067 /* Do not allow AL or NV. */
6068 set_default_error ();
6074 case AARCH64_OPND_ADDR_ADRP
:
6075 po_misc_or_fail (parse_adrp (&str
));
6076 /* Clear the value as operand needs to be relocated. */
6077 info
->imm
.value
= 0;
6080 case AARCH64_OPND_ADDR_PCREL14
:
6081 case AARCH64_OPND_ADDR_PCREL19
:
6082 case AARCH64_OPND_ADDR_PCREL21
:
6083 case AARCH64_OPND_ADDR_PCREL26
:
6084 po_misc_or_fail (parse_address (&str
, info
));
6085 if (!info
->addr
.pcrel
)
6087 set_syntax_error (_("invalid pc-relative address"));
6090 if (inst
.gen_lit_pool
6091 && (opcode
->iclass
!= loadlit
|| opcode
->op
== OP_PRFM_LIT
))
6093 /* Only permit "=value" in the literal load instructions.
6094 The literal will be generated by programmer_friendly_fixup. */
6095 set_syntax_error (_("invalid use of \"=immediate\""));
6098 if (inst
.reloc
.exp
.X_op
== O_symbol
&& find_reloc_table_entry (&str
))
6100 set_syntax_error (_("unrecognized relocation suffix"));
6103 if (inst
.reloc
.exp
.X_op
== O_constant
&& !inst
.gen_lit_pool
)
6105 info
->imm
.value
= inst
.reloc
.exp
.X_add_number
;
6106 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6110 info
->imm
.value
= 0;
6111 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6112 switch (opcode
->iclass
)
6116 /* e.g. CBZ or B.COND */
6117 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6118 inst
.reloc
.type
= BFD_RELOC_AARCH64_BRANCH19
;
6122 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL14
);
6123 inst
.reloc
.type
= BFD_RELOC_AARCH64_TSTBR14
;
6127 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL26
);
6129 (opcode
->op
== OP_BL
) ? BFD_RELOC_AARCH64_CALL26
6130 : BFD_RELOC_AARCH64_JUMP26
;
6133 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL19
);
6134 inst
.reloc
.type
= BFD_RELOC_AARCH64_LD_LO19_PCREL
;
6137 gas_assert (operands
[i
] == AARCH64_OPND_ADDR_PCREL21
);
6138 inst
.reloc
.type
= BFD_RELOC_AARCH64_ADR_LO21_PCREL
;
6144 inst
.reloc
.pc_rel
= 1;
6148 case AARCH64_OPND_ADDR_SIMPLE
:
6149 case AARCH64_OPND_SIMD_ADDR_SIMPLE
:
6151 /* [<Xn|SP>{, #<simm>}] */
6153 /* First use the normal address-parsing routines, to get
6154 the usual syntax errors. */
6155 po_misc_or_fail (parse_address (&str
, info
));
6156 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6157 || !info
->addr
.preind
|| info
->addr
.postind
6158 || info
->addr
.writeback
)
6160 set_syntax_error (_("invalid addressing mode"));
6164 /* Then retry, matching the specific syntax of these addresses. */
6166 po_char_or_fail ('[');
6167 po_reg_or_fail (REG_TYPE_R64_SP
);
6168 /* Accept optional ", #0". */
6169 if (operands
[i
] == AARCH64_OPND_ADDR_SIMPLE
6170 && skip_past_char (&str
, ','))
6172 skip_past_char (&str
, '#');
6173 if (! skip_past_char (&str
, '0'))
6175 set_fatal_syntax_error
6176 (_("the optional immediate offset can only be 0"));
6180 po_char_or_fail (']');
6184 case AARCH64_OPND_ADDR_REGOFF
:
6185 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
6186 po_misc_or_fail (parse_address (&str
, info
));
6188 if (info
->addr
.pcrel
|| !info
->addr
.offset
.is_reg
6189 || !info
->addr
.preind
|| info
->addr
.postind
6190 || info
->addr
.writeback
)
6192 set_syntax_error (_("invalid addressing mode"));
6195 if (!info
->shifter
.operator_present
)
6197 /* Default to LSL if not present. Libopcodes prefers shifter
6198 kind to be explicit. */
6199 gas_assert (info
->shifter
.kind
== AARCH64_MOD_NONE
);
6200 info
->shifter
.kind
= AARCH64_MOD_LSL
;
6202 /* Qualifier to be deduced by libopcodes. */
6205 case AARCH64_OPND_ADDR_SIMM7
:
6206 po_misc_or_fail (parse_address (&str
, info
));
6207 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6208 || (!info
->addr
.preind
&& !info
->addr
.postind
))
6210 set_syntax_error (_("invalid addressing mode"));
6213 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6215 set_syntax_error (_("relocation not allowed"));
6218 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6220 /* need_libopcodes_p */ 1,
6224 case AARCH64_OPND_ADDR_SIMM9
:
6225 case AARCH64_OPND_ADDR_SIMM9_2
:
6226 case AARCH64_OPND_ADDR_SIMM11
:
6227 case AARCH64_OPND_ADDR_SIMM13
:
6228 po_misc_or_fail (parse_address (&str
, info
));
6229 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6230 || (!info
->addr
.preind
&& !info
->addr
.postind
)
6231 || (operands
[i
] == AARCH64_OPND_ADDR_SIMM9_2
6232 && info
->addr
.writeback
))
6234 set_syntax_error (_("invalid addressing mode"));
6237 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6239 set_syntax_error (_("relocation not allowed"));
6242 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6244 /* need_libopcodes_p */ 1,
6248 case AARCH64_OPND_ADDR_SIMM10
:
6249 case AARCH64_OPND_ADDR_OFFSET
:
6250 po_misc_or_fail (parse_address (&str
, info
));
6251 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6252 || !info
->addr
.preind
|| info
->addr
.postind
)
6254 set_syntax_error (_("invalid addressing mode"));
6257 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
6259 set_syntax_error (_("relocation not allowed"));
6262 assign_imm_if_const_or_fixup_later (&inst
.reloc
, info
,
6264 /* need_libopcodes_p */ 1,
6268 case AARCH64_OPND_ADDR_UIMM12
:
6269 po_misc_or_fail (parse_address (&str
, info
));
6270 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6271 || !info
->addr
.preind
|| info
->addr
.writeback
)
6273 set_syntax_error (_("invalid addressing mode"));
6276 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6277 aarch64_set_gas_internal_fixup (&inst
.reloc
, info
, 1);
6278 else if (inst
.reloc
.type
== BFD_RELOC_AARCH64_LDST_LO12
6280 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
)
6282 == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
)
6284 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
)
6286 == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
))
6287 inst
.reloc
.type
= ldst_lo12_determine_real_reloc_type ();
6288 /* Leave qualifier to be determined by libopcodes. */
6291 case AARCH64_OPND_SIMD_ADDR_POST
:
6292 /* [<Xn|SP>], <Xm|#<amount>> */
6293 po_misc_or_fail (parse_address (&str
, info
));
6294 if (!info
->addr
.postind
|| !info
->addr
.writeback
)
6296 set_syntax_error (_("invalid addressing mode"));
6299 if (!info
->addr
.offset
.is_reg
)
6301 if (inst
.reloc
.exp
.X_op
== O_constant
)
6302 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6305 set_fatal_syntax_error
6306 (_("writeback value must be an immediate constant"));
6313 case AARCH64_OPND_SVE_ADDR_RI_S4x16
:
6314 case AARCH64_OPND_SVE_ADDR_RI_S4xVL
:
6315 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
:
6316 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
:
6317 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
:
6318 case AARCH64_OPND_SVE_ADDR_RI_S6xVL
:
6319 case AARCH64_OPND_SVE_ADDR_RI_S9xVL
:
6320 case AARCH64_OPND_SVE_ADDR_RI_U6
:
6321 case AARCH64_OPND_SVE_ADDR_RI_U6x2
:
6322 case AARCH64_OPND_SVE_ADDR_RI_U6x4
:
6323 case AARCH64_OPND_SVE_ADDR_RI_U6x8
:
6324 /* [X<n>{, #imm, MUL VL}]
6326 but recognizing SVE registers. */
6327 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6328 &offset_qualifier
));
6329 if (base_qualifier
!= AARCH64_OPND_QLF_X
)
6331 set_syntax_error (_("invalid addressing mode"));
6335 if (info
->addr
.pcrel
|| info
->addr
.offset
.is_reg
6336 || !info
->addr
.preind
|| info
->addr
.writeback
)
6338 set_syntax_error (_("invalid addressing mode"));
6341 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
6342 || inst
.reloc
.exp
.X_op
!= O_constant
)
6344 /* Make sure this has priority over
6345 "invalid addressing mode". */
6346 set_fatal_syntax_error (_("constant offset required"));
6349 info
->addr
.offset
.imm
= inst
.reloc
.exp
.X_add_number
;
6352 case AARCH64_OPND_SVE_ADDR_R
:
6353 /* [<Xn|SP>{, <R><m>}]
6354 but recognizing SVE registers. */
6355 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6356 &offset_qualifier
));
6357 if (offset_qualifier
== AARCH64_OPND_QLF_NIL
)
6359 offset_qualifier
= AARCH64_OPND_QLF_X
;
6360 info
->addr
.offset
.is_reg
= 1;
6361 info
->addr
.offset
.regno
= 31;
6363 else if (base_qualifier
!= AARCH64_OPND_QLF_X
6364 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6366 set_syntax_error (_("invalid addressing mode"));
6371 case AARCH64_OPND_SVE_ADDR_RR
:
6372 case AARCH64_OPND_SVE_ADDR_RR_LSL1
:
6373 case AARCH64_OPND_SVE_ADDR_RR_LSL2
:
6374 case AARCH64_OPND_SVE_ADDR_RR_LSL3
:
6375 case AARCH64_OPND_SVE_ADDR_RX
:
6376 case AARCH64_OPND_SVE_ADDR_RX_LSL1
:
6377 case AARCH64_OPND_SVE_ADDR_RX_LSL2
:
6378 case AARCH64_OPND_SVE_ADDR_RX_LSL3
:
6379 /* [<Xn|SP>, <R><m>{, lsl #<amount>}]
6380 but recognizing SVE registers. */
6381 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6382 &offset_qualifier
));
6383 if (base_qualifier
!= AARCH64_OPND_QLF_X
6384 || offset_qualifier
!= AARCH64_OPND_QLF_X
)
6386 set_syntax_error (_("invalid addressing mode"));
6391 case AARCH64_OPND_SVE_ADDR_RZ
:
6392 case AARCH64_OPND_SVE_ADDR_RZ_LSL1
:
6393 case AARCH64_OPND_SVE_ADDR_RZ_LSL2
:
6394 case AARCH64_OPND_SVE_ADDR_RZ_LSL3
:
6395 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14
:
6396 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22
:
6397 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
:
6398 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
:
6399 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
:
6400 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
:
6401 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
:
6402 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
:
6403 /* [<Xn|SP>, Z<m>.D{, LSL #<amount>}]
6404 [<Xn|SP>, Z<m>.<T>, <extend> {#<amount>}] */
6405 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6406 &offset_qualifier
));
6407 if (base_qualifier
!= AARCH64_OPND_QLF_X
6408 || (offset_qualifier
!= AARCH64_OPND_QLF_S_S
6409 && offset_qualifier
!= AARCH64_OPND_QLF_S_D
))
6411 set_syntax_error (_("invalid addressing mode"));
6414 info
->qualifier
= offset_qualifier
;
6417 case AARCH64_OPND_SVE_ADDR_ZI_U5
:
6418 case AARCH64_OPND_SVE_ADDR_ZI_U5x2
:
6419 case AARCH64_OPND_SVE_ADDR_ZI_U5x4
:
6420 case AARCH64_OPND_SVE_ADDR_ZI_U5x8
:
6421 /* [Z<n>.<T>{, #imm}] */
6422 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6423 &offset_qualifier
));
6424 if (base_qualifier
!= AARCH64_OPND_QLF_S_S
6425 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6427 set_syntax_error (_("invalid addressing mode"));
6430 info
->qualifier
= base_qualifier
;
6433 case AARCH64_OPND_SVE_ADDR_ZZ_LSL
:
6434 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW
:
6435 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW
:
6436 /* [Z<n>.<T>, Z<m>.<T>{, LSL #<amount>}]
6437 [Z<n>.D, Z<m>.D, <extend> {#<amount>}]
6441 [Z<n>.S, Z<m>.S, <extend> {#<amount>}]
6443 here since we get better error messages by leaving it to
6444 the qualifier checking routines. */
6445 po_misc_or_fail (parse_sve_address (&str
, info
, &base_qualifier
,
6446 &offset_qualifier
));
6447 if ((base_qualifier
!= AARCH64_OPND_QLF_S_S
6448 && base_qualifier
!= AARCH64_OPND_QLF_S_D
)
6449 || offset_qualifier
!= base_qualifier
)
6451 set_syntax_error (_("invalid addressing mode"));
6454 info
->qualifier
= base_qualifier
;
6457 case AARCH64_OPND_SYSREG
:
6459 uint32_t sysreg_flags
;
6460 if ((val
= parse_sys_reg (&str
, aarch64_sys_regs_hsh
, 1, 0,
6461 &sysreg_flags
)) == PARSE_FAIL
)
6463 set_syntax_error (_("unknown or missing system register name"));
6466 inst
.base
.operands
[i
].sysreg
.value
= val
;
6467 inst
.base
.operands
[i
].sysreg
.flags
= sysreg_flags
;
6471 case AARCH64_OPND_PSTATEFIELD
:
6472 if ((val
= parse_sys_reg (&str
, aarch64_pstatefield_hsh
, 0, 1, NULL
))
6475 set_syntax_error (_("unknown or missing PSTATE field name"));
6478 inst
.base
.operands
[i
].pstatefield
= val
;
6481 case AARCH64_OPND_SYSREG_IC
:
6482 inst
.base
.operands
[i
].sysins_op
=
6483 parse_sys_ins_reg (&str
, aarch64_sys_regs_ic_hsh
);
6486 case AARCH64_OPND_SYSREG_DC
:
6487 inst
.base
.operands
[i
].sysins_op
=
6488 parse_sys_ins_reg (&str
, aarch64_sys_regs_dc_hsh
);
6491 case AARCH64_OPND_SYSREG_AT
:
6492 inst
.base
.operands
[i
].sysins_op
=
6493 parse_sys_ins_reg (&str
, aarch64_sys_regs_at_hsh
);
6496 case AARCH64_OPND_SYSREG_SR
:
6497 inst
.base
.operands
[i
].sysins_op
=
6498 parse_sys_ins_reg (&str
, aarch64_sys_regs_sr_hsh
);
6501 case AARCH64_OPND_SYSREG_TLBI
:
6502 inst
.base
.operands
[i
].sysins_op
=
6503 parse_sys_ins_reg (&str
, aarch64_sys_regs_tlbi_hsh
);
6505 if (inst
.base
.operands
[i
].sysins_op
== NULL
)
6507 set_fatal_syntax_error ( _("unknown or missing operation name"));
6512 case AARCH64_OPND_BARRIER
:
6513 case AARCH64_OPND_BARRIER_ISB
:
6514 val
= parse_barrier (&str
);
6515 if (val
!= PARSE_FAIL
6516 && operands
[i
] == AARCH64_OPND_BARRIER_ISB
&& val
!= 0xf)
6518 /* ISB only accepts options name 'sy'. */
6520 (_("the specified option is not accepted in ISB"));
6521 /* Turn off backtrack as this optional operand is present. */
6525 /* This is an extension to accept a 0..15 immediate. */
6526 if (val
== PARSE_FAIL
)
6527 po_imm_or_fail (0, 15);
6528 info
->barrier
= aarch64_barrier_options
+ val
;
6531 case AARCH64_OPND_PRFOP
:
6532 val
= parse_pldop (&str
);
6533 /* This is an extension to accept a 0..31 immediate. */
6534 if (val
== PARSE_FAIL
)
6535 po_imm_or_fail (0, 31);
6536 inst
.base
.operands
[i
].prfop
= aarch64_prfops
+ val
;
6539 case AARCH64_OPND_BARRIER_PSB
:
6540 val
= parse_barrier_psb (&str
, &(info
->hint_option
));
6541 if (val
== PARSE_FAIL
)
6545 case AARCH64_OPND_BTI_TARGET
:
6546 val
= parse_bti_operand (&str
, &(info
->hint_option
));
6547 if (val
== PARSE_FAIL
)
6552 as_fatal (_("unhandled operand code %d"), operands
[i
]);
6555 /* If we get here, this operand was successfully parsed. */
6556 inst
.base
.operands
[i
].present
= 1;
6560 /* The parse routine should already have set the error, but in case
6561 not, set a default one here. */
6563 set_default_error ();
6565 if (! backtrack_pos
)
6566 goto parse_operands_return
;
6569 /* We reach here because this operand is marked as optional, and
6570 either no operand was supplied or the operand was supplied but it
6571 was syntactically incorrect. In the latter case we report an
6572 error. In the former case we perform a few more checks before
6573 dropping through to the code to insert the default operand. */
6575 char *tmp
= backtrack_pos
;
6576 char endchar
= END_OF_INSN
;
6578 if (i
!= (aarch64_num_of_operands (opcode
) - 1))
6580 skip_past_char (&tmp
, ',');
6582 if (*tmp
!= endchar
)
6583 /* The user has supplied an operand in the wrong format. */
6584 goto parse_operands_return
;
6586 /* Make sure there is not a comma before the optional operand.
6587 For example the fifth operand of 'sys' is optional:
6589 sys #0,c0,c0,#0, <--- wrong
6590 sys #0,c0,c0,#0 <--- correct. */
6591 if (comma_skipped_p
&& i
&& endchar
== END_OF_INSN
)
6593 set_fatal_syntax_error
6594 (_("unexpected comma before the omitted optional operand"));
6595 goto parse_operands_return
;
6599 /* Reaching here means we are dealing with an optional operand that is
6600 omitted from the assembly line. */
6601 gas_assert (optional_operand_p (opcode
, i
));
6603 process_omitted_operand (operands
[i
], opcode
, i
, info
);
6605 /* Try again, skipping the optional operand at backtrack_pos. */
6606 str
= backtrack_pos
;
6609 /* Clear any error record after the omitted optional operand has been
6610 successfully handled. */
6614 /* Check if we have parsed all the operands. */
6615 if (*str
!= '\0' && ! error_p ())
6617 /* Set I to the index of the last present operand; this is
6618 for the purpose of diagnostics. */
6619 for (i
-= 1; i
>= 0 && !inst
.base
.operands
[i
].present
; --i
)
6621 set_fatal_syntax_error
6622 (_("unexpected characters following instruction"));
6625 parse_operands_return
:
6629 DEBUG_TRACE ("parsing FAIL: %s - %s",
6630 operand_mismatch_kind_names
[get_error_kind ()],
6631 get_error_message ());
6632 /* Record the operand error properly; this is useful when there
6633 are multiple instruction templates for a mnemonic name, so that
6634 later on, we can select the error that most closely describes
6636 record_operand_error (opcode
, i
, get_error_kind (),
6637 get_error_message ());
6642 DEBUG_TRACE ("parsing SUCCESS");
6647 /* It does some fix-up to provide some programmer friendly feature while
6648 keeping the libopcodes happy, i.e. libopcodes only accepts
6649 the preferred architectural syntax.
6650 Return FALSE if there is any failure; otherwise return TRUE. */
6653 programmer_friendly_fixup (aarch64_instruction
*instr
)
6655 aarch64_inst
*base
= &instr
->base
;
6656 const aarch64_opcode
*opcode
= base
->opcode
;
6657 enum aarch64_op op
= opcode
->op
;
6658 aarch64_opnd_info
*operands
= base
->operands
;
6660 DEBUG_TRACE ("enter");
6662 switch (opcode
->iclass
)
6665 /* TBNZ Xn|Wn, #uimm6, label
6666 Test and Branch Not Zero: conditionally jumps to label if bit number
6667 uimm6 in register Xn is not zero. The bit number implies the width of
6668 the register, which may be written and should be disassembled as Wn if
6669 uimm is less than 32. */
6670 if (operands
[0].qualifier
== AARCH64_OPND_QLF_W
)
6672 if (operands
[1].imm
.value
>= 32)
6674 record_operand_out_of_range_error (opcode
, 1, _("immediate value"),
6678 operands
[0].qualifier
= AARCH64_OPND_QLF_X
;
6682 /* LDR Wt, label | =value
6683 As a convenience assemblers will typically permit the notation
6684 "=value" in conjunction with the pc-relative literal load instructions
6685 to automatically place an immediate value or symbolic address in a
6686 nearby literal pool and generate a hidden label which references it.
6687 ISREG has been set to 0 in the case of =value. */
6688 if (instr
->gen_lit_pool
6689 && (op
== OP_LDR_LIT
|| op
== OP_LDRV_LIT
|| op
== OP_LDRSW_LIT
))
6691 int size
= aarch64_get_qualifier_esize (operands
[0].qualifier
);
6692 if (op
== OP_LDRSW_LIT
)
6694 if (instr
->reloc
.exp
.X_op
!= O_constant
6695 && instr
->reloc
.exp
.X_op
!= O_big
6696 && instr
->reloc
.exp
.X_op
!= O_symbol
)
6698 record_operand_error (opcode
, 1,
6699 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
6700 _("constant expression expected"));
6703 if (! add_to_lit_pool (&instr
->reloc
.exp
, size
))
6705 record_operand_error (opcode
, 1,
6706 AARCH64_OPDE_OTHER_ERROR
,
6707 _("literal pool insertion failed"));
6715 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
6716 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
6717 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
6718 A programmer-friendly assembler should accept a destination Xd in
6719 place of Wd, however that is not the preferred form for disassembly.
6721 if ((op
== OP_UXTB
|| op
== OP_UXTH
|| op
== OP_UXTW
)
6722 && operands
[1].qualifier
== AARCH64_OPND_QLF_W
6723 && operands
[0].qualifier
== AARCH64_OPND_QLF_X
)
6724 operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
6729 /* In the 64-bit form, the final register operand is written as Wm
6730 for all but the (possibly omitted) UXTX/LSL and SXTX
6732 As a programmer-friendly assembler, we accept e.g.
6733 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
6734 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
6735 int idx
= aarch64_operand_index (opcode
->operands
,
6736 AARCH64_OPND_Rm_EXT
);
6737 gas_assert (idx
== 1 || idx
== 2);
6738 if (operands
[0].qualifier
== AARCH64_OPND_QLF_X
6739 && operands
[idx
].qualifier
== AARCH64_OPND_QLF_X
6740 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_LSL
6741 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_UXTX
6742 && operands
[idx
].shifter
.kind
!= AARCH64_MOD_SXTX
)
6743 operands
[idx
].qualifier
= AARCH64_OPND_QLF_W
;
6751 DEBUG_TRACE ("exit with SUCCESS");
6755 /* Check for loads and stores that will cause unpredictable behavior. */
6758 warn_unpredictable_ldst (aarch64_instruction
*instr
, char *str
)
6760 aarch64_inst
*base
= &instr
->base
;
6761 const aarch64_opcode
*opcode
= base
->opcode
;
6762 const aarch64_opnd_info
*opnds
= base
->operands
;
6763 switch (opcode
->iclass
)
6770 /* Loading/storing the base register is unpredictable if writeback. */
6771 if ((aarch64_get_operand_class (opnds
[0].type
)
6772 == AARCH64_OPND_CLASS_INT_REG
)
6773 && opnds
[0].reg
.regno
== opnds
[1].addr
.base_regno
6774 && opnds
[1].addr
.base_regno
!= REG_SP
6775 /* Exempt STG/STZG/ST2G/STZ2G. */
6776 && !(opnds
[1].type
== AARCH64_OPND_ADDR_SIMM13
)
6777 && opnds
[1].addr
.writeback
)
6778 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6782 case ldstnapair_offs
:
6783 case ldstpair_indexed
:
6784 /* Loading/storing the base register is unpredictable if writeback. */
6785 if ((aarch64_get_operand_class (opnds
[0].type
)
6786 == AARCH64_OPND_CLASS_INT_REG
)
6787 && (opnds
[0].reg
.regno
== opnds
[2].addr
.base_regno
6788 || opnds
[1].reg
.regno
== opnds
[2].addr
.base_regno
)
6789 && opnds
[2].addr
.base_regno
!= REG_SP
6791 && !(opnds
[2].type
== AARCH64_OPND_ADDR_SIMM11
)
6792 && opnds
[2].addr
.writeback
)
6793 as_warn (_("unpredictable transfer with writeback -- `%s'"), str
);
6794 /* Load operations must load different registers. */
6795 if ((opcode
->opcode
& (1 << 22))
6796 && opnds
[0].reg
.regno
== opnds
[1].reg
.regno
)
6797 as_warn (_("unpredictable load of register pair -- `%s'"), str
);
6801 /* It is unpredictable if the destination and status registers are the
6803 if ((aarch64_get_operand_class (opnds
[0].type
)
6804 == AARCH64_OPND_CLASS_INT_REG
)
6805 && (aarch64_get_operand_class (opnds
[1].type
)
6806 == AARCH64_OPND_CLASS_INT_REG
)
6807 && (opnds
[0].reg
.regno
== opnds
[1].reg
.regno
6808 || opnds
[0].reg
.regno
== opnds
[2].reg
.regno
))
6809 as_warn (_("unpredictable: identical transfer and status registers"
6821 force_automatic_sequence_close (void)
6823 if (now_instr_sequence
.instr
)
6825 as_warn (_("previous `%s' sequence has not been closed"),
6826 now_instr_sequence
.instr
->opcode
->name
);
6827 init_insn_sequence (NULL
, &now_instr_sequence
);
6831 /* A wrapper function to interface with libopcodes on encoding and
6832 record the error message if there is any.
6834 Return TRUE on success; otherwise return FALSE. */
6837 do_encode (const aarch64_opcode
*opcode
, aarch64_inst
*instr
,
6840 aarch64_operand_error error_info
;
6841 memset (&error_info
, '\0', sizeof (error_info
));
6842 error_info
.kind
= AARCH64_OPDE_NIL
;
6843 if (aarch64_opcode_encode (opcode
, instr
, code
, NULL
, &error_info
, insn_sequence
)
6844 && !error_info
.non_fatal
)
6847 gas_assert (error_info
.kind
!= AARCH64_OPDE_NIL
);
6848 record_operand_error_info (opcode
, &error_info
);
6849 return error_info
.non_fatal
;
6852 #ifdef DEBUG_AARCH64
6854 dump_opcode_operands (const aarch64_opcode
*opcode
)
6857 while (opcode
->operands
[i
] != AARCH64_OPND_NIL
)
6859 aarch64_verbose ("\t\t opnd%d: %s", i
,
6860 aarch64_get_operand_name (opcode
->operands
[i
])[0] != '\0'
6861 ? aarch64_get_operand_name (opcode
->operands
[i
])
6862 : aarch64_get_operand_desc (opcode
->operands
[i
]));
6866 #endif /* DEBUG_AARCH64 */
6868 /* This is the guts of the machine-dependent assembler. STR points to a
6869 machine dependent instruction. This function is supposed to emit
6870 the frags/bytes it assembles to. */
6873 md_assemble (char *str
)
6876 templates
*template;
6877 aarch64_opcode
*opcode
;
6878 aarch64_inst
*inst_base
;
6879 unsigned saved_cond
;
6881 /* Align the previous label if needed. */
6882 if (last_label_seen
!= NULL
)
6884 symbol_set_frag (last_label_seen
, frag_now
);
6885 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6886 S_SET_SEGMENT (last_label_seen
, now_seg
);
6889 /* Update the current insn_sequence from the segment. */
6890 insn_sequence
= &seg_info (now_seg
)->tc_segment_info_data
.insn_sequence
;
6892 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6894 DEBUG_TRACE ("\n\n");
6895 DEBUG_TRACE ("==============================");
6896 DEBUG_TRACE ("Enter md_assemble with %s", str
);
6898 template = opcode_lookup (&p
);
6901 /* It wasn't an instruction, but it might be a register alias of
6902 the form alias .req reg directive. */
6903 if (!create_register_alias (str
, p
))
6904 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str
),
6909 skip_whitespace (p
);
6912 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
6913 get_mnemonic_name (str
), str
);
6917 init_operand_error_report ();
6919 /* Sections are assumed to start aligned. In executable section, there is no
6920 MAP_DATA symbol pending. So we only align the address during
6921 MAP_DATA --> MAP_INSN transition.
6922 For other sections, this is not guaranteed. */
6923 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
6924 if (!need_pass_2
&& subseg_text_p (now_seg
) && mapstate
== MAP_DATA
)
6925 frag_align_code (2, 0);
6927 saved_cond
= inst
.cond
;
6928 reset_aarch64_instruction (&inst
);
6929 inst
.cond
= saved_cond
;
6931 /* Iterate through all opcode entries with the same mnemonic name. */
6934 opcode
= template->opcode
;
6936 DEBUG_TRACE ("opcode %s found", opcode
->name
);
6937 #ifdef DEBUG_AARCH64
6939 dump_opcode_operands (opcode
);
6940 #endif /* DEBUG_AARCH64 */
6942 mapping_state (MAP_INSN
);
6944 inst_base
= &inst
.base
;
6945 inst_base
->opcode
= opcode
;
6947 /* Truly conditionally executed instructions, e.g. b.cond. */
6948 if (opcode
->flags
& F_COND
)
6950 gas_assert (inst
.cond
!= COND_ALWAYS
);
6951 inst_base
->cond
= get_cond_from_value (inst
.cond
);
6952 DEBUG_TRACE ("condition found %s", inst_base
->cond
->names
[0]);
6954 else if (inst
.cond
!= COND_ALWAYS
)
6956 /* It shouldn't arrive here, where the assembly looks like a
6957 conditional instruction but the found opcode is unconditional. */
6962 if (parse_operands (p
, opcode
)
6963 && programmer_friendly_fixup (&inst
)
6964 && do_encode (inst_base
->opcode
, &inst
.base
, &inst_base
->value
))
6966 /* Check that this instruction is supported for this CPU. */
6967 if (!opcode
->avariant
6968 || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant
, *opcode
->avariant
))
6970 as_bad (_("selected processor does not support `%s'"), str
);
6974 warn_unpredictable_ldst (&inst
, str
);
6976 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
6977 || !inst
.reloc
.need_libopcodes_p
)
6981 /* If there is relocation generated for the instruction,
6982 store the instruction information for the future fix-up. */
6983 struct aarch64_inst
*copy
;
6984 gas_assert (inst
.reloc
.type
!= BFD_RELOC_UNUSED
);
6985 copy
= XNEW (struct aarch64_inst
);
6986 memcpy (copy
, &inst
.base
, sizeof (struct aarch64_inst
));
6990 /* Issue non-fatal messages if any. */
6991 output_operand_error_report (str
, TRUE
);
6995 template = template->next
;
6996 if (template != NULL
)
6998 reset_aarch64_instruction (&inst
);
6999 inst
.cond
= saved_cond
;
7002 while (template != NULL
);
7004 /* Issue the error messages if any. */
7005 output_operand_error_report (str
, FALSE
);
7008 /* Various frobbings of labels and their addresses. */
7011 aarch64_start_line_hook (void)
7013 last_label_seen
= NULL
;
7017 aarch64_frob_label (symbolS
* sym
)
7019 last_label_seen
= sym
;
7021 dwarf2_emit_label (sym
);
7025 aarch64_frob_section (asection
*sec ATTRIBUTE_UNUSED
)
7027 /* Check to see if we have a block to close. */
7028 force_automatic_sequence_close ();
7032 aarch64_data_in_code (void)
7034 if (!strncmp (input_line_pointer
+ 1, "data:", 5))
7036 *input_line_pointer
= '/';
7037 input_line_pointer
+= 5;
7038 *input_line_pointer
= 0;
7046 aarch64_canonicalize_symbol_name (char *name
)
7050 if ((len
= strlen (name
)) > 5 && streq (name
+ len
- 5, "/data"))
7051 *(name
+ len
- 5) = 0;
7056 /* Table of all register names defined by default. The user can
7057 define additional names with .req. Note that all register names
7058 should appear in both upper and lowercase variants. Some registers
7059 also have mixed-case names. */
7061 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7062 #define REGDEF_ALIAS(s, n, t) { #s, n, REG_TYPE_##t, FALSE}
7063 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7064 #define REGSET16(p,t) \
7065 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7066 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7067 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7068 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7069 #define REGSET31(p,t) \
7071 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
7072 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
7073 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
7074 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
7075 #define REGSET(p,t) \
7076 REGSET31(p,t), REGNUM(p,31,t)
7078 /* These go into aarch64_reg_hsh hash-table. */
7079 static const reg_entry reg_names
[] = {
7080 /* Integer registers. */
7081 REGSET31 (x
, R_64
), REGSET31 (X
, R_64
),
7082 REGSET31 (w
, R_32
), REGSET31 (W
, R_32
),
7084 REGDEF_ALIAS (ip0
, 16, R_64
), REGDEF_ALIAS (IP0
, 16, R_64
),
7085 REGDEF_ALIAS (ip1
, 17, R_64
), REGDEF_ALIAS (IP1
, 17, R_64
),
7086 REGDEF_ALIAS (fp
, 29, R_64
), REGDEF_ALIAS (FP
, 29, R_64
),
7087 REGDEF_ALIAS (lr
, 30, R_64
), REGDEF_ALIAS (LR
, 30, R_64
),
7088 REGDEF (wsp
, 31, SP_32
), REGDEF (WSP
, 31, SP_32
),
7089 REGDEF (sp
, 31, SP_64
), REGDEF (SP
, 31, SP_64
),
7091 REGDEF (wzr
, 31, Z_32
), REGDEF (WZR
, 31, Z_32
),
7092 REGDEF (xzr
, 31, Z_64
), REGDEF (XZR
, 31, Z_64
),
7094 /* Floating-point single precision registers. */
7095 REGSET (s
, FP_S
), REGSET (S
, FP_S
),
7097 /* Floating-point double precision registers. */
7098 REGSET (d
, FP_D
), REGSET (D
, FP_D
),
7100 /* Floating-point half precision registers. */
7101 REGSET (h
, FP_H
), REGSET (H
, FP_H
),
7103 /* Floating-point byte precision registers. */
7104 REGSET (b
, FP_B
), REGSET (B
, FP_B
),
7106 /* Floating-point quad precision registers. */
7107 REGSET (q
, FP_Q
), REGSET (Q
, FP_Q
),
7109 /* FP/SIMD registers. */
7110 REGSET (v
, VN
), REGSET (V
, VN
),
7112 /* SVE vector registers. */
7113 REGSET (z
, ZN
), REGSET (Z
, ZN
),
7115 /* SVE predicate registers. */
7116 REGSET16 (p
, PN
), REGSET16 (P
, PN
)
7134 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
7135 static const asm_nzcv nzcv_names
[] = {
7136 {"nzcv", B (n
, z
, c
, v
)},
7137 {"nzcV", B (n
, z
, c
, V
)},
7138 {"nzCv", B (n
, z
, C
, v
)},
7139 {"nzCV", B (n
, z
, C
, V
)},
7140 {"nZcv", B (n
, Z
, c
, v
)},
7141 {"nZcV", B (n
, Z
, c
, V
)},
7142 {"nZCv", B (n
, Z
, C
, v
)},
7143 {"nZCV", B (n
, Z
, C
, V
)},
7144 {"Nzcv", B (N
, z
, c
, v
)},
7145 {"NzcV", B (N
, z
, c
, V
)},
7146 {"NzCv", B (N
, z
, C
, v
)},
7147 {"NzCV", B (N
, z
, C
, V
)},
7148 {"NZcv", B (N
, Z
, c
, v
)},
7149 {"NZcV", B (N
, Z
, c
, V
)},
7150 {"NZCv", B (N
, Z
, C
, v
)},
7151 {"NZCV", B (N
, Z
, C
, V
)}
7164 /* MD interface: bits in the object file. */
7166 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
7167 for use in the a.out file, and stores them in the array pointed to by buf.
7168 This knows about the endian-ness of the target machine and does
7169 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
7170 2 (short) and 4 (long) Floating numbers are put out as a series of
7171 LITTLENUMS (shorts, here at least). */
7174 md_number_to_chars (char *buf
, valueT val
, int n
)
7176 if (target_big_endian
)
7177 number_to_chars_bigendian (buf
, val
, n
);
7179 number_to_chars_littleendian (buf
, val
, n
);
7182 /* MD interface: Sections. */
7184 /* Estimate the size of a frag before relaxing. Assume everything fits in
7188 md_estimate_size_before_relax (fragS
* fragp
, segT segtype ATTRIBUTE_UNUSED
)
7194 /* Round up a section size to the appropriate boundary. */
7197 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7202 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
7203 of an rs_align_code fragment.
7205 Here we fill the frag with the appropriate info for padding the
7206 output stream. The resulting frag will consist of a fixed (fr_fix)
7207 and of a repeating (fr_var) part.
7209 The fixed content is always emitted before the repeating content and
7210 these two parts are used as follows in constructing the output:
7211 - the fixed part will be used to align to a valid instruction word
7212 boundary, in case that we start at a misaligned address; as no
7213 executable instruction can live at the misaligned location, we
7214 simply fill with zeros;
7215 - the variable part will be used to cover the remaining padding and
7216 we fill using the AArch64 NOP instruction.
7218 Note that the size of a RS_ALIGN_CODE fragment is always 7 to provide
7219 enough storage space for up to 3 bytes for padding the back to a valid
7220 instruction alignment and exactly 4 bytes to store the NOP pattern. */
7223 aarch64_handle_align (fragS
* fragP
)
7225 /* NOP = d503201f */
7226 /* AArch64 instructions are always little-endian. */
7227 static unsigned char const aarch64_noop
[4] = { 0x1f, 0x20, 0x03, 0xd5 };
7229 int bytes
, fix
, noop_size
;
7232 if (fragP
->fr_type
!= rs_align_code
)
7235 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
7236 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
7239 gas_assert (fragP
->tc_frag_data
.recorded
);
7242 noop_size
= sizeof (aarch64_noop
);
7244 fix
= bytes
& (noop_size
- 1);
7248 insert_data_mapping_symbol (MAP_INSN
, fragP
->fr_fix
, fragP
, fix
);
7252 fragP
->fr_fix
+= fix
;
7256 memcpy (p
, aarch64_noop
, noop_size
);
7257 fragP
->fr_var
= noop_size
;
7260 /* Perform target specific initialisation of a frag.
7261 Note - despite the name this initialisation is not done when the frag
7262 is created, but only when its type is assigned. A frag can be created
7263 and used a long time before its type is set, so beware of assuming that
7264 this initialisation is performed first. */
7268 aarch64_init_frag (fragS
* fragP ATTRIBUTE_UNUSED
,
7269 int max_chars ATTRIBUTE_UNUSED
)
7273 #else /* OBJ_ELF is defined. */
7275 aarch64_init_frag (fragS
* fragP
, int max_chars
)
7277 /* Record a mapping symbol for alignment frags. We will delete this
7278 later if the alignment ends up empty. */
7279 if (!fragP
->tc_frag_data
.recorded
)
7280 fragP
->tc_frag_data
.recorded
= 1;
7282 /* PR 21809: Do not set a mapping state for debug sections
7283 - it just confuses other tools. */
7284 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
7287 switch (fragP
->fr_type
)
7291 mapping_state_2 (MAP_DATA
, max_chars
);
7294 /* PR 20364: We can get alignment frags in code sections,
7295 so do not just assume that we should use the MAP_DATA state. */
7296 mapping_state_2 (subseg_text_p (now_seg
) ? MAP_INSN
: MAP_DATA
, max_chars
);
7299 mapping_state_2 (MAP_INSN
, max_chars
);
7306 /* Initialize the DWARF-2 unwind information for this procedure. */
7309 tc_aarch64_frame_initial_instructions (void)
7311 cfi_add_CFA_def_cfa (REG_SP
, 0);
7313 #endif /* OBJ_ELF */
7315 /* Convert REGNAME to a DWARF-2 register number. */
7318 tc_aarch64_regname_to_dw2regnum (char *regname
)
7320 const reg_entry
*reg
= parse_reg (®name
);
7326 case REG_TYPE_SP_32
:
7327 case REG_TYPE_SP_64
:
7337 return reg
->number
+ 64;
7345 /* Implement DWARF2_ADDR_SIZE. */
7348 aarch64_dwarf2_addr_size (void)
7350 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7354 return bfd_arch_bits_per_address (stdoutput
) / 8;
7357 /* MD interface: Symbol and relocation handling. */
7359 /* Return the address within the segment that a PC-relative fixup is
7360 relative to. For AArch64 PC-relative fixups applied to instructions
7361 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
7364 md_pcrel_from_section (fixS
* fixP
, segT seg
)
7366 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7368 /* If this is pc-relative and we are going to emit a relocation
7369 then we just want to put out any pipeline compensation that the linker
7370 will need. Otherwise we want to use the calculated base. */
7372 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
7373 || aarch64_force_relocation (fixP
)))
7376 /* AArch64 should be consistent for all pc-relative relocations. */
7377 return base
+ AARCH64_PCREL_OFFSET
;
7380 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
7381 Otherwise we have no need to default values of symbols. */
7384 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7387 if (name
[0] == '_' && name
[1] == 'G'
7388 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
7392 if (symbol_find (name
))
7393 as_bad (_("GOT already in the symbol table"));
7395 GOT_symbol
= symbol_new (name
, undefined_section
,
7396 (valueT
) 0, &zero_address_frag
);
7406 /* Return non-zero if the indicated VALUE has overflowed the maximum
7407 range expressible by a unsigned number with the indicated number of
7411 unsigned_overflow (valueT value
, unsigned bits
)
7414 if (bits
>= sizeof (valueT
) * 8)
7416 lim
= (valueT
) 1 << bits
;
7417 return (value
>= lim
);
7421 /* Return non-zero if the indicated VALUE has overflowed the maximum
7422 range expressible by an signed number with the indicated number of
7426 signed_overflow (offsetT value
, unsigned bits
)
7429 if (bits
>= sizeof (offsetT
) * 8)
7431 lim
= (offsetT
) 1 << (bits
- 1);
7432 return (value
< -lim
|| value
>= lim
);
7435 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
7436 unsigned immediate offset load/store instruction, try to encode it as
7437 an unscaled, 9-bit, signed immediate offset load/store instruction.
7438 Return TRUE if it is successful; otherwise return FALSE.
7440 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
7441 in response to the standard LDR/STR mnemonics when the immediate offset is
7442 unambiguous, i.e. when it is negative or unaligned. */
7445 try_to_encode_as_unscaled_ldst (aarch64_inst
*instr
)
7448 enum aarch64_op new_op
;
7449 const aarch64_opcode
*new_opcode
;
7451 gas_assert (instr
->opcode
->iclass
== ldst_pos
);
7453 switch (instr
->opcode
->op
)
7455 case OP_LDRB_POS
:new_op
= OP_LDURB
; break;
7456 case OP_STRB_POS
: new_op
= OP_STURB
; break;
7457 case OP_LDRSB_POS
: new_op
= OP_LDURSB
; break;
7458 case OP_LDRH_POS
: new_op
= OP_LDURH
; break;
7459 case OP_STRH_POS
: new_op
= OP_STURH
; break;
7460 case OP_LDRSH_POS
: new_op
= OP_LDURSH
; break;
7461 case OP_LDR_POS
: new_op
= OP_LDUR
; break;
7462 case OP_STR_POS
: new_op
= OP_STUR
; break;
7463 case OP_LDRF_POS
: new_op
= OP_LDURV
; break;
7464 case OP_STRF_POS
: new_op
= OP_STURV
; break;
7465 case OP_LDRSW_POS
: new_op
= OP_LDURSW
; break;
7466 case OP_PRFM_POS
: new_op
= OP_PRFUM
; break;
7467 default: new_op
= OP_NIL
; break;
7470 if (new_op
== OP_NIL
)
7473 new_opcode
= aarch64_get_opcode (new_op
);
7474 gas_assert (new_opcode
!= NULL
);
7476 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
7477 instr
->opcode
->op
, new_opcode
->op
);
7479 aarch64_replace_opcode (instr
, new_opcode
);
7481 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
7482 qualifier matching may fail because the out-of-date qualifier will
7483 prevent the operand being updated with a new and correct qualifier. */
7484 idx
= aarch64_operand_index (instr
->opcode
->operands
,
7485 AARCH64_OPND_ADDR_SIMM9
);
7486 gas_assert (idx
== 1);
7487 instr
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
7489 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
7491 if (!aarch64_opcode_encode (instr
->opcode
, instr
, &instr
->value
, NULL
, NULL
,
7498 /* Called by fix_insn to fix a MOV immediate alias instruction.
7500 Operand for a generic move immediate instruction, which is an alias
7501 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
7502 a 32-bit/64-bit immediate value into general register. An assembler error
7503 shall result if the immediate cannot be created by a single one of these
7504 instructions. If there is a choice, then to ensure reversability an
7505 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
7508 fix_mov_imm_insn (fixS
*fixP
, char *buf
, aarch64_inst
*instr
, offsetT value
)
7510 const aarch64_opcode
*opcode
;
7512 /* Need to check if the destination is SP/ZR. The check has to be done
7513 before any aarch64_replace_opcode. */
7514 int try_mov_wide_p
= !aarch64_stack_pointer_p (&instr
->operands
[0]);
7515 int try_mov_bitmask_p
= !aarch64_zero_register_p (&instr
->operands
[0]);
7517 instr
->operands
[1].imm
.value
= value
;
7518 instr
->operands
[1].skip
= 0;
7522 /* Try the MOVZ alias. */
7523 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDE
);
7524 aarch64_replace_opcode (instr
, opcode
);
7525 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7526 &instr
->value
, NULL
, NULL
, insn_sequence
))
7528 put_aarch64_insn (buf
, instr
->value
);
7531 /* Try the MOVK alias. */
7532 opcode
= aarch64_get_opcode (OP_MOV_IMM_WIDEN
);
7533 aarch64_replace_opcode (instr
, opcode
);
7534 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7535 &instr
->value
, NULL
, NULL
, insn_sequence
))
7537 put_aarch64_insn (buf
, instr
->value
);
7542 if (try_mov_bitmask_p
)
7544 /* Try the ORR alias. */
7545 opcode
= aarch64_get_opcode (OP_MOV_IMM_LOG
);
7546 aarch64_replace_opcode (instr
, opcode
);
7547 if (aarch64_opcode_encode (instr
->opcode
, instr
,
7548 &instr
->value
, NULL
, NULL
, insn_sequence
))
7550 put_aarch64_insn (buf
, instr
->value
);
7555 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7556 _("immediate cannot be moved by a single instruction"));
7559 /* An instruction operand which is immediate related may have symbol used
7560 in the assembly, e.g.
7563 .set u32, 0x00ffff00
7565 At the time when the assembly instruction is parsed, a referenced symbol,
7566 like 'u32' in the above example may not have been seen; a fixS is created
7567 in such a case and is handled here after symbols have been resolved.
7568 Instruction is fixed up with VALUE using the information in *FIXP plus
7569 extra information in FLAGS.
7571 This function is called by md_apply_fix to fix up instructions that need
7572 a fix-up described above but does not involve any linker-time relocation. */
7575 fix_insn (fixS
*fixP
, uint32_t flags
, offsetT value
)
7579 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7580 enum aarch64_opnd opnd
= fixP
->tc_fix_data
.opnd
;
7581 aarch64_inst
*new_inst
= fixP
->tc_fix_data
.inst
;
7585 /* Now the instruction is about to be fixed-up, so the operand that
7586 was previously marked as 'ignored' needs to be unmarked in order
7587 to get the encoding done properly. */
7588 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7589 new_inst
->operands
[idx
].skip
= 0;
7592 gas_assert (opnd
!= AARCH64_OPND_NIL
);
7596 case AARCH64_OPND_EXCEPTION
:
7597 if (unsigned_overflow (value
, 16))
7598 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7599 _("immediate out of range"));
7600 insn
= get_aarch64_insn (buf
);
7601 insn
|= encode_svc_imm (value
);
7602 put_aarch64_insn (buf
, insn
);
7605 case AARCH64_OPND_AIMM
:
7606 /* ADD or SUB with immediate.
7607 NOTE this assumes we come here with a add/sub shifted reg encoding
7608 3 322|2222|2 2 2 21111 111111
7609 1 098|7654|3 2 1 09876 543210 98765 43210
7610 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
7611 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
7612 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
7613 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
7615 3 322|2222|2 2 221111111111
7616 1 098|7654|3 2 109876543210 98765 43210
7617 11000000 sf 001|0001|shift imm12 Rn Rd ADD
7618 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
7619 51000000 sf 101|0001|shift imm12 Rn Rd SUB
7620 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
7621 Fields sf Rn Rd are already set. */
7622 insn
= get_aarch64_insn (buf
);
7626 insn
= reencode_addsub_switch_add_sub (insn
);
7630 if ((flags
& FIXUP_F_HAS_EXPLICIT_SHIFT
) == 0
7631 && unsigned_overflow (value
, 12))
7633 /* Try to shift the value by 12 to make it fit. */
7634 if (((value
>> 12) << 12) == value
7635 && ! unsigned_overflow (value
, 12 + 12))
7638 insn
|= encode_addsub_imm_shift_amount (1);
7642 if (unsigned_overflow (value
, 12))
7643 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7644 _("immediate out of range"));
7646 insn
|= encode_addsub_imm (value
);
7648 put_aarch64_insn (buf
, insn
);
7651 case AARCH64_OPND_SIMD_IMM
:
7652 case AARCH64_OPND_SIMD_IMM_SFT
:
7653 case AARCH64_OPND_LIMM
:
7654 /* Bit mask immediate. */
7655 gas_assert (new_inst
!= NULL
);
7656 idx
= aarch64_operand_index (new_inst
->opcode
->operands
, opnd
);
7657 new_inst
->operands
[idx
].imm
.value
= value
;
7658 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7659 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7660 put_aarch64_insn (buf
, new_inst
->value
);
7662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7663 _("invalid immediate"));
7666 case AARCH64_OPND_HALF
:
7667 /* 16-bit unsigned immediate. */
7668 if (unsigned_overflow (value
, 16))
7669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7670 _("immediate out of range"));
7671 insn
= get_aarch64_insn (buf
);
7672 insn
|= encode_movw_imm (value
& 0xffff);
7673 put_aarch64_insn (buf
, insn
);
7676 case AARCH64_OPND_IMM_MOV
:
7677 /* Operand for a generic move immediate instruction, which is
7678 an alias instruction that generates a single MOVZ, MOVN or ORR
7679 instruction to loads a 32-bit/64-bit immediate value into general
7680 register. An assembler error shall result if the immediate cannot be
7681 created by a single one of these instructions. If there is a choice,
7682 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
7683 and MOVZ or MOVN to ORR. */
7684 gas_assert (new_inst
!= NULL
);
7685 fix_mov_imm_insn (fixP
, buf
, new_inst
, value
);
7688 case AARCH64_OPND_ADDR_SIMM7
:
7689 case AARCH64_OPND_ADDR_SIMM9
:
7690 case AARCH64_OPND_ADDR_SIMM9_2
:
7691 case AARCH64_OPND_ADDR_SIMM10
:
7692 case AARCH64_OPND_ADDR_UIMM12
:
7693 case AARCH64_OPND_ADDR_SIMM11
:
7694 case AARCH64_OPND_ADDR_SIMM13
:
7695 /* Immediate offset in an address. */
7696 insn
= get_aarch64_insn (buf
);
7698 gas_assert (new_inst
!= NULL
&& new_inst
->value
== insn
);
7699 gas_assert (new_inst
->opcode
->operands
[1] == opnd
7700 || new_inst
->opcode
->operands
[2] == opnd
);
7702 /* Get the index of the address operand. */
7703 if (new_inst
->opcode
->operands
[1] == opnd
)
7704 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
7707 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
7710 /* Update the resolved offset value. */
7711 new_inst
->operands
[idx
].addr
.offset
.imm
= value
;
7713 /* Encode/fix-up. */
7714 if (aarch64_opcode_encode (new_inst
->opcode
, new_inst
,
7715 &new_inst
->value
, NULL
, NULL
, insn_sequence
))
7717 put_aarch64_insn (buf
, new_inst
->value
);
7720 else if (new_inst
->opcode
->iclass
== ldst_pos
7721 && try_to_encode_as_unscaled_ldst (new_inst
))
7723 put_aarch64_insn (buf
, new_inst
->value
);
7727 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7728 _("immediate offset out of range"));
7733 as_fatal (_("unhandled operand code %d"), opnd
);
7737 /* Apply a fixup (fixP) to segment data, once it has been determined
7738 by our caller that we have all the info we need to fix it up.
7740 Parameter valP is the pointer to the value of the bits. */
7743 md_apply_fix (fixS
* fixP
, valueT
* valP
, segT seg
)
7745 offsetT value
= *valP
;
7747 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7749 unsigned flags
= fixP
->fx_addnumber
;
7751 DEBUG_TRACE ("\n\n");
7752 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
7753 DEBUG_TRACE ("Enter md_apply_fix");
7755 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
7757 /* Note whether this will delete the relocation. */
7759 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
7762 /* Process the relocations. */
7763 switch (fixP
->fx_r_type
)
7765 case BFD_RELOC_NONE
:
7766 /* This will need to go in the object file. */
7771 case BFD_RELOC_8_PCREL
:
7772 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7773 md_number_to_chars (buf
, value
, 1);
7777 case BFD_RELOC_16_PCREL
:
7778 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7779 md_number_to_chars (buf
, value
, 2);
7783 case BFD_RELOC_32_PCREL
:
7784 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7785 md_number_to_chars (buf
, value
, 4);
7789 case BFD_RELOC_64_PCREL
:
7790 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7791 md_number_to_chars (buf
, value
, 8);
7794 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
7795 /* We claim that these fixups have been processed here, even if
7796 in fact we generate an error because we do not have a reloc
7797 for them, so tc_gen_reloc() will reject them. */
7799 if (fixP
->fx_addsy
&& !S_IS_DEFINED (fixP
->fx_addsy
))
7801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7802 _("undefined symbol %s used as an immediate value"),
7803 S_GET_NAME (fixP
->fx_addsy
));
7804 goto apply_fix_return
;
7806 fix_insn (fixP
, flags
, value
);
7809 case BFD_RELOC_AARCH64_LD_LO19_PCREL
:
7810 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7814 _("pc-relative load offset not word aligned"));
7815 if (signed_overflow (value
, 21))
7816 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7817 _("pc-relative load offset out of range"));
7818 insn
= get_aarch64_insn (buf
);
7819 insn
|= encode_ld_lit_ofs_19 (value
>> 2);
7820 put_aarch64_insn (buf
, insn
);
7824 case BFD_RELOC_AARCH64_ADR_LO21_PCREL
:
7825 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7827 if (signed_overflow (value
, 21))
7828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7829 _("pc-relative address offset out of range"));
7830 insn
= get_aarch64_insn (buf
);
7831 insn
|= encode_adr_imm (value
);
7832 put_aarch64_insn (buf
, insn
);
7836 case BFD_RELOC_AARCH64_BRANCH19
:
7837 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7841 _("conditional branch target not word aligned"));
7842 if (signed_overflow (value
, 21))
7843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7844 _("conditional branch out of range"));
7845 insn
= get_aarch64_insn (buf
);
7846 insn
|= encode_cond_branch_ofs_19 (value
>> 2);
7847 put_aarch64_insn (buf
, insn
);
7851 case BFD_RELOC_AARCH64_TSTBR14
:
7852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7856 _("conditional branch target not word aligned"));
7857 if (signed_overflow (value
, 16))
7858 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7859 _("conditional branch out of range"));
7860 insn
= get_aarch64_insn (buf
);
7861 insn
|= encode_tst_branch_ofs_14 (value
>> 2);
7862 put_aarch64_insn (buf
, insn
);
7866 case BFD_RELOC_AARCH64_CALL26
:
7867 case BFD_RELOC_AARCH64_JUMP26
:
7868 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7872 _("branch target not word aligned"));
7873 if (signed_overflow (value
, 28))
7874 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7875 _("branch out of range"));
7876 insn
= get_aarch64_insn (buf
);
7877 insn
|= encode_branch_ofs_26 (value
>> 2);
7878 put_aarch64_insn (buf
, insn
);
7882 case BFD_RELOC_AARCH64_MOVW_G0
:
7883 case BFD_RELOC_AARCH64_MOVW_G0_NC
:
7884 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7885 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
:
7886 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7887 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
:
7890 case BFD_RELOC_AARCH64_MOVW_G1
:
7891 case BFD_RELOC_AARCH64_MOVW_G1_NC
:
7892 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7893 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7894 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7895 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
:
7898 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
7900 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7901 /* Should always be exported to object file, see
7902 aarch64_force_relocation(). */
7903 gas_assert (!fixP
->fx_done
);
7904 gas_assert (seg
->use_rela_p
);
7906 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7908 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7909 /* Should always be exported to object file, see
7910 aarch64_force_relocation(). */
7911 gas_assert (!fixP
->fx_done
);
7912 gas_assert (seg
->use_rela_p
);
7914 case BFD_RELOC_AARCH64_MOVW_G2
:
7915 case BFD_RELOC_AARCH64_MOVW_G2_NC
:
7916 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7917 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7918 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
:
7921 case BFD_RELOC_AARCH64_MOVW_G3
:
7922 case BFD_RELOC_AARCH64_MOVW_PREL_G3
:
7925 if (fixP
->fx_done
|| !seg
->use_rela_p
)
7927 insn
= get_aarch64_insn (buf
);
7931 /* REL signed addend must fit in 16 bits */
7932 if (signed_overflow (value
, 16))
7933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7934 _("offset out of range"));
7938 /* Check for overflow and scale. */
7939 switch (fixP
->fx_r_type
)
7941 case BFD_RELOC_AARCH64_MOVW_G0
:
7942 case BFD_RELOC_AARCH64_MOVW_G1
:
7943 case BFD_RELOC_AARCH64_MOVW_G2
:
7944 case BFD_RELOC_AARCH64_MOVW_G3
:
7945 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
:
7946 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
7947 if (unsigned_overflow (value
, scale
+ 16))
7948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7949 _("unsigned value out of range"));
7951 case BFD_RELOC_AARCH64_MOVW_G0_S
:
7952 case BFD_RELOC_AARCH64_MOVW_G1_S
:
7953 case BFD_RELOC_AARCH64_MOVW_G2_S
:
7954 case BFD_RELOC_AARCH64_MOVW_PREL_G0
:
7955 case BFD_RELOC_AARCH64_MOVW_PREL_G1
:
7956 case BFD_RELOC_AARCH64_MOVW_PREL_G2
:
7957 /* NOTE: We can only come here with movz or movn. */
7958 if (signed_overflow (value
, scale
+ 16))
7959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7960 _("signed value out of range"));
7963 /* Force use of MOVN. */
7965 insn
= reencode_movzn_to_movn (insn
);
7969 /* Force use of MOVZ. */
7970 insn
= reencode_movzn_to_movz (insn
);
7974 /* Unchecked relocations. */
7980 /* Insert value into MOVN/MOVZ/MOVK instruction. */
7981 insn
|= encode_movw_imm (value
& 0xffff);
7983 put_aarch64_insn (buf
, insn
);
7987 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
7988 fixP
->fx_r_type
= (ilp32_p
7989 ? BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7990 : BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
);
7991 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7992 /* Should always be exported to object file, see
7993 aarch64_force_relocation(). */
7994 gas_assert (!fixP
->fx_done
);
7995 gas_assert (seg
->use_rela_p
);
7998 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
7999 fixP
->fx_r_type
= (ilp32_p
8000 ? BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
8001 : BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
);
8002 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8003 /* Should always be exported to object file, see
8004 aarch64_force_relocation(). */
8005 gas_assert (!fixP
->fx_done
);
8006 gas_assert (seg
->use_rela_p
);
8009 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8010 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8011 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8012 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8013 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8014 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8015 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8016 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8017 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8018 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8019 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8020 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8021 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8022 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8023 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8024 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8025 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8026 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8027 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8028 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8029 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8030 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8031 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8032 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8033 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8034 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8035 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8036 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8037 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8038 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8039 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8040 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8041 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8042 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8043 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8044 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8045 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8046 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8047 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8048 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8049 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8050 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8051 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8052 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8053 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8054 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8055 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8056 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8057 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8058 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8059 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8060 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8061 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
8062 /* Should always be exported to object file, see
8063 aarch64_force_relocation(). */
8064 gas_assert (!fixP
->fx_done
);
8065 gas_assert (seg
->use_rela_p
);
8068 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8069 /* Should always be exported to object file, see
8070 aarch64_force_relocation(). */
8071 fixP
->fx_r_type
= (ilp32_p
8072 ? BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
8073 : BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
);
8074 gas_assert (!fixP
->fx_done
);
8075 gas_assert (seg
->use_rela_p
);
8078 case BFD_RELOC_AARCH64_ADD_LO12
:
8079 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8080 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8081 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8082 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8083 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8084 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8085 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8086 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8087 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8088 case BFD_RELOC_AARCH64_LDST128_LO12
:
8089 case BFD_RELOC_AARCH64_LDST16_LO12
:
8090 case BFD_RELOC_AARCH64_LDST32_LO12
:
8091 case BFD_RELOC_AARCH64_LDST64_LO12
:
8092 case BFD_RELOC_AARCH64_LDST8_LO12
:
8093 /* Should always be exported to object file, see
8094 aarch64_force_relocation(). */
8095 gas_assert (!fixP
->fx_done
);
8096 gas_assert (seg
->use_rela_p
);
8099 case BFD_RELOC_AARCH64_TLSDESC_ADD
:
8100 case BFD_RELOC_AARCH64_TLSDESC_CALL
:
8101 case BFD_RELOC_AARCH64_TLSDESC_LDR
:
8104 case BFD_RELOC_UNUSED
:
8105 /* An error will already have been reported. */
8109 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8110 _("unexpected %s fixup"),
8111 bfd_get_reloc_code_name (fixP
->fx_r_type
));
8116 /* Free the allocated the struct aarch64_inst.
8117 N.B. currently there are very limited number of fix-up types actually use
8118 this field, so the impact on the performance should be minimal . */
8119 if (fixP
->tc_fix_data
.inst
!= NULL
)
8120 free (fixP
->tc_fix_data
.inst
);
8125 /* Translate internal representation of relocation info to BFD target
8129 tc_gen_reloc (asection
* section
, fixS
* fixp
)
8132 bfd_reloc_code_real_type code
;
8134 reloc
= XNEW (arelent
);
8136 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
8137 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8138 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8142 if (section
->use_rela_p
)
8143 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
8145 fixp
->fx_offset
= reloc
->address
;
8147 reloc
->addend
= fixp
->fx_offset
;
8149 code
= fixp
->fx_r_type
;
8154 code
= BFD_RELOC_16_PCREL
;
8159 code
= BFD_RELOC_32_PCREL
;
8164 code
= BFD_RELOC_64_PCREL
;
8171 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8172 if (reloc
->howto
== NULL
)
8174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8176 ("cannot represent %s relocation in this object file format"),
8177 bfd_get_reloc_code_name (code
));
8184 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
8187 cons_fix_new_aarch64 (fragS
* frag
, int where
, int size
, expressionS
* exp
)
8189 bfd_reloc_code_real_type type
;
8193 FIXME: @@ Should look at CPU word size. */
8200 type
= BFD_RELOC_16
;
8203 type
= BFD_RELOC_32
;
8206 type
= BFD_RELOC_64
;
8209 as_bad (_("cannot do %u-byte relocation"), size
);
8210 type
= BFD_RELOC_UNUSED
;
8214 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
8218 aarch64_force_relocation (struct fix
*fixp
)
8220 switch (fixp
->fx_r_type
)
8222 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
:
8223 /* Perform these "immediate" internal relocations
8224 even if the symbol is extern or weak. */
8227 case BFD_RELOC_AARCH64_LD_GOT_LO12_NC
:
8228 case BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
:
8229 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
:
8230 /* Pseudo relocs that need to be fixed up according to
8234 case BFD_RELOC_AARCH64_ADD_LO12
:
8235 case BFD_RELOC_AARCH64_ADR_GOT_PAGE
:
8236 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
:
8237 case BFD_RELOC_AARCH64_ADR_HI21_PCREL
:
8238 case BFD_RELOC_AARCH64_GOT_LD_PREL19
:
8239 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
:
8240 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
:
8241 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
:
8242 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
:
8243 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
:
8244 case BFD_RELOC_AARCH64_LDST128_LO12
:
8245 case BFD_RELOC_AARCH64_LDST16_LO12
:
8246 case BFD_RELOC_AARCH64_LDST32_LO12
:
8247 case BFD_RELOC_AARCH64_LDST64_LO12
:
8248 case BFD_RELOC_AARCH64_LDST8_LO12
:
8249 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
:
8250 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
:
8251 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
:
8252 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
:
8253 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
:
8254 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
:
8255 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
:
8256 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1
:
8257 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
:
8258 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
:
8259 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
:
8260 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
:
8261 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1
:
8262 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
:
8263 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
:
8264 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
:
8265 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
:
8266 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
:
8267 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
:
8268 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
:
8269 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
:
8270 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
:
8271 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
:
8272 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
:
8273 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
:
8274 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
:
8275 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
:
8276 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
:
8277 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
:
8278 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
:
8279 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
:
8280 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
:
8281 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
:
8282 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
:
8283 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
:
8284 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
:
8285 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
:
8286 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
:
8287 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
:
8288 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
:
8289 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
:
8290 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
:
8291 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
:
8292 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
:
8293 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
:
8294 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
:
8295 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
:
8296 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
:
8297 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
:
8298 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
:
8299 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
:
8300 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
:
8301 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
:
8302 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
:
8303 /* Always leave these relocations for the linker. */
8310 return generic_force_reloc (fixp
);
8315 /* Implement md_after_parse_args. This is the earliest time we need to decide
8316 ABI. If no -mabi specified, the ABI will be decided by target triplet. */
8319 aarch64_after_parse_args (void)
8321 if (aarch64_abi
!= AARCH64_ABI_NONE
)
8324 /* DEFAULT_ARCH will have ":32" extension if it's configured for ILP32. */
8325 if (strlen (default_arch
) > 7 && strcmp (default_arch
+ 7, ":32") == 0)
8326 aarch64_abi
= AARCH64_ABI_ILP32
;
8328 aarch64_abi
= AARCH64_ABI_LP64
;
8332 elf64_aarch64_target_format (void)
8334 if (strcmp (TARGET_OS
, "cloudabi") == 0)
8336 /* FIXME: What to do for ilp32_p ? */
8337 return target_big_endian
? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
8339 if (target_big_endian
)
8340 return ilp32_p
? "elf32-bigaarch64" : "elf64-bigaarch64";
8342 return ilp32_p
? "elf32-littleaarch64" : "elf64-littleaarch64";
8346 aarch64elf_frob_symbol (symbolS
* symp
, int *puntp
)
8348 elf_frob_symbol (symp
, puntp
);
8352 /* MD interface: Finalization. */
8354 /* A good place to do this, although this was probably not intended
8355 for this kind of use. We need to dump the literal pool before
8356 references are made to a null symbol pointer. */
8359 aarch64_cleanup (void)
8363 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
8365 /* Put it at the end of the relevant section. */
8366 subseg_set (pool
->section
, pool
->sub_section
);
8372 /* Remove any excess mapping symbols generated for alignment frags in
8373 SEC. We may have created a mapping symbol before a zero byte
8374 alignment; remove it if there's a mapping symbol after the
8377 check_mapping_symbols (bfd
* abfd ATTRIBUTE_UNUSED
, asection
* sec
,
8378 void *dummy ATTRIBUTE_UNUSED
)
8380 segment_info_type
*seginfo
= seg_info (sec
);
8383 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
8386 for (fragp
= seginfo
->frchainP
->frch_root
;
8387 fragp
!= NULL
; fragp
= fragp
->fr_next
)
8389 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
8390 fragS
*next
= fragp
->fr_next
;
8392 /* Variable-sized frags have been converted to fixed size by
8393 this point. But if this was variable-sized to start with,
8394 there will be a fixed-size frag after it. So don't handle
8396 if (sym
== NULL
|| next
== NULL
)
8399 if (S_GET_VALUE (sym
) < next
->fr_address
)
8400 /* Not at the end of this frag. */
8402 know (S_GET_VALUE (sym
) == next
->fr_address
);
8406 if (next
->tc_frag_data
.first_map
!= NULL
)
8408 /* Next frag starts with a mapping symbol. Discard this
8410 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8414 if (next
->fr_next
== NULL
)
8416 /* This mapping symbol is at the end of the section. Discard
8418 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
8419 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
8423 /* As long as we have empty frags without any mapping symbols,
8425 /* If the next frag is non-empty and does not start with a
8426 mapping symbol, then this mapping symbol is required. */
8427 if (next
->fr_address
!= next
->fr_next
->fr_address
)
8430 next
= next
->fr_next
;
8432 while (next
!= NULL
);
8437 /* Adjust the symbol table. */
8440 aarch64_adjust_symtab (void)
8443 /* Remove any overlapping mapping symbols generated by alignment frags. */
8444 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
8445 /* Now do generic ELF adjustments. */
8446 elf_adjust_symtab ();
8451 checked_hash_insert (struct hash_control
*table
, const char *key
, void *value
)
8453 const char *hash_err
;
8455 hash_err
= hash_insert (table
, key
, value
);
8457 printf ("Internal Error: Can't hash %s\n", key
);
8461 fill_instruction_hash_table (void)
8463 aarch64_opcode
*opcode
= aarch64_opcode_table
;
8465 while (opcode
->name
!= NULL
)
8467 templates
*templ
, *new_templ
;
8468 templ
= hash_find (aarch64_ops_hsh
, opcode
->name
);
8470 new_templ
= XNEW (templates
);
8471 new_templ
->opcode
= opcode
;
8472 new_templ
->next
= NULL
;
8475 checked_hash_insert (aarch64_ops_hsh
, opcode
->name
, (void *) new_templ
);
8478 new_templ
->next
= templ
->next
;
8479 templ
->next
= new_templ
;
8486 convert_to_upper (char *dst
, const char *src
, size_t num
)
8489 for (i
= 0; i
< num
&& *src
!= '\0'; ++i
, ++dst
, ++src
)
8490 *dst
= TOUPPER (*src
);
8494 /* Assume STR point to a lower-case string, allocate, convert and return
8495 the corresponding upper-case string. */
8496 static inline const char*
8497 get_upper_str (const char *str
)
8500 size_t len
= strlen (str
);
8501 ret
= XNEWVEC (char, len
+ 1);
8502 convert_to_upper (ret
, str
, len
);
8506 /* MD interface: Initialization. */
8514 if ((aarch64_ops_hsh
= hash_new ()) == NULL
8515 || (aarch64_cond_hsh
= hash_new ()) == NULL
8516 || (aarch64_shift_hsh
= hash_new ()) == NULL
8517 || (aarch64_sys_regs_hsh
= hash_new ()) == NULL
8518 || (aarch64_pstatefield_hsh
= hash_new ()) == NULL
8519 || (aarch64_sys_regs_ic_hsh
= hash_new ()) == NULL
8520 || (aarch64_sys_regs_dc_hsh
= hash_new ()) == NULL
8521 || (aarch64_sys_regs_at_hsh
= hash_new ()) == NULL
8522 || (aarch64_sys_regs_tlbi_hsh
= hash_new ()) == NULL
8523 || (aarch64_sys_regs_sr_hsh
= hash_new ()) == NULL
8524 || (aarch64_reg_hsh
= hash_new ()) == NULL
8525 || (aarch64_barrier_opt_hsh
= hash_new ()) == NULL
8526 || (aarch64_nzcv_hsh
= hash_new ()) == NULL
8527 || (aarch64_pldop_hsh
= hash_new ()) == NULL
8528 || (aarch64_hint_opt_hsh
= hash_new ()) == NULL
)
8529 as_fatal (_("virtual memory exhausted"));
8531 fill_instruction_hash_table ();
8533 for (i
= 0; aarch64_sys_regs
[i
].name
!= NULL
; ++i
)
8534 checked_hash_insert (aarch64_sys_regs_hsh
, aarch64_sys_regs
[i
].name
,
8535 (void *) (aarch64_sys_regs
+ i
));
8537 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
8538 checked_hash_insert (aarch64_pstatefield_hsh
,
8539 aarch64_pstatefields
[i
].name
,
8540 (void *) (aarch64_pstatefields
+ i
));
8542 for (i
= 0; aarch64_sys_regs_ic
[i
].name
!= NULL
; i
++)
8543 checked_hash_insert (aarch64_sys_regs_ic_hsh
,
8544 aarch64_sys_regs_ic
[i
].name
,
8545 (void *) (aarch64_sys_regs_ic
+ i
));
8547 for (i
= 0; aarch64_sys_regs_dc
[i
].name
!= NULL
; i
++)
8548 checked_hash_insert (aarch64_sys_regs_dc_hsh
,
8549 aarch64_sys_regs_dc
[i
].name
,
8550 (void *) (aarch64_sys_regs_dc
+ i
));
8552 for (i
= 0; aarch64_sys_regs_at
[i
].name
!= NULL
; i
++)
8553 checked_hash_insert (aarch64_sys_regs_at_hsh
,
8554 aarch64_sys_regs_at
[i
].name
,
8555 (void *) (aarch64_sys_regs_at
+ i
));
8557 for (i
= 0; aarch64_sys_regs_tlbi
[i
].name
!= NULL
; i
++)
8558 checked_hash_insert (aarch64_sys_regs_tlbi_hsh
,
8559 aarch64_sys_regs_tlbi
[i
].name
,
8560 (void *) (aarch64_sys_regs_tlbi
+ i
));
8562 for (i
= 0; aarch64_sys_regs_sr
[i
].name
!= NULL
; i
++)
8563 checked_hash_insert (aarch64_sys_regs_sr_hsh
,
8564 aarch64_sys_regs_sr
[i
].name
,
8565 (void *) (aarch64_sys_regs_sr
+ i
));
8567 for (i
= 0; i
< ARRAY_SIZE (reg_names
); i
++)
8568 checked_hash_insert (aarch64_reg_hsh
, reg_names
[i
].name
,
8569 (void *) (reg_names
+ i
));
8571 for (i
= 0; i
< ARRAY_SIZE (nzcv_names
); i
++)
8572 checked_hash_insert (aarch64_nzcv_hsh
, nzcv_names
[i
].template,
8573 (void *) (nzcv_names
+ i
));
8575 for (i
= 0; aarch64_operand_modifiers
[i
].name
!= NULL
; i
++)
8577 const char *name
= aarch64_operand_modifiers
[i
].name
;
8578 checked_hash_insert (aarch64_shift_hsh
, name
,
8579 (void *) (aarch64_operand_modifiers
+ i
));
8580 /* Also hash the name in the upper case. */
8581 checked_hash_insert (aarch64_shift_hsh
, get_upper_str (name
),
8582 (void *) (aarch64_operand_modifiers
+ i
));
8585 for (i
= 0; i
< ARRAY_SIZE (aarch64_conds
); i
++)
8588 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
8589 the same condition code. */
8590 for (j
= 0; j
< ARRAY_SIZE (aarch64_conds
[i
].names
); ++j
)
8592 const char *name
= aarch64_conds
[i
].names
[j
];
8595 checked_hash_insert (aarch64_cond_hsh
, name
,
8596 (void *) (aarch64_conds
+ i
));
8597 /* Also hash the name in the upper case. */
8598 checked_hash_insert (aarch64_cond_hsh
, get_upper_str (name
),
8599 (void *) (aarch64_conds
+ i
));
8603 for (i
= 0; i
< ARRAY_SIZE (aarch64_barrier_options
); i
++)
8605 const char *name
= aarch64_barrier_options
[i
].name
;
8606 /* Skip xx00 - the unallocated values of option. */
8609 checked_hash_insert (aarch64_barrier_opt_hsh
, name
,
8610 (void *) (aarch64_barrier_options
+ i
));
8611 /* Also hash the name in the upper case. */
8612 checked_hash_insert (aarch64_barrier_opt_hsh
, get_upper_str (name
),
8613 (void *) (aarch64_barrier_options
+ i
));
8616 for (i
= 0; i
< ARRAY_SIZE (aarch64_prfops
); i
++)
8618 const char* name
= aarch64_prfops
[i
].name
;
8619 /* Skip the unallocated hint encodings. */
8622 checked_hash_insert (aarch64_pldop_hsh
, name
,
8623 (void *) (aarch64_prfops
+ i
));
8624 /* Also hash the name in the upper case. */
8625 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8626 (void *) (aarch64_prfops
+ i
));
8629 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
8631 const char* name
= aarch64_hint_options
[i
].name
;
8633 checked_hash_insert (aarch64_hint_opt_hsh
, name
,
8634 (void *) (aarch64_hint_options
+ i
));
8635 /* Also hash the name in the upper case. */
8636 checked_hash_insert (aarch64_pldop_hsh
, get_upper_str (name
),
8637 (void *) (aarch64_hint_options
+ i
));
8640 /* Set the cpu variant based on the command-line options. */
8642 mcpu_cpu_opt
= march_cpu_opt
;
8645 mcpu_cpu_opt
= &cpu_default
;
8647 cpu_variant
= *mcpu_cpu_opt
;
8649 /* Record the CPU type. */
8650 mach
= ilp32_p
? bfd_mach_aarch64_ilp32
: bfd_mach_aarch64
;
8652 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
8655 /* Command line processing. */
8657 const char *md_shortopts
= "m:";
8659 #ifdef AARCH64_BI_ENDIAN
8660 #define OPTION_EB (OPTION_MD_BASE + 0)
8661 #define OPTION_EL (OPTION_MD_BASE + 1)
8663 #if TARGET_BYTES_BIG_ENDIAN
8664 #define OPTION_EB (OPTION_MD_BASE + 0)
8666 #define OPTION_EL (OPTION_MD_BASE + 1)
8670 struct option md_longopts
[] = {
8672 {"EB", no_argument
, NULL
, OPTION_EB
},
8675 {"EL", no_argument
, NULL
, OPTION_EL
},
8677 {NULL
, no_argument
, NULL
, 0}
8680 size_t md_longopts_size
= sizeof (md_longopts
);
8682 struct aarch64_option_table
8684 const char *option
; /* Option name to match. */
8685 const char *help
; /* Help information. */
8686 int *var
; /* Variable to change. */
8687 int value
; /* What to change it to. */
8688 char *deprecated
; /* If non-null, print this message. */
8691 static struct aarch64_option_table aarch64_opts
[] = {
8692 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
8693 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
8695 #ifdef DEBUG_AARCH64
8696 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump
, 1, NULL
},
8697 #endif /* DEBUG_AARCH64 */
8698 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p
, 1,
8700 {"mno-verbose-error", N_("do not output verbose error messages"),
8701 &verbose_error_p
, 0, NULL
},
8702 {NULL
, NULL
, NULL
, 0, NULL
}
8705 struct aarch64_cpu_option_table
8708 const aarch64_feature_set value
;
8709 /* The canonical name of the CPU, or NULL to use NAME converted to upper
8711 const char *canonical_name
;
8714 /* This list should, at a minimum, contain all the cpu names
8715 recognized by GCC. */
8716 static const struct aarch64_cpu_option_table aarch64_cpus
[] = {
8717 {"all", AARCH64_ANY
, NULL
},
8718 {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8719 AARCH64_FEATURE_CRC
), "Cortex-A35"},
8720 {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8721 AARCH64_FEATURE_CRC
), "Cortex-A53"},
8722 {"cortex-a57", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8723 AARCH64_FEATURE_CRC
), "Cortex-A57"},
8724 {"cortex-a72", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8725 AARCH64_FEATURE_CRC
), "Cortex-A72"},
8726 {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8727 AARCH64_FEATURE_CRC
), "Cortex-A73"},
8728 {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8729 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8731 {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8732 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8734 {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8735 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
| AARCH64_FEATURE_DOTPROD
),
8737 {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8738 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8739 | AARCH64_FEATURE_DOTPROD
8740 | AARCH64_FEATURE_PROFILE
),
8742 {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8743 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8744 "Samsung Exynos M1"},
8745 {"falkor", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8746 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8747 | AARCH64_FEATURE_RDMA
),
8749 {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8750 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8751 | AARCH64_FEATURE_DOTPROD
8752 | AARCH64_FEATURE_SSBS
),
8754 {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2
,
8755 AARCH64_FEATURE_RCPC
| AARCH64_FEATURE_F16
8756 | AARCH64_FEATURE_DOTPROD
8757 | AARCH64_FEATURE_PROFILE
),
8759 {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8760 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
8761 | AARCH64_FEATURE_RDMA
),
8762 "Qualcomm QDF24XX"},
8763 {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4
,
8764 AARCH64_FEATURE_CRYPTO
| AARCH64_FEATURE_PROFILE
),
8765 "Qualcomm Saphira"},
8766 {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8767 AARCH64_FEATURE_CRC
| AARCH64_FEATURE_CRYPTO
),
8769 {"vulcan", AARCH64_FEATURE (AARCH64_ARCH_V8_1
,
8770 AARCH64_FEATURE_CRYPTO
),
8772 /* The 'xgene-1' name is an older name for 'xgene1', which was used
8773 in earlier releases and is superseded by 'xgene1' in all
8775 {"xgene-1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8776 {"xgene1", AARCH64_ARCH_V8
, "APM X-Gene 1"},
8777 {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8
,
8778 AARCH64_FEATURE_CRC
), "APM X-Gene 2"},
8779 {"generic", AARCH64_ARCH_V8
, NULL
},
8781 {NULL
, AARCH64_ARCH_NONE
, NULL
}
8784 struct aarch64_arch_option_table
8787 const aarch64_feature_set value
;
8790 /* This list should, at a minimum, contain all the architecture names
8791 recognized by GCC. */
8792 static const struct aarch64_arch_option_table aarch64_archs
[] = {
8793 {"all", AARCH64_ANY
},
8794 {"armv8-a", AARCH64_ARCH_V8
},
8795 {"armv8.1-a", AARCH64_ARCH_V8_1
},
8796 {"armv8.2-a", AARCH64_ARCH_V8_2
},
8797 {"armv8.3-a", AARCH64_ARCH_V8_3
},
8798 {"armv8.4-a", AARCH64_ARCH_V8_4
},
8799 {"armv8.5-a", AARCH64_ARCH_V8_5
},
8800 {NULL
, AARCH64_ARCH_NONE
}
8803 /* ISA extensions. */
8804 struct aarch64_option_cpu_value_table
8807 const aarch64_feature_set value
;
8808 const aarch64_feature_set require
; /* Feature dependencies. */
8811 static const struct aarch64_option_cpu_value_table aarch64_features
[] = {
8812 {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0),
8814 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
8815 | AARCH64_FEATURE_AES
8816 | AARCH64_FEATURE_SHA2
, 0),
8817 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8818 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0),
8820 {"lse", AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0),
8822 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0),
8823 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8824 {"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN
, 0),
8826 {"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0),
8828 {"ras", AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0),
8830 {"rdma", AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0),
8831 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0)},
8832 {"fp16", AARCH64_FEATURE (AARCH64_FEATURE_F16
, 0),
8833 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0)},
8834 {"fp16fml", AARCH64_FEATURE (AARCH64_FEATURE_F16_FML
, 0),
8835 AARCH64_FEATURE (AARCH64_FEATURE_FP
8836 | AARCH64_FEATURE_F16
, 0)},
8837 {"profile", AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0),
8839 {"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE
, 0),
8840 AARCH64_FEATURE (AARCH64_FEATURE_F16
8841 | AARCH64_FEATURE_SIMD
8842 | AARCH64_FEATURE_COMPNUM
, 0)},
8843 {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM
, 0),
8844 AARCH64_FEATURE (AARCH64_FEATURE_F16
8845 | AARCH64_FEATURE_SIMD
, 0)},
8846 {"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC
, 0),
8848 {"dotprod", AARCH64_FEATURE (AARCH64_FEATURE_DOTPROD
, 0),
8850 {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
, 0),
8852 {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB
, 0),
8854 {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES
, 0),
8856 {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES
, 0),
8858 {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4
, 0),
8860 {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
8861 | AARCH64_FEATURE_SHA3
, 0),
8863 {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG
, 0),
8865 {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS
, 0),
8867 {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG
, 0),
8869 {NULL
, AARCH64_ARCH_NONE
, AARCH64_ARCH_NONE
},
8872 struct aarch64_long_option_table
8874 const char *option
; /* Substring to match. */
8875 const char *help
; /* Help information. */
8876 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
8877 char *deprecated
; /* If non-null, print this message. */
8880 /* Transitive closure of features depending on set. */
8881 static aarch64_feature_set
8882 aarch64_feature_disable_set (aarch64_feature_set set
)
8884 const struct aarch64_option_cpu_value_table
*opt
;
8885 aarch64_feature_set prev
= 0;
8887 while (prev
!= set
) {
8889 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8890 if (AARCH64_CPU_HAS_ANY_FEATURES (opt
->require
, set
))
8891 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->value
);
8896 /* Transitive closure of dependencies of set. */
8897 static aarch64_feature_set
8898 aarch64_feature_enable_set (aarch64_feature_set set
)
8900 const struct aarch64_option_cpu_value_table
*opt
;
8901 aarch64_feature_set prev
= 0;
8903 while (prev
!= set
) {
8905 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8906 if (AARCH64_CPU_HAS_FEATURE (set
, opt
->value
))
8907 AARCH64_MERGE_FEATURE_SETS (set
, set
, opt
->require
);
8913 aarch64_parse_features (const char *str
, const aarch64_feature_set
**opt_p
,
8914 bfd_boolean ext_only
)
8916 /* We insist on extensions being added before being removed. We achieve
8917 this by using the ADDING_VALUE variable to indicate whether we are
8918 adding an extension (1) or removing it (0) and only allowing it to
8919 change in the order -1 -> 1 -> 0. */
8920 int adding_value
= -1;
8921 aarch64_feature_set
*ext_set
= XNEW (aarch64_feature_set
);
8923 /* Copy the feature set, so that we can modify it. */
8927 while (str
!= NULL
&& *str
!= 0)
8929 const struct aarch64_option_cpu_value_table
*opt
;
8930 const char *ext
= NULL
;
8937 as_bad (_("invalid architectural extension"));
8941 ext
= strchr (++str
, '+');
8947 optlen
= strlen (str
);
8949 if (optlen
>= 2 && strncmp (str
, "no", 2) == 0)
8951 if (adding_value
!= 0)
8956 else if (optlen
> 0)
8958 if (adding_value
== -1)
8960 else if (adding_value
!= 1)
8962 as_bad (_("must specify extensions to add before specifying "
8963 "those to remove"));
8970 as_bad (_("missing architectural extension"));
8974 gas_assert (adding_value
!= -1);
8976 for (opt
= aarch64_features
; opt
->name
!= NULL
; opt
++)
8977 if (strncmp (opt
->name
, str
, optlen
) == 0)
8979 aarch64_feature_set set
;
8981 /* Add or remove the extension. */
8984 set
= aarch64_feature_enable_set (opt
->value
);
8985 AARCH64_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, set
);
8989 set
= aarch64_feature_disable_set (opt
->value
);
8990 AARCH64_CLEAR_FEATURE (*ext_set
, *ext_set
, set
);
8995 if (opt
->name
== NULL
)
8997 as_bad (_("unknown architectural extension `%s'"), str
);
9008 aarch64_parse_cpu (const char *str
)
9010 const struct aarch64_cpu_option_table
*opt
;
9011 const char *ext
= strchr (str
, '+');
9017 optlen
= strlen (str
);
9021 as_bad (_("missing cpu name `%s'"), str
);
9025 for (opt
= aarch64_cpus
; opt
->name
!= NULL
; opt
++)
9026 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9028 mcpu_cpu_opt
= &opt
->value
;
9030 return aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
);
9035 as_bad (_("unknown cpu `%s'"), str
);
9040 aarch64_parse_arch (const char *str
)
9042 const struct aarch64_arch_option_table
*opt
;
9043 const char *ext
= strchr (str
, '+');
9049 optlen
= strlen (str
);
9053 as_bad (_("missing architecture name `%s'"), str
);
9057 for (opt
= aarch64_archs
; opt
->name
!= NULL
; opt
++)
9058 if (strlen (opt
->name
) == optlen
&& strncmp (str
, opt
->name
, optlen
) == 0)
9060 march_cpu_opt
= &opt
->value
;
9062 return aarch64_parse_features (ext
, &march_cpu_opt
, FALSE
);
9067 as_bad (_("unknown architecture `%s'\n"), str
);
9072 struct aarch64_option_abi_value_table
9075 enum aarch64_abi_type value
;
9078 static const struct aarch64_option_abi_value_table aarch64_abis
[] = {
9079 {"ilp32", AARCH64_ABI_ILP32
},
9080 {"lp64", AARCH64_ABI_LP64
},
9084 aarch64_parse_abi (const char *str
)
9090 as_bad (_("missing abi name `%s'"), str
);
9094 for (i
= 0; i
< ARRAY_SIZE (aarch64_abis
); i
++)
9095 if (strcmp (str
, aarch64_abis
[i
].name
) == 0)
9097 aarch64_abi
= aarch64_abis
[i
].value
;
9101 as_bad (_("unknown abi `%s'\n"), str
);
9105 static struct aarch64_long_option_table aarch64_long_opts
[] = {
9107 {"mabi=", N_("<abi name>\t specify for ABI <abi name>"),
9108 aarch64_parse_abi
, NULL
},
9109 #endif /* OBJ_ELF */
9110 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
9111 aarch64_parse_cpu
, NULL
},
9112 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
9113 aarch64_parse_arch
, NULL
},
9114 {NULL
, NULL
, 0, NULL
}
9118 md_parse_option (int c
, const char *arg
)
9120 struct aarch64_option_table
*opt
;
9121 struct aarch64_long_option_table
*lopt
;
9127 target_big_endian
= 1;
9133 target_big_endian
= 0;
9138 /* Listing option. Just ignore these, we don't support additional
9143 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9145 if (c
== opt
->option
[0]
9146 && ((arg
== NULL
&& opt
->option
[1] == 0)
9147 || streq (arg
, opt
->option
+ 1)))
9149 /* If the option is deprecated, tell the user. */
9150 if (opt
->deprecated
!= NULL
)
9151 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
9152 arg
? arg
: "", _(opt
->deprecated
));
9154 if (opt
->var
!= NULL
)
9155 *opt
->var
= opt
->value
;
9161 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9163 /* These options are expected to have an argument. */
9164 if (c
== lopt
->option
[0]
9166 && strncmp (arg
, lopt
->option
+ 1,
9167 strlen (lopt
->option
+ 1)) == 0)
9169 /* If the option is deprecated, tell the user. */
9170 if (lopt
->deprecated
!= NULL
)
9171 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
9172 _(lopt
->deprecated
));
9174 /* Call the sup-option parser. */
9175 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
9186 md_show_usage (FILE * fp
)
9188 struct aarch64_option_table
*opt
;
9189 struct aarch64_long_option_table
*lopt
;
9191 fprintf (fp
, _(" AArch64-specific assembler options:\n"));
9193 for (opt
= aarch64_opts
; opt
->option
!= NULL
; opt
++)
9194 if (opt
->help
!= NULL
)
9195 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
9197 for (lopt
= aarch64_long_opts
; lopt
->option
!= NULL
; lopt
++)
9198 if (lopt
->help
!= NULL
)
9199 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
9203 -EB assemble code for a big-endian cpu\n"));
9208 -EL assemble code for a little-endian cpu\n"));
9212 /* Parse a .cpu directive. */
9215 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED
)
9217 const struct aarch64_cpu_option_table
*opt
;
9223 name
= input_line_pointer
;
9224 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9225 input_line_pointer
++;
9226 saved_char
= *input_line_pointer
;
9227 *input_line_pointer
= 0;
9229 ext
= strchr (name
, '+');
9232 optlen
= ext
- name
;
9234 optlen
= strlen (name
);
9236 /* Skip the first "all" entry. */
9237 for (opt
= aarch64_cpus
+ 1; opt
->name
!= NULL
; opt
++)
9238 if (strlen (opt
->name
) == optlen
9239 && strncmp (name
, opt
->name
, optlen
) == 0)
9241 mcpu_cpu_opt
= &opt
->value
;
9243 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9246 cpu_variant
= *mcpu_cpu_opt
;
9248 *input_line_pointer
= saved_char
;
9249 demand_empty_rest_of_line ();
9252 as_bad (_("unknown cpu `%s'"), name
);
9253 *input_line_pointer
= saved_char
;
9254 ignore_rest_of_line ();
9258 /* Parse a .arch directive. */
9261 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED
)
9263 const struct aarch64_arch_option_table
*opt
;
9269 name
= input_line_pointer
;
9270 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9271 input_line_pointer
++;
9272 saved_char
= *input_line_pointer
;
9273 *input_line_pointer
= 0;
9275 ext
= strchr (name
, '+');
9278 optlen
= ext
- name
;
9280 optlen
= strlen (name
);
9282 /* Skip the first "all" entry. */
9283 for (opt
= aarch64_archs
+ 1; opt
->name
!= NULL
; opt
++)
9284 if (strlen (opt
->name
) == optlen
9285 && strncmp (name
, opt
->name
, optlen
) == 0)
9287 mcpu_cpu_opt
= &opt
->value
;
9289 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, FALSE
))
9292 cpu_variant
= *mcpu_cpu_opt
;
9294 *input_line_pointer
= saved_char
;
9295 demand_empty_rest_of_line ();
9299 as_bad (_("unknown architecture `%s'\n"), name
);
9300 *input_line_pointer
= saved_char
;
9301 ignore_rest_of_line ();
9304 /* Parse a .arch_extension directive. */
9307 s_aarch64_arch_extension (int ignored ATTRIBUTE_UNUSED
)
9310 char *ext
= input_line_pointer
;;
9312 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
9313 input_line_pointer
++;
9314 saved_char
= *input_line_pointer
;
9315 *input_line_pointer
= 0;
9317 if (!aarch64_parse_features (ext
, &mcpu_cpu_opt
, TRUE
))
9320 cpu_variant
= *mcpu_cpu_opt
;
9322 *input_line_pointer
= saved_char
;
9323 demand_empty_rest_of_line ();
9326 /* Copy symbol information. */
9329 aarch64_copy_symbol_attributes (symbolS
* dest
, symbolS
* src
)
9331 AARCH64_GET_FLAG (dest
) = AARCH64_GET_FLAG (src
);